From patchwork Fri Jun 22 08:38:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhao1, Wei" X-Patchwork-Id: 41383 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F2DF11BB2E; Fri, 22 Jun 2018 10:59:43 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 68B8E1BB20; Fri, 22 Jun 2018 10:59:42 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jun 2018 01:59:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,256,1526367600"; d="scan'208";a="239662067" Received: from dpdk6.bj.intel.com ([172.16.182.94]) by fmsmga006.fm.intel.com with ESMTP; 22 Jun 2018 01:59:39 -0700 From: Wei Zhao To: dev@dpdk.org Cc: wenzhuo.lu@intel.com, qi.z.zhang@intel.com, stable@dpdk.org, Wei Zhao Date: Fri, 22 Jun 2018 16:38:47 +0800 Message-Id: <1529656727-40207-1-git-send-email-wei.zhao1@intel.com> X-Mailer: git-send-email 2.7.5 Subject: [dpdk-dev] [PATCH] net/ixgbe: fix Tx check descriptor status APIs error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is a issue involve RS bit set rule in ixgbe. Let us take function ixgbe_xmit_pkts_vec () as an example, in this function RS bit will be set for descriptor with index txq->tx_next_rs, and also descriptor free function ixgbe_tx_free_bufs() also check RS bit for descriptor with index txq->tx_next_rs, This is perfect ok. Let us take an example, if app set tx_rs_thresh = 32 and nb_desc = 512, then ixgbe PMD code will init txq->tx_next_rs = 31 in function ixgbe_reset_tx_queue when tx queue setup. And also txq->tx_next_rs will be update as 63, 95 and so on. But, in the function ixgbe_dev_tx_descriptor_status(), the RS bit to check is " desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * txq-tx_rs_thresh", which is 32 ,64, 96 and so on. So, they are all wrong! In tx function of ixgbe_xmit_pkts_simple, the RS bit rule is also the same, it also set index 31 ,64, 95. we need to correct it. Fixes: a2919e13d95e ("net/ixgbe: implement descriptor status API") Signed-off-by: Wei Zhao --- drivers/net/ixgbe/ixgbe_rxtx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 3e13d26..f185219 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -3146,15 +3146,15 @@ ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) return -EINVAL; desc = txq->tx_tail + offset; + if (desc >= txq->nb_tx_desc) + desc -= txq->nb_tx_desc; /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { + desc = (desc / txq->tx_rs_thresh + 1) * + txq->tx_rs_thresh - 1; + if (desc >= txq->nb_tx_desc) desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; - } + desc = txq->sw_ring[desc].last_id; status = &txq->tx_ring[desc].wb.status; if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)) return RTE_ETH_TX_DESC_DONE;