From patchwork Tue Nov 2 03:17:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103392 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1C569A0C4D; Tue, 2 Nov 2021 04:20:21 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 428B4410FE; Tue, 2 Nov 2021 04:19:41 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id 881E741101 for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Hjw7S1n6wz1DHwk; Tue, 2 Nov 2021 11:17:24 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:27 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:21 +0800 Message-ID: <20211102031729.35536-2-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 1/9] net/hns3: fix the shift of DMA address in Rx/Tx queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Huisong Li The patch obtains the upper 32 bits of the Rx/Tx queue DMA address in one step instead of two steps. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Signed-off-by: Huisong Li --- drivers/net/hns3/hns3_rxtx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index ceb98025f8..00af73c850 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -322,7 +322,7 @@ hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq) hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr); hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG, - (uint32_t)((dma_addr >> 31) >> 1)); + (uint32_t)(dma_addr >> 32)); hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG, hns3_buf_size2type(rx_buf_len)); @@ -337,7 +337,7 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq) hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr); hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG, - (uint32_t)((dma_addr >> 31) >> 1)); + (uint32_t)(dma_addr >> 32)); hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG, HNS3_CFG_DESC_NUM(txq->nb_tx_desc)); From patchwork Tue Nov 2 03:17:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103386 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 995D7A0C4D; Tue, 2 Nov 2021 04:19:39 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 03AFF410FF; Tue, 2 Nov 2021 04:19:35 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 4C3FC410E5 for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4Hjw4N0wbszcb4x; Tue, 2 Nov 2021 11:14:44 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:27 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:22 +0800 Message-ID: <20211102031729.35536-3-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 2/9] net/hns3: remove a redundant function declaration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Huisong Li This patch removes a redundant function declaration for hns3_rx_check_vec_support(). Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 33ee8c61a0..63bafc68b6 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -711,7 +711,6 @@ uint16_t hns3_recv_pkts_vec_sve(void *rx_queue, struct rte_mbuf **rx_pkts, int hns3_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, struct rte_eth_burst_mode *mode); -int hns3_rx_check_vec_support(struct rte_eth_dev *dev); uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); uint16_t hns3_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts, From patchwork Tue Nov 2 03:17:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103387 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DFA10A0C4D; Tue, 2 Nov 2021 04:19:45 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 19A3141109; Tue, 2 Nov 2021 04:19:36 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id 54BD2410FD for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Hjw7S4Brrz1DH9w; Tue, 2 Nov 2021 11:17:24 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:27 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:23 +0800 Message-ID: <20211102031729.35536-4-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 3/9] net/hns3: modifying code alignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Huisong Li This patch modifies some code alignment issues to make the code style more consistent. Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 00af73c850..7e55b24cb8 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -1907,7 +1907,7 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, */ if (hns->is_vf || hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) rxq->pvid_sw_discard_en = hw->port_base_vlan_cfg.state == - HNS3_PORT_BASE_VLAN_ENABLE; + HNS3_PORT_BASE_VLAN_ENABLE; else rxq->pvid_sw_discard_en = false; rxq->ptype_en = hns3_dev_get_support(hw, RXD_ADV_LAYOUT) ? true : false; From patchwork Tue Nov 2 03:17:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103388 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC6F0A0C4D; Tue, 2 Nov 2021 04:19:52 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2D04E4111F; Tue, 2 Nov 2021 04:19:37 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id 58F41410FE for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Hjw7S5Pvmz1DHwn; Tue, 2 Nov 2021 11:17:24 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:27 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:24 +0800 Message-ID: <20211102031729.35536-5-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 4/9] net/hns3: use unsigned integer for bitwise operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Huisong Li Bitwise operations should be used only with unsigned integer. This patch modifies some code that does not meet this rule. Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index ccae75baa0..50e73b00b7 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2104,7 +2104,7 @@ hns3_check_mq_mode(struct rte_eth_dev *dev) int max_tc = 0; int i; - if ((rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) || + if (((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) || (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB || tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) { hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.", @@ -2114,7 +2114,7 @@ hns3_check_mq_mode(struct rte_eth_dev *dev) dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; - if (rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) { + if ((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) { if (dcb_rx_conf->nb_tcs > pf->tc_max) { hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", dcb_rx_conf->nb_tcs, pf->tc_max); From patchwork Tue Nov 2 03:17:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103393 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7BA7A0C4D; Tue, 2 Nov 2021 04:20:26 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4AB5541149; Tue, 2 Nov 2021 04:19:42 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 392EB40DF6 for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4Hjw4N59yYzcb4X; Tue, 2 Nov 2021 11:14:44 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:27 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:25 +0800 Message-ID: <20211102031729.35536-6-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 5/9] net/hns3: extract a common file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Huisong Li This patch extracts a common file to store the common code for PF and VF driver. Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_cmd.c | 2 +- drivers/net/hns3/hns3_common.c | 427 +++++++++++++++++++++++++++++ drivers/net/hns3/hns3_common.h | 48 ++++ drivers/net/hns3/hns3_ethdev.c | 430 +----------------------------- drivers/net/hns3/hns3_ethdev.h | 30 +-- drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_intr.c | 2 +- drivers/net/hns3/hns3_mbx.c | 2 +- drivers/net/hns3/hns3_rxtx.c | 2 +- drivers/net/hns3/meson.build | 1 + 10 files changed, 485 insertions(+), 460 deletions(-) create mode 100644 drivers/net/hns3/hns3_common.c create mode 100644 drivers/net/hns3/hns3_common.h diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 50769c6226..2ce59d8de6 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -5,7 +5,7 @@ #include #include -#include "hns3_ethdev.h" +#include "hns3_common.h" #include "hns3_regs.h" #include "hns3_intr.h" #include "hns3_logs.h" diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c new file mode 100644 index 0000000000..5fe0ff5ce7 --- /dev/null +++ b/drivers/net/hns3/hns3_common.c @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 HiSilicon Limited + */ + +#include + +#include "hns3_logs.h" +#include "hns3_common.h" + +static int +hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) +{ + uint32_t hint = HNS3_IO_FUNC_HINT_NONE; + + RTE_SET_USED(key); + + if (strcmp(value, "vec") == 0) + hint = HNS3_IO_FUNC_HINT_VEC; + else if (strcmp(value, "sve") == 0) + hint = HNS3_IO_FUNC_HINT_SVE; + else if (strcmp(value, "simple") == 0) + hint = HNS3_IO_FUNC_HINT_SIMPLE; + else if (strcmp(value, "common") == 0) + hint = HNS3_IO_FUNC_HINT_COMMON; + + /* If the hint is valid then update output parameters */ + if (hint != HNS3_IO_FUNC_HINT_NONE) + *(uint32_t *)extra_args = hint; + + return 0; +} + +static const char * +hns3_get_io_hint_func_name(uint32_t hint) +{ + switch (hint) { + case HNS3_IO_FUNC_HINT_VEC: + return "vec"; + case HNS3_IO_FUNC_HINT_SVE: + return "sve"; + case HNS3_IO_FUNC_HINT_SIMPLE: + return "simple"; + case HNS3_IO_FUNC_HINT_COMMON: + return "common"; + default: + return "none"; + } +} + +static int +hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) +{ + uint64_t val; + + RTE_SET_USED(key); + + val = strtoull(value, NULL, 16); + *(uint64_t *)extra_args = val; + + return 0; +} + +static int +hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args) +{ + uint32_t val; + + RTE_SET_USED(key); + + val = strtoul(value, NULL, 10); + if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX) + *(uint16_t *)extra_args = val; + + return 0; +} + +void +hns3_parse_devargs(struct rte_eth_dev *dev) +{ + uint16_t mbx_time_limit_ms = HNS3_MBX_DEF_TIME_LIMIT_MS; + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; + uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; + struct hns3_hw *hw = &hns->hw; + uint64_t dev_caps_mask = 0; + struct rte_kvargs *kvlist; + + if (dev->device->devargs == NULL) + return; + + kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); + if (!kvlist) + return; + + (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, + &hns3_parse_io_hint_func, &rx_func_hint); + (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, + &hns3_parse_io_hint_func, &tx_func_hint); + (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK, + &hns3_parse_dev_caps_mask, &dev_caps_mask); + (void)rte_kvargs_process(kvlist, HNS3_DEVARG_MBX_TIME_LIMIT_MS, + &hns3_parse_mbx_time_limit, &mbx_time_limit_ms); + + rte_kvargs_free(kvlist); + + if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, + hns3_get_io_hint_func_name(rx_func_hint)); + hns->rx_func_hint = rx_func_hint; + if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, + hns3_get_io_hint_func_name(tx_func_hint)); + hns->tx_func_hint = tx_func_hint; + + if (dev_caps_mask != 0) + hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".", + HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask); + hns->dev_caps_mask = dev_caps_mask; +} + +void +hns3_clock_gettime(struct timeval *tv) +{ +#ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ +#define CLOCK_TYPE CLOCK_MONOTONIC_RAW +#else +#define CLOCK_TYPE CLOCK_MONOTONIC +#endif +#define NSEC_TO_USEC_DIV 1000 + + struct timespec spec; + (void)clock_gettime(CLOCK_TYPE, &spec); + + tv->tv_sec = spec.tv_sec; + tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV; +} + +uint64_t +hns3_clock_calctime_ms(struct timeval *tv) +{ + return (uint64_t)tv->tv_sec * MSEC_PER_SEC + + tv->tv_usec / USEC_PER_MSEC; +} + +uint64_t +hns3_clock_gettime_ms(void) +{ + struct timeval tv; + + hns3_clock_gettime(&tv); + return hns3_clock_calctime_ms(&tv); +} + +void hns3_ether_format_addr(char *buf, uint16_t size, + const struct rte_ether_addr *ether_addr) +{ + snprintf(buf, size, "%02X:**:**:**:%02X:%02X", + ether_addr->addr_bytes[0], + ether_addr->addr_bytes[4], + ether_addr->addr_bytes[5]); +} + +static int +hns3_set_mc_addr_chk_param(struct hns3_hw *hw, + struct rte_ether_addr *mc_addr_set, + uint32_t nb_mc_addr) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; + struct rte_ether_addr *addr; + uint16_t mac_addrs_capa; + uint32_t i; + uint32_t j; + + if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { + hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " + "invalid. valid range: 0~%d", + nb_mc_addr, HNS3_MC_MACADDR_NUM); + return -EINVAL; + } + + /* Check if input mac addresses are valid */ + for (i = 0; i < nb_mc_addr; i++) { + addr = &mc_addr_set[i]; + if (!rte_is_multicast_ether_addr(addr)) { + hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, + addr); + hns3_err(hw, + "failed to set mc mac addr, addr(%s) invalid.", + mac_str); + return -EINVAL; + } + + /* Check if there are duplicate addresses */ + for (j = i + 1; j < nb_mc_addr; j++) { + if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { + hns3_ether_format_addr(mac_str, + RTE_ETHER_ADDR_FMT_SIZE, + addr); + hns3_err(hw, "failed to set mc mac addr, " + "addrs invalid. two same addrs(%s).", + mac_str); + return -EINVAL; + } + } + + /* + * Check if there are duplicate addresses between mac_addrs + * and mc_addr_set + */ + mac_addrs_capa = hns->is_vf ? HNS3_VF_UC_MACADDR_NUM : + HNS3_UC_MACADDR_NUM; + for (j = 0; j < mac_addrs_capa; j++) { + if (rte_is_same_ether_addr(addr, + &hw->data->mac_addrs[j])) { + hns3_ether_format_addr(mac_str, + RTE_ETHER_ADDR_FMT_SIZE, + addr); + hns3_err(hw, "failed to set mc mac addr, " + "addrs invalid. addrs(%s) has already " + "configured in mac_addr add API", + mac_str); + return -EINVAL; + } + } + } + + return 0; +} + +int +hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, + struct rte_ether_addr *mc_addr_set, + uint32_t nb_mc_addr) +{ + struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_ether_addr *addr; + int cur_addr_num; + int set_addr_num; + int num; + int ret; + int i; + + /* Check if input parameters are valid */ + ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); + if (ret) + return ret; + + rte_spinlock_lock(&hw->lock); + cur_addr_num = hw->mc_addrs_num; + for (i = 0; i < cur_addr_num; i++) { + num = cur_addr_num - i - 1; + addr = &hw->mc_addrs[num]; + ret = hw->ops.del_mc_mac_addr(hw, addr); + if (ret) { + rte_spinlock_unlock(&hw->lock); + return ret; + } + + hw->mc_addrs_num--; + } + + set_addr_num = (int)nb_mc_addr; + for (i = 0; i < set_addr_num; i++) { + addr = &mc_addr_set[i]; + ret = hw->ops.add_mc_mac_addr(hw, addr); + if (ret) { + rte_spinlock_unlock(&hw->lock); + return ret; + } + + rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); + hw->mc_addrs_num++; + } + rte_spinlock_unlock(&hw->lock); + + return 0; +} + +int +hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) +{ + char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; + struct hns3_hw *hw = &hns->hw; + struct rte_ether_addr *addr; + int ret = 0; + int i; + + for (i = 0; i < hw->mc_addrs_num; i++) { + addr = &hw->mc_addrs[i]; + if (!rte_is_multicast_ether_addr(addr)) + continue; + if (del) + ret = hw->ops.del_mc_mac_addr(hw, addr); + else + ret = hw->ops.add_mc_mac_addr(hw, addr); + if (ret) { + hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, + addr); + hns3_dbg(hw, "failed to %s mc mac addr: %s ret = %d", + del ? "Remove" : "Restore", mac_str, ret); + } + } + return ret; +} + +int +hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) +{ + char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; + struct hns3_hw *hw = &hns->hw; + struct hns3_hw_ops *ops = &hw->ops; + struct rte_ether_addr *addr; + uint16_t mac_addrs_capa; + int ret = 0; + int i; + + mac_addrs_capa = + hns->is_vf ? HNS3_VF_UC_MACADDR_NUM : HNS3_UC_MACADDR_NUM; + for (i = 0; i < mac_addrs_capa; i++) { + addr = &hw->data->mac_addrs[i]; + if (rte_is_zero_ether_addr(addr)) + continue; + if (rte_is_multicast_ether_addr(addr)) + ret = del ? ops->del_mc_mac_addr(hw, addr) : + ops->add_mc_mac_addr(hw, addr); + else + ret = del ? ops->del_uc_mac_addr(hw, addr) : + ops->add_uc_mac_addr(hw, addr); + + if (ret) { + hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, + addr); + hns3_err(hw, "failed to %s mac addr(%s) index:%d ret = %d.", + del ? "remove" : "restore", mac_str, i, ret); + } + } + + return ret; +} + +static bool +hns3_find_duplicate_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mc_addr) +{ + char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; + struct rte_ether_addr *addr; + int i; + + for (i = 0; i < hw->mc_addrs_num; i++) { + addr = &hw->mc_addrs[i]; + /* Check if there are duplicate addresses in mc_addrs[] */ + if (rte_is_same_ether_addr(addr, mc_addr)) { + hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, + addr); + hns3_err(hw, "failed to add mc mac addr, same addrs" + "(%s) is added by the set_mc_mac_addr_list " + "API", mac_str); + return true; + } + } + + return false; +} + +int +hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, + __rte_unused uint32_t idx, __rte_unused uint32_t pool) +{ + struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); + char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; + int ret; + + rte_spinlock_lock(&hw->lock); + + /* + * In hns3 network engine adding UC and MC mac address with different + * commands with firmware. We need to determine whether the input + * address is a UC or a MC address to call different commands. + * By the way, it is recommended calling the API function named + * rte_eth_dev_set_mc_addr_list to set the MC mac address, because + * using the rte_eth_dev_mac_addr_add API function to set MC mac address + * may affect the specifications of UC mac addresses. + */ + if (rte_is_multicast_ether_addr(mac_addr)) { + if (hns3_find_duplicate_mc_addr(hw, mac_addr)) { + rte_spinlock_unlock(&hw->lock); + return -EINVAL; + } + ret = hw->ops.add_mc_mac_addr(hw, mac_addr); + } else { + ret = hw->ops.add_uc_mac_addr(hw, mac_addr); + } + rte_spinlock_unlock(&hw->lock); + if (ret) { + hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, + mac_addr); + hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, + ret); + } + + return ret; +} + +void +hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) +{ + struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); + /* index will be checked by upper level rte interface */ + struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; + char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; + int ret; + + rte_spinlock_lock(&hw->lock); + + if (rte_is_multicast_ether_addr(mac_addr)) + ret = hw->ops.del_mc_mac_addr(hw, mac_addr); + else + ret = hw->ops.del_uc_mac_addr(hw, mac_addr); + rte_spinlock_unlock(&hw->lock); + if (ret) { + hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, + mac_addr); + hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, + ret); + } +} + diff --git a/drivers/net/hns3/hns3_common.h b/drivers/net/hns3/hns3_common.h new file mode 100644 index 0000000000..094a0bc5ff --- /dev/null +++ b/drivers/net/hns3/hns3_common.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 HiSilicon Limited + */ + +#ifndef _HNS3_COMMON_H_ +#define _HNS3_COMMON_H_ + +#include + +#include "hns3_ethdev.h" + +enum { + HNS3_IO_FUNC_HINT_NONE = 0, + HNS3_IO_FUNC_HINT_VEC, + HNS3_IO_FUNC_HINT_SVE, + HNS3_IO_FUNC_HINT_SIMPLE, + HNS3_IO_FUNC_HINT_COMMON +}; + +#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" +#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" + +#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask" + +#define HNS3_DEVARG_MBX_TIME_LIMIT_MS "mbx_time_limit_ms" + +#define MSEC_PER_SEC 1000L +#define USEC_PER_MSEC 1000L + +void hns3_clock_gettime(struct timeval *tv); +uint64_t hns3_clock_calctime_ms(struct timeval *tv); +uint64_t hns3_clock_gettime_ms(void); + +void hns3_parse_devargs(struct rte_eth_dev *dev); + +int hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del); +int hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del); +int hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, + __rte_unused uint32_t idx, __rte_unused uint32_t pool); + +void hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx); +int hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, + struct rte_ether_addr *mc_addr_set, + uint32_t nb_mc_addr); +void hns3_ether_format_addr(char *buf, uint16_t size, + const struct rte_ether_addr *ether_addr); + +#endif /* _HNS3_COMMON_H_ */ diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 50e73b00b7..2f1ecffd5a 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6,9 +6,9 @@ #include #include #include -#include #include "hns3_ethdev.h" +#include "hns3_common.h" #include "hns3_logs.h" #include "hns3_rxtx.h" #include "hns3_intr.h" @@ -105,14 +105,6 @@ static int hns3_do_stop(struct hns3_adapter *hns); static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds); static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable); -void hns3_ether_format_addr(char *buf, uint16_t size, - const struct rte_ether_addr *ether_addr) -{ - snprintf(buf, size, "%02X:**:**:**:%02X:%02X", - ether_addr->addr_bytes[0], - ether_addr->addr_bytes[4], - ether_addr->addr_bytes[5]); -} static void hns3_pf_disable_irq0(struct hns3_hw *hw) @@ -1609,68 +1601,6 @@ hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) return ret; } -static bool -hns3_find_duplicate_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mc_addr) -{ - char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; - struct rte_ether_addr *addr; - int i; - - for (i = 0; i < hw->mc_addrs_num; i++) { - addr = &hw->mc_addrs[i]; - /* Check if there are duplicate addresses in mc_addrs[] */ - if (rte_is_same_ether_addr(addr, mc_addr)) { - hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, - addr); - hns3_err(hw, "failed to add mc mac addr, same addrs" - "(%s) is added by the set_mc_mac_addr_list " - "API", mac_str); - return true; - } - } - - return false; -} - -int -hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, - __rte_unused uint32_t idx, __rte_unused uint32_t pool) -{ - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; - int ret; - - rte_spinlock_lock(&hw->lock); - - /* - * In hns3 network engine adding UC and MC mac address with different - * commands with firmware. We need to determine whether the input - * address is a UC or a MC address to call different commands. - * By the way, it is recommended calling the API function named - * rte_eth_dev_set_mc_addr_list to set the MC mac address, because - * using the rte_eth_dev_mac_addr_add API function to set MC mac address - * may affect the specifications of UC mac addresses. - */ - if (rte_is_multicast_ether_addr(mac_addr)) { - if (hns3_find_duplicate_mc_addr(hw, mac_addr)) { - rte_spinlock_unlock(&hw->lock); - return -EINVAL; - } - ret = hw->ops.add_mc_mac_addr(hw, mac_addr); - } else { - ret = hw->ops.add_uc_mac_addr(hw, mac_addr); - } - rte_spinlock_unlock(&hw->lock); - if (ret) { - hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, - mac_addr); - hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, - ret); - } - - return ret; -} - static int hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) { @@ -1699,30 +1629,6 @@ hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) return ret; } -void -hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) -{ - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - /* index will be checked by upper level rte interface */ - struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; - char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; - int ret; - - rte_spinlock_lock(&hw->lock); - - if (rte_is_multicast_ether_addr(mac_addr)) - ret = hw->ops.del_mc_mac_addr(hw, mac_addr); - else - ret = hw->ops.del_uc_mac_addr(hw, mac_addr); - rte_spinlock_unlock(&hw->lock); - if (ret) { - hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, - mac_addr); - hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, - ret); - } -} - static int hns3_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) @@ -1787,41 +1693,6 @@ hns3_set_default_mac_addr(struct rte_eth_dev *dev, return ret; } -int -hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) -{ - char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; - struct hns3_hw *hw = &hns->hw; - struct hns3_hw_ops *ops = &hw->ops; - struct rte_ether_addr *addr; - uint16_t mac_addrs_capa; - int ret = 0; - int i; - - mac_addrs_capa = - hns->is_vf ? HNS3_VF_UC_MACADDR_NUM : HNS3_UC_MACADDR_NUM; - for (i = 0; i < mac_addrs_capa; i++) { - addr = &hw->data->mac_addrs[i]; - if (rte_is_zero_ether_addr(addr)) - continue; - if (rte_is_multicast_ether_addr(addr)) - ret = del ? ops->del_mc_mac_addr(hw, addr) : - ops->add_mc_mac_addr(hw, addr); - else - ret = del ? ops->del_uc_mac_addr(hw, addr) : - ops->add_uc_mac_addr(hw, addr); - - if (ret) { - hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, - addr); - hns3_err(hw, "failed to %s mac addr(%s) index:%d ret = %d.", - del ? "remove" : "restore", mac_str, i, ret); - } - } - - return ret; -} - static void hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) { @@ -1947,150 +1818,6 @@ hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) return ret; } -static int -hns3_set_mc_addr_chk_param(struct hns3_hw *hw, - struct rte_ether_addr *mc_addr_set, - uint32_t nb_mc_addr) -{ - struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; - struct rte_ether_addr *addr; - uint16_t mac_addrs_capa; - uint32_t i; - uint32_t j; - - if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { - hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " - "invalid. valid range: 0~%d", - nb_mc_addr, HNS3_MC_MACADDR_NUM); - return -EINVAL; - } - - /* Check if input mac addresses are valid */ - for (i = 0; i < nb_mc_addr; i++) { - addr = &mc_addr_set[i]; - if (!rte_is_multicast_ether_addr(addr)) { - hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, - addr); - hns3_err(hw, - "failed to set mc mac addr, addr(%s) invalid.", - mac_str); - return -EINVAL; - } - - /* Check if there are duplicate addresses */ - for (j = i + 1; j < nb_mc_addr; j++) { - if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { - hns3_ether_format_addr(mac_str, - RTE_ETHER_ADDR_FMT_SIZE, - addr); - hns3_err(hw, "failed to set mc mac addr, " - "addrs invalid. two same addrs(%s).", - mac_str); - return -EINVAL; - } - } - - /* - * Check if there are duplicate addresses between mac_addrs - * and mc_addr_set - */ - mac_addrs_capa = hns->is_vf ? HNS3_VF_UC_MACADDR_NUM : - HNS3_UC_MACADDR_NUM; - for (j = 0; j < mac_addrs_capa; j++) { - if (rte_is_same_ether_addr(addr, - &hw->data->mac_addrs[j])) { - hns3_ether_format_addr(mac_str, - RTE_ETHER_ADDR_FMT_SIZE, - addr); - hns3_err(hw, "failed to set mc mac addr, " - "addrs invalid. addrs(%s) has already " - "configured in mac_addr add API", - mac_str); - return -EINVAL; - } - } - } - - return 0; -} - -int -hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, - struct rte_ether_addr *mc_addr_set, - uint32_t nb_mc_addr) -{ - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - struct rte_ether_addr *addr; - int cur_addr_num; - int set_addr_num; - int num; - int ret; - int i; - - /* Check if input parameters are valid */ - ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); - if (ret) - return ret; - - rte_spinlock_lock(&hw->lock); - cur_addr_num = hw->mc_addrs_num; - for (i = 0; i < cur_addr_num; i++) { - num = cur_addr_num - i - 1; - addr = &hw->mc_addrs[num]; - ret = hw->ops.del_mc_mac_addr(hw, addr); - if (ret) { - rte_spinlock_unlock(&hw->lock); - return ret; - } - - hw->mc_addrs_num--; - } - - set_addr_num = (int)nb_mc_addr; - for (i = 0; i < set_addr_num; i++) { - addr = &mc_addr_set[i]; - ret = hw->ops.add_mc_mac_addr(hw, addr); - if (ret) { - rte_spinlock_unlock(&hw->lock); - return ret; - } - - rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]); - hw->mc_addrs_num++; - } - rte_spinlock_unlock(&hw->lock); - - return 0; -} - -int -hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) -{ - char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; - struct hns3_hw *hw = &hns->hw; - struct rte_ether_addr *addr; - int ret = 0; - int i; - - for (i = 0; i < hw->mc_addrs_num; i++) { - addr = &hw->mc_addrs[i]; - if (!rte_is_multicast_ether_addr(addr)) - continue; - if (del) - ret = hw->ops.del_mc_mac_addr(hw, addr); - else - ret = hw->ops.add_mc_mac_addr(hw, addr); - if (ret) { - hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, - addr); - hns3_dbg(hw, "failed to %s mc mac addr: %s ret = %d", - del ? "Remove" : "Restore", mac_str, ret); - } - } - return ret; -} - static int hns3_check_mq_mode(struct rte_eth_dev *dev) { @@ -7110,161 +6837,6 @@ hns3_get_module_info(struct rte_eth_dev *dev, return 0; } -void -hns3_clock_gettime(struct timeval *tv) -{ -#ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ -#define CLOCK_TYPE CLOCK_MONOTONIC_RAW -#else -#define CLOCK_TYPE CLOCK_MONOTONIC -#endif -#define NSEC_TO_USEC_DIV 1000 - - struct timespec spec; - (void)clock_gettime(CLOCK_TYPE, &spec); - - tv->tv_sec = spec.tv_sec; - tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV; -} - -uint64_t -hns3_clock_calctime_ms(struct timeval *tv) -{ - return (uint64_t)tv->tv_sec * MSEC_PER_SEC + - tv->tv_usec / USEC_PER_MSEC; -} - -uint64_t -hns3_clock_gettime_ms(void) -{ - struct timeval tv; - - hns3_clock_gettime(&tv); - return hns3_clock_calctime_ms(&tv); -} - -static int -hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) -{ - uint32_t hint = HNS3_IO_FUNC_HINT_NONE; - - RTE_SET_USED(key); - - if (strcmp(value, "vec") == 0) - hint = HNS3_IO_FUNC_HINT_VEC; - else if (strcmp(value, "sve") == 0) - hint = HNS3_IO_FUNC_HINT_SVE; - else if (strcmp(value, "simple") == 0) - hint = HNS3_IO_FUNC_HINT_SIMPLE; - else if (strcmp(value, "common") == 0) - hint = HNS3_IO_FUNC_HINT_COMMON; - - /* If the hint is valid then update output parameters */ - if (hint != HNS3_IO_FUNC_HINT_NONE) - *(uint32_t *)extra_args = hint; - - return 0; -} - -static const char * -hns3_get_io_hint_func_name(uint32_t hint) -{ - switch (hint) { - case HNS3_IO_FUNC_HINT_VEC: - return "vec"; - case HNS3_IO_FUNC_HINT_SVE: - return "sve"; - case HNS3_IO_FUNC_HINT_SIMPLE: - return "simple"; - case HNS3_IO_FUNC_HINT_COMMON: - return "common"; - default: - return "none"; - } -} - -static int -hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) -{ - uint64_t val; - - RTE_SET_USED(key); - - val = strtoull(value, NULL, 16); - *(uint64_t *)extra_args = val; - - return 0; -} - -static int -hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args) -{ - uint32_t val; - - RTE_SET_USED(key); - - val = strtoul(value, NULL, 10); - - /* - * 500ms is empirical value in process of mailbox communication. If - * the delay value is set to one lower thanthe empirical value, mailbox - * communication may fail. - */ - if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX) - *(uint16_t *)extra_args = val; - - return 0; -} - -void -hns3_parse_devargs(struct rte_eth_dev *dev) -{ - uint16_t mbx_time_limit_ms = HNS3_MBX_DEF_TIME_LIMIT_MS; - struct hns3_adapter *hns = dev->data->dev_private; - uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; - uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; - struct hns3_hw *hw = &hns->hw; - uint64_t dev_caps_mask = 0; - struct rte_kvargs *kvlist; - - if (dev->device->devargs == NULL) - return; - - kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); - if (!kvlist) - return; - - (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, - &hns3_parse_io_hint_func, &rx_func_hint); - (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, - &hns3_parse_io_hint_func, &tx_func_hint); - (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK, - &hns3_parse_dev_caps_mask, &dev_caps_mask); - (void)rte_kvargs_process(kvlist, HNS3_DEVARG_MBX_TIME_LIMIT_MS, - &hns3_parse_mbx_time_limit, &mbx_time_limit_ms); - - rte_kvargs_free(kvlist); - - if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) - hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, - hns3_get_io_hint_func_name(rx_func_hint)); - hns->rx_func_hint = rx_func_hint; - if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) - hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, - hns3_get_io_hint_func_name(tx_func_hint)); - hns->tx_func_hint = tx_func_hint; - - if (dev_caps_mask != 0) - hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".", - HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask); - hns->dev_caps_mask = dev_caps_mask; - - if (mbx_time_limit_ms != HNS3_MBX_DEF_TIME_LIMIT_MS) - hns3_warn(hw, "parsed %s = %u.", HNS3_DEVARG_MBX_TIME_LIMIT_MS, - mbx_time_limit_ms); - hns->mbx_time_limit_ms = mbx_time_limit_ms; -} - static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index f3cc88f43e..634018c847 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -6,7 +6,6 @@ #define _HNS3_ETHDEV_H_ #include -#include #include #include #include @@ -869,14 +868,6 @@ struct hns3_adapter { struct hns3_ptype_table ptype_tbl __rte_cache_aligned; }; -enum { - HNS3_IO_FUNC_HINT_NONE = 0, - HNS3_IO_FUNC_HINT_VEC, - HNS3_IO_FUNC_HINT_SVE, - HNS3_IO_FUNC_HINT_SIMPLE, - HNS3_IO_FUNC_HINT_COMMON -}; - #define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" #define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" @@ -1011,13 +1002,6 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) } \ } while (0) -#define MSEC_PER_SEC 1000L -#define USEC_PER_MSEC 1000L - -void hns3_clock_gettime(struct timeval *tv); -uint64_t hns3_clock_calctime_ms(struct timeval *tv); -uint64_t hns3_clock_gettime_ms(void); - static inline uint64_t hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) { @@ -1047,28 +1031,20 @@ hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; } +uint32_t hns3_get_speed_capa(struct hns3_hw *hw); + int hns3_buffer_alloc(struct hns3_hw *hw); int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); bool hns3_is_reset_pending(struct hns3_adapter *hns); bool hns3vf_is_reset_pending(struct hns3_adapter *hns); void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); -void hns3_ether_format_addr(char *buf, uint16_t size, - const struct rte_ether_addr *ether_addr); int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); -void hns3_parse_devargs(struct rte_eth_dev *dev); void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); -int hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del); -int hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del); -int hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, - __rte_unused uint32_t idx, __rte_unused uint32_t pool); -void hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx); -int hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, - struct rte_ether_addr *mc_addr_set, - uint32_t nb_mc_addr); + int hns3_restore_ptp(struct hns3_adapter *hns); int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev, struct rte_eth_conf *conf); diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 27701a919e..d06f863249 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -10,6 +10,7 @@ #include #include "hns3_ethdev.h" +#include "hns3_common.h" #include "hns3_logs.h" #include "hns3_rxtx.h" #include "hns3_regs.h" diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 3484c76d23..66dc509086 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -8,7 +8,7 @@ #include #include -#include "hns3_ethdev.h" +#include "hns3_common.h" #include "hns3_logs.h" #include "hns3_intr.h" #include "hns3_regs.h" diff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c index 245652e2ed..b3563d4694 100644 --- a/drivers/net/hns3/hns3_mbx.c +++ b/drivers/net/hns3/hns3_mbx.c @@ -5,7 +5,7 @@ #include #include -#include "hns3_ethdev.h" +#include "hns3_common.h" #include "hns3_regs.h" #include "hns3_logs.h" #include "hns3_intr.h" diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 7e55b24cb8..d26e262335 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -16,7 +16,7 @@ #include #endif -#include "hns3_ethdev.h" +#include "hns3_common.h" #include "hns3_rxtx.h" #include "hns3_regs.h" #include "hns3_logs.h" diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index a99e0dbb74..8a4c7cc100 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -29,6 +29,7 @@ sources = files( 'hns3_mp.c', 'hns3_tm.c', 'hns3_ptp.c', + 'hns3_common.c', ) deps += ['hash'] From patchwork Tue Nov 2 03:17:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103391 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 966FDA0C4D; Tue, 2 Nov 2021 04:20:14 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 386774113E; Tue, 2 Nov 2021 04:19:40 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 2F12F4068F for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4Hjw4N5rtnzcb59; Tue, 2 Nov 2021 11:14:44 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:27 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:26 +0800 Message-ID: <20211102031729.35536-7-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 6/9] net/hns3: add hns3 flow header file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds a hns3_flow.h to make the code easier to maintain. Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev.h | 3 +-- drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_fdir.h | 31 ---------------------- drivers/net/hns3/hns3_flow.c | 1 + drivers/net/hns3/hns3_flow.h | 44 +++++++++++++++++++++++++++++++ 6 files changed, 48 insertions(+), 33 deletions(-) create mode 100644 drivers/net/hns3/hns3_flow.h diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 2f1ecffd5a..2f4beacb87 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -15,6 +15,7 @@ #include "hns3_regs.h" #include "hns3_dcb.h" #include "hns3_mp.h" +#include "hns3_flow.h" #define HNS3_SERVICE_INTERVAL 1000000 /* us */ #define HNS3_SERVICE_QUICK_INTERVAL 10 diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 634018c847..a28c7c262b 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -17,6 +17,7 @@ #include "hns3_fdir.h" #include "hns3_stats.h" #include "hns3_tm.h" +#include "hns3_flow.h" /* Vendor ID */ #define PCI_VENDOR_ID_HUAWEI 0x19e5 @@ -1034,8 +1035,6 @@ hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) uint32_t hns3_get_speed_capa(struct hns3_hw *hw); int hns3_buffer_alloc(struct hns3_hw *hw); -int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, - const struct rte_flow_ops **ops); bool hns3_is_reset_pending(struct hns3_adapter *hns); bool hns3vf_is_reset_pending(struct hns3_adapter *hns); void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index d06f863249..7e60090fd3 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -17,6 +17,7 @@ #include "hns3_intr.h" #include "hns3_dcb.h" #include "hns3_mp.h" +#include "hns3_flow.h" #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ #define HNS3VF_SERVICE_INTERVAL 1000000 /* us */ diff --git a/drivers/net/hns3/hns3_fdir.h b/drivers/net/hns3/hns3_fdir.h index 3f610f7b11..f9efff3b52 100644 --- a/drivers/net/hns3/hns3_fdir.h +++ b/drivers/net/hns3/hns3_fdir.h @@ -5,8 +5,6 @@ #ifndef _HNS3_FDIR_H_ #define _HNS3_FDIR_H_ -#include - struct hns3_fd_key_cfg { uint8_t key_sel; uint8_t inner_sipv6_word_en; @@ -124,14 +122,6 @@ struct hns3_fd_ad_data { uint16_t rule_id; }; -struct hns3_flow_counter { - LIST_ENTRY(hns3_flow_counter) next; /* Pointer to the next counter. */ - uint32_t shared:1; /* Share counter ID with other flow rules. */ - uint32_t ref_cnt:31; /* Reference counter. */ - uint16_t id; /* Counter ID. */ - uint64_t hits; /* Number of packets matched by the rule. */ -}; - #define HNS3_RULE_FLAG_FDID 0x1 #define HNS3_RULE_FLAG_VF_ID 0x2 #define HNS3_RULE_FLAG_COUNTER 0x4 @@ -173,21 +163,7 @@ struct hns3_fdir_rule_ele { struct hns3_fdir_rule fdir_conf; }; -/* rss filter list structure */ -struct hns3_rss_conf_ele { - TAILQ_ENTRY(hns3_rss_conf_ele) entries; - struct hns3_rss_conf filter_info; -}; - -/* hns3_flow memory list structure */ -struct hns3_flow_mem { - TAILQ_ENTRY(hns3_flow_mem) entries; - struct rte_flow *flow; -}; - TAILQ_HEAD(hns3_fdir_rule_list, hns3_fdir_rule_ele); -TAILQ_HEAD(hns3_rss_filter_list, hns3_rss_conf_ele); -TAILQ_HEAD(hns3_flow_mem_list, hns3_flow_mem); /* * A structure used to define fields of a FDIR related info. @@ -199,11 +175,6 @@ struct hns3_fdir_info { struct hns3_fd_cfg fd_cfg; }; -struct rte_flow { - enum rte_filter_type filter_type; - void *rule; - uint32_t counter_id; -}; struct hns3_adapter; int hns3_init_fd_config(struct hns3_adapter *hns); @@ -213,8 +184,6 @@ int hns3_fdir_filter_program(struct hns3_adapter *hns, struct hns3_fdir_rule *rule, bool del); int hns3_clear_all_fdir_filter(struct hns3_adapter *hns); int hns3_get_count(struct hns3_hw *hw, uint32_t id, uint64_t *value); -void hns3_flow_init(struct rte_eth_dev *dev); -void hns3_flow_uninit(struct rte_eth_dev *dev); int hns3_restore_all_fdir_filter(struct hns3_adapter *hns); #endif /* _HNS3_FDIR_H_ */ diff --git a/drivers/net/hns3/hns3_flow.c b/drivers/net/hns3/hns3_flow.c index da6918fddd..9f2f9cb6cd 100644 --- a/drivers/net/hns3/hns3_flow.c +++ b/drivers/net/hns3/hns3_flow.c @@ -8,6 +8,7 @@ #include "hns3_ethdev.h" #include "hns3_logs.h" +#include "hns3_flow.h" /* Default default keys */ static uint8_t hns3_hash_key[] = { diff --git a/drivers/net/hns3/hns3_flow.h b/drivers/net/hns3/hns3_flow.h new file mode 100644 index 0000000000..2eb451b720 --- /dev/null +++ b/drivers/net/hns3/hns3_flow.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 HiSilicon Limited + */ + +#ifndef _HNS3_FLOW_H_ +#define _HNS3_FLOW_H_ + +#include + +struct hns3_flow_counter { + LIST_ENTRY(hns3_flow_counter) next; /* Pointer to the next counter. */ + uint32_t shared:1; /* Share counter ID with other flow rules. */ + uint32_t ref_cnt:31; /* Reference counter. */ + uint16_t id; /* Counter ID. */ + uint64_t hits; /* Number of packets matched by the rule. */ +}; + +struct rte_flow { + enum rte_filter_type filter_type; + void *rule; + uint32_t counter_id; +}; + +/* rss filter list structure */ +struct hns3_rss_conf_ele { + TAILQ_ENTRY(hns3_rss_conf_ele) entries; + struct hns3_rss_conf filter_info; +}; + +/* hns3_flow memory list structure */ +struct hns3_flow_mem { + TAILQ_ENTRY(hns3_flow_mem) entries; + struct rte_flow *flow; +}; + +TAILQ_HEAD(hns3_rss_filter_list, hns3_rss_conf_ele); +TAILQ_HEAD(hns3_flow_mem_list, hns3_flow_mem); + +int hns3_dev_flow_ops_get(struct rte_eth_dev *dev, + const struct rte_flow_ops **ops); +void hns3_flow_init(struct rte_eth_dev *dev); +void hns3_flow_uninit(struct rte_eth_dev *dev); + +#endif /* _HNS3_FLOW_H_ */ From patchwork Tue Nov 2 03:17:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103385 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D8DFA0C4D; Tue, 2 Nov 2021 04:19:34 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ED2B94069F; Tue, 2 Nov 2021 04:19:33 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 347B44069F for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4Hjw4N6yhvzcZxR; Tue, 2 Nov 2021 11:14:44 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:28 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:27 +0800 Message-ID: <20211102031729.35536-8-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 7/9] net/hns3: remove magic numbers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Huisong Li Removing magic numbers with macros. Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_common.c | 4 ++-- drivers/net/hns3/hns3_common.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c index 5fe0ff5ce7..290999f594 100644 --- a/drivers/net/hns3/hns3_common.c +++ b/drivers/net/hns3/hns3_common.c @@ -54,7 +54,7 @@ hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) RTE_SET_USED(key); - val = strtoull(value, NULL, 16); + val = strtoull(value, NULL, HNS3_CONVERT_TO_HEXADECIMAL); *(uint64_t *)extra_args = val; return 0; @@ -67,7 +67,7 @@ hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args) RTE_SET_USED(key); - val = strtoul(value, NULL, 10); + val = strtoul(value, NULL, HNS3_CONVERT_TO_DECIMAL); if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX) *(uint16_t *)extra_args = val; diff --git a/drivers/net/hns3/hns3_common.h b/drivers/net/hns3/hns3_common.h index 094a0bc5ff..68f9b1b96a 100644 --- a/drivers/net/hns3/hns3_common.h +++ b/drivers/net/hns3/hns3_common.h @@ -9,6 +9,9 @@ #include "hns3_ethdev.h" +#define HNS3_CONVERT_TO_DECIMAL 10 +#define HNS3_CONVERT_TO_HEXADECIMAL 16 + enum { HNS3_IO_FUNC_HINT_NONE = 0, HNS3_IO_FUNC_HINT_VEC, From patchwork Tue Nov 2 03:17:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103389 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F46FA0C4D; Tue, 2 Nov 2021 04:20:00 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C01B41125; Tue, 2 Nov 2021 04:19:38 +0100 (CET) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id 5CDEC410FF for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Hjw7T2v4Cz1DJ4C; Tue, 2 Nov 2021 11:17:25 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:28 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:28 +0800 Message-ID: <20211102031729.35536-9-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 8/9] net/hns3: fix the return value of the function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Huisong Li Fixing the return value of the function to clear static warning. Signed-off-by: Huisong Li Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c index 290999f594..974219f9bf 100644 --- a/drivers/net/hns3/hns3_common.c +++ b/drivers/net/hns3/hns3_common.c @@ -154,10 +154,10 @@ hns3_clock_gettime_ms(void) void hns3_ether_format_addr(char *buf, uint16_t size, const struct rte_ether_addr *ether_addr) { - snprintf(buf, size, "%02X:**:**:**:%02X:%02X", - ether_addr->addr_bytes[0], - ether_addr->addr_bytes[4], - ether_addr->addr_bytes[5]); + (void)snprintf(buf, size, "%02X:**:**:**:%02X:%02X", + ether_addr->addr_bytes[0], + ether_addr->addr_bytes[4], + ether_addr->addr_bytes[5]); } static int From patchwork Tue Nov 2 03:17:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 103394 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FE96A0C4D; Tue, 2 Nov 2021 04:20:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9C9AE41155; Tue, 2 Nov 2021 04:19:43 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 50964410E6 for ; Tue, 2 Nov 2021 04:19:32 +0100 (CET) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Hjw9h5Ldgz90kP; Tue, 2 Nov 2021 11:19:20 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.15; Tue, 2 Nov 2021 11:19:28 +0800 From: "Min Hu (Connor)" To: CC: , Date: Tue, 2 Nov 2021 11:17:29 +0800 Message-ID: <20211102031729.35536-10-humin29@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102031729.35536-1-humin29@huawei.com> References: <20211102031729.35536-1-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 9/9] net/hns3: remove PF/VF duplicate code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng This patch remove PF/VF duplicate code of: 1. get firmware version. 2. get device info. 3. rx interrupt related functions. Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_common.c | 337 +++++++++++++++++++++++++++++- drivers/net/hns3/hns3_common.h | 10 + drivers/net/hns3/hns3_ethdev.c | 313 +-------------------------- drivers/net/hns3/hns3_ethdev.h | 14 +- drivers/net/hns3/hns3_ethdev_vf.c | 325 +--------------------------- drivers/net/hns3/hns3_tm.c | 2 +- 6 files changed, 361 insertions(+), 640 deletions(-) diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c index 974219f9bf..c9797d839d 100644 --- a/drivers/net/hns3/hns3_common.c +++ b/drivers/net/hns3/hns3_common.c @@ -3,9 +3,153 @@ */ #include +#include +#include +#include -#include "hns3_logs.h" #include "hns3_common.h" +#include "hns3_logs.h" +#include "hns3_regs.h" +#include "hns3_rxtx.h" + +int +hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, + size_t fw_size) +{ + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + uint32_t version = hw->fw_version; + int ret; + + ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", + hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, + HNS3_FW_VERSION_BYTE3_S), + hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, + HNS3_FW_VERSION_BYTE2_S), + hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, + HNS3_FW_VERSION_BYTE1_S), + hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, + HNS3_FW_VERSION_BYTE0_S)); + if (ret < 0) + return -EINVAL; + + ret += 1; /* add the size of '\0' */ + if (fw_size < (size_t)ret) + return ret; + else + return 0; +} + +int +hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) +{ + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + uint16_t queue_num = hw->tqps_num; + + /* + * In interrupt mode, 'max_rx_queues' is set based on the number of + * MSI-X interrupt resources of the hardware. + */ + if (hw->data->dev_conf.intr_conf.rxq == 1) + queue_num = hw->intr_tqps_num; + + info->max_rx_queues = queue_num; + info->max_tx_queues = hw->tqps_num; + info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ + info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; + info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; + info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; + info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | + DEV_RX_OFFLOAD_TCP_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM | + DEV_RX_OFFLOAD_SCTP_CKSUM | + DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | + DEV_RX_OFFLOAD_SCATTER | + DEV_RX_OFFLOAD_VLAN_STRIP | + DEV_RX_OFFLOAD_VLAN_FILTER | + DEV_RX_OFFLOAD_RSS_HASH | + DEV_RX_OFFLOAD_TCP_LRO); + info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_TX_OFFLOAD_IPV4_CKSUM | + DEV_TX_OFFLOAD_TCP_CKSUM | + DEV_TX_OFFLOAD_UDP_CKSUM | + DEV_TX_OFFLOAD_SCTP_CKSUM | + DEV_TX_OFFLOAD_MULTI_SEGS | + DEV_TX_OFFLOAD_TCP_TSO | + DEV_TX_OFFLOAD_VXLAN_TNL_TSO | + DEV_TX_OFFLOAD_GRE_TNL_TSO | + DEV_TX_OFFLOAD_GENEVE_TNL_TSO | + DEV_TX_OFFLOAD_MBUF_FAST_FREE | + DEV_TX_OFFLOAD_VLAN_INSERT); + + if (!hw->port_base_vlan_cfg.state) + info->tx_offload_capa |= DEV_TX_OFFLOAD_QINQ_INSERT; + + if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + + if (hns3_dev_get_support(hw, INDEP_TXRX)) + info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | + RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; + + if (hns3_dev_get_support(hw, PTP)) + info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; + + info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = HNS3_MAX_RING_DESC, + .nb_min = HNS3_MIN_RING_DESC, + .nb_align = HNS3_ALIGN_RING_DESC, + }; + + info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = HNS3_MAX_RING_DESC, + .nb_min = HNS3_MIN_RING_DESC, + .nb_align = HNS3_ALIGN_RING_DESC, + .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, + .nb_mtu_seg_max = hw->max_non_tso_bd_num, + }; + + info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, + /* + * If there are no available Rx buffer descriptors, incoming + * packets are always dropped by hardware based on hns3 network + * engine. + */ + .rx_drop_en = 1, + .offloads = 0, + }; + info->default_txconf = (struct rte_eth_txconf) { + .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, + .offloads = 0, + }; + + info->reta_size = hw->rss_ind_tbl_size; + info->hash_key_size = HNS3_RSS_KEY_SIZE; + info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; + + info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; + info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; + info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; + info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; + info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; + info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; + + /* + * Next is the PF/VF difference section. + */ + if (!hns->is_vf) { + info->max_mac_addrs = HNS3_UC_MACADDR_NUM; + info->rx_offload_capa |= DEV_RX_OFFLOAD_KEEP_CRC; + info->speed_capa = hns3_get_speed_capa(hw); + } else { + info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; + } + + return 0; +} static int hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) @@ -68,6 +212,12 @@ hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args) RTE_SET_USED(key); val = strtoul(value, NULL, HNS3_CONVERT_TO_DECIMAL); + + /* + * 500ms is empirical value in process of mailbox communication. If + * the delay value is set to one lower thanthe empirical value, mailbox + * communication may fail. + */ if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX) *(uint16_t *)extra_args = val; @@ -116,6 +266,11 @@ hns3_parse_devargs(struct rte_eth_dev *dev) hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".", HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask); hns->dev_caps_mask = dev_caps_mask; + + if (mbx_time_limit_ms != HNS3_MBX_DEF_TIME_LIMIT_MS) + hns3_warn(hw, "parsed %s = %u.", HNS3_DEVARG_MBX_TIME_LIMIT_MS, + mbx_time_limit_ms); + hns->mbx_time_limit_ms = mbx_time_limit_ms; } void @@ -425,3 +580,183 @@ hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) } } +int +hns3_init_ring_with_vector(struct hns3_hw *hw) +{ + uint16_t vec; + int ret; + int i; + + /* + * In hns3 network engine, vector 0 is always the misc interrupt of this + * function, vector 1~N can be used respectively for the queues of the + * function. Tx and Rx queues with the same number share the interrupt + * vector. In the initialization clearing the all hardware mapping + * relationship configurations between queues and interrupt vectors is + * needed, so some error caused by the residual configurations, such as + * the unexpected Tx interrupt, can be avoid. + */ + vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ + if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) + vec = vec - 1; /* the last interrupt is reserved */ + hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); + for (i = 0; i < hw->intr_tqps_num; i++) { + /* + * Set gap limiter/rate limiter/quanity limiter algorithm + * configuration for interrupt coalesce of queue's interrupt. + */ + hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, + HNS3_TQP_INTR_GL_DEFAULT); + hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, + HNS3_TQP_INTR_GL_DEFAULT); + hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); + /* + * QL(quantity limiter) is not used currently, just set 0 to + * close it. + */ + hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); + + ret = hw->ops.bind_ring_with_vector(hw, vec, false, + HNS3_RING_TYPE_TX, i); + if (ret) { + PMD_INIT_LOG(ERR, "fail to unbind TX ring(%d) with " + "vector: %u, ret=%d", i, vec, ret); + return ret; + } + + ret = hw->ops.bind_ring_with_vector(hw, vec, false, + HNS3_RING_TYPE_RX, i); + if (ret) { + PMD_INIT_LOG(ERR, "fail to unbind RX ring(%d) with " + "vector: %u, ret=%d", i, vec, ret); + return ret; + } + } + + return 0; +} + +int +hns3_map_rx_interrupt(struct rte_eth_dev *dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint16_t base = RTE_INTR_VEC_ZERO_OFFSET; + uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET; + uint32_t intr_vector; + uint16_t q_id; + int ret; + + /* + * hns3 needs a separate interrupt to be used as event interrupt which + * could not be shared with task queue pair, so KERNEL drivers need + * support multiple interrupt vectors. + */ + if (dev->data->dev_conf.intr_conf.rxq == 0 || + !rte_intr_cap_multiple(intr_handle)) + return 0; + + rte_intr_disable(intr_handle); + intr_vector = hw->used_rx_queues; + /* creates event fd for each intr vector when MSIX is used */ + if (rte_intr_efd_enable(intr_handle, intr_vector)) + return -EINVAL; + + /* Allocate vector list */ + if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", + hw->used_rx_queues)) { + hns3_err(hw, "failed to allocate %u rx_queues intr_vec", + hw->used_rx_queues); + ret = -ENOMEM; + goto alloc_intr_vec_error; + } + + if (rte_intr_allow_others(intr_handle)) { + vec = RTE_INTR_VEC_RXTX_OFFSET; + base = RTE_INTR_VEC_RXTX_OFFSET; + } + + for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { + ret = hw->ops.bind_ring_with_vector(hw, vec, true, + HNS3_RING_TYPE_RX, q_id); + if (ret) + goto bind_vector_error; + + if (rte_intr_vec_list_index_set(intr_handle, q_id, vec)) + goto bind_vector_error; + /* + * If there are not enough efds (e.g. not enough interrupt), + * remaining queues will be bond to the last interrupt. + */ + if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1) + vec++; + } + rte_intr_enable(intr_handle); + return 0; + +bind_vector_error: + rte_intr_vec_list_free(intr_handle); +alloc_intr_vec_error: + rte_intr_efd_disable(intr_handle); + return ret; +} + +void +hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; + uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; + uint16_t q_id; + + if (dev->data->dev_conf.intr_conf.rxq == 0) + return; + + /* unmap the ring with vector */ + if (rte_intr_allow_others(intr_handle)) { + vec = RTE_INTR_VEC_RXTX_OFFSET; + base = RTE_INTR_VEC_RXTX_OFFSET; + } + if (rte_intr_dp_is_en(intr_handle)) { + for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { + (void)hw->ops.bind_ring_with_vector(hw, vec, false, + HNS3_RING_TYPE_RX, + q_id); + if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1) + vec++; + } + } + /* Clean datapath event and queue/vec mapping */ + rte_intr_efd_disable(intr_handle); + rte_intr_vec_list_free(intr_handle); +} + +int +hns3_restore_rx_interrupt(struct hns3_hw *hw) +{ + struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = pci_dev->intr_handle; + uint16_t q_id; + int ret; + + if (dev->data->dev_conf.intr_conf.rxq == 0) + return 0; + + if (rte_intr_dp_is_en(intr_handle)) { + for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { + ret = hw->ops.bind_ring_with_vector(hw, + rte_intr_vec_list_index_get(intr_handle, + q_id), + true, HNS3_RING_TYPE_RX, q_id); + if (ret) + return ret; + } + } + + return 0; +} \ No newline at end of file diff --git a/drivers/net/hns3/hns3_common.h b/drivers/net/hns3/hns3_common.h index 68f9b1b96a..0dbb1c0413 100644 --- a/drivers/net/hns3/hns3_common.h +++ b/drivers/net/hns3/hns3_common.h @@ -30,6 +30,11 @@ enum { #define MSEC_PER_SEC 1000L #define USEC_PER_MSEC 1000L +int hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, + size_t fw_size); +int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, + struct rte_eth_dev_info *info); + void hns3_clock_gettime(struct timeval *tv); uint64_t hns3_clock_calctime_ms(struct timeval *tv); uint64_t hns3_clock_gettime_ms(void); @@ -48,4 +53,9 @@ int hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, void hns3_ether_format_addr(char *buf, uint16_t size, const struct rte_ether_addr *ether_addr); +int hns3_init_ring_with_vector(struct hns3_hw *hw); +int hns3_map_rx_interrupt(struct rte_eth_dev *dev); +void hns3_unmap_rx_interrupt(struct rte_eth_dev *dev); +int hns3_restore_rx_interrupt(struct hns3_hw *hw); + #endif /* _HNS3_COMMON_H_ */ diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 2f4beacb87..847e660f44 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -1929,62 +1929,6 @@ hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, return 0; } -static int -hns3_init_ring_with_vector(struct hns3_hw *hw) -{ - uint16_t vec; - int ret; - int i; - - /* - * In hns3 network engine, vector 0 is always the misc interrupt of this - * function, vector 1~N can be used respectively for the queues of the - * function. Tx and Rx queues with the same number share the interrupt - * vector. In the initialization clearing the all hardware mapping - * relationship configurations between queues and interrupt vectors is - * needed, so some error caused by the residual configurations, such as - * the unexpected Tx interrupt, can be avoid. - */ - vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ - if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) - vec = vec - 1; /* the last interrupt is reserved */ - hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); - for (i = 0; i < hw->intr_tqps_num; i++) { - /* - * Set gap limiter/rate limiter/quanity limiter algorithm - * configuration for interrupt coalesce of queue's interrupt. - */ - hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, - HNS3_TQP_INTR_GL_DEFAULT); - hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, - HNS3_TQP_INTR_GL_DEFAULT); - hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); - /* - * QL(quantity limiter) is not used currently, just set 0 to - * close it. - */ - hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); - - ret = hns3_bind_ring_with_vector(hw, vec, false, - HNS3_RING_TYPE_TX, i); - if (ret) { - PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " - "vector: %u, ret=%d", i, vec, ret); - return ret; - } - - ret = hns3_bind_ring_with_vector(hw, vec, false, - HNS3_RING_TYPE_RX, i); - if (ret) { - PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " - "vector: %u, ret=%d", i, vec, ret); - return ret; - } - } - - return 0; -} - static int hns3_setup_dcb(struct rte_eth_dev *dev) { @@ -2255,7 +2199,7 @@ hns3_get_firber_port_speed_capa(uint32_t supported_speed) return speed_capa; } -static uint32_t +uint32_t hns3_get_speed_capa(struct hns3_hw *hw) { struct hns3_mac *mac = &hw->mac; @@ -2274,134 +2218,6 @@ hns3_get_speed_capa(struct hns3_hw *hw) return speed_capa; } -int -hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) -{ - struct hns3_adapter *hns = eth_dev->data->dev_private; - struct hns3_hw *hw = &hns->hw; - uint16_t queue_num = hw->tqps_num; - - /* - * In interrupt mode, 'max_rx_queues' is set based on the number of - * MSI-X interrupt resources of the hardware. - */ - if (hw->data->dev_conf.intr_conf.rxq == 1) - queue_num = hw->intr_tqps_num; - - info->max_rx_queues = queue_num; - info->max_tx_queues = hw->tqps_num; - info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ - info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; - info->max_mac_addrs = HNS3_UC_MACADDR_NUM; - info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; - info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; - info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | - RTE_ETH_RX_OFFLOAD_TCP_CKSUM | - RTE_ETH_RX_OFFLOAD_UDP_CKSUM | - RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | - RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | - RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | - RTE_ETH_RX_OFFLOAD_KEEP_CRC | - RTE_ETH_RX_OFFLOAD_SCATTER | - RTE_ETH_RX_OFFLOAD_VLAN_STRIP | - RTE_ETH_RX_OFFLOAD_VLAN_FILTER | - RTE_ETH_RX_OFFLOAD_RSS_HASH | - RTE_ETH_RX_OFFLOAD_TCP_LRO); - info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | - RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | - RTE_ETH_TX_OFFLOAD_TCP_CKSUM | - RTE_ETH_TX_OFFLOAD_UDP_CKSUM | - RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | - RTE_ETH_TX_OFFLOAD_MULTI_SEGS | - RTE_ETH_TX_OFFLOAD_TCP_TSO | - RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | - RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | - RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | - RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | - hns3_txvlan_cap_get(hw)); - - if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM)) - info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM; - - if (hns3_dev_get_support(hw, INDEP_TXRX)) - info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | - RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; - - if (hns3_dev_get_support(hw, PTP)) - info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP; - - info->rx_desc_lim = (struct rte_eth_desc_lim) { - .nb_max = HNS3_MAX_RING_DESC, - .nb_min = HNS3_MIN_RING_DESC, - .nb_align = HNS3_ALIGN_RING_DESC, - }; - - info->tx_desc_lim = (struct rte_eth_desc_lim) { - .nb_max = HNS3_MAX_RING_DESC, - .nb_min = HNS3_MIN_RING_DESC, - .nb_align = HNS3_ALIGN_RING_DESC, - .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, - .nb_mtu_seg_max = hw->max_non_tso_bd_num, - }; - - info->speed_capa = hns3_get_speed_capa(hw); - info->default_rxconf = (struct rte_eth_rxconf) { - .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, - /* - * If there are no available Rx buffer descriptors, incoming - * packets are always dropped by hardware based on hns3 network - * engine. - */ - .rx_drop_en = 1, - .offloads = 0, - }; - info->default_txconf = (struct rte_eth_txconf) { - .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, - .offloads = 0, - }; - - info->reta_size = hw->rss_ind_tbl_size; - info->hash_key_size = HNS3_RSS_KEY_SIZE; - info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; - - info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; - info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; - info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; - info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; - info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; - info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; - - return 0; -} - -static int -hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, - size_t fw_size) -{ - struct hns3_adapter *hns = eth_dev->data->dev_private; - struct hns3_hw *hw = &hns->hw; - uint32_t version = hw->fw_version; - int ret; - - ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", - hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, - HNS3_FW_VERSION_BYTE3_S), - hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, - HNS3_FW_VERSION_BYTE2_S), - hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, - HNS3_FW_VERSION_BYTE1_S), - hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, - HNS3_FW_VERSION_BYTE0_S)); - if (ret < 0) - return -EINVAL; - - ret += 1; /* add the size of '\0' */ - if (fw_size < (size_t)ret) - return ret; - else - return 0; -} - static int hns3_update_port_link_info(struct rte_eth_dev *eth_dev) { @@ -5280,98 +5096,6 @@ hns3_do_start(struct hns3_adapter *hns, bool reset_queue) return ret; } -static int -hns3_map_rx_interrupt(struct rte_eth_dev *dev) -{ - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev->intr_handle; - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint16_t base = RTE_INTR_VEC_ZERO_OFFSET; - uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET; - uint32_t intr_vector; - uint16_t q_id; - int ret; - - /* - * hns3 needs a separate interrupt to be used as event interrupt which - * could not be shared with task queue pair, so KERNEL drivers need - * support multiple interrupt vectors. - */ - if (dev->data->dev_conf.intr_conf.rxq == 0 || - !rte_intr_cap_multiple(intr_handle)) - return 0; - - rte_intr_disable(intr_handle); - intr_vector = hw->used_rx_queues; - /* creates event fd for each intr vector when MSIX is used */ - if (rte_intr_efd_enable(intr_handle, intr_vector)) - return -EINVAL; - - /* Allocate vector list */ - if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", - hw->used_rx_queues)) { - hns3_err(hw, "failed to allocate %u rx_queues intr_vec", - hw->used_rx_queues); - ret = -ENOMEM; - goto alloc_intr_vec_error; - } - - if (rte_intr_allow_others(intr_handle)) { - vec = RTE_INTR_VEC_RXTX_OFFSET; - base = RTE_INTR_VEC_RXTX_OFFSET; - } - - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - ret = hns3_bind_ring_with_vector(hw, vec, true, - HNS3_RING_TYPE_RX, q_id); - if (ret) - goto bind_vector_error; - - if (rte_intr_vec_list_index_set(intr_handle, q_id, vec)) - goto bind_vector_error; - /* - * If there are not enough efds (e.g. not enough interrupt), - * remaining queues will be bond to the last interrupt. - */ - if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1) - vec++; - } - rte_intr_enable(intr_handle); - return 0; - -bind_vector_error: - rte_intr_vec_list_free(intr_handle); -alloc_intr_vec_error: - rte_intr_efd_disable(intr_handle); - return ret; -} - -static int -hns3_restore_rx_interrupt(struct hns3_hw *hw) -{ - struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev->intr_handle; - uint16_t q_id; - int ret; - - if (dev->data->dev_conf.intr_conf.rxq == 0) - return 0; - - if (rte_intr_dp_is_en(intr_handle)) { - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - ret = hns3_bind_ring_with_vector(hw, - rte_intr_vec_list_index_get(intr_handle, - q_id), - true, HNS3_RING_TYPE_RX, q_id); - if (ret) - return ret; - } - } - - return 0; -} - static void hns3_restore_filter(struct rte_eth_dev *dev) { @@ -5502,40 +5226,6 @@ hns3_do_stop(struct hns3_adapter *hns) return 0; } -static void -hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) -{ - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev->intr_handle; - struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_hw *hw = &hns->hw; - uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; - uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; - uint16_t q_id; - - if (dev->data->dev_conf.intr_conf.rxq == 0) - return; - - /* unmap the ring with vector */ - if (rte_intr_allow_others(intr_handle)) { - vec = RTE_INTR_VEC_RXTX_OFFSET; - base = RTE_INTR_VEC_RXTX_OFFSET; - } - if (rte_intr_dp_is_en(intr_handle)) { - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - (void)hns3_bind_ring_with_vector(hw, vec, false, - HNS3_RING_TYPE_RX, - q_id); - if (vec < base + rte_intr_nb_efd_get(intr_handle) - - 1) - vec++; - } - } - /* Clean datapath event and queue/vec mapping */ - rte_intr_efd_disable(intr_handle); - rte_intr_vec_list_free(intr_handle); -} - static int hns3_dev_stop(struct rte_eth_dev *dev) { @@ -6926,6 +6616,7 @@ hns3_init_hw_ops(struct hns3_hw *hw) hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr; hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr; hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr; + hw->ops.bind_ring_with_vector = hns3_bind_ring_with_vector; } static int diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index a28c7c262b..55518a913d 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -437,6 +437,9 @@ struct hns3_hw_ops { struct rte_ether_addr *mac_addr); int (*del_uc_mac_addr)(struct hns3_hw *hw, struct rte_ether_addr *mac_addr); + int (*bind_ring_with_vector)(struct hns3_hw *hw, uint16_t vector_id, + bool en, enum hns3_ring_type queue_type, + uint16_t queue_id); }; #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0 @@ -1038,8 +1041,6 @@ int hns3_buffer_alloc(struct hns3_hw *hw); bool hns3_is_reset_pending(struct hns3_adapter *hns); bool hns3vf_is_reset_pending(struct hns3_adapter *hns); void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query); -int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, - struct rte_eth_dev_info *info); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported); @@ -1071,13 +1072,4 @@ is_reset_pending(struct hns3_adapter *hns) return ret; } -static inline uint64_t -hns3_txvlan_cap_get(struct hns3_hw *hw) -{ - if (hw->port_base_vlan_cfg.state) - return RTE_ETH_TX_OFFLOAD_VLAN_INSERT; - else - return RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT; -} - #endif /* _HNS3_ETHDEV_H_ */ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 7e60090fd3..d8a99693e0 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -422,7 +422,7 @@ hns3vf_restore_promisc(struct hns3_adapter *hns) } static int -hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, +hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool mmap, enum hns3_ring_type queue_type, uint16_t queue_id) { @@ -434,7 +434,7 @@ hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, memset(&bind_msg, 0, sizeof(bind_msg)); code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR : HNS3_MBX_UNMAP_RING_TO_VECTOR; - bind_msg.vector_id = vector_id; + bind_msg.vector_id = (uint8_t)vector_id; if (queue_type == HNS3_RING_TYPE_RX) bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX; @@ -454,62 +454,6 @@ hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, return ret; } -static int -hns3vf_init_ring_with_vector(struct hns3_hw *hw) -{ - uint16_t vec; - int ret; - int i; - - /* - * In hns3 network engine, vector 0 is always the misc interrupt of this - * function, vector 1~N can be used respectively for the queues of the - * function. Tx and Rx queues with the same number share the interrupt - * vector. In the initialization clearing the all hardware mapping - * relationship configurations between queues and interrupt vectors is - * needed, so some error caused by the residual configurations, such as - * the unexpected Tx interrupt, can be avoid. - */ - vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ - if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) - vec = vec - 1; /* the last interrupt is reserved */ - hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); - for (i = 0; i < hw->intr_tqps_num; i++) { - /* - * Set gap limiter/rate limiter/quanity limiter algorithm - * configuration for interrupt coalesce of queue's interrupt. - */ - hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, - HNS3_TQP_INTR_GL_DEFAULT); - hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, - HNS3_TQP_INTR_GL_DEFAULT); - hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); - /* - * QL(quantity limiter) is not used currently, just set 0 to - * close it. - */ - hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); - - ret = hns3vf_bind_ring_with_vector(hw, vec, false, - HNS3_RING_TYPE_TX, i); - if (ret) { - PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with " - "vector: %u, ret=%d", i, vec, ret); - return ret; - } - - ret = hns3vf_bind_ring_with_vector(hw, vec, false, - HNS3_RING_TYPE_RX, i); - if (ret) { - PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with " - "vector: %u, ret=%d", i, vec, ret); - return ret; - } - } - - return 0; -} - static int hns3vf_dev_configure(struct rte_eth_dev *dev) { @@ -649,102 +593,6 @@ hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) return 0; } -static int -hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) -{ - struct hns3_adapter *hns = eth_dev->data->dev_private; - struct hns3_hw *hw = &hns->hw; - uint16_t q_num = hw->tqps_num; - - /* - * In interrupt mode, 'max_rx_queues' is set based on the number of - * MSI-X interrupt resources of the hardware. - */ - if (hw->data->dev_conf.intr_conf.rxq == 1) - q_num = hw->intr_tqps_num; - - info->max_rx_queues = q_num; - info->max_tx_queues = hw->tqps_num; - info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ - info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; - info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; - info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; - info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; - - info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | - RTE_ETH_RX_OFFLOAD_UDP_CKSUM | - RTE_ETH_RX_OFFLOAD_TCP_CKSUM | - RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | - RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | - RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | - RTE_ETH_RX_OFFLOAD_SCATTER | - RTE_ETH_RX_OFFLOAD_VLAN_STRIP | - RTE_ETH_RX_OFFLOAD_VLAN_FILTER | - RTE_ETH_RX_OFFLOAD_RSS_HASH | - RTE_ETH_RX_OFFLOAD_TCP_LRO); - info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | - RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | - RTE_ETH_TX_OFFLOAD_TCP_CKSUM | - RTE_ETH_TX_OFFLOAD_UDP_CKSUM | - RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | - RTE_ETH_TX_OFFLOAD_MULTI_SEGS | - RTE_ETH_TX_OFFLOAD_TCP_TSO | - RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | - RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | - RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | - RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | - hns3_txvlan_cap_get(hw)); - - if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM)) - info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM; - - if (hns3_dev_get_support(hw, INDEP_TXRX)) - info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | - RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; - - info->rx_desc_lim = (struct rte_eth_desc_lim) { - .nb_max = HNS3_MAX_RING_DESC, - .nb_min = HNS3_MIN_RING_DESC, - .nb_align = HNS3_ALIGN_RING_DESC, - }; - - info->tx_desc_lim = (struct rte_eth_desc_lim) { - .nb_max = HNS3_MAX_RING_DESC, - .nb_min = HNS3_MIN_RING_DESC, - .nb_align = HNS3_ALIGN_RING_DESC, - .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, - .nb_mtu_seg_max = hw->max_non_tso_bd_num, - }; - - info->default_rxconf = (struct rte_eth_rxconf) { - .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, - /* - * If there are no available Rx buffer descriptors, incoming - * packets are always dropped by hardware based on hns3 network - * engine. - */ - .rx_drop_en = 1, - .offloads = 0, - }; - info->default_txconf = (struct rte_eth_txconf) { - .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, - .offloads = 0, - }; - - info->reta_size = hw->rss_ind_tbl_size; - info->hash_key_size = HNS3_RSS_KEY_SIZE; - info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; - - info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; - info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; - info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; - info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; - info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; - info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; - - return 0; -} - static void hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr) { @@ -1633,7 +1481,7 @@ hns3vf_init_hardware(struct hns3_adapter *hns) * some error caused by the residual configurations, such as the * unexpected interrupt, can be avoid. */ - ret = hns3vf_init_ring_with_vector(hw); + ret = hns3_init_ring_with_vector(hw); if (ret) { PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); goto err_init_hardware; @@ -1820,41 +1668,6 @@ hns3vf_do_stop(struct hns3_adapter *hns) return 0; } -static void -hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev) -{ - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev->intr_handle; - uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; - uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; - uint16_t q_id; - - if (dev->data->dev_conf.intr_conf.rxq == 0) - return; - - /* unmap the ring with vector */ - if (rte_intr_allow_others(intr_handle)) { - vec = RTE_INTR_VEC_RXTX_OFFSET; - base = RTE_INTR_VEC_RXTX_OFFSET; - } - if (rte_intr_dp_is_en(intr_handle)) { - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - (void)hns3vf_bind_ring_with_vector(hw, vec, false, - HNS3_RING_TYPE_RX, - q_id); - if (vec < base + rte_intr_nb_efd_get(intr_handle) - - 1) - vec++; - } - } - /* Clean datapath event and queue/vec mapping */ - rte_intr_efd_disable(intr_handle); - - /* Cleanup vector list */ - rte_intr_vec_list_free(intr_handle); -} - static int hns3vf_dev_stop(struct rte_eth_dev *dev) { @@ -1876,7 +1689,7 @@ hns3vf_dev_stop(struct rte_eth_dev *dev) if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { hns3_stop_tqps(hw); hns3vf_do_stop(hns); - hns3vf_unmap_rx_interrupt(dev); + hns3_unmap_rx_interrupt(dev); hw->adapter_state = HNS3_NIC_CONFIGURED; } hns3_rx_scattered_reset(dev); @@ -1917,34 +1730,6 @@ hns3vf_dev_close(struct rte_eth_dev *eth_dev) return ret; } -static int -hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, - size_t fw_size) -{ - struct hns3_adapter *hns = eth_dev->data->dev_private; - struct hns3_hw *hw = &hns->hw; - uint32_t version = hw->fw_version; - int ret; - - ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", - hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, - HNS3_FW_VERSION_BYTE3_S), - hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, - HNS3_FW_VERSION_BYTE2_S), - hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, - HNS3_FW_VERSION_BYTE1_S), - hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, - HNS3_FW_VERSION_BYTE0_S)); - if (ret < 0) - return -EINVAL; - - ret += 1; /* add the size of '\0' */ - if (fw_size < (size_t)ret) - return ret; - else - return 0; -} - static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete) @@ -2006,99 +1791,6 @@ hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue) return ret; } -static int -hns3vf_map_rx_interrupt(struct rte_eth_dev *dev) -{ - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev->intr_handle; - struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; - uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; - uint32_t intr_vector; - uint16_t q_id; - int ret; - - /* - * hns3 needs a separate interrupt to be used as event interrupt which - * could not be shared with task queue pair, so KERNEL drivers need - * support multiple interrupt vectors. - */ - if (dev->data->dev_conf.intr_conf.rxq == 0 || - !rte_intr_cap_multiple(intr_handle)) - return 0; - - rte_intr_disable(intr_handle); - intr_vector = hw->used_rx_queues; - /* It creates event fd for each intr vector when MSIX is used */ - if (rte_intr_efd_enable(intr_handle, intr_vector)) - return -EINVAL; - - /* Allocate vector list */ - if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", - hw->used_rx_queues)) { - hns3_err(hw, "Failed to allocate %u rx_queues" - " intr_vec", hw->used_rx_queues); - ret = -ENOMEM; - goto vf_alloc_intr_vec_error; - } - - if (rte_intr_allow_others(intr_handle)) { - vec = RTE_INTR_VEC_RXTX_OFFSET; - base = RTE_INTR_VEC_RXTX_OFFSET; - } - - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - ret = hns3vf_bind_ring_with_vector(hw, vec, true, - HNS3_RING_TYPE_RX, q_id); - if (ret) - goto vf_bind_vector_error; - - if (rte_intr_vec_list_index_set(intr_handle, q_id, vec)) - goto vf_bind_vector_error; - - /* - * If there are not enough efds (e.g. not enough interrupt), - * remaining queues will be bond to the last interrupt. - */ - if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1) - vec++; - } - rte_intr_enable(intr_handle); - return 0; - -vf_bind_vector_error: - rte_intr_vec_list_free(intr_handle); -vf_alloc_intr_vec_error: - rte_intr_efd_disable(intr_handle); - return ret; -} - -static int -hns3vf_restore_rx_interrupt(struct hns3_hw *hw) -{ - struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev->intr_handle; - uint16_t q_id; - int ret; - - if (dev->data->dev_conf.intr_conf.rxq == 0) - return 0; - - if (rte_intr_dp_is_en(intr_handle)) { - for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { - ret = hns3vf_bind_ring_with_vector(hw, - rte_intr_vec_list_index_get(intr_handle, - q_id), - true, HNS3_RING_TYPE_RX, q_id); - if (ret) - return ret; - } - } - - return 0; -} - static void hns3vf_restore_filter(struct rte_eth_dev *dev) { @@ -2124,7 +1816,7 @@ hns3vf_dev_start(struct rte_eth_dev *dev) rte_spinlock_unlock(&hw->lock); return ret; } - ret = hns3vf_map_rx_interrupt(dev); + ret = hns3_map_rx_interrupt(dev); if (ret) goto map_rx_inter_err; @@ -2441,7 +2133,7 @@ hns3vf_restore_conf(struct hns3_adapter *hns) if (ret) goto err_vlan_table; - ret = hns3vf_restore_rx_interrupt(hw); + ret = hns3_restore_rx_interrupt(hw); if (ret) goto err_vlan_table; @@ -2615,8 +2307,8 @@ static const struct eth_dev_ops hns3vf_eth_dev_ops = { .xstats_reset = hns3_dev_xstats_reset, .xstats_get_by_id = hns3_dev_xstats_get_by_id, .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, - .dev_infos_get = hns3vf_dev_infos_get, - .fw_version_get = hns3vf_fw_version_get, + .dev_infos_get = hns3_dev_infos_get, + .fw_version_get = hns3_fw_version_get, .rx_queue_setup = hns3_rx_queue_setup, .tx_queue_setup = hns3_tx_queue_setup, .rx_queue_release = hns3_dev_rx_queue_release, @@ -2665,6 +2357,7 @@ hns3vf_init_hw_ops(struct hns3_hw *hw) hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr; hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr; hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr; + hw->ops.bind_ring_with_vector = hns3vf_bind_ring_with_vector; } static int diff --git a/drivers/net/hns3/hns3_tm.c b/drivers/net/hns3/hns3_tm.c index 44b607af7a..e1089b6bd0 100644 --- a/drivers/net/hns3/hns3_tm.c +++ b/drivers/net/hns3/hns3_tm.c @@ -4,7 +4,7 @@ #include -#include "hns3_ethdev.h" +#include "hns3_common.h" #include "hns3_dcb.h" #include "hns3_logs.h" #include "hns3_tm.h"