From patchwork Wed Oct 20 08:45:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102394 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 997A1A0C43; Wed, 20 Oct 2021 10:46:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D733F411B6; Wed, 20 Oct 2021 10:46:03 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id EB1DB411B6 for ; Wed, 20 Oct 2021 10:46:01 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 65DFBED1; Wed, 20 Oct 2021 01:46:01 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 91E943F70D; Wed, 20 Oct 2021 01:45:59 -0700 (PDT) From: Feifei Wang To: Ruifeng Wang Cc: konstantin.ananyev@intel.com, dev@dpdk.org, nd@arm.com, Feifei Wang Date: Wed, 20 Oct 2021 16:45:19 +0800 Message-Id: <20211020084523.1309177-2-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020084523.1309177-1-feifei.wang2@arm.com> References: <20210926063302.1541193-1-feifei.wang2@arm.com> <20211020084523.1309177-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 1/5] eal: add new definitions for wait scheme X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introduce macros as generic interface for address monitoring. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/arm/include/rte_pause_64.h | 126 ++++++++++++++++------------ lib/eal/include/generic/rte_pause.h | 32 +++++++ 2 files changed, 104 insertions(+), 54 deletions(-) diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h index e87d10b8cc..23954c2de2 100644 --- a/lib/eal/arm/include/rte_pause_64.h +++ b/lib/eal/arm/include/rte_pause_64.h @@ -31,20 +31,12 @@ static inline void rte_pause(void) /* Put processor into low power WFE(Wait For Event) state. */ #define __WFE() { asm volatile("wfe" : : : "memory"); } -static __rte_always_inline void -rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, - int memorder) -{ - uint16_t value; - - assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - - /* - * Atomic exclusive load from addr, it returns the 16-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ +/* + * Atomic exclusive load from addr, it returns the 16-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and a event is generated + * implicitly to exit WFE. + */ #define __LOAD_EXC_16(src, dst, memorder) { \ if (memorder == __ATOMIC_RELAXED) { \ asm volatile("ldxrh %w[tmp], [%x[addr]]" \ @@ -58,6 +50,52 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, : "memory"); \ } } +/* + * Atomic exclusive load from addr, it returns the 32-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and a event is generated + * implicitly to exit WFE. + */ +#define __LOAD_EXC_32(src, dst, memorder) { \ + if (memorder == __ATOMIC_RELAXED) { \ + asm volatile("ldxr %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } else { \ + asm volatile("ldaxr %w[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } } + +/* + * Atomic exclusive load from addr, it returns the 64-bit content of + * *addr while making it 'monitored', when it is written by someone + * else, the 'monitored' state is cleared and a event is generated + * implicitly to exit WFE. + */ +#define __LOAD_EXC_64(src, dst, memorder) { \ + if (memorder == __ATOMIC_RELAXED) { \ + asm volatile("ldxr %x[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } else { \ + asm volatile("ldaxr %x[tmp], [%x[addr]]" \ + : [tmp] "=&r" (dst) \ + : [addr] "r"(src) \ + : "memory"); \ + } } + +static __rte_always_inline void +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, + int memorder) +{ + uint16_t value; + + assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); + __LOAD_EXC_16(addr, value, memorder) if (value != expected) { __SEVL() @@ -66,7 +104,6 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, __LOAD_EXC_16(addr, value, memorder) } while (value != expected); } -#undef __LOAD_EXC_16 } static __rte_always_inline void @@ -77,25 +114,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - /* - * Atomic exclusive load from addr, it returns the 32-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ -#define __LOAD_EXC_32(src, dst, memorder) { \ - if (memorder == __ATOMIC_RELAXED) { \ - asm volatile("ldxr %w[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } else { \ - asm volatile("ldaxr %w[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } } - __LOAD_EXC_32(addr, value, memorder) if (value != expected) { __SEVL() @@ -104,7 +122,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, __LOAD_EXC_32(addr, value, memorder) } while (value != expected); } -#undef __LOAD_EXC_32 } static __rte_always_inline void @@ -115,25 +132,6 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, assert(memorder == __ATOMIC_ACQUIRE || memorder == __ATOMIC_RELAXED); - /* - * Atomic exclusive load from addr, it returns the 64-bit content of - * *addr while making it 'monitored',when it is written by someone - * else, the 'monitored' state is cleared and a event is generated - * implicitly to exit WFE. - */ -#define __LOAD_EXC_64(src, dst, memorder) { \ - if (memorder == __ATOMIC_RELAXED) { \ - asm volatile("ldxr %x[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } else { \ - asm volatile("ldaxr %x[tmp], [%x[addr]]" \ - : [tmp] "=&r" (dst) \ - : [addr] "r"(src) \ - : "memory"); \ - } } - __LOAD_EXC_64(addr, value, memorder) if (value != expected) { __SEVL() @@ -143,6 +141,26 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, } while (value != expected); } } + +#define rte_wait_event(addr, mask, expected, cond, memorder, size) \ +do { \ + RTE_BUILD_BUG_ON(!__builtin_constant_p(memorder)); \ + RTE_BUILD_BUG_ON(memorder != __ATOMIC_ACQUIRE && \ + memorder != __ATOMIC_RELAXED); \ + RTE_BUILD_BUG_ON(size != 16 && size != 32 && size != 64); \ + uint##size_t value; \ + __LOAD_EXC_##size(addr, value, memorder) \ + if ((value & mask) cond expected) { \ + __SEVL() \ + do { \ + __WFE() \ + __LOAD_EXC_##size(addr, value, memorder) \ + } while ((value & mask) cond expected); \ + } \ +} while (0) + +#undef __LOAD_EXC_16 +#undef __LOAD_EXC_32 #undef __LOAD_EXC_64 #undef __SEVL diff --git a/lib/eal/include/generic/rte_pause.h b/lib/eal/include/generic/rte_pause.h index 668ee4a184..20a5d2a9fd 100644 --- a/lib/eal/include/generic/rte_pause.h +++ b/lib/eal/include/generic/rte_pause.h @@ -111,6 +111,38 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uint64_t expected, while (__atomic_load_n(addr, memorder) != expected) rte_pause(); } + +/* + * Wait until *addr breaks the condition, with a relaxed memory + * ordering model meaning the loads around this API can be reordered. + * + * @param addr + * A pointer to the memory location. + * @param mask + * A mask of value bits in interest. + * @param expected + * A 16-bit expected value to be in the memory location. + * @param cond + * A symbol representing the condition (==, !=). + * @param memorder + * Two different memory orders that can be specified: + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to + * C++11 memory orders with the same names, see the C++11 standard or + * the GCC wiki on atomic synchronization for detailed definition. + * @param size + * The bit size of *addr: + * It is used for arm architecture to choose load instructions, + * and the optional value is 16, 32 and 64. + */ +#define rte_wait_event(addr, mask, expected, cond, memorder, size) \ +do { \ + RTE_BUILD_BUG_ON(!__builtin_constant_p(memorder)); \ + RTE_BUILD_BUG_ON(memorder != __ATOMIC_ACQUIRE && \ + memorder != __ATOMIC_RELAXED); \ + RTE_BUILD_BUG_ON(size != 16 && size != 32 && size != 64); \ + while ((__atomic_load_n(addr, memorder) & mask) cond expected) \ + rte_pause(); \ +} while (0) #endif #endif /* _RTE_PAUSE_H_ */ From patchwork Wed Oct 20 08:45:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102395 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9426BA0C43; Wed, 20 Oct 2021 10:46:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EF76C411C0; Wed, 20 Oct 2021 10:46:04 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 681FE411BE for ; Wed, 20 Oct 2021 10:46:04 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D37BD106F; Wed, 20 Oct 2021 01:46:03 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 01FC83F70D; Wed, 20 Oct 2021 01:46:01 -0700 (PDT) From: Feifei Wang To: Cc: konstantin.ananyev@intel.com, dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Wed, 20 Oct 2021 16:45:20 +0800 Message-Id: <20211020084523.1309177-3-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020084523.1309177-1-feifei.wang2@arm.com> References: <20210926063302.1541193-1-feifei.wang2@arm.com> <20211020084523.1309177-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 2/5] eal: use wait event for read pflock X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for read pflock update, use wait event scheme for this case. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/include/generic/rte_pflock.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/lib/eal/include/generic/rte_pflock.h b/lib/eal/include/generic/rte_pflock.h index e57c179ef2..c1c230d131 100644 --- a/lib/eal/include/generic/rte_pflock.h +++ b/lib/eal/include/generic/rte_pflock.h @@ -121,9 +121,7 @@ rte_pflock_read_lock(rte_pflock_t *pf) return; /* Wait for current write phase to complete. */ - while ((__atomic_load_n(&pf->rd.in, __ATOMIC_ACQUIRE) - & RTE_PFLOCK_WBITS) == w) - rte_pause(); + rte_wait_event(&pf->rd.in, RTE_PFLOCK_WBITS, w, ==, __ATOMIC_ACQUIRE, 16); } /** From patchwork Wed Oct 20 08:45:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102396 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C2A9DA0C43; Wed, 20 Oct 2021 10:46:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 47E98411BF; Wed, 20 Oct 2021 10:46:08 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 0DA0540142 for ; Wed, 20 Oct 2021 10:46:07 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C626ED1; Wed, 20 Oct 2021 01:46:06 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 703ED3F70D; Wed, 20 Oct 2021 01:46:04 -0700 (PDT) From: Feifei Wang To: Honnappa Nagarahalli Cc: konstantin.ananyev@intel.com, dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Wed, 20 Oct 2021 16:45:21 +0800 Message-Id: <20211020084523.1309177-4-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020084523.1309177-1-feifei.wang2@arm.com> References: <20210926063302.1541193-1-feifei.wang2@arm.com> <20211020084523.1309177-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 3/5] eal: use wait event scheme for mcslock X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for mcslock to be updated, use wait event scheme for this case. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/eal/include/generic/rte_mcslock.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/lib/eal/include/generic/rte_mcslock.h b/lib/eal/include/generic/rte_mcslock.h index 34f33c64a5..08137c361b 100644 --- a/lib/eal/include/generic/rte_mcslock.h +++ b/lib/eal/include/generic/rte_mcslock.h @@ -116,8 +116,13 @@ rte_mcslock_unlock(rte_mcslock_t **msl, rte_mcslock_t *me) /* More nodes added to the queue by other CPUs. * Wait until the next pointer is set. */ - while (__atomic_load_n(&me->next, __ATOMIC_RELAXED) == NULL) - rte_pause(); +#ifdef RTE_ARCH_32 + rte_wait_event((uint32_t *)&me->next, UINT32_MAX, 0, ==, + __ATOMIC_RELAXED, 32); +#else + rte_wait_event((uint64_t *)&me->next, UINT64_MAX, 0, ==, + __ATOMIC_RELAXED, 64); +#endif } /* Pass lock to next waiter. */ From patchwork Wed Oct 20 08:45:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102397 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B750A0C43; Wed, 20 Oct 2021 10:46:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 52B86411C7; Wed, 20 Oct 2021 10:46:10 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 8416F411CE for ; Wed, 20 Oct 2021 10:46:09 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 05714ED1; Wed, 20 Oct 2021 01:46:09 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 28DE63F70D; Wed, 20 Oct 2021 01:46:06 -0700 (PDT) From: Feifei Wang To: Konstantin Ananyev Cc: dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Wed, 20 Oct 2021 16:45:22 +0800 Message-Id: <20211020084523.1309177-5-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020084523.1309177-1-feifei.wang2@arm.com> References: <20210926063302.1541193-1-feifei.wang2@arm.com> <20211020084523.1309177-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 4/5] lib/bpf: use wait event scheme for Rx/Tx iteration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for cbi->use to be updated, use wait event scheme. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/bpf/bpf_pkt.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/lib/bpf/bpf_pkt.c b/lib/bpf/bpf_pkt.c index 6e8248f0d6..00a5748061 100644 --- a/lib/bpf/bpf_pkt.c +++ b/lib/bpf/bpf_pkt.c @@ -113,7 +113,7 @@ bpf_eth_cbi_unuse(struct bpf_eth_cbi *cbi) static void bpf_eth_cbi_wait(const struct bpf_eth_cbi *cbi) { - uint32_t nuse, puse; + uint32_t puse; /* make sure all previous loads and stores are completed */ rte_smp_mb(); @@ -122,11 +122,8 @@ bpf_eth_cbi_wait(const struct bpf_eth_cbi *cbi) /* in use, busy wait till current RX/TX iteration is finished */ if ((puse & BPF_ETH_CBI_INUSE) != 0) { - do { - rte_pause(); - rte_compiler_barrier(); - nuse = cbi->use; - } while (nuse == puse); + rte_wait_event(&cbi->use, UINT32_MAX, puse, ==, + __ATOMIC_RELAXED, 32); } } From patchwork Wed Oct 20 08:45:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 102398 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 05760A0C43; Wed, 20 Oct 2021 10:46:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4DDE7411C1; Wed, 20 Oct 2021 10:46:13 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 29E1D411D2 for ; Wed, 20 Oct 2021 10:46:12 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A8D52ED1; Wed, 20 Oct 2021 01:46:11 -0700 (PDT) Received: from net-x86-dell-8268.shanghai.arm.com (net-x86-dell-8268.shanghai.arm.com [10.169.210.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 962593F70D; Wed, 20 Oct 2021 01:46:09 -0700 (PDT) From: Feifei Wang To: David Hunt Cc: konstantin.ananyev@intel.com, dev@dpdk.org, nd@arm.com, Feifei Wang , Ruifeng Wang Date: Wed, 20 Oct 2021 16:45:23 +0800 Message-Id: <20211020084523.1309177-6-feifei.wang2@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211020084523.1309177-1-feifei.wang2@arm.com> References: <20210926063302.1541193-1-feifei.wang2@arm.com> <20211020084523.1309177-1-feifei.wang2@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v4 5/5] lib/distributor: use wait event scheme X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of polling for bufptr64 to be updated, use wait event for this case. Signed-off-by: Feifei Wang Reviewed-by: Ruifeng Wang --- lib/distributor/rte_distributor_single.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/lib/distributor/rte_distributor_single.c b/lib/distributor/rte_distributor_single.c index f4725b1d0b..c623bb135d 100644 --- a/lib/distributor/rte_distributor_single.c +++ b/lib/distributor/rte_distributor_single.c @@ -33,9 +33,8 @@ rte_distributor_request_pkt_single(struct rte_distributor_single *d, union rte_distributor_buffer_single *buf = &d->bufs[worker_id]; int64_t req = (((int64_t)(uintptr_t)oldpkt) << RTE_DISTRIB_FLAG_BITS) | RTE_DISTRIB_GET_BUF; - while (unlikely(__atomic_load_n(&buf->bufptr64, __ATOMIC_RELAXED) - & RTE_DISTRIB_FLAGS_MASK)) - rte_pause(); + rte_wait_event(&buf->bufptr64, RTE_DISTRIB_FLAGS_MASK, + 0, !=, __ATOMIC_RELAXED, 64); /* Sync with distributor on GET_BUF flag. */ __atomic_store_n(&(buf->bufptr64), req, __ATOMIC_RELEASE); @@ -74,9 +73,8 @@ rte_distributor_return_pkt_single(struct rte_distributor_single *d, union rte_distributor_buffer_single *buf = &d->bufs[worker_id]; uint64_t req = (((int64_t)(uintptr_t)oldpkt) << RTE_DISTRIB_FLAG_BITS) | RTE_DISTRIB_RETURN_BUF; - while (unlikely(__atomic_load_n(&buf->bufptr64, __ATOMIC_RELAXED) - & RTE_DISTRIB_FLAGS_MASK)) - rte_pause(); + rte_wait_event(&buf->bufptr64, RTE_DISTRIB_FLAGS_MASK, + 0, !=, __ATOMIC_RELAXED, 64); /* Sync with distributor on RETURN_BUF flag. */ __atomic_store_n(&(buf->bufptr64), req, __ATOMIC_RELEASE);