From patchwork Wed Sep 22 07:46:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liguzinski, WojciechX" X-Patchwork-Id: 99399 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 94310A0C45; Wed, 22 Sep 2021 09:47:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C45104069E; Wed, 22 Sep 2021 09:47:07 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 4A46540141 for ; Wed, 22 Sep 2021 09:47:04 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10114"; a="309092887" X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="309092887" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 00:47:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="703625061" Received: from silpixa00400629.ir.intel.com ([10.237.213.30]) by fmsmga005.fm.intel.com with ESMTP; 22 Sep 2021 00:47:02 -0700 From: "Liguzinski, WojciechX" To: dev@dpdk.org, jasvinder.singh@intel.com, cristian.dumitrescu@intel.com Cc: megha.ajmera@intel.com Date: Wed, 22 Sep 2021 07:46:33 +0000 Message-Id: <20210922074637.883074-2-wojciechx.liguzinski@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922074637.883074-1-wojciechx.liguzinski@intel.com> References: <20210907141151.1502383-1-wojciechx.liguzinski@intel.com> <20210922074637.883074-1-wojciechx.liguzinski@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [RFC PATCH v7 1/5] sched: add PIE based congestion management X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Implement PIE based congestion management based on rfc8033 Signed-off-by: Liguzinski, WojciechX --- drivers/net/softnic/rte_eth_softnic_tm.c | 6 +- lib/sched/meson.build | 10 +- lib/sched/rte_pie.c | 82 +++++ lib/sched/rte_pie.h | 393 +++++++++++++++++++++++ lib/sched/rte_sched.c | 228 +++++++++---- lib/sched/rte_sched.h | 53 ++- lib/sched/version.map | 3 + 7 files changed, 685 insertions(+), 90 deletions(-) create mode 100644 lib/sched/rte_pie.c create mode 100644 lib/sched/rte_pie.h diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c index 90baba15ce..5b6c4e6d4b 100644 --- a/drivers/net/softnic/rte_eth_softnic_tm.c +++ b/drivers/net/softnic/rte_eth_softnic_tm.c @@ -420,7 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev, return 0; } -#ifdef RTE_SCHED_RED +#ifdef RTE_SCHED_AQM #define WRED_SUPPORTED 1 #else #define WRED_SUPPORTED 0 @@ -2306,7 +2306,7 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id) return NULL; } -#ifdef RTE_SCHED_RED +#ifdef RTE_SCHED_AQM static void wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id) @@ -2321,7 +2321,7 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id) for (tc_id = 0; tc_id < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; tc_id++) for (color = RTE_COLOR_GREEN; color < RTE_COLORS; color++) { struct rte_red_params *dst = - &pp->red_params[tc_id][color]; + &pp->wred_params[tc_id][color]; struct tm_wred_profile *src_wp = tm_tc_wred_profile_get(dev, tc_id); struct rte_tm_red_params *src = diff --git a/lib/sched/meson.build b/lib/sched/meson.build index b24f7b8775..e7ae9bcf19 100644 --- a/lib/sched/meson.build +++ b/lib/sched/meson.build @@ -1,11 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -sources = files('rte_sched.c', 'rte_red.c', 'rte_approx.c') -headers = files( - 'rte_approx.h', - 'rte_red.h', - 'rte_sched.h', - 'rte_sched_common.h', -) +sources = files('rte_sched.c', 'rte_red.c', 'rte_approx.c', 'rte_pie.c') +headers = files('rte_sched.h', 'rte_sched_common.h', + 'rte_red.h', 'rte_approx.h', 'rte_pie.h') deps += ['mbuf', 'meter'] diff --git a/lib/sched/rte_pie.c b/lib/sched/rte_pie.c new file mode 100644 index 0000000000..2fcecb2db4 --- /dev/null +++ b/lib/sched/rte_pie.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2020 Intel Corporation + */ + +#include + +#include "rte_pie.h" +#include +#include +#include + +#ifdef __INTEL_COMPILER +#pragma warning(disable:2259) /* conversion may lose significant bits */ +#endif + +void +rte_pie_rt_data_init(struct rte_pie *pie) +{ + if (pie == NULL) { + /* Allocate memory to use the PIE data structure */ + pie = rte_malloc(NULL, sizeof(struct rte_pie), 0); + + if (pie == NULL) + RTE_LOG(ERR, SCHED, "%s: Memory allocation fails\n", __func__); + } + + pie->active = 0; + pie->in_measurement = 0; + pie->departed_bytes_count = 0; + pie->start_measurement = 0; + pie->last_measurement = 0; + pie->qlen = 0; + pie->avg_dq_time = 0; + pie->burst_allowance = 0; + pie->qdelay_old = 0; + pie->drop_prob = 0; + pie->accu_prob = 0; +} + +int +rte_pie_config_init(struct rte_pie_config *pie_cfg, + const uint16_t qdelay_ref, + const uint16_t dp_update_interval, + const uint16_t max_burst, + const uint16_t tailq_th) +{ + uint64_t tsc_hz = rte_get_tsc_hz(); + + if (pie_cfg == NULL) + return -1; + + if (qdelay_ref <= 0) { + RTE_LOG(ERR, SCHED, + "%s: Incorrect value for qdelay_ref\n", __func__); + return -EINVAL; + } + + if (dp_update_interval <= 0) { + RTE_LOG(ERR, SCHED, + "%s: Incorrect value for dp_update_interval\n", __func__); + return -EINVAL; + } + + if (max_burst <= 0) { + RTE_LOG(ERR, SCHED, + "%s: Incorrect value for max_burst\n", __func__); + return -EINVAL; + } + + if (tailq_th <= 0) { + RTE_LOG(ERR, SCHED, + "%s: Incorrect value for tailq_th\n", __func__); + return -EINVAL; + } + + pie_cfg->qdelay_ref = (tsc_hz * qdelay_ref) / 1000; + pie_cfg->dp_update_interval = (tsc_hz * dp_update_interval) / 1000; + pie_cfg->max_burst = (tsc_hz * max_burst) / 1000; + pie_cfg->tailq_th = tailq_th; + + return 0; +} diff --git a/lib/sched/rte_pie.h b/lib/sched/rte_pie.h new file mode 100644 index 0000000000..f83c95664f --- /dev/null +++ b/lib/sched/rte_pie.h @@ -0,0 +1,393 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2020 Intel Corporation + */ + +#ifndef __RTE_PIE_H_INCLUDED__ +#define __RTE_PIE_H_INCLUDED__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file + * RTE Proportional Integral controller Enhanced (PIE) + * + * + ***/ + +#include + +#include +#include + +#define RTE_DQ_THRESHOLD 16384 /**< Queue length threshold (2^14) + * to start measurement cycle (bytes) + */ +#define RTE_DQ_WEIGHT 0.25 /**< Weight (RTE_DQ_THRESHOLD/2^16) to compute dequeue rate */ +#define RTE_ALPHA 0.125 /**< Weights in drop probability calculations */ +#define RTE_BETA 1.25 /**< Weights in drop probability calculations */ +#define RTE_RAND_MAX ~0LLU /**< Max value of the random number */ + + +/** + * PIE configuration parameters passed by user + * + */ +struct rte_pie_params { + uint16_t qdelay_ref; /**< Latency Target (milliseconds) */ + uint16_t dp_update_interval; /**< Update interval for drop probability (milliseconds) */ + uint16_t max_burst; /**< Max Burst Allowance (milliseconds) */ + uint16_t tailq_th; /**< Tailq drop threshold (packet counts) */ +}; + +/** + * PIE configuration parameters + * + */ +struct rte_pie_config { + uint64_t qdelay_ref; /**< Latency Target (in CPU cycles.) */ + uint64_t dp_update_interval; /**< Update interval for drop probability (in CPU cycles) */ + uint64_t max_burst; /**< Max Burst Allowance (in CPU cycles.) */ + uint16_t tailq_th; /**< Tailq drop threshold (packet counts) */ +}; + +/** + * RED run-time data + */ +struct rte_pie { + uint16_t active; /**< Flag for activating/deactivating pie */ + uint16_t in_measurement; /**< Flag for activation of measurement cycle */ + uint32_t departed_bytes_count; /**< Number of bytes departed in current measurement cycle */ + uint64_t start_measurement; /**< Time to start to measurement cycle (in cpu cycles) */ + uint64_t last_measurement; /**< Time of last measurement (in cpu cycles) */ + uint64_t qlen; /**< Queue length (packets count) */ + uint64_t qlen_bytes; /**< Queue length (bytes count) */ + uint64_t avg_dq_time; /**< Time averaged dequeue rate (in cpu cycles) */ + uint32_t burst_allowance; /**< Current burst allowance (bytes) */ + uint64_t qdelay_old; /**< Old queue delay (bytes) */ + double drop_prob; /**< Current packet drop probability */ + double accu_prob; /**< Accumulated packet drop probability */ +}; + +/** + * @brief Initialises run-time data + * + * @param pie [in,out] data pointer to PIE runtime data + */ +void +__rte_experimental +rte_pie_rt_data_init(struct rte_pie *pie); + +/** + * @brief Configures a single PIE configuration parameter structure. + * + * @param pie_cfg [in,out] config pointer to a PIE configuration parameter structure + * @param qdelay_ref [in] latency target(milliseconds) + * @param dp_update_interval [in] update interval for drop probability (milliseconds) + * @param max_burst [in] maximum burst allowance (milliseconds) + * @param tailq_th [in] tail drop threshold for the queue (number of packets) + * + * @return Operation status + * @retval 0 success + * @retval !0 error + */ +int +__rte_experimental +rte_pie_config_init(struct rte_pie_config *pie_cfg, + const uint16_t qdelay_ref, + const uint16_t dp_update_interval, + const uint16_t max_burst, + const uint16_t tailq_th); + +/** + * @brief Decides packet enqueue when queue is empty + * + * Note: packet is never dropped in this particular case. + * + * @param pie_cfg [in] config pointer to a PIE configuration parameter structure + * @param pie [in, out] data pointer to PIE runtime data + * @param pkt_len [in] packet length in bytes + * + * @return Operation status + * @retval 0 enqueue the packet + * @retval !0 drop the packet + */ +static inline int +__rte_experimental +rte_pie_enqueue_empty(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie, + uint32_t pkt_len) +{ + RTE_ASSERT(pkt_len != NULL); + + /* Update the PIE qlen parameter */ + pie->qlen++; + pie->qlen_bytes += pkt_len; + + /** + * If the queue has been idle for a while, turn off PIE and Reset counters + */ + if ((pie->active == 1) && + (pie->qlen < (pie_cfg->tailq_th * 0.1))) { + pie->active = 0; + pie->in_measurement = 0; + } + + return 0; +} + +/** + * @brief make a decision to drop or enqueue a packet based on probability + * criteria + * + * @param pie_cfg [in] config pointer to a PIE configuration parameter structure + * @param pie [in, out] data pointer to PIE runtime data + * @param time [in] current time (measured in cpu cycles) + */ +static inline void +__rte_experimental +_calc_drop_probability(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie, uint64_t time) +{ + uint64_t qdelay_ref = pie_cfg->qdelay_ref; + + /* Note: can be implemented using integer multiply. + * DQ_THRESHOLD is power of 2 value. + */ + double current_qdelay = pie->qlen * (pie->avg_dq_time / RTE_DQ_THRESHOLD); + + double p = RTE_ALPHA * (current_qdelay - qdelay_ref) + + RTE_BETA * (current_qdelay - pie->qdelay_old); + + if (pie->drop_prob < 0.000001) + p = p * 0.00048828125; /* (1/2048) = 0.00048828125 */ + else if (pie->drop_prob < 0.00001) + p = p * 0.001953125; /* (1/512) = 0.001953125 */ + else if (pie->drop_prob < 0.0001) + p = p * 0.0078125; /* (1/128) = 0.0078125 */ + else if (pie->drop_prob < 0.001) + p = p * 0.03125; /* (1/32) = 0.03125 */ + else if (pie->drop_prob < 0.01) + p = p * 0.125; /* (1/8) = 0.125 */ + else if (pie->drop_prob < 0.1) + p = p * 0.5; /* (1/2) = 0.5 */ + + if (pie->drop_prob >= 0.1 && p > 0.02) + p = 0.02; + + pie->drop_prob += p; + + double qdelay = qdelay_ref * 0.5; + + /* Exponentially decay drop prob when congestion goes away */ + if (current_qdelay < qdelay && pie->qdelay_old < qdelay) + pie->drop_prob *= 0.98; /* 1 - 1/64 is sufficient */ + + /* Bound drop probability */ + if (pie->drop_prob < 0) + pie->drop_prob = 0; + if (pie->drop_prob > 1) + pie->drop_prob = 1; + + pie->qdelay_old = current_qdelay; + pie->last_measurement = time; + + uint64_t burst_allowance = pie->burst_allowance - pie_cfg->dp_update_interval; + + pie->burst_allowance = (burst_allowance > 0) ? burst_allowance : 0; +} + +/** + * @brief make a decision to drop or enqueue a packet based on probability + * criteria + * + * @param pie_cfg [in] config pointer to a PIE configuration parameter structure + * @param pie [in, out] data pointer to PIE runtime data + * + * @return operation status + * @retval 0 enqueue the packet + * @retval 1 drop the packet + */ +static inline int +__rte_experimental +_rte_pie_drop(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie) +{ + uint64_t rand_value; + double qdelay = pie_cfg->qdelay_ref * 0.5; + + /* PIE is active but the queue is not congested: return 0 */ + if (((pie->qdelay_old < qdelay) && (pie->drop_prob < 0.2)) || + (pie->qlen <= (pie_cfg->tailq_th * 0.1))) + return 0; + + if (pie->drop_prob == 0) + pie->accu_prob = 0; + + /* For practical reasons, drop probability can be further scaled according + * to packet size, but one needs to set a bound to avoid unnecessary bias + * Random drop + */ + pie->accu_prob += pie->drop_prob; + + if (pie->accu_prob < 0.85) + return 0; + + if (pie->accu_prob >= 8.5) + return 1; + + rand_value = rte_rand()/RTE_RAND_MAX; + + if ((double)rand_value < pie->drop_prob) { + pie->accu_prob = 0; + return 1; + } + + /* No drop */ + return 0; +} + +/** + * @brief Decides if new packet should be enqeued or dropped for non-empty queue + * + * @param pie_cfg [in] config pointer to a PIE configuration parameter structure + * @param pie [in,out] data pointer to PIE runtime data + * @param pkt_len [in] packet length in bytes + * @param time [in] current time (measured in cpu cycles) + * + * @return Operation status + * @retval 0 enqueue the packet + * @retval 1 drop the packet based on max threshold criterion + * @retval 2 drop the packet based on mark probability criterion + */ +static inline int +__rte_experimental +rte_pie_enqueue_nonempty(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie, + uint32_t pkt_len, + const uint64_t time) +{ + /* Check queue space against the tail drop threshold */ + if (pie->qlen >= pie_cfg->tailq_th) { + + pie->accu_prob = 0; + return 1; + } + + if (pie->active) { + /* Update drop probability after certain interval */ + if ((time - pie->last_measurement) >= pie_cfg->dp_update_interval) + _calc_drop_probability(pie_cfg, pie, time); + + /* Decide whether packet to be dropped or enqueued */ + if (_rte_pie_drop(pie_cfg, pie) && pie->burst_allowance == 0) + return 2; + } + + /* When queue occupancy is over a certain threshold, turn on PIE */ + if ((pie->active == 0) && + (pie->qlen >= (pie_cfg->tailq_th * 0.1))) { + pie->active = 1; + pie->qdelay_old = 0; + pie->drop_prob = 0; + pie->in_measurement = 1; + pie->departed_bytes_count = 0; + pie->avg_dq_time = 0; + pie->last_measurement = time; + pie->burst_allowance = pie_cfg->max_burst; + pie->accu_prob = 0; + pie->start_measurement = time; + } + + /* when queue has been idle for a while, turn off PIE and Reset counters */ + if (pie->active == 1 && + pie->qlen < (pie_cfg->tailq_th * 0.1)) { + pie->active = 0; + pie->in_measurement = 0; + } + + /* Update PIE qlen parameter */ + pie->qlen++; + pie->qlen_bytes += pkt_len; + + /* No drop */ + return 0; +} + +/** + * @brief Decides if new packet should be enqeued or dropped + * Updates run time data and gives verdict whether to enqueue or drop the packet. + * + * @param pie_cfg [in] config pointer to a PIE configuration parameter structure + * @param pie [in,out] data pointer to PIE runtime data + * @param qlen [in] queue length + * @param pkt_len [in] packet length in bytes + * @param time [in] current time stamp (measured in cpu cycles) + * + * @return Operation status + * @retval 0 enqueue the packet + * @retval 1 drop the packet based on drop probility criteria + */ +static inline int +__rte_experimental +rte_pie_enqueue(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie, + const unsigned int qlen, + uint32_t pkt_len, + const uint64_t time) +{ + RTE_ASSERT(pie_cfg != NULL); + RTE_ASSERT(pie != NULL); + + if (qlen != 0) + return rte_pie_enqueue_nonempty(pie_cfg, pie, pkt_len, time); + else + return rte_pie_enqueue_empty(pie_cfg, pie, pkt_len); +} + +/** + * @brief PIE rate estimation method + * Called on each packet departure. + * + * @param pie [in] data pointer to PIE runtime data + * @param pkt_len [in] packet length in bytes + * @param time [in] current time stamp in cpu cycles + */ +static inline void +__rte_experimental +rte_pie_dequeue(struct rte_pie *pie, + uint32_t pkt_len, + uint64_t time) +{ + /* Dequeue rate estimation */ + if (pie->in_measurement) { + pie->departed_bytes_count += pkt_len; + + /* Start a new measurement cycle when enough packets */ + if (pie->departed_bytes_count >= RTE_DQ_THRESHOLD) { + uint64_t dq_time = time - pie->start_measurement; + + if (pie->avg_dq_time == 0) + pie->avg_dq_time = dq_time; + else + pie->avg_dq_time = dq_time * RTE_DQ_WEIGHT + pie->avg_dq_time + * (1 - RTE_DQ_WEIGHT); + + pie->in_measurement = 0; + } + } + + /* Start measurement cycle when enough data in the queue */ + if ((pie->qlen_bytes >= RTE_DQ_THRESHOLD) && (pie->in_measurement == 0)) { + pie->in_measurement = 1; + pie->start_measurement = time; + pie->departed_bytes_count = 0; + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* __RTE_PIE_H_INCLUDED__ */ diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c index a858f61f95..320435ed91 100644 --- a/lib/sched/rte_sched.c +++ b/lib/sched/rte_sched.c @@ -89,8 +89,12 @@ struct rte_sched_queue { struct rte_sched_queue_extra { struct rte_sched_queue_stats stats; -#ifdef RTE_SCHED_RED - struct rte_red red; +#ifdef RTE_SCHED_AQM + RTE_STD_C11 + union { + struct rte_red red; + struct rte_pie pie; + }; #endif }; @@ -183,8 +187,13 @@ struct rte_sched_subport { /* Pipe queues size */ uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; -#ifdef RTE_SCHED_RED - struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; + enum rte_sched_aqm_mode aqm; +#ifdef RTE_SCHED_AQM + RTE_STD_C11 + union { + struct rte_red_config wred_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; + struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; + }; #endif /* Scheduling loop detection */ @@ -1078,6 +1087,91 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports) rte_free(port); } +#ifdef RTE_SCHED_AQM + +static int +rte_sched_red_config(struct rte_sched_port *port, + struct rte_sched_subport *s, + struct rte_sched_subport_params *params, + uint32_t n_subports) +{ + uint32_t i; + + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { + + uint32_t j; + + for (j = 0; j < RTE_COLORS; j++) { + /* if min/max are both zero, then RED is disabled */ + if ((params->wred_params[i][j].min_th | + params->wred_params[i][j].max_th) == 0) { + continue; + } + + if (rte_red_config_init(&s->wred_config[i][j], + params->wred_params[i][j].wq_log2, + params->wred_params[i][j].min_th, + params->wred_params[i][j].max_th, + params->wred_params[i][j].maxp_inv) != 0) { + rte_sched_free_memory(port, n_subports); + + RTE_LOG(NOTICE, SCHED, + "%s: RED configuration init fails\n", __func__); + return -EINVAL; + } + } + } + s->aqm = RTE_SCHED_AQM_WRED; + return 0; +} + +static int +rte_sched_pie_config(struct rte_sched_port *port, + struct rte_sched_subport *s, + struct rte_sched_subport_params *params, + uint32_t n_subports) +{ + uint32_t i; + + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { + if (params->pie_params[i].tailq_th > params->qsize[i]) { + RTE_LOG(NOTICE, SCHED, + "%s: PIE tailq threshold incorrect\n", __func__); + return -EINVAL; + } + + if (rte_pie_config_init(&s->pie_config[i], + params->pie_params[i].qdelay_ref, + params->pie_params[i].dp_update_interval, + params->pie_params[i].max_burst, + params->pie_params[i].tailq_th) != 0) { + rte_sched_free_memory(port, n_subports); + + RTE_LOG(NOTICE, SCHED, + "%s: PIE configuration init fails\n", __func__); + return -EINVAL; + } + } + s->aqm = RTE_SCHED_AQM_PIE; + return 0; +} + +static int +rte_sched_aqm_config(struct rte_sched_port *port, + struct rte_sched_subport *s, + struct rte_sched_subport_params *params, + uint32_t n_subports) +{ + if (params->aqm == RTE_SCHED_AQM_WRED) + return rte_sched_red_config(port, s, params, n_subports); + + else if (params->aqm == RTE_SCHED_AQM_PIE) + return rte_sched_pie_config(port, s, params, n_subports); + + return -EINVAL; +} +#endif + int rte_sched_subport_config(struct rte_sched_port *port, uint32_t subport_id, @@ -1167,29 +1261,11 @@ rte_sched_subport_config(struct rte_sched_port *port, s->n_pipe_profiles = params->n_pipe_profiles; s->n_max_pipe_profiles = params->n_max_pipe_profiles; -#ifdef RTE_SCHED_RED - for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { - uint32_t j; - - for (j = 0; j < RTE_COLORS; j++) { - /* if min/max are both zero, then RED is disabled */ - if ((params->red_params[i][j].min_th | - params->red_params[i][j].max_th) == 0) { - continue; - } - - if (rte_red_config_init(&s->red_config[i][j], - params->red_params[i][j].wq_log2, - params->red_params[i][j].min_th, - params->red_params[i][j].max_th, - params->red_params[i][j].maxp_inv) != 0) { - RTE_LOG(NOTICE, SCHED, - "%s: RED configuration init fails\n", - __func__); - ret = -EINVAL; - goto out; - } - } +#ifdef RTE_SCHED_AQM + status = rte_sched_aqm_config(port, s, params, n_subports); + if (status) { + RTE_LOG(NOTICE, SCHED, "%s: AQM configuration fails\n", __func__); + return status; } #endif @@ -1718,29 +1794,20 @@ rte_sched_port_update_subport_stats(struct rte_sched_port *port, subport->stats.n_bytes_tc[tc_index] += pkt_len; } -#ifdef RTE_SCHED_RED -static inline void -rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, - struct rte_sched_subport *subport, - uint32_t qindex, - struct rte_mbuf *pkt, - uint32_t red) -#else static inline void rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, struct rte_sched_subport *subport, uint32_t qindex, struct rte_mbuf *pkt, - __rte_unused uint32_t red) -#endif + __rte_unused uint32_t drops) { uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex); uint32_t pkt_len = pkt->pkt_len; subport->stats.n_pkts_tc_dropped[tc_index] += 1; subport->stats.n_bytes_tc_dropped[tc_index] += pkt_len; -#ifdef RTE_SCHED_RED - subport->stats.n_pkts_red_dropped[tc_index] += red; +#ifdef RTE_SCHED_AQM + subport->stats.n_pkts_aqm_dropped[tc_index] += drops; #endif } @@ -1756,58 +1823,61 @@ rte_sched_port_update_queue_stats(struct rte_sched_subport *subport, qe->stats.n_bytes += pkt_len; } -#ifdef RTE_SCHED_RED -static inline void -rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport, - uint32_t qindex, - struct rte_mbuf *pkt, - uint32_t red) -#else static inline void rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport, uint32_t qindex, struct rte_mbuf *pkt, - __rte_unused uint32_t red) -#endif + __rte_unused uint32_t drops) { struct rte_sched_queue_extra *qe = subport->queue_extra + qindex; uint32_t pkt_len = pkt->pkt_len; qe->stats.n_pkts_dropped += 1; qe->stats.n_bytes_dropped += pkt_len; -#ifdef RTE_SCHED_RED - qe->stats.n_pkts_red_dropped += red; +#ifdef RTE_SCHED_AQM + qe->stats.n_pkts_aqm_dropped += drops; #endif } #endif /* RTE_SCHED_COLLECT_STATS */ -#ifdef RTE_SCHED_RED +#ifdef RTE_SCHED_AQM static inline int -rte_sched_port_red_drop(struct rte_sched_port *port, +rte_sched_port_aqm_drop(struct rte_sched_port *port, struct rte_sched_subport *subport, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen) { struct rte_sched_queue_extra *qe; - struct rte_red_config *red_cfg; - struct rte_red *red; uint32_t tc_index; - enum rte_color color; tc_index = rte_sched_port_pipe_tc(port, qindex); - color = rte_sched_port_pkt_read_color(pkt); - red_cfg = &subport->red_config[tc_index][color]; + qe = subport->queue_extra + qindex; - if ((red_cfg->min_th | red_cfg->max_th) == 0) - return 0; + /* WRED */ + if (subport->aqm == RTE_SCHED_AQM_WRED) { + struct rte_red_config *red_cfg; + struct rte_red *red; + enum rte_color color; - qe = subport->queue_extra + qindex; - red = &qe->red; + color = rte_sched_port_pkt_read_color(pkt); + red_cfg = &subport->wred_config[tc_index][color]; + + if ((red_cfg->min_th | red_cfg->max_th) == 0) + return 0; - return rte_red_enqueue(red_cfg, red, qlen, port->time); + red = &qe->red; + + return rte_red_enqueue(red_cfg, red, qlen, port->time); + } + + /* PIE */ + struct rte_pie_config *pie_cfg = &subport->pie_config[tc_index]; + struct rte_pie *pie = &qe->pie; + + return rte_pie_enqueue(pie_cfg, pie, pkt->pkt_len, qlen, port->time_cpu_cycles); } static inline void @@ -1815,14 +1885,29 @@ rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, struct rte_sched_subport *subport, uint32_t qindex) { struct rte_sched_queue_extra *qe = subport->queue_extra + qindex; - struct rte_red *red = &qe->red; + if (subport->aqm == RTE_SCHED_AQM_WRED) { + struct rte_red *red = &qe->red; + + rte_red_mark_queue_empty(red, port->time); + } +} + +static inline void +rte_sched_port_pie_dequeue(struct rte_sched_subport *subport, +uint32_t qindex, uint32_t pkt_len, uint64_t time) { + struct rte_sched_queue_extra *qe = subport->queue_extra + qindex; + struct rte_pie *pie = &qe->pie; - rte_red_mark_queue_empty(red, port->time); + /* Update queue length */ + pie->qlen -= 1; + pie->qlen_bytes -= pkt_len; + + rte_pie_dequeue(pie, pkt_len, time); } #else -static inline int rte_sched_port_red_drop(struct rte_sched_port *port __rte_unused, +static inline int rte_sched_port_aqm_drop(struct rte_sched_port *port __rte_unused, struct rte_sched_subport *subport __rte_unused, struct rte_mbuf *pkt __rte_unused, uint32_t qindex __rte_unused, @@ -1833,7 +1918,7 @@ static inline int rte_sched_port_red_drop(struct rte_sched_port *port __rte_unus #define rte_sched_port_set_queue_empty_timestamp(port, subport, qindex) -#endif /* RTE_SCHED_RED */ +#endif /* RTE_SCHED_AQM */ #ifdef RTE_SCHED_DEBUG @@ -1929,7 +2014,7 @@ rte_sched_port_enqueue_qwa(struct rte_sched_port *port, qlen = q->qw - q->qr; /* Drop the packet (and update drop stats) when queue is full */ - if (unlikely(rte_sched_port_red_drop(port, subport, pkt, qindex, qlen) || + if (unlikely(rte_sched_port_aqm_drop(port, subport, pkt, qindex, qlen) || (qlen >= qsize))) { rte_pktmbuf_free(pkt); #ifdef RTE_SCHED_COLLECT_STATS @@ -2402,6 +2487,7 @@ grinder_schedule(struct rte_sched_port *port, { struct rte_sched_grinder *grinder = subport->grinder + pos; struct rte_sched_queue *queue = grinder->queue[grinder->qpos]; + uint32_t qindex = grinder->qindex[grinder->qpos]; struct rte_mbuf *pkt = grinder->pkt; uint32_t pkt_len = pkt->pkt_len + port->frame_overhead; uint32_t be_tc_active; @@ -2421,15 +2507,19 @@ grinder_schedule(struct rte_sched_port *port, (pkt_len * grinder->wrr_cost[grinder->qpos]) & be_tc_active; if (queue->qr == queue->qw) { - uint32_t qindex = grinder->qindex[grinder->qpos]; - rte_bitmap_clear(subport->bmp, qindex); grinder->qmask &= ~(1 << grinder->qpos); if (be_tc_active) grinder->wrr_mask[grinder->qpos] = 0; + rte_sched_port_set_queue_empty_timestamp(port, subport, qindex); } +#ifdef RTE_SCHED_AQM + if (subport->aqm == RTE_SCHED_AQM_PIE) + rte_sched_port_pie_dequeue(subport, qindex, pkt_len, port->time_cpu_cycles); +#endif + /* Reset pipe loop detection */ subport->pipe_loop = RTE_SCHED_PIPE_INVALID; grinder->productive = 1; diff --git a/lib/sched/rte_sched.h b/lib/sched/rte_sched.h index c1a772b70c..a5fe6266cd 100644 --- a/lib/sched/rte_sched.h +++ b/lib/sched/rte_sched.h @@ -61,9 +61,10 @@ extern "C" { #include #include -/** Random Early Detection (RED) */ -#ifdef RTE_SCHED_RED +/** Active Queue Management */ +#ifdef RTE_SCHED_AQM #include "rte_red.h" +#include "rte_pie.h" #endif /** Maximum number of queues per pipe. @@ -110,6 +111,28 @@ extern "C" { #define RTE_SCHED_FRAME_OVERHEAD_DEFAULT 24 #endif +/** + * Active Queue Management (AQM) mode + * + * This is used for controlling the admission of packets into a packet queue or + * group of packet queues on congestion. + * + * The *Random Early Detection (RED)* algorithm works by proactively dropping + * more and more input packets as the queue occupancy builds up. When the queue + * is full or almost full, RED effectively works as *tail drop*. The *Weighted + * RED* algorithm uses a separate set of RED thresholds for each packet color. + * + * Similar to RED, Proportional Integral Controller Enhanced (PIE) randomly + * drops a packet at the onset of the congestion and tries to control the + * latency around the target value. The congestion detection, however, is based + * on the queueing latency instead of the queue length like RED. For more + * information, refer RFC8033. + */ +enum rte_sched_aqm_mode { + RTE_SCHED_AQM_WRED, /**< Weighted Random Early Detection (WRED) */ + RTE_SCHED_AQM_PIE, /**< Proportional Integral Controller Enhanced (PIE) */ +}; + /* * Pipe configuration parameters. The period and credits_per_period * parameters are measured in bytes, with one byte meaning the time @@ -174,9 +197,17 @@ struct rte_sched_subport_params { /** Max allowed profiles in the pipe profile table */ uint32_t n_max_pipe_profiles; -#ifdef RTE_SCHED_RED - /** RED parameters */ - struct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; +#ifdef RTE_SCHED_AQM + /** Active Queue Management mode */ + enum rte_sched_aqm_mode aqm; + + RTE_STD_C11 + union { + /** WRED parameters */ + struct rte_red_params wred_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; + /** PIE parameters */ + struct rte_pie_params pie_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; + }; #endif }; @@ -208,9 +239,9 @@ struct rte_sched_subport_stats { /** Number of bytes dropped for each traffic class */ uint64_t n_bytes_tc_dropped[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; -#ifdef RTE_SCHED_RED - /** Number of packets dropped by red */ - uint64_t n_pkts_red_dropped[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; +#ifdef RTE_SCHED_AQM + /** Number of packets dropped by active queue management scheme */ + uint64_t n_pkts_aqm_dropped[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; #endif }; @@ -222,9 +253,9 @@ struct rte_sched_queue_stats { /** Packets dropped */ uint64_t n_pkts_dropped; -#ifdef RTE_SCHED_RED - /** Packets dropped by RED */ - uint64_t n_pkts_red_dropped; +#ifdef RTE_SCHED_AQM + /** Packets dropped by active queue management scheme */ + uint64_t n_pkts_aqm_dropped; #endif /** Bytes successfully written */ diff --git a/lib/sched/version.map b/lib/sched/version.map index ace284b7de..3422821ac8 100644 --- a/lib/sched/version.map +++ b/lib/sched/version.map @@ -30,4 +30,7 @@ EXPERIMENTAL { rte_sched_subport_pipe_profile_add; # added in 20.11 rte_sched_port_subport_profile_add; + + rte_pie_rt_data_init; + rte_pie_config_init; }; From patchwork Wed Sep 22 07:46:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liguzinski, WojciechX" X-Patchwork-Id: 99400 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93B6EA0C45; Wed, 22 Sep 2021 09:47:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44E2E411B3; Wed, 22 Sep 2021 09:47:12 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id B23C7411AD for ; Wed, 22 Sep 2021 09:47:06 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10114"; a="309092893" X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="309092893" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 00:47:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="703625099" Received: from silpixa00400629.ir.intel.com ([10.237.213.30]) by fmsmga005.fm.intel.com with ESMTP; 22 Sep 2021 00:47:05 -0700 From: "Liguzinski, WojciechX" To: dev@dpdk.org, jasvinder.singh@intel.com, cristian.dumitrescu@intel.com Cc: megha.ajmera@intel.com Date: Wed, 22 Sep 2021 07:46:34 +0000 Message-Id: <20210922074637.883074-3-wojciechx.liguzinski@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922074637.883074-1-wojciechx.liguzinski@intel.com> References: <20210907141151.1502383-1-wojciechx.liguzinski@intel.com> <20210922074637.883074-1-wojciechx.liguzinski@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [RFC PATCH v7 2/5] example/qos_sched: add PIE support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" patch add support enable PIE or RED by parsing config file. Signed-off-by: Liguzinski, WojciechX --- config/rte_config.h | 1 - examples/qos_sched/app_thread.c | 1 - examples/qos_sched/cfg_file.c | 82 ++++++++++--- examples/qos_sched/init.c | 7 +- examples/qos_sched/profile.cfg | 196 +++++++++++++++++++++----------- 5 files changed, 200 insertions(+), 87 deletions(-) diff --git a/config/rte_config.h b/config/rte_config.h index 590903c07d..48132f27df 100644 --- a/config/rte_config.h +++ b/config/rte_config.h @@ -89,7 +89,6 @@ #define RTE_MAX_LCORE_FREQS 64 /* rte_sched defines */ -#undef RTE_SCHED_RED #undef RTE_SCHED_COLLECT_STATS #undef RTE_SCHED_SUBPORT_TC_OV #define RTE_SCHED_PORT_N_GRINDERS 8 diff --git a/examples/qos_sched/app_thread.c b/examples/qos_sched/app_thread.c index dbc878b553..895c0d3592 100644 --- a/examples/qos_sched/app_thread.c +++ b/examples/qos_sched/app_thread.c @@ -205,7 +205,6 @@ app_worker_thread(struct thread_conf **confs) if (likely(nb_pkt)) { int nb_sent = rte_sched_port_enqueue(conf->sched_port, mbufs, nb_pkt); - APP_STATS_ADD(conf->stat.nb_drop, nb_pkt - nb_sent); APP_STATS_ADD(conf->stat.nb_rx, nb_pkt); } diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c index cd167bd8e6..657763ca90 100644 --- a/examples/qos_sched/cfg_file.c +++ b/examples/qos_sched/cfg_file.c @@ -242,20 +242,20 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo memset(active_queues, 0, sizeof(active_queues)); n_active_queues = 0; -#ifdef RTE_SCHED_RED - char sec_name[CFG_NAME_LEN]; - struct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; +#ifdef RTE_SCHED_AQM + enum rte_sched_aqm_mode aqm_mode; - snprintf(sec_name, sizeof(sec_name), "red"); + struct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; - if (rte_cfgfile_has_section(cfg, sec_name)) { + if (rte_cfgfile_has_section(cfg, "red")) { + aqm_mode = RTE_SCHED_AQM_WRED; for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { char str[32]; /* Parse WRED min thresholds */ snprintf(str, sizeof(str), "tc %d wred min", i); - entry = rte_cfgfile_get_entry(cfg, sec_name, str); + entry = rte_cfgfile_get_entry(cfg, "red", str); if (entry) { char *next; /* for each packet colour (green, yellow, red) */ @@ -315,7 +315,42 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } } -#endif /* RTE_SCHED_RED */ + + struct rte_pie_params pie_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; + + if (rte_cfgfile_has_section(cfg, "pie")) { + aqm_mode = RTE_SCHED_AQM_PIE; + + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { + char str[32]; + + /* Parse Queue Delay Ref value */ + snprintf(str, sizeof(str), "tc %d qdelay ref", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].qdelay_ref = (uint16_t) atoi(entry); + + /* Parse Max Burst value */ + snprintf(str, sizeof(str), "tc %d max burst", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].max_burst = (uint16_t) atoi(entry); + + /* Parse Update Interval Value */ + snprintf(str, sizeof(str), "tc %d update interval", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].dp_update_interval = (uint16_t) atoi(entry); + + /* Parse Tailq Threshold Value */ + snprintf(str, sizeof(str), "tc %d tailq th", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].tailq_th = (uint16_t) atoi(entry); + + } + } +#endif /* RTE_SCHED_AQM */ for (i = 0; i < MAX_SCHED_SUBPORTS; i++) { char sec_name[CFG_NAME_LEN]; @@ -393,17 +428,30 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } } -#ifdef RTE_SCHED_RED +#ifdef RTE_SCHED_AQM + subport_params[i].aqm = aqm_mode; + for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) { - for (k = 0; k < RTE_COLORS; k++) { - subport_params[i].red_params[j][k].min_th = - red_params[j][k].min_th; - subport_params[i].red_params[j][k].max_th = - red_params[j][k].max_th; - subport_params[i].red_params[j][k].maxp_inv = - red_params[j][k].maxp_inv; - subport_params[i].red_params[j][k].wq_log2 = - red_params[j][k].wq_log2; + if (subport_params[i].aqm == RTE_SCHED_AQM_WRED) { + for (k = 0; k < RTE_COLORS; k++) { + subport_params[i].wred_params[j][k].min_th = + red_params[j][k].min_th; + subport_params[i].wred_params[j][k].max_th = + red_params[j][k].max_th; + subport_params[i].wred_params[j][k].maxp_inv = + red_params[j][k].maxp_inv; + subport_params[i].wred_params[j][k].wq_log2 = + red_params[j][k].wq_log2; + } + } else { + subport_params[i].pie_params[j].qdelay_ref = + pie_params[j].qdelay_ref; + subport_params[i].pie_params[j].dp_update_interval = + pie_params[j].dp_update_interval; + subport_params[i].pie_params[j].max_burst = + pie_params[j].max_burst; + subport_params[i].pie_params[j].tailq_th = + pie_params[j].tailq_th; } } #endif diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c index 1abe003fc6..96ba3b6616 100644 --- a/examples/qos_sched/init.c +++ b/examples/qos_sched/init.c @@ -212,8 +212,9 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { .n_pipe_profiles = sizeof(pipe_profiles) / sizeof(struct rte_sched_pipe_params), .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, -#ifdef RTE_SCHED_RED - .red_params = { +#ifdef RTE_SCHED_AQM + .aqm = RTE_SCHED_AQM_WRED, + .wred_params = { /* Traffic Class 0 Colors Green / Yellow / Red */ [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, @@ -279,7 +280,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, }, -#endif /* RTE_SCHED_RED */ +#endif /* RTE_SCHED_AQM */ }, }; diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg index 4486d2799e..d4b21c0170 100644 --- a/examples/qos_sched/profile.cfg +++ b/examples/qos_sched/profile.cfg @@ -76,68 +76,134 @@ tc 12 oversubscription weight = 1 tc 12 wrr weights = 1 1 1 1 ; RED params per traffic class and color (Green / Yellow / Red) -[red] -tc 0 wred min = 48 40 32 -tc 0 wred max = 64 64 64 -tc 0 wred inv prob = 10 10 10 -tc 0 wred weight = 9 9 9 - -tc 1 wred min = 48 40 32 -tc 1 wred max = 64 64 64 -tc 1 wred inv prob = 10 10 10 -tc 1 wred weight = 9 9 9 - -tc 2 wred min = 48 40 32 -tc 2 wred max = 64 64 64 -tc 2 wred inv prob = 10 10 10 -tc 2 wred weight = 9 9 9 - -tc 3 wred min = 48 40 32 -tc 3 wred max = 64 64 64 -tc 3 wred inv prob = 10 10 10 -tc 3 wred weight = 9 9 9 - -tc 4 wred min = 48 40 32 -tc 4 wred max = 64 64 64 -tc 4 wred inv prob = 10 10 10 -tc 4 wred weight = 9 9 9 - -tc 5 wred min = 48 40 32 -tc 5 wred max = 64 64 64 -tc 5 wred inv prob = 10 10 10 -tc 5 wred weight = 9 9 9 - -tc 6 wred min = 48 40 32 -tc 6 wred max = 64 64 64 -tc 6 wred inv prob = 10 10 10 -tc 6 wred weight = 9 9 9 - -tc 7 wred min = 48 40 32 -tc 7 wred max = 64 64 64 -tc 7 wred inv prob = 10 10 10 -tc 7 wred weight = 9 9 9 - -tc 8 wred min = 48 40 32 -tc 8 wred max = 64 64 64 -tc 8 wred inv prob = 10 10 10 -tc 8 wred weight = 9 9 9 - -tc 9 wred min = 48 40 32 -tc 9 wred max = 64 64 64 -tc 9 wred inv prob = 10 10 10 -tc 9 wred weight = 9 9 9 - -tc 10 wred min = 48 40 32 -tc 10 wred max = 64 64 64 -tc 10 wred inv prob = 10 10 10 -tc 10 wred weight = 9 9 9 - -tc 11 wred min = 48 40 32 -tc 11 wred max = 64 64 64 -tc 11 wred inv prob = 10 10 10 -tc 11 wred weight = 9 9 9 - -tc 12 wred min = 48 40 32 -tc 12 wred max = 64 64 64 -tc 12 wred inv prob = 10 10 10 -tc 12 wred weight = 9 9 9 +;[red] +;tc 0 wred min = 48 40 32 +;tc 0 wred max = 64 64 64 +;tc 0 wred inv prob = 10 10 10 +;tc 0 wred weight = 9 9 9 + +;tc 1 wred min = 48 40 32 +;tc 1 wred max = 64 64 64 +;tc 1 wred inv prob = 10 10 10 +;tc 1 wred weight = 9 9 9 + +;tc 2 wred min = 48 40 32 +;tc 2 wred max = 64 64 64 +;tc 2 wred inv prob = 10 10 10 +;tc 2 wred weight = 9 9 9 + +;tc 3 wred min = 48 40 32 +;tc 3 wred max = 64 64 64 +;tc 3 wred inv prob = 10 10 10 +;tc 3 wred weight = 9 9 9 + +;tc 4 wred min = 48 40 32 +;tc 4 wred max = 64 64 64 +;tc 4 wred inv prob = 10 10 10 +;tc 4 wred weight = 9 9 9 + +;tc 5 wred min = 48 40 32 +;tc 5 wred max = 64 64 64 +;tc 5 wred inv prob = 10 10 10 +;tc 5 wred weight = 9 9 9 + +;tc 6 wred min = 48 40 32 +;tc 6 wred max = 64 64 64 +;tc 6 wred inv prob = 10 10 10 +;tc 6 wred weight = 9 9 9 + +;tc 7 wred min = 48 40 32 +;tc 7 wred max = 64 64 64 +;tc 7 wred inv prob = 10 10 10 +;tc 7 wred weight = 9 9 9 + +;tc 8 wred min = 48 40 32 +;tc 8 wred max = 64 64 64 +;tc 8 wred inv prob = 10 10 10 +;tc 8 wred weight = 9 9 9 + +;tc 9 wred min = 48 40 32 +;tc 9 wred max = 64 64 64 +;tc 9 wred inv prob = 10 10 10 +;tc 9 wred weight = 9 9 9 + +;tc 10 wred min = 48 40 32 +;tc 10 wred max = 64 64 64 +;tc 10 wred inv prob = 10 10 10 +;tc 10 wred weight = 9 9 9 + +;tc 11 wred min = 48 40 32 +;tc 11 wred max = 64 64 64 +;tc 11 wred inv prob = 10 10 10 +;tc 11 wred weight = 9 9 9 + +;tc 12 wred min = 48 40 32 +;tc 12 wred max = 64 64 64 +;tc 12 wred inv prob = 10 10 10 +;tc 12 wred weight = 9 9 9 + +[pie] +tc 0 qdelay ref = 15 +tc 0 max burst = 150 +tc 0 update interval = 15 +tc 0 tailq th = 64 + +tc 1 qdelay ref = 15 +tc 1 max burst = 150 +tc 1 update interval = 15 +tc 1 tailq th = 64 + +tc 2 qdelay ref = 15 +tc 2 max burst = 150 +tc 2 update interval = 15 +tc 2 tailq th = 64 + +tc 3 qdelay ref = 15 +tc 3 max burst = 150 +tc 3 update interval = 15 +tc 3 tailq th = 64 + +tc 4 qdelay ref = 15 +tc 4 max burst = 150 +tc 4 update interval = 15 +tc 4 tailq th = 64 + +tc 5 qdelay ref = 15 +tc 5 max burst = 150 +tc 5 update interval = 15 +tc 5 tailq th = 64 + +tc 6 qdelay ref = 15 +tc 6 max burst = 150 +tc 6 update interval = 15 +tc 6 tailq th = 64 + +tc 7 qdelay ref = 15 +tc 7 max burst = 150 +tc 7 update interval = 15 +tc 7 tailq th = 64 + +tc 8 qdelay ref = 15 +tc 8 max burst = 150 +tc 8 update interval = 15 +tc 8 tailq th = 64 + +tc 9 qdelay ref = 15 +tc 9 max burst = 150 +tc 9 update interval = 15 +tc 9 tailq th = 64 + +tc 10 qdelay ref = 15 +tc 10 max burst = 150 +tc 10 update interval = 15 +tc 10 tailq th = 64 + +tc 11 qdelay ref = 15 +tc 11 max burst = 150 +tc 11 update interval = 15 +tc 11 tailq th = 64 + +tc 12 qdelay ref = 15 +tc 12 max burst = 150 +tc 12 update interval = 15 +tc 12 tailq th = 64 From patchwork Wed Sep 22 07:46:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liguzinski, WojciechX" X-Patchwork-Id: 99401 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50755A0C45; Wed, 22 Sep 2021 09:47:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 53AE5411BD; Wed, 22 Sep 2021 09:47:13 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id B2710411B3 for ; Wed, 22 Sep 2021 09:47:08 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10114"; a="309092895" X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="309092895" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 00:47:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="703625123" Received: from silpixa00400629.ir.intel.com ([10.237.213.30]) by fmsmga005.fm.intel.com with ESMTP; 22 Sep 2021 00:47:07 -0700 From: "Liguzinski, WojciechX" To: dev@dpdk.org, jasvinder.singh@intel.com, cristian.dumitrescu@intel.com Cc: megha.ajmera@intel.com Date: Wed, 22 Sep 2021 07:46:35 +0000 Message-Id: <20210922074637.883074-4-wojciechx.liguzinski@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922074637.883074-1-wojciechx.liguzinski@intel.com> References: <20210907141151.1502383-1-wojciechx.liguzinski@intel.com> <20210922074637.883074-1-wojciechx.liguzinski@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [RFC PATCH v7 3/5] example/ip_pipeline: add PIE support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding the PIE support for IP Pipeline Signed-off-by: Liguzinski, WojciechX --- examples/ip_pipeline/tmgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c index e4e364cbc0..73da2da870 100644 --- a/examples/ip_pipeline/tmgr.c +++ b/examples/ip_pipeline/tmgr.c @@ -25,8 +25,8 @@ static const struct rte_sched_subport_params subport_params_default = { .pipe_profiles = pipe_profile, .n_pipe_profiles = 0, /* filled at run time */ .n_max_pipe_profiles = RTE_DIM(pipe_profile), -#ifdef RTE_SCHED_RED -.red_params = { +#ifdef RTE_SCHED_AQM +.wred_params = { /* Traffic Class 0 Colors Green / Yellow / Red */ [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, @@ -92,7 +92,7 @@ static const struct rte_sched_subport_params subport_params_default = { [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, }, -#endif /* RTE_SCHED_RED */ +#endif /* RTE_SCHED_AQM */ }; static struct tmgr_port_list tmgr_port_list; From patchwork Wed Sep 22 07:46:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liguzinski, WojciechX" X-Patchwork-Id: 99402 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30B92A0C45; Wed, 22 Sep 2021 09:47:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66980411AC; Wed, 22 Sep 2021 09:47:18 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id EFF0F41198 for ; Wed, 22 Sep 2021 09:47:10 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10114"; a="309092899" X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="309092899" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 00:47:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="703625133" Received: from silpixa00400629.ir.intel.com ([10.237.213.30]) by fmsmga005.fm.intel.com with ESMTP; 22 Sep 2021 00:47:09 -0700 From: "Liguzinski, WojciechX" To: dev@dpdk.org, jasvinder.singh@intel.com, cristian.dumitrescu@intel.com Cc: megha.ajmera@intel.com Date: Wed, 22 Sep 2021 07:46:36 +0000 Message-Id: <20210922074637.883074-5-wojciechx.liguzinski@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922074637.883074-1-wojciechx.liguzinski@intel.com> References: <20210907141151.1502383-1-wojciechx.liguzinski@intel.com> <20210922074637.883074-1-wojciechx.liguzinski@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [RFC PATCH v7 4/5] doc/guides/prog_guide: added PIE X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added PIE related information to documentation. Signed-off-by: Liguzinski, WojciechX --- doc/guides/prog_guide/glossary.rst | 3 + doc/guides/prog_guide/qos_framework.rst | 60 +++++++++++++++++--- doc/guides/prog_guide/traffic_management.rst | 13 ++++- 3 files changed, 66 insertions(+), 10 deletions(-) diff --git a/doc/guides/prog_guide/glossary.rst b/doc/guides/prog_guide/glossary.rst index 7044a7df2a..fb0910ba5b 100644 --- a/doc/guides/prog_guide/glossary.rst +++ b/doc/guides/prog_guide/glossary.rst @@ -158,6 +158,9 @@ PCI PHY An abbreviation for the physical layer of the OSI model. +PIE + Proportional Integral Controller Enhanced (RFC8033) + pktmbuf An *mbuf* carrying a network packet. diff --git a/doc/guides/prog_guide/qos_framework.rst b/doc/guides/prog_guide/qos_framework.rst index 3b8a1184b0..7c8450181d 100644 --- a/doc/guides/prog_guide/qos_framework.rst +++ b/doc/guides/prog_guide/qos_framework.rst @@ -56,7 +56,8 @@ A functional description of each block is provided in the following table. | | | | +---+------------------------+--------------------------------------------------------------------------------+ | 7 | Dropper | Congestion management using the Random Early Detection (RED) algorithm | - | | | (specified by the Sally Floyd - Van Jacobson paper) or Weighted RED (WRED). | + | | | (specified by the Sally Floyd - Van Jacobson paper) or Weighted RED (WRED) | + | | | or Proportional Integral Controller Enhanced (PIE). | | | | Drop packets based on the current scheduler queue load level and packet | | | | priority. When congestion is experienced, lower priority packets are dropped | | | | first. | @@ -421,7 +422,7 @@ No input packet can be part of more than one pipeline stage at a given time. The congestion management scheme implemented by the enqueue pipeline described above is very basic: packets are enqueued until a specific queue becomes full, then all the packets destined to the same queue are dropped until packets are consumed (by the dequeue operation). -This can be improved by enabling RED/WRED as part of the enqueue pipeline which looks at the queue occupancy and +This can be improved by enabling RED/WRED or PIE as part of the enqueue pipeline which looks at the queue occupancy and packet priority in order to yield the enqueue/drop decision for a specific packet (as opposed to enqueuing all packets / dropping all packets indiscriminately). @@ -1155,13 +1156,13 @@ If the number of queues is small, then the performance of the port scheduler for the same level of active traffic is expected to be worse than the performance of a small set of message passing queues. -.. _Dropper: +.. _Droppers: -Dropper +Droppers ------- The purpose of the DPDK dropper is to drop packets arriving at a packet scheduler to avoid congestion. -The dropper supports the Random Early Detection (RED), +The dropper supports the Proportional Integral Controller Enhanced (PIE), Random Early Detection (RED), Weighted Random Early Detection (WRED) and tail drop algorithms. :numref:`figure_blk_diag_dropper` illustrates how the dropper integrates with the scheduler. The DPDK currently does not support congestion management @@ -1174,9 +1175,13 @@ so the dropper provides the only method for congestion avoidance. High-level Block Diagram of the DPDK Dropper -The dropper uses the Random Early Detection (RED) congestion avoidance algorithm as documented in the reference publication. -The purpose of the RED algorithm is to monitor a packet queue, +The dropper uses one of two congestion avoidance algorithms: + - the Random Early Detection (RED) as documented in the reference publication. + - the Proportional Integral Controller Enhanced (PIE) as documented in RFC8033 publication. + +The purpose of the RED/PIE algorithm is to monitor a packet queue, determine the current congestion level in the queue and decide whether an arriving packet should be enqueued or dropped. + The RED algorithm uses an Exponential Weighted Moving Average (EWMA) filter to compute average queue size which gives an indication of the current congestion level in the queue. @@ -1192,7 +1197,7 @@ This occurs when a packet queue has reached maximum capacity and cannot store an In this situation, all arriving packets are dropped. The flow through the dropper is illustrated in :numref:`figure_flow_tru_droppper`. -The RED/WRED algorithm is exercised first and tail drop second. +The RED/WRED/PIE algorithm is exercised first and tail drop second. .. _figure_flow_tru_droppper: @@ -1200,6 +1205,16 @@ The RED/WRED algorithm is exercised first and tail drop second. Flow Through the Dropper +The PIE algorithm periodically updates the drop probability based on the latency samples. +The current latency sample but also analyze whether the latency is trending up or down. +This is the classical Proportional Integral (PI) controller method, which is known for +eliminating steady-state errors. + +When a congestion period ends, we might be left with a high drop probability with light +packet arrivals. Hence, the PIE algorithm includes a mechanism by which the drop probability +decays exponentially (rather than linearly) when the system is not congested. +This would help the drop probability converge to 0 more quickly, while the PI controller ensures +that it would eventually reach zero. The use cases supported by the dropper are: @@ -1253,6 +1268,35 @@ to a mark probability of 1/10 (that is, 1 in 10 packets will be dropped). The EWMA filter weight parameter is specified as an inverse log value, for example, a filter weight parameter value of 9 corresponds to a filter weight of 1/29. +A PIE configuration contains the parameters given in :numref:`table_qos_16a`. + +.. _table_qos_16a: + +.. table:: PIE Configuration Parameters + + +--------------------------+---------+---------+------------------+ + | Parameter | Minimum | Maximum | Default | + | | | | | + +==========================+=========+=========+==================+ + | Queue delay reference | 1 | uint16 | 15 | + | Latency Target Value | | | | + | Unit: ms | | | | + +--------------------------+---------+---------+------------------+ + | Max Burst Allowance | 1 | uint16 | 150 | + | Unit: ms | | | | + +--------------------------+---------+---------+------------------+ + | Tail Drop Threshold | 1 | uint16 | 64 | + | Unit: bytes | | | | + +--------------------------+---------+---------+------------------+ + | Period to calculate | 1 | uint16 | 15 | + | drop probability | | | | + | Unit: ms | | | | + +--------------------------+---------+---------+------------------+ + +The meaning of these parameters is explained in more detail in the next sections. +The format of these parameters as specified to the dropper module API. +They could made self calculated for fine tuning, within the apps. + .. _Enqueue_Operation: Enqueue Operation diff --git a/doc/guides/prog_guide/traffic_management.rst b/doc/guides/prog_guide/traffic_management.rst index 05b34d93a5..c356791a45 100644 --- a/doc/guides/prog_guide/traffic_management.rst +++ b/doc/guides/prog_guide/traffic_management.rst @@ -22,6 +22,7 @@ Main features: shared (by multiple nodes) shapers * Congestion management for hierarchy leaf nodes: algorithms of tail drop, head drop, WRED, private (per node) and shared (by multiple nodes) WRED contexts + and PIE. * Packet marking: IEEE 802.1q (VLAN DEI), IETF RFC 3168 (IPv4/IPv6 ECN for TCP and SCTP), IETF RFC 2597 (IPv4 / IPv6 DSCP) @@ -103,8 +104,9 @@ Congestion Management Congestion management is used to control the admission of packets into a packet queue or group of packet queues on congestion. The congestion management algorithms that are supported are: Tail Drop, Head Drop and Weighted Random -Early Detection (WRED). They are made available for every leaf node in the -hierarchy, subject to the specific implementation supporting them. +Early Detection (WRED), Proportional Integral Controller Enhanced (PIE). +They are made available for every leaf node in the hierarchy, subject to +the specific implementation supporting them. On request of writing a new packet into the current queue while the queue is full, the Tail Drop algorithm drops the new packet while leaving the queue unmodified, as opposed to the Head Drop* algorithm, which drops the packet @@ -128,6 +130,13 @@ The configuration of WRED private and shared contexts is done through the definition of WRED profiles. Any WRED profile can be used by one or several WRED contexts (either private or shared). +The Proportional Integral Controller Enhanced (PIE) algorithm works by proactively +dropping packets randomly. Calculated drop probability is updated periodically, +based on latency measured and desired and whether the queuing latency is currently +trending up or down. Queuing latency can be obtained using direct measurement or +on estimations calculated from the queue length and dequeue rate. The random drop +is triggered by a packet's arrival before enqueuing into a queue. + Packet Marking -------------- From patchwork Wed Sep 22 07:46:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liguzinski, WojciechX" X-Patchwork-Id: 99403 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8869AA0C45; Wed, 22 Sep 2021 09:47:36 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9E03C411BA; Wed, 22 Sep 2021 09:47:19 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 28941411C1 for ; Wed, 22 Sep 2021 09:47:13 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10114"; a="309092903" X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="309092903" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 00:47:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,313,1624345200"; d="scan'208";a="703625151" Received: from silpixa00400629.ir.intel.com ([10.237.213.30]) by fmsmga005.fm.intel.com with ESMTP; 22 Sep 2021 00:47:11 -0700 From: "Liguzinski, WojciechX" To: dev@dpdk.org, jasvinder.singh@intel.com, cristian.dumitrescu@intel.com Cc: megha.ajmera@intel.com Date: Wed, 22 Sep 2021 07:46:37 +0000 Message-Id: <20210922074637.883074-6-wojciechx.liguzinski@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210922074637.883074-1-wojciechx.liguzinski@intel.com> References: <20210907141151.1502383-1-wojciechx.liguzinski@intel.com> <20210922074637.883074-1-wojciechx.liguzinski@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [RFC PATCH v7 5/5] app/test: add tests for PIE X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Tests for PIE code added to test application. Signed-off-by: Liguzinski, WojciechX --- app/test/autotest_data.py | 18 + app/test/meson.build | 4 + app/test/test_pie.c | 1065 +++++++++++++++++++++++++++++++++++++ lib/sched/rte_pie.c | 6 +- lib/sched/rte_pie.h | 9 +- lib/sched/rte_sched.c | 2 +- 6 files changed, 1100 insertions(+), 4 deletions(-) create mode 100644 app/test/test_pie.c diff --git a/app/test/autotest_data.py b/app/test/autotest_data.py index 302d6374c1..1d4418b6a3 100644 --- a/app/test/autotest_data.py +++ b/app/test/autotest_data.py @@ -279,6 +279,12 @@ "Func": default_autotest, "Report": None, }, + { + "Name": "Pie autotest", + "Command": "pie_autotest", + "Func": default_autotest, + "Report": None, + }, { "Name": "PMD ring autotest", "Command": "ring_pmd_autotest", @@ -525,6 +531,12 @@ "Func": default_autotest, "Report": None, }, + { + "Name": "Pie all", + "Command": "red_all", + "Func": default_autotest, + "Report": None, + }, { "Name": "Fbarray autotest", "Command": "fbarray_autotest", @@ -731,6 +743,12 @@ "Func": default_autotest, "Report": None, }, + { + "Name": "Pie_perf", + "Command": "pie_perf", + "Func": default_autotest, + "Report": None, + }, { "Name": "Lpm6 perf autotest", "Command": "lpm6_perf_autotest", diff --git a/app/test/meson.build b/app/test/meson.build index a7611686ad..f224b0c17e 100644 --- a/app/test/meson.build +++ b/app/test/meson.build @@ -111,6 +111,7 @@ test_sources = files( 'test_reciprocal_division.c', 'test_reciprocal_division_perf.c', 'test_red.c', + 'test_pie.c', 'test_reorder.c', 'test_rib.c', 'test_rib6.c', @@ -241,6 +242,7 @@ fast_tests = [ ['prefetch_autotest', true], ['rcu_qsbr_autotest', true], ['red_autotest', true], + ['pie_autotest', true], ['rib_autotest', true], ['rib6_autotest', true], ['ring_autotest', true], @@ -292,6 +294,7 @@ perf_test_names = [ 'fib_slow_autotest', 'fib_perf_autotest', 'red_all', + 'pie_all', 'barrier_autotest', 'hash_multiwriter_autotest', 'timer_racecond_autotest', @@ -305,6 +308,7 @@ perf_test_names = [ 'fib6_perf_autotest', 'rcu_qsbr_perf_autotest', 'red_perf', + 'pie_perf', 'distributor_perf_autotest', 'pmd_perf_autotest', 'stack_perf_autotest', diff --git a/app/test/test_pie.c b/app/test/test_pie.c new file mode 100644 index 0000000000..6fae55edfd --- /dev/null +++ b/app/test/test_pie.c @@ -0,0 +1,1065 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2010-2014 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "test.h" + +#include + +#ifdef __INTEL_COMPILER +#pragma warning(disable:2259) /* conversion may lose significant bits */ +#pragma warning(disable:181) /* Arg incompatible with format string */ +#endif + +/**< structures for testing rte_pie performance and function */ +struct test_rte_pie_config { /**< Test structure for RTE_PIE config */ + struct rte_pie_config *pconfig; /**< RTE_PIE configuration parameters */ + uint8_t num_cfg; /**< Number of RTE_PIE configs to test */ + uint16_t qdelay_ref; /**< Latency Target (milliseconds) */ + uint16_t *dp_update_interval; /**< Update interval for drop probability + * (milliseconds) + */ + uint16_t *max_burst; /**< Max Burst Allowance (milliseconds) */ + uint16_t tailq_th; /**< Tailq drop threshold (packet counts) */ +}; + +struct test_queue { /**< Test structure for RTE_PIE Queues */ + struct rte_pie *pdata_in; /**< RTE_PIE runtime data input */ + struct rte_pie *pdata_out; /**< RTE_PIE runtime data output*/ + uint32_t num_queues; /**< Number of RTE_PIE queues to test */ + uint32_t *qlen; /**< Queue size */ + uint32_t q_ramp_up; /**< Num of enqueues to ramp up the queue */ + double drop_tolerance; /**< Drop tolerance of packets not enqueued */ +}; + +struct test_var { /**< Test variables used for testing RTE_PIE */ + uint32_t num_iterations; /**< Number of test iterations */ + uint32_t num_ops; /**< Number of test operations */ + uint64_t clk_freq; /**< CPU clock frequency */ + uint32_t *dropped; /**< Test operations dropped */ + uint32_t *enqueued; /**< Test operations enqueued */ + uint32_t *dequeued; /**< Test operations dequeued */ +}; + +struct test_config { /**< Primary test structure for RTE_PIE */ + const char *ifname; /**< Interface name */ + const char *msg; /**< Test message for display */ + const char *htxt; /**< Header txt display for result output */ + struct test_rte_pie_config *tconfig; /**< Test structure for RTE_PIE config */ + struct test_queue *tqueue; /**< Test structure for RTE_PIE Queues */ + struct test_var *tvar; /**< Test variables used for testing RTE_PIE */ + uint32_t *tlevel; /**< Queue levels */ +}; + +enum test_result { + FAIL = 0, + PASS +}; + +/**< Test structure to define tests to run */ +struct tests { + struct test_config *testcfg; + enum test_result (*testfn)(struct test_config *cfg); +}; + +struct rdtsc_prof { + uint64_t clk_start; + uint64_t clk_min; /**< min clocks */ + uint64_t clk_max; /**< max clocks */ + uint64_t clk_avgc; /**< count to calc average */ + double clk_avg; /**< cumulative sum to calc average */ + const char *name; +}; + +static const uint64_t port_speed_bytes = (10ULL*1000ULL*1000ULL*1000ULL)/8ULL; +static double inv_cycles_per_byte; + +static void init_port_ts(uint64_t cpu_clock) +{ + double cycles_per_byte = (double)(cpu_clock) / (double)(port_speed_bytes); + inv_cycles_per_byte = 1.0 / cycles_per_byte; +} + +static uint64_t get_port_ts(void) +{ + return (uint64_t)((double)rte_rdtsc() * inv_cycles_per_byte); +} + +static void rdtsc_prof_init(struct rdtsc_prof *p, const char *name) +{ + p->clk_min = (uint64_t)(-1LL); + p->clk_max = 0; + p->clk_avg = 0; + p->clk_avgc = 0; + p->name = name; +} + +static inline void rdtsc_prof_start(struct rdtsc_prof *p) +{ + p->clk_start = rte_rdtsc_precise(); +} + +static inline void rdtsc_prof_end(struct rdtsc_prof *p) +{ + uint64_t clk_start = rte_rdtsc() - p->clk_start; + + p->clk_avgc++; + p->clk_avg += (double) clk_start; + + if (clk_start > p->clk_max) + p->clk_max = clk_start; + if (clk_start < p->clk_min) + p->clk_min = clk_start; +} + +static void rdtsc_prof_print(struct rdtsc_prof *p) +{ + if (p->clk_avgc > 0) { + printf("RDTSC stats for %s: n=%" PRIu64 ", min=%" PRIu64 + ",max=%" PRIu64 ", avg=%.1f\n", + p->name, + p->clk_avgc, + p->clk_min, + p->clk_max, + (p->clk_avg / ((double) p->clk_avgc))); + } +} + +static uint16_t rte_pie_get_active(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie) +{ + /**< Flag for activating/deactivating pie */ + RTE_SET_USED(pie_cfg); + return pie->active; +} + +static void rte_pie_set_active(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie, + uint16_t active) +{ + /**< Flag for activating/deactivating pie */ + RTE_SET_USED(pie_cfg); + pie->active = active; +} + +/** + * Read the drop probability + */ +static double rte_pie_get_drop_prob(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie) +{ + /**< Current packet drop probability */ + RTE_SET_USED(pie_cfg); + return pie->drop_prob; +} + +static double rte_pie_get_avg_dq_time(const struct rte_pie_config *pie_cfg, + struct rte_pie *pie) +{ + /**< Current packet drop probability */ + RTE_SET_USED(pie_cfg); + return pie->avg_dq_time; +} + +static double calc_drop_rate(uint32_t enqueued, uint32_t dropped) +{ + return (double)dropped / ((double)enqueued + (double)dropped); +} + +/** + * check if drop rate matches drop probability within tolerance + */ +static int check_drop_rate(double *diff, double drop_rate, double drop_prob, + double tolerance) +{ + double abs_diff = 0.0; + int ret = 1; + + abs_diff = fabs(drop_rate - drop_prob); + if ((int)abs_diff == 0) { + *diff = 0.0; + } else { + *diff = (abs_diff / drop_prob) * 100.0; + if (*diff > tolerance) + ret = 0; + } + return ret; +} + +/** + * initialize the test rte_pie config + */ +static enum test_result +test_rte_pie_init(struct test_config *tcfg) +{ + unsigned int i = 0; + + tcfg->tvar->clk_freq = rte_get_timer_hz(); + init_port_ts(tcfg->tvar->clk_freq); + + for (i = 0; i < tcfg->tconfig->num_cfg; i++) { + if (rte_pie_config_init(&tcfg->tconfig->pconfig[i], + (uint16_t)tcfg->tconfig->qdelay_ref, + (uint16_t)tcfg->tconfig->dp_update_interval[i], + (uint16_t)tcfg->tconfig->max_burst[i], + (uint16_t)tcfg->tconfig->tailq_th) != 0) { + return FAIL; + } + } + + *tcfg->tqueue->qlen = 0; + *tcfg->tvar->dropped = 0; + *tcfg->tvar->enqueued = 0; + + return PASS; +} + +/** + * enqueue until actual queue size reaches target level + */ +static int +increase_qsize(struct rte_pie_config *pie_cfg, + struct rte_pie *pie, + uint32_t *qlen, + uint32_t pkt_len, + uint32_t attempts) +{ + uint32_t i = 0; + + for (i = 0; i < attempts; i++) { + int ret = 0; + + /** + * enqueue + */ + ret = rte_pie_enqueue(pie_cfg, pie, *qlen, pkt_len, get_port_ts()); + /** + * check if target actual queue size has been reached + */ + if (ret == 0) + return 0; + } + /** + * no success + */ + return -1; +} + +/** + * functional test enqueue/dequeue packets + */ +static void +enqueue_dequeue_func(struct rte_pie_config *pie_cfg, + struct rte_pie *pie, + uint32_t *qlen, + uint32_t num_ops, + uint32_t *enqueued, + uint32_t *dropped) +{ + uint32_t i = 0; + + for (i = 0; i < num_ops; i++) { + int ret = 0; + + /** + * enqueue + */ + ret = rte_pie_enqueue(pie_cfg, pie, *qlen, sizeof(uint32_t), + get_port_ts()); + if (ret == 0) + (*enqueued)++; + else + (*dropped)++; + } +} + +/** + * setup default values for the Functional test structures + */ +static struct rte_pie_config ft_wpconfig[1]; +static struct rte_pie ft_rtdata[1]; +static uint32_t ft_q[] = {0}; +static uint32_t ft_dropped[] = {0}; +static uint32_t ft_enqueued[] = {0}; +static uint16_t ft_max_burst[] = {64}; +static uint16_t ft_dp_update_interval[] = {150}; + +static struct test_rte_pie_config ft_tconfig = { + .pconfig = ft_wpconfig, + .num_cfg = RTE_DIM(ft_wpconfig), + .qdelay_ref = 15, + .dp_update_interval = ft_dp_update_interval, + .max_burst = ft_max_burst, + .tailq_th = 15, +}; + +static struct test_queue ft_tqueue = { + .pdata_in = ft_rtdata, + .num_queues = RTE_DIM(ft_rtdata), + .qlen = ft_q, + .q_ramp_up = 10, + .drop_tolerance = 0, +}; + +static struct test_var ft_tvar = { + .num_iterations = 0, + .num_ops = 10000, + .clk_freq = 0, + .dropped = ft_dropped, + .enqueued = ft_enqueued, +}; + +/** + * Test F1: functional test 1 + */ +static uint32_t ft_tlevels[] = {6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, + 72, 78, 84, 90, 96, 102, 108, 114, 120, 126, 132, 138, 144}; + +static struct test_config func_test_config1 = { + .ifname = "functional test interface", + .msg = "functional test : use one pie configuration\n\n", + .htxt = " " + "drop probability " + "enqueued " + "dropped " + "drop prob % " + "drop rate % " + "diff % " + "tolerance % " + "active " + "\n", + .tconfig = &ft_tconfig, + .tqueue = &ft_tqueue, + .tvar = &ft_tvar, + .tlevel = ft_tlevels, +}; + +static enum test_result func_test1(struct test_config *tcfg) +{ + enum test_result result = PASS; + uint32_t i = 0; + + printf("%s", tcfg->msg); + + if (test_rte_pie_init(tcfg) != PASS) { + result = FAIL; + goto out; + } + + printf("%s", tcfg->htxt); + + /** + * reset rte_pie run-time data + */ + rte_pie_rt_data_init(tcfg->tqueue->pdata_in); + rte_pie_set_active(NULL, tcfg->tqueue->pdata_in, 1); + *tcfg->tvar->enqueued = 0; + *tcfg->tvar->dropped = 0; + + if (increase_qsize(&tcfg->tconfig->pconfig[i], + tcfg->tqueue->pdata_in, + tcfg->tqueue->qlen, + tcfg->tlevel[i], + tcfg->tqueue->q_ramp_up) != 0) { + fprintf(stderr, "Fail: increase qsize\n"); + result = FAIL; + goto out; + } + + for (i = 0; i < RTE_DIM(ft_tlevels); i++) { + const char *label = NULL; + uint16_t prob = 0; + uint16_t active = 0; + double drop_rate = 1.0; + double drop_prob = 0.0; + double diff = 0.0; + + enqueue_dequeue_func(&tcfg->tconfig->pconfig[i], + tcfg->tqueue->pdata_in, + tcfg->tqueue->qlen, + tcfg->tvar->num_ops, + tcfg->tvar->enqueued, + tcfg->tvar->dropped); + + drop_rate = calc_drop_rate(*tcfg->tvar->enqueued, + *tcfg->tvar->dropped); + drop_prob = rte_pie_get_drop_prob(NULL, tcfg->tqueue->pdata_in); + + if (drop_prob != 0) { + fprintf(stderr, "Fail: check drop prob\n"); + result = FAIL; + } + + if (drop_rate != 0) { + fprintf(stderr, "Fail: check drop rate\n"); + result = FAIL; + } + + label = "Summary "; + active = rte_pie_get_active(NULL, tcfg->tqueue->pdata_in); + printf("%s%-16u%-12u%-12u%-12.4lf%-12.4lf%-12.4lf%-12.4lf%-8i\n", + label, prob, *tcfg->tvar->enqueued, *tcfg->tvar->dropped, + drop_prob * 100.0, drop_rate * 100.0, diff, + (double)tcfg->tqueue->drop_tolerance, active); + } +out: + return result; +} + +/** + * Test F2: functional test 2 + */ +static uint32_t ft2_tlevel[] = {127}; +static uint16_t ft2_max_burst[] = {1, 2, 8, 16, 32, 64, 128, 256, 512, 1024}; +static uint16_t ft2_dp_update_interval[] = + {10, 20, 50, 150, 300, 600, 900, 1200, 1500, 3000}; +static struct rte_pie_config ft2_pconfig[10]; + +static struct test_rte_pie_config ft2_tconfig = { + .pconfig = ft2_pconfig, + .num_cfg = RTE_DIM(ft2_pconfig), + .qdelay_ref = 15, + .dp_update_interval = ft2_dp_update_interval, + .max_burst = ft2_max_burst, + .tailq_th = 15, +}; + +static struct test_config func_test_config2 = { + .ifname = "functional test 2 interface", + .msg = "functional test 2 : use several PIE configurations,\n" + " compare drop rate to drop probability\n\n", + .htxt = "PIE config " + "avg queue size " + "enqueued " + "dropped " + "drop prob % " + "drop rate % " + "diff % " + "tolerance % " + "\n", + .tconfig = &ft2_tconfig, + .tqueue = &ft_tqueue, + .tvar = &ft_tvar, + .tlevel = ft2_tlevel, +}; + +static enum test_result func_test2(struct test_config *tcfg) +{ + enum test_result result = PASS; + uint32_t i = 0; + + printf("%s", tcfg->msg); + + printf("%s", tcfg->htxt); + + for (i = 0; i < tcfg->tconfig->num_cfg; i++) { + uint32_t avg = 0; + double drop_rate = 0.0; + double drop_prob = 0.0; + double diff = 0.0; + + if (test_rte_pie_init(tcfg) != PASS) { + result = FAIL; + goto out; + } + + rte_pie_rt_data_init(tcfg->tqueue->pdata_in); + rte_pie_set_active(NULL, tcfg->tqueue->pdata_in, 1); + *tcfg->tvar->enqueued = 0; + *tcfg->tvar->dropped = 0; + + if (increase_qsize(&tcfg->tconfig->pconfig[i], + tcfg->tqueue->pdata_in, + tcfg->tqueue->qlen, + *tcfg->tlevel, + tcfg->tqueue->q_ramp_up) != 0) { + result = FAIL; + goto out; + } + + enqueue_dequeue_func(&tcfg->tconfig->pconfig[i], + tcfg->tqueue->pdata_in, + tcfg->tqueue->qlen, + tcfg->tvar->num_ops, + tcfg->tvar->enqueued, + tcfg->tvar->dropped); + + avg = rte_pie_get_avg_dq_time(NULL, tcfg->tqueue->pdata_in); + + drop_rate = calc_drop_rate(*tcfg->tvar->enqueued, + *tcfg->tvar->dropped); + drop_prob = rte_pie_get_drop_prob(NULL, tcfg->tqueue->pdata_in); + + if (!check_drop_rate(&diff, drop_rate, drop_prob, + (double)tcfg->tqueue->drop_tolerance)) { + fprintf(stderr, "Fail: drop rate outside tolerance\n"); + result = FAIL; + } + + printf("%-15u%-15u%-15u%-15u%-15.4lf%-15.4lf%-15.4lf%-15.4lf\n", + i, avg, *tcfg->tvar->enqueued, *tcfg->tvar->dropped, + drop_prob * 100.0, drop_rate * 100.0, diff, + (double)tcfg->tqueue->drop_tolerance); + } +out: + return result; +} + +static uint32_t ft3_qlen[] = {100}; + +static struct test_rte_pie_config ft3_tconfig = { + .pconfig = ft_wpconfig, + .num_cfg = RTE_DIM(ft_wpconfig), + .qdelay_ref = 15, + .dp_update_interval = ft_dp_update_interval, + .max_burst = ft_max_burst, + .tailq_th = 15, +}; + +static struct test_queue ft3_tqueue = { + .pdata_in = ft_rtdata, + .num_queues = RTE_DIM(ft_rtdata), + .qlen = ft3_qlen, + .q_ramp_up = 10, + .drop_tolerance = 0, +}; + +static struct test_var ft3_tvar = { + .num_iterations = 0, + .num_ops = 10000, + .clk_freq = 0, + .dropped = ft_dropped, + .enqueued = ft_enqueued, +}; + +/** + * Test F3: functional test 3 + */ +static uint32_t ft3_tlevels[] = {64, 127, 222}; + +static struct test_config func_test_config3 = { + .ifname = "functional test interface", + .msg = "functional test 2 : use one pie configuration\n" + "using non zero qlen\n\n", + .htxt = " " + "drop probability " + "enqueued " + "dropped " + "drop prob % " + "drop rate % " + "diff % " + "tolerance % " + "active " + "\n", + .tconfig = &ft3_tconfig, + .tqueue = &ft3_tqueue, + .tvar = &ft3_tvar, + .tlevel = ft3_tlevels, +}; + +static enum test_result func_test3(struct test_config *tcfg) +{ + enum test_result result = PASS; + uint32_t i = 0; + + printf("%s", tcfg->msg); + + if (test_rte_pie_init(tcfg) != PASS) { + result = FAIL; + goto out; + } + + printf("%s", tcfg->htxt); + + /** + * reset rte_pie run-time data + */ + rte_pie_rt_data_init(tcfg->tqueue->pdata_in); + rte_pie_set_active(NULL, tcfg->tqueue->pdata_in, 1); + *tcfg->tvar->enqueued = 0; + *tcfg->tvar->dropped = 0; + + if (increase_qsize(&tcfg->tconfig->pconfig[i], + tcfg->tqueue->pdata_in, + tcfg->tqueue->qlen, + tcfg->tlevel[i], + tcfg->tqueue->q_ramp_up) != 0) { + fprintf(stderr, "Fail: increase qsize\n"); + result = FAIL; + goto out; + } + + for (i = 0; i < RTE_DIM(ft_tlevels); i++) { + const char *label = NULL; + uint16_t prob = 0; + uint16_t active = 0; + double drop_rate = 1.0; + double drop_prob = 0.0; + double diff = 0.0; + + enqueue_dequeue_func(&tcfg->tconfig->pconfig[i], + tcfg->tqueue->pdata_in, + tcfg->tqueue->qlen, + tcfg->tvar->num_ops, + tcfg->tvar->enqueued, + tcfg->tvar->dropped); + + drop_rate = calc_drop_rate(*tcfg->tvar->enqueued, + *tcfg->tvar->dropped); + drop_prob = rte_pie_get_drop_prob(NULL, tcfg->tqueue->pdata_in); + + if (drop_prob != 0) { + fprintf(stderr, "Fail: check drop prob\n"); + result = FAIL; + } + + if (drop_rate != 0) { + fprintf(stderr, "Fail: check drop rate\n"); + result = FAIL; + } + + label = "Summary "; + active = rte_pie_get_active(NULL, tcfg->tqueue->pdata_in); + printf("%s%-16u%-12u%-12u%-12.4lf%-12.4lf%-12.4lf%-12.4lf%-8i\n", + label, prob, *tcfg->tvar->enqueued, *tcfg->tvar->dropped, + drop_prob * 100.0, drop_rate * 100.0, diff, + (double)tcfg->tqueue->drop_tolerance, active); + } +out: + return result; +} + +/** + * setup default values for the Performance test structures + */ +static struct rte_pie_config pt_wrconfig[1]; +static struct rte_pie pt_rtdata[1]; +static struct rte_pie pt_wtdata[1]; +static uint32_t pt_q[] = {0}; +static uint32_t pt_dropped[] = {0}; +static uint32_t pt_enqueued[] = {0}; +static uint32_t pt_dequeued[] = {0}; +static uint16_t pt_max_burst[] = {64}; +static uint16_t pt_dp_update_interval[] = {150}; + +static struct test_rte_pie_config pt_tconfig = { + .pconfig = pt_wrconfig, + .num_cfg = RTE_DIM(pt_wrconfig), + .qdelay_ref = 15, + .dp_update_interval = pt_dp_update_interval, + .max_burst = pt_max_burst, + .tailq_th = 150, +}; + +static struct test_queue pt_tqueue = { + .pdata_in = pt_rtdata, + .num_queues = RTE_DIM(pt_rtdata), + .qlen = pt_q, + .q_ramp_up = 1000000, + .drop_tolerance = 0, /* 0 percent */ +}; + +static struct test_rte_pie_config pt_tconfig2 = { + .pconfig = pt_wrconfig, + .num_cfg = RTE_DIM(pt_wrconfig), + .qdelay_ref = 15, + .dp_update_interval = pt_dp_update_interval, + .max_burst = pt_max_burst, + .tailq_th = 150, +}; + +static struct test_queue pt_tqueue2 = { + .pdata_in = pt_rtdata, + .pdata_out = pt_wtdata, + .num_queues = RTE_DIM(pt_rtdata), + .qlen = pt_q, + .q_ramp_up = 1000000, + .drop_tolerance = 0, /* 0 percent */ +}; + +/** + * enqueue/dequeue packets + * aka + * rte_sched_port_enqueue(port, in_mbufs, 10); + * rte_sched_port_dequeue(port, out_mbufs, 10); + */ +static void enqueue_dequeue_perf(struct rte_pie_config *pie_cfg, + struct rte_pie *pie_in, + struct rte_pie *pie_out, + uint32_t *qlen, + uint32_t num_ops, + uint32_t *enqueued, + uint32_t *dropped, + uint32_t *dequeued, + struct rdtsc_prof *prof) +{ + uint32_t i = 0; + + if (pie_cfg == NULL) { + printf("%s: Error: PIE configuration cannot be empty.\n", __func__); + return; + } + + if (pie_in == NULL) { + printf("%s: Error: PIE enqueue data cannot be empty.\n", __func__); + return; + } + + for (i = 0; i < num_ops; i++) { + uint64_t ts = 0; + int ret = 0; + + /** + * enqueue + */ + ts = get_port_ts(); + rdtsc_prof_start(prof); + ret = rte_pie_enqueue(pie_cfg, pie_in, *qlen, + 1000*sizeof(uint32_t), ts); + rdtsc_prof_end(prof); + + if (ret == 0) + (*enqueued)++; + else + (*dropped)++; + + if (pie_out != NULL) { + ts = get_port_ts(); + rdtsc_prof_start(prof); + rte_pie_dequeue(pie_out, 1000*sizeof(uint32_t), ts); + rdtsc_prof_end(prof); + + (*dequeued)++; + } + } +} + +/** + * Setup test structures for tests P1 + * performance tests 1 + */ +static uint32_t pt1_tlevel[] = {80}; + +static struct test_var perf1_tvar = { + .num_iterations = 0, + .num_ops = 30000, + .clk_freq = 0, + .dropped = pt_dropped, + .enqueued = pt_enqueued +}; + +static struct test_config perf_test_config = { + .ifname = "performance test 1 interface", + .msg = "performance test 1 : use one PIE configuration,\n" + " measure enqueue performance\n\n", + .tconfig = &pt_tconfig, + .tqueue = &pt_tqueue, + .tvar = &perf1_tvar, + .tlevel = pt1_tlevel, +}; + +/** + * Performance test function to measure enqueue performance. + * + */ +static enum test_result perf_test(struct test_config *tcfg) +{ + enum test_result result = PASS; + struct rdtsc_prof prof = {0, 0, 0, 0, 0.0, NULL}; + uint32_t total = 0; + + printf("%s", tcfg->msg); + + rdtsc_prof_init(&prof, "enqueue"); + + if (test_rte_pie_init(tcfg) != PASS) { + result = FAIL; + goto out; + } + + /** + * initialize the rte_pie run time data structure + */ + rte_pie_rt_data_init(tcfg->tqueue->pdata_in); + rte_pie_set_active(NULL, tcfg->tqueue->pdata_in, 1); + *tcfg->tvar->enqueued = 0; + *tcfg->tvar->dropped = 0; + + enqueue_dequeue_perf(tcfg->tconfig->pconfig, + tcfg->tqueue->pdata_in, + NULL, + tcfg->tqueue->qlen, + tcfg->tvar->num_ops, + tcfg->tvar->enqueued, + tcfg->tvar->dropped, + tcfg->tvar->dequeued, + &prof); + + total = *tcfg->tvar->enqueued + *tcfg->tvar->dropped; + + printf("\ntotal: %u, enqueued: %u (%.2lf%%), dropped: %u (%.2lf%%)\n", + total, *tcfg->tvar->enqueued, + ((double)(*tcfg->tvar->enqueued) / (double)total) * 100.0, + *tcfg->tvar->dropped, + ((double)(*tcfg->tvar->dropped) / (double)total) * 100.0); + + rdtsc_prof_print(&prof); +out: + return result; +} + + + +/** + * Setup test structures for tests P2 + * performance tests 2 + */ +static uint32_t pt2_tlevel[] = {80}; + +static struct test_var perf2_tvar = { + .num_iterations = 0, + .num_ops = 30000, + .clk_freq = 0, + .dropped = pt_dropped, + .enqueued = pt_enqueued, + .dequeued = pt_dequeued +}; + +static struct test_config perf_test_config2 = { + .ifname = "performance test 2 interface", + .msg = "performance test 2 : use one PIE configuration,\n" + " measure enqueue & dequeue performance\n\n", + .tconfig = &pt_tconfig2, + .tqueue = &pt_tqueue2, + .tvar = &perf2_tvar, + .tlevel = pt2_tlevel, +}; + +/** + * Performance test function to measure enqueue & dequeue performance. + * + */ +static enum test_result perf_test2(struct test_config *tcfg) +{ + enum test_result result = PASS; + struct rdtsc_prof prof = {0, 0, 0, 0, 0.0, NULL}; + uint32_t total = 0; + + printf("%s", tcfg->msg); + + rdtsc_prof_init(&prof, "enqueue"); + + if (test_rte_pie_init(tcfg) != PASS) { + result = FAIL; + goto out; + } + + /** + * initialize the rte_pie run time data structure + */ + rte_pie_rt_data_init(tcfg->tqueue->pdata_in); + rte_pie_set_active(NULL, tcfg->tqueue->pdata_in, 1); + *tcfg->tvar->enqueued = 0; + *tcfg->tvar->dequeued = 0; + *tcfg->tvar->dropped = 0; + + enqueue_dequeue_perf(tcfg->tconfig->pconfig, + tcfg->tqueue->pdata_in, + tcfg->tqueue->pdata_out, + tcfg->tqueue->qlen, + tcfg->tvar->num_ops, + tcfg->tvar->enqueued, + tcfg->tvar->dropped, + tcfg->tvar->dequeued, + &prof); + + total = *tcfg->tvar->enqueued + *tcfg->tvar->dropped; + + printf("\ntotal: %u, dequeued: %u (%.2lf%%), dropped: %u (%.2lf%%)\n", + total, *tcfg->tvar->dequeued, + ((double)(*tcfg->tvar->dequeued) / (double)total) * 100.0, + *tcfg->tvar->dropped, + ((double)(*tcfg->tvar->dropped) / (double)total) * 100.0); + + rdtsc_prof_print(&prof); +out: + return result; +} + +/** + * define the functional tests to be executed fast + */ +struct tests func_pie_tests_quick[] = { + { &func_test_config1, func_test1 }, + { &func_test_config2, func_test2 }, +}; + +/** + * define the functional and performance tests to be executed + */ +struct tests func_pie_tests[] = { + { &func_test_config1, func_test1 }, + { &func_test_config2, func_test2 }, + { &func_test_config3, func_test3 }, +}; + +struct tests perf_pie_tests[] = { + { &perf_test_config, perf_test }, + { &perf_test_config2, perf_test2 }, +}; + +/** + * function to execute the required pie tests + */ +static void run_tests(struct tests *test_type, uint32_t test_count, + uint32_t *num_tests, uint32_t *num_pass) +{ + enum test_result result = PASS; + uint32_t i = 0; + static const char *bar_str = "-------------------------------------" + "-------------------------------------------"; + static const char *bar_pass_str = "-------------------------------------" + "-------------------------------------"; + static const char *bar_fail_str = "-------------------------------------" + "-------------------------------------"; + + for (i = 0; i < test_count; i++) { + printf("\n%s\n", bar_str); + result = test_type[i].testfn(test_type[i].testcfg); + (*num_tests)++; + if (result == PASS) { + (*num_pass)++; + printf("%s\n", bar_pass_str); + } else { + printf("%s\n", bar_fail_str); + } + } +} + +/** + * check if functions accept invalid parameters + * + * First, all functions will be called without initialized PIE + * Then, all of them will be called with NULL/invalid parameters + * + * Some functions are not tested as they are performance-critical and thus + * don't do any parameter checking. + */ +static int +test_invalid_parameters(void) +{ + struct rte_pie_config config; + static const char *shf_str = "rte_pie_config_init should have failed!"; + static const char *shf_rt_str = "rte_pie_rt_data_init should have failed!"; + + /* NULL config */ + if (rte_pie_rt_data_init(NULL) == 0) { + printf("%i: %s\n", __LINE__, shf_rt_str); + return -1; + } + + /* NULL config */ + if (rte_pie_config_init(NULL, 0, 0, 0, 0) == 0) { + printf("%i%s\n", __LINE__, shf_str); + return -1; + } + + /* qdelay_ref <= 0 */ + if (rte_pie_config_init(&config, 0, 1, 1, 1) == 0) { + printf("%i%s\n", __LINE__, shf_str); + return -1; + } + + /* dp_update_interval <= 0 */ + if (rte_pie_config_init(&config, 1, 0, 1, 1) == 0) { + printf("%i%s\n", __LINE__, shf_str); + return -1; + } + + /* max_burst <= 0 */ + if (rte_pie_config_init(&config, 1, 1, 0, 1) == 0) { + printf("%i%s\n", __LINE__, shf_str); + return -1; + } + + /* tailq_th <= 0 */ + if (rte_pie_config_init(&config, 1, 1, 1, 0) == 0) { + printf("%i%s\n", __LINE__, shf_str); + return -1; + } + + RTE_SET_USED(config); + + return 0; +} + +static void +show_stats(const uint32_t num_tests, const uint32_t num_pass) +{ + if (num_pass == num_tests) + printf("[total: %u, pass: %u]\n", num_tests, num_pass); + else + printf("[total: %u, pass: %u, fail: %u]\n", num_tests, num_pass, + num_tests - num_pass); +} + +static int +tell_the_result(const uint32_t num_tests, const uint32_t num_pass) +{ + return (num_pass == num_tests) ? 0 : 1; +} + +static int +test_pie(void) +{ + uint32_t num_tests = 0; + uint32_t num_pass = 0; + + if (test_invalid_parameters() < 0) + return -1; + + run_tests(func_pie_tests_quick, RTE_DIM(func_pie_tests_quick), + &num_tests, &num_pass); + show_stats(num_tests, num_pass); + return tell_the_result(num_tests, num_pass); +} + +static int +test_pie_perf(void) +{ + uint32_t num_tests = 0; + uint32_t num_pass = 0; + + run_tests(perf_pie_tests, RTE_DIM(perf_pie_tests), &num_tests, &num_pass); + show_stats(num_tests, num_pass); + return tell_the_result(num_tests, num_pass); +} + +static int +test_pie_all(void) +{ + uint32_t num_tests = 0; + uint32_t num_pass = 0; + + if (test_invalid_parameters() < 0) + return -1; + + run_tests(func_pie_tests, RTE_DIM(func_pie_tests), &num_tests, &num_pass); + run_tests(perf_pie_tests, RTE_DIM(perf_pie_tests), &num_tests, &num_pass); + show_stats(num_tests, num_pass); + return tell_the_result(num_tests, num_pass); +} + +REGISTER_TEST_COMMAND(pie_autotest, test_pie); +REGISTER_TEST_COMMAND(pie_perf, test_pie_perf); +REGISTER_TEST_COMMAND(pie_all, test_pie_all); diff --git a/lib/sched/rte_pie.c b/lib/sched/rte_pie.c index 2fcecb2db4..934e9aee50 100644 --- a/lib/sched/rte_pie.c +++ b/lib/sched/rte_pie.c @@ -13,7 +13,7 @@ #pragma warning(disable:2259) /* conversion may lose significant bits */ #endif -void +int rte_pie_rt_data_init(struct rte_pie *pie) { if (pie == NULL) { @@ -22,6 +22,8 @@ rte_pie_rt_data_init(struct rte_pie *pie) if (pie == NULL) RTE_LOG(ERR, SCHED, "%s: Memory allocation fails\n", __func__); + + return -1; } pie->active = 0; @@ -35,6 +37,8 @@ rte_pie_rt_data_init(struct rte_pie *pie) pie->qdelay_old = 0; pie->drop_prob = 0; pie->accu_prob = 0; + + return 0; } int diff --git a/lib/sched/rte_pie.h b/lib/sched/rte_pie.h index f83c95664f..d9cf61e04c 100644 --- a/lib/sched/rte_pie.h +++ b/lib/sched/rte_pie.h @@ -20,6 +20,7 @@ extern "C" { #include #include +#include #define RTE_DQ_THRESHOLD 16384 /**< Queue length threshold (2^14) * to start measurement cycle (bytes) @@ -53,7 +54,7 @@ struct rte_pie_config { }; /** - * RED run-time data + * PIE run-time data */ struct rte_pie { uint16_t active; /**< Flag for activating/deactivating pie */ @@ -74,8 +75,12 @@ struct rte_pie { * @brief Initialises run-time data * * @param pie [in,out] data pointer to PIE runtime data + * + * @return Operation status + * @retval 0 success + * @retval !0 error */ -void +int __rte_experimental rte_pie_rt_data_init(struct rte_pie *pie); diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c index 320435ed91..480b6e531d 100644 --- a/lib/sched/rte_sched.c +++ b/lib/sched/rte_sched.c @@ -1877,7 +1877,7 @@ rte_sched_port_aqm_drop(struct rte_sched_port *port, struct rte_pie_config *pie_cfg = &subport->pie_config[tc_index]; struct rte_pie *pie = &qe->pie; - return rte_pie_enqueue(pie_cfg, pie, pkt->pkt_len, qlen, port->time_cpu_cycles); + return rte_pie_enqueue(pie_cfg, pie, qlen, pkt->pkt_len, port->time_cpu_cycles); } static inline void