From patchwork Mon Sep 20 07:42:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 99297 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6D6DEA0548; Mon, 20 Sep 2021 09:42:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5AD70410EE; Mon, 20 Sep 2021 09:42:22 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.231]) by mails.dpdk.org (Postfix) with ESMTP id 7F35D40DF5 for ; Mon, 20 Sep 2021 09:42:20 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 02813EA; Mon, 20 Sep 2021 00:42:18 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 02813EA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1632123739; bh=0RrJ5ZF6g4lXYBzPCurYhuQ/B5jPWAqIFXP5qgGmXp8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ey82//V2A9HkdMAGbFpm4IfRLL8VwWfVpWxCC0L9bAxOJK8GvgcbUYJsJ0hQrakN9 ZCcxmLXXBB2Zfprtr5A3pSanXVq24BgynUhqnd8CTo7GTSDHGlKzb0fQFBUJPi8OFt ElMHXTvdlep645ijmgK5lf5wl2wRnJhGaXmJHRkA= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith Date: Mon, 20 Sep 2021 13:12:02 +0530 Message-Id: <20210920074214.23747-2-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> References: <20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com> <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH v4 01/13] net/bnxt: updates to TF core index table X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Update the TRUFLOW core index table and remove unused shadow table functionality. Signed-off-by: Farah Smith Reviewed-by: Peter Spreadborough Acked-by: Ajit Khaparde --- drivers/net/bnxt/tf_core/tf_core.c | 65 -------------- drivers/net/bnxt/tf_core/tf_core.h | 103 +---------------------- drivers/net/bnxt/tf_core/tf_device.h | 22 ----- drivers/net/bnxt/tf_core/tf_device_p4.c | 2 - drivers/net/bnxt/tf_core/tf_device_p58.c | 2 - drivers/net/bnxt/tf_core/tf_em_common.c | 4 + drivers/net/bnxt/tf_core/tf_tbl.c | 21 ----- drivers/net/bnxt/tf_core/tf_tbl.h | 72 ---------------- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 3 +- 9 files changed, 7 insertions(+), 287 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 97e6165e92..5458f76e2d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1105,71 +1105,6 @@ tf_alloc_tbl_entry(struct tf *tfp, return 0; } -int -tf_search_tbl_entry(struct tf *tfp, - struct tf_search_tbl_entry_parms *parms) -{ - int rc; - struct tf_session *tfs; - struct tf_dev_info *dev; - struct tf_tbl_alloc_search_parms sparms; - - TF_CHECK_PARMS2(tfp, parms); - - /* Retrieve the session information */ - rc = tf_session_get_session(tfp, &tfs); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup session, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - /* Retrieve the device information */ - rc = tf_session_get_device(tfs, &dev); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to lookup device, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - if (dev->ops->tf_dev_alloc_search_tbl == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - memset(&sparms, 0, sizeof(struct tf_tbl_alloc_search_parms)); - sparms.dir = parms->dir; - sparms.type = parms->type; - sparms.result = parms->result; - sparms.result_sz_in_bytes = parms->result_sz_in_bytes; - sparms.alloc = parms->alloc; - sparms.tbl_scope_id = parms->tbl_scope_id; - rc = dev->ops->tf_dev_alloc_search_tbl(tfp, &sparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: TBL allocation failed, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; - } - - /* Return the outputs from the search */ - parms->hit = sparms.hit; - parms->search_status = sparms.search_status; - parms->ref_cnt = sparms.ref_cnt; - parms->idx = sparms.idx; - - return 0; -} - int tf_free_tbl_entry(struct tf *tfp, struct tf_free_tbl_entry_parms *parms) diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 84b234f0e3..7e0cdf7e0d 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -1622,79 +1622,6 @@ int tf_clear_tcam_shared_entries(struct tf *tfp, * @ref tf_get_shared_tbl_increment */ -/** - * tf_alloc_tbl_entry parameter definition - */ -struct tf_search_tbl_entry_parms { - /** - * [in] Receive or transmit direction - */ - enum tf_dir dir; - /** - * [in] Type of the allocation - */ - enum tf_tbl_type type; - /** - * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT) - */ - uint32_t tbl_scope_id; - /** - * [in] Result data to search for - */ - uint8_t *result; - /** - * [in] Result data size in bytes - */ - uint16_t result_sz_in_bytes; - /** - * [in] Allocate on miss. - */ - uint8_t alloc; - /** - * [out] Set if matching entry found - */ - uint8_t hit; - /** - * [out] Search result status (hit, miss, reject) - */ - enum tf_search_status search_status; - /** - * [out] Current ref count after allocation - */ - uint16_t ref_cnt; - /** - * [out] Idx of allocated entry or found entry - */ - uint32_t idx; -}; - -/** - * search Table Entry (experimental) - * - * This function searches the shadow copy of an index table for a matching - * entry. The result data must match for hit to be set. Only TruFlow core - * data is accessed. If shadow_copy is not enabled, an error is returned. - * - * Implementation: - * - * A hash is performed on the result data and mapped to a shadow copy entry - * where the result is populated. If the result matches the entry, hit is set, - * ref_cnt is incremented (if alloc), and the search status indicates what - * action the caller can take regarding setting the entry. - * - * search status should be used as follows: - * - On MISS, the caller should set the result into the returned index. - * - * - On REJECT, the caller should reject the flow since there are no resources. - * - * - On Hit, the matching index is returned to the caller. Additionally, the - * ref_cnt is updated. - * - * Also returns success or failure code. - */ -int tf_search_tbl_entry(struct tf *tfp, - struct tf_search_tbl_entry_parms *parms); - /** * tf_alloc_tbl_entry parameter definition */ @@ -1711,30 +1638,9 @@ struct tf_alloc_tbl_entry_parms { * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT) */ uint32_t tbl_scope_id; + /** - * [in] Enable search for matching entry. If the table type is - * internal the shadow copy will be searched before - * alloc. Session must be configured with shadow copy enabled. - */ - uint8_t search_enable; - /** - * [in] Result data to search for (if search_enable) - */ - uint8_t *result; - /** - * [in] Result data size in bytes (if search_enable) - */ - uint16_t result_sz_in_bytes; - /** - * [out] If search_enable, set if matching entry found - */ - uint8_t hit; - /** - * [out] Current ref count after allocation (if search_enable) - */ - uint16_t ref_cnt; - /** - * [out] Idx of allocated entry or found entry (if search_enable) + * [out] Idx of allocated entry */ uint32_t idx; }; @@ -1790,11 +1696,6 @@ struct tf_free_tbl_entry_parms { * [in] Index to free */ uint32_t idx; - /** - * [out] Reference count after free, only valid if session has been - * created with shadow_copy. - */ - uint16_t ref_cnt; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index da3f541685..b43cfc6925 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -347,28 +347,6 @@ struct tf_dev_ops { int (*tf_dev_free_ext_tbl)(struct tf *tfp, struct tf_tbl_free_parms *parms); - /** - * Searches for the specified table type element in a shadow DB. - * - * This API searches for the specified table type element in a - * device specific shadow DB. If the element is found the - * reference count for the element is updated. If the element - * is not found a new element is allocated from the table type - * DB and then inserted into the shadow DB. - * - * [in] tfp - * Pointer to TF handle - * - * [in] parms - * Pointer to table allocation and search parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ - int (*tf_dev_alloc_search_tbl)(struct tf *tfp, - struct tf_tbl_alloc_search_parms *parms); - /** * Sets the specified table type element. * diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 971fab7bda..2e7ccec123 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -236,7 +236,6 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_alloc_tbl = NULL, .tf_dev_free_ext_tbl = NULL, .tf_dev_free_tbl = NULL, - .tf_dev_alloc_search_tbl = NULL, .tf_dev_set_tbl = NULL, .tf_dev_set_ext_tbl = NULL, .tf_dev_get_tbl = NULL, @@ -282,7 +281,6 @@ const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, .tf_dev_free_tbl = tf_tbl_free, .tf_dev_free_ext_tbl = tf_tbl_ext_free, - .tf_dev_alloc_search_tbl = tf_tbl_alloc_search, .tf_dev_set_tbl = tf_tbl_set, .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, .tf_dev_get_tbl = tf_tbl_get, diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 6bbc5e21e9..ce4d8c661f 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -280,7 +280,6 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_alloc_tbl = NULL, .tf_dev_free_ext_tbl = NULL, .tf_dev_free_tbl = NULL, - .tf_dev_alloc_search_tbl = NULL, .tf_dev_set_tbl = NULL, .tf_dev_set_ext_tbl = NULL, .tf_dev_get_tbl = NULL, @@ -326,7 +325,6 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, .tf_dev_free_tbl = tf_tbl_free, .tf_dev_free_ext_tbl = tf_tbl_ext_free, - .tf_dev_alloc_search_tbl = tf_tbl_alloc_search, .tf_dev_set_tbl = tf_tbl_set, .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, .tf_dev_get_tbl = tf_tbl_get, diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index 812ccb0d29..3bdfc14e05 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -23,6 +23,10 @@ #include "bnxt.h" + +/** Invalid table scope id */ +#define TF_TBL_SCOPE_INVALID 0xffffffff + /* Number of pointers per page_size */ #define MAX_PAGE_PTRS(page_size) ((page_size) / sizeof(void *)) diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index ced59130b2..e77399c6bd 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -26,11 +26,6 @@ struct tf; -/** - * Table Shadow DBs - */ -static void *shadow_tbl_db[TF_DIR_MAX]; - /** * Shadow init flag, set on bind and cleared on unbind */ @@ -327,22 +322,6 @@ tf_tbl_free(struct tf *tfp __rte_unused, return 0; } -int -tf_tbl_alloc_search(struct tf *tfp, - struct tf_tbl_alloc_search_parms *parms) -{ - int rc = 0; - TF_CHECK_PARMS2(tfp, parms); - - if (!shadow_init || !shadow_tbl_db[parms->dir]) { - TFP_DRV_LOG(ERR, "%s: Shadow TBL not initialized.\n", - tf_dir_2_str(parms->dir)); - return -EINVAL; - } - - return rc; -} - int tf_tbl_set(struct tf *tfp, struct tf_tbl_set_parms *parms) diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h index aba46fd161..7e1107ffe7 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_tbl.h @@ -15,8 +15,6 @@ struct tf; * The Table module provides processing of Internal TF table types. */ -/** Invalid table scope id */ -#define TF_TBL_SCOPE_INVALID 0xffffffff /** * Table configuration parameters @@ -86,57 +84,6 @@ struct tf_tbl_free_parms { * [in] Index to free */ uint32_t idx; - /** - * [out] Reference count after free, only valid if session has been - * created with shadow_copy. - */ - uint16_t ref_cnt; -}; - -/** - * Table allocate search parameters - */ -struct tf_tbl_alloc_search_parms { - /** - * [in] Receive or transmit direction - */ - enum tf_dir dir; - /** - * [in] Type of the allocation - */ - enum tf_tbl_type type; - /** - * [in] Table scope identifier (ignored unless TF_TBL_TYPE_EXT) - */ - uint32_t tbl_scope_id; - /** - * [in] Result data to search for - */ - uint8_t *result; - /** - * [in] Result data size in bytes - */ - uint16_t result_sz_in_bytes; - /** - * [in] Whether or not to allocate on MISS, 1 is allocate. - */ - uint8_t alloc; - /** - * [out] If search_enable, set if matching entry found - */ - uint8_t hit; - /** - * [out] The status of the search (REJECT, MISS, HIT) - */ - enum tf_search_status search_status; - /** - * [out] Current ref count after allocation - */ - uint16_t ref_cnt; - /** - * [out] Idx of allocated entry or found entry - */ - uint32_t idx; }; /** @@ -326,25 +273,6 @@ int tf_tbl_alloc(struct tf *tfp, int tf_tbl_free(struct tf *tfp, struct tf_tbl_free_parms *parms); -/** - * Supported if Shadow DB is configured. Searches the Shadow DB for - * any matching element. If found the refcount in the shadow DB is - * updated accordingly. If not found a new element is allocated and - * installed into the shadow DB. - * - * [in] tfp - * Pointer to TF handle, used for HCAPI communication - * - * [in] parms - * Pointer to parameters - * - * Returns - * - (0) if successful. - * - (-EINVAL) on failure. - */ -int tf_tbl_alloc_search(struct tf *tfp, - struct tf_tbl_alloc_search_parms *parms); - /** * Configures the requested element by sending a firmware request which * then installs it into the device internal structures. diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 871dbad0fe..f3a60cc880 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -189,13 +189,12 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, aparms.type = glb_res->resource_type; aparms.dir = glb_res->direction; - aparms.search_enable = 0; aparms.tbl_scope_id = tbl_scope_id; /* Allocate the index tbl using tf api */ rc = tf_alloc_tbl_entry(tfp, &aparms); if (rc) { - BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n", + BNXT_TF_DBG(ERR, "Failed to alloc index table [%s][%d]\n", tf_dir_2_str(aparms.dir), aparms.type); return rc; } From patchwork Mon Sep 20 07:42:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 99298 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36BFDA0548; Mon, 20 Sep 2021 09:42:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E7AB4410F4; Mon, 20 Sep 2021 09:42:29 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) by mails.dpdk.org (Postfix) with ESMTP id EC54F410EB for ; Mon, 20 Sep 2021 09:42:21 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 6FE69E5; Mon, 20 Sep 2021 00:42:20 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 6FE69E5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1632123741; bh=5A8XjubdMbek8/cGLDY9F4YJJKl7jZ9Hg99+lWyONuk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QyzBtSElV/BkqU2mZGKBt8lZ7PKRdMHDkS57X+eIN2y/vq/pwYnL3W5gJ2XTTa2le gGZ7HbNU1a1JeULRYM9RQcD5X6JvxlqIAXOdVoj8DHIPjDI2SfG+YFIEq3NzAEMXti qeREhYJEJIC5xdjr4TQyfZyDmi0p7ZCNa07sNqnU= From: Venkat Duvvuru To: dev@dpdk.org Cc: Peter Spreadborough Date: Mon, 20 Sep 2021 13:12:03 +0530 Message-Id: <20210920074214.23747-3-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> References: <20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com> <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH v4 02/13] net/bnxt: enable dpool allocator X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Peter Spreadborough Enable dynamic entry allocator for Exact Match SRAM entries. Deprecate static entry allocator code. Signed-off-by: Peter Spreadborough Reviewed-by: Randy Schacher Acked-by: Ajit Khaparde --- drivers/net/bnxt/tf_core/tf_device_p58.c | 4 - drivers/net/bnxt/tf_core/tf_em.h | 10 - .../net/bnxt/tf_core/tf_em_hash_internal.c | 34 ---- drivers/net/bnxt/tf_core/tf_em_internal.c | 180 +----------------- 4 files changed, 1 insertion(+), 227 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index ce4d8c661f..808dcb1f77 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -348,11 +348,7 @@ const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, -#if (TF_EM_ALLOC == 1) .tf_dev_move_int_em_entry = tf_em_move_int_entry, -#else - .tf_dev_move_int_em_entry = NULL, -#endif .tf_dev_insert_ext_em_entry = NULL, .tf_dev_delete_ext_em_entry = NULL, .tf_dev_get_em_resc_info = tf_em_get_resc_info, diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 568071ad8c..074c128651 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -13,16 +13,6 @@ #include "hcapi_cfa_defs.h" -/** - * TF_EM_ALLOC - * - * 0: Use stack allocator with fixed sized entries - * (default). - * 1: Use dpool allocator with variable size - * entries. - */ -#define TF_EM_ALLOC 0 - #define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */ #define TF_EM_MAX_ENTRIES (1 << 27) /* 128M */ diff --git a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c index 098e8af07e..60273a798c 100644 --- a/drivers/net/bnxt/tf_core/tf_em_hash_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_hash_internal.c @@ -22,9 +22,7 @@ /** * EM Pool */ -#if (TF_EM_ALLOC == 1) #include "dpool.h" -#endif /** * Insert EM internal entry API @@ -41,11 +39,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, uint16_t rptr_index = 0; uint8_t rptr_entry = 0; uint8_t num_of_entries = 0; -#if (TF_EM_ALLOC == 1) struct dpool *pool; -#else - struct stack *pool; -#endif uint32_t index; uint32_t key0_hash; uint32_t key1_hash; @@ -62,7 +56,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp, rc = tf_session_get_device(tfs, &dev); if (rc) return rc; -#if (TF_EM_ALLOC == 1) pool = (struct dpool *)tfs->em_pool[parms->dir]; index = dpool_alloc(pool, parms->em_record_sz_in_bits / 128, @@ -74,16 +67,6 @@ tf_em_hash_insert_int_entry(struct tf *tfp, tf_dir_2_str(parms->dir)); return -1; } -#else - pool = (struct stack *)tfs->em_pool[parms->dir]; - rc = stack_pop(pool, &index); - if (rc) { - PMD_DRV_LOG(ERR, - "%s, EM entry index allocation failed\n", - tf_dir_2_str(parms->dir)); - return rc; - } -#endif if (dev->ops->tf_dev_cfa_key_hash == NULL) return -EINVAL; @@ -103,11 +86,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, &num_of_entries); if (rc) { /* Free the allocated index before returning */ -#if (TF_EM_ALLOC == 1) dpool_free(pool, index); -#else - stack_push(pool, index); -#endif return -1; } @@ -128,9 +107,7 @@ tf_em_hash_insert_int_entry(struct tf *tfp, rptr_index, rptr_entry, 0); -#if (TF_EM_ALLOC == 1) dpool_set_entry_data(pool, index, parms->flow_handle); -#endif return 0; } @@ -146,11 +123,7 @@ tf_em_hash_delete_int_entry(struct tf *tfp, { int rc = 0; struct tf_session *tfs; -#if (TF_EM_ALLOC == 1) struct dpool *pool; -#else - struct stack *pool; -#endif /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); if (rc) { @@ -165,19 +138,13 @@ tf_em_hash_delete_int_entry(struct tf *tfp, /* Return resource to pool */ if (rc == 0) { -#if (TF_EM_ALLOC == 1) pool = (struct dpool *)tfs->em_pool[parms->dir]; dpool_free(pool, parms->index); -#else - pool = (struct stack *)tfs->em_pool[parms->dir]; - stack_push(pool, parms->index); -#endif } return rc; } -#if (TF_EM_ALLOC == 1) /** Move EM internal entry API * * returns: @@ -212,4 +179,3 @@ tf_em_move_int_entry(struct tf *tfp, return rc; } -#endif diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c index 0720bb905d..2d57595f17 100644 --- a/drivers/net/bnxt/tf_core/tf_em_internal.c +++ b/drivers/net/bnxt/tf_core/tf_em_internal.c @@ -22,145 +22,7 @@ /** * EM Pool */ -#if (TF_EM_ALLOC == 1) #include "dpool.h" -#else - -/** - * Create EM Tbl pool of memory indexes. - * - * [in] dir - * direction - * [in] num_entries - * number of entries to write - * [in] start - * starting offset - * - * Return: - * 0 - Success, entry allocated - no search support - * -ENOMEM -EINVAL -EOPNOTSUPP - * - Failure, entry not allocated, out of resources - */ -static int -tf_create_em_pool(struct tf_session *tfs, - enum tf_dir dir, - uint32_t num_entries, - uint32_t start) -{ - struct tfp_calloc_parms parms; - uint32_t i, j; - int rc = 0; - struct stack *pool; - - /* - * Allocate stack pool - */ - parms.nitems = 1; - parms.size = sizeof(struct stack); - parms.alignment = 0; - - rc = tfp_calloc(&parms); - - if (rc) { - TFP_DRV_LOG(ERR, - "%s, EM stack allocation failure %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - pool = (struct stack *)parms.mem_va; - tfs->em_pool[dir] = (void *)pool; - - /* Assumes that num_entries has been checked before we get here */ - parms.nitems = num_entries / TF_SESSION_EM_ENTRY_SIZE; - parms.size = sizeof(uint32_t); - parms.alignment = 0; - - rc = tfp_calloc(&parms); - - if (rc) { - TFP_DRV_LOG(ERR, - "%s, EM pool allocation failure %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - return rc; - } - - /* Create empty stack - */ - rc = stack_init(num_entries / TF_SESSION_EM_ENTRY_SIZE, - (uint32_t *)parms.mem_va, - pool); - - if (rc) { - TFP_DRV_LOG(ERR, - "%s, EM pool stack init failure %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - goto cleanup; - } - - /* Fill pool with indexes - */ - j = start + num_entries - TF_SESSION_EM_ENTRY_SIZE; - - for (i = 0; i < (num_entries / TF_SESSION_EM_ENTRY_SIZE); i++) { - rc = stack_push(pool, j); - if (rc) { - TFP_DRV_LOG(ERR, - "%s, EM pool stack push failure %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - goto cleanup; - } - - j -= TF_SESSION_EM_ENTRY_SIZE; - } - - if (!stack_is_full(pool)) { - rc = -EINVAL; - TFP_DRV_LOG(ERR, - "%s, EM pool stack failure %s\n", - tf_dir_2_str(dir), - strerror(-rc)); - goto cleanup; - } - - return 0; -cleanup: - tfp_free((void *)parms.mem_va); - tfp_free((void *)tfs->em_pool[dir]); - tfs->em_pool[dir] = NULL; - return rc; -} - -/** - * Create EM Tbl pool of memory indexes. - * - * [in] dir - * direction - * - * Return: - */ -static void -tf_free_em_pool(struct tf_session *tfs, - enum tf_dir dir) -{ - struct stack *pool = (struct stack *)tfs->em_pool[dir]; - uint32_t *ptr; - - if (pool != NULL) { - ptr = stack_items(pool); - - if (ptr != NULL) - tfp_free(ptr); - - tfp_free(pool); - tfs->em_pool[dir] = NULL; - } -} -#endif /* TF_EM_ALLOC != 1 */ /** * Insert EM internal entry API @@ -178,11 +40,7 @@ tf_em_insert_int_entry(struct tf *tfp, uint8_t rptr_entry = 0; uint8_t num_of_entries = 0; struct tf_session *tfs; -#if (TF_EM_ALLOC == 1) struct dpool *pool; -#else - struct stack *pool; -#endif uint32_t index; /* Retrieve the session information */ @@ -195,7 +53,6 @@ tf_em_insert_int_entry(struct tf *tfp, return rc; } -#if (TF_EM_ALLOC == 1) pool = (struct dpool *)tfs->em_pool[parms->dir]; index = dpool_alloc(pool, TF_SESSION_EM_ENTRY_SIZE, 0); if (index == DP_INVALID_INDEX) { @@ -204,16 +61,6 @@ tf_em_insert_int_entry(struct tf *tfp, tf_dir_2_str(parms->dir)); return -1; } -#else - pool = (struct stack *)tfs->em_pool[parms->dir]; - rc = stack_pop(pool, &index); - if (rc) { - PMD_DRV_LOG(ERR, - "%s, EM entry index allocation failed\n", - tf_dir_2_str(parms->dir)); - return rc; - } -#endif rptr_index = index; @@ -224,11 +71,7 @@ tf_em_insert_int_entry(struct tf *tfp, &num_of_entries); if (rc) { /* Free the allocated index before returning */ -#if (TF_EM_ALLOC == 1) dpool_free(pool, index); -#else - stack_push(pool, index); -#endif return -1; } TF_SET_GFID(gfid, @@ -264,11 +107,7 @@ tf_em_delete_int_entry(struct tf *tfp, { int rc = 0; struct tf_session *tfs; -#if (TF_EM_ALLOC == 1) struct dpool *pool; -#else - struct stack *pool; -#endif /* Retrieve the session information */ rc = tf_session_get_session(tfp, &tfs); if (rc) { @@ -283,19 +122,13 @@ tf_em_delete_int_entry(struct tf *tfp, /* Return resource to pool */ if (rc == 0) { -#if (TF_EM_ALLOC == 1) pool = (struct dpool *)tfs->em_pool[parms->dir]; dpool_free(pool, parms->index); -#else - pool = (struct stack *)tfs->em_pool[parms->dir]; - stack_push(pool, parms->index); -#endif } return rc; } -#if (TF_EM_ALLOC == 1) static int tf_em_move_callback(void *user_data, uint64_t entry_data, @@ -342,7 +175,6 @@ tf_em_move_callback(void *user_data, return rc; } -#endif int tf_em_int_bind(struct tf *tfp, @@ -434,7 +266,7 @@ tf_em_int_bind(struct tf *tfp, tf_dir_2_str(i)); return rc; } -#if (TF_EM_ALLOC == 1) + /* * Allocate stack pool */ @@ -460,12 +292,6 @@ tf_em_int_bind(struct tf *tfp, 7, (void *)tfp, tf_em_move_callback); -#else - rc = tf_create_em_pool(tfs, - i, - iparms.info->entry.stride, - iparms.info->entry.start); -#endif /* Logging handled in tf_create_em_pool */ if (rc) return rc; @@ -501,11 +327,7 @@ tf_em_int_unbind(struct tf *tfp) if (!tf_session_is_shared_session(tfs)) { for (i = 0; i < TF_DIR_MAX; i++) -#if (TF_EM_ALLOC == 1) dpool_free_all(tfs->em_pool[i]); -#else - tf_free_em_pool(tfs, i); -#endif } rc = tf_session_get_db(tfp, TF_MODULE_TYPE_EM, &em_db_ptr); From patchwork Mon Sep 20 07:42:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 99299 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 333FEA0548; Mon, 20 Sep 2021 09:42:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 505C3410FA; Mon, 20 Sep 2021 09:42:31 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.231]) by mails.dpdk.org (Postfix) with ESMTP id 18141410F4 for ; Mon, 20 Sep 2021 09:42:25 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 5168FEA; Mon, 20 Sep 2021 00:42:21 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 5168FEA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1632123744; bh=LlQuapMPtKSHUOM4NR3qaYcl3AYYMrkUK3brfjADUTk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fVRXQ16o4dlaE4rlbrzlaTe1265hVUzWi8Jg0XZB7bjQcVFu/Ma1erNogDgnyj1xg cGHVk6EJwJUVa7GO8W4Xa+tuIsIn+pRlEZZ5bexfzCV7W+XVvLnJ1Cp83SrC9zLg7j Zh1fhl4/hzYjX9d+kvAFxoUjCgQZjn83dFohfB4I= From: Venkat Duvvuru To: dev@dpdk.org Cc: Jay Ding Date: Mon, 20 Sep 2021 13:12:04 +0530 Message-Id: <20210920074214.23747-4-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> References: <20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com> <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH v4 03/13] net/bnxt: add flow meter drop counter support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding This patch adds flow meter drop counter support for Thor. Signed-off-by: Jay Ding Reviewed-by: Farah Smith Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +- drivers/net/bnxt/tf_core/tf_core.h | 8 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 1 + drivers/net/bnxt/tf_core/tf_device_p58.h | 14 ++++ drivers/net/bnxt/tf_core/tf_tbl.c | 74 +++++++++++-------- drivers/net/bnxt/tf_core/tf_util.c | 2 + 6 files changed, 68 insertions(+), 36 deletions(-) diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index cbab0d0078..36a55d4e17 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -104,10 +104,11 @@ #define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL /* VEB TCAM */ #define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL +/* Metadata */ +#define CFA_RESOURCE_TYPE_P58_METADATA 0x14UL /* Meter drop counter */ #define CFA_RESOURCE_TYPE_P58_METER_DROP_CNT 0x15UL -#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT - +#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_METER_DROP_CNT /* Multicast Group */ #define CFA_RESOURCE_TYPE_P45_MCG 0x0UL diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 7e0cdf7e0d..af8d13bd7e 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -283,9 +283,9 @@ enum tf_tbl_type { TF_TBL_TYPE_ACT_MODIFY_32B, /** TH 64B Modify Record */ TF_TBL_TYPE_ACT_MODIFY_64B, - /** (Future) Meter Profiles */ + /** Meter Profiles */ TF_TBL_TYPE_METER_PROF, - /** (Future) Meter Instance */ + /** Meter Instance */ TF_TBL_TYPE_METER_INST, /** Wh+/SR/Th Mirror Config */ TF_TBL_TYPE_MIRROR_CONFIG, @@ -301,6 +301,8 @@ enum tf_tbl_type { TF_TBL_TYPE_EM_FKB, /** TH WC Flexible Key builder */ TF_TBL_TYPE_WC_FKB, + /** Meter Drop Counter */ + TF_TBL_TYPE_METER_DROP_CNT, /* External */ @@ -2194,6 +2196,8 @@ enum tf_global_config_type { TF_TUNNEL_ENCAP, /**< Tunnel Encap Config(TECT) */ TF_ACTION_BLOCK, /**< Action Block Config(ABCR) */ TF_COUNTER_CFG, /**< Counter Configuration (CNTRS_CTRL) */ + TF_METER_CFG, /**< Meter Config(ACTP4_FMTCR) */ + TF_METER_INTERVAL_CFG, /**< Meter Interval Config(FMTCR_INTERVAL) */ TF_GLOBAL_CFG_TYPE_MAX }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index 808dcb1f77..a492c62bff 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -43,6 +43,7 @@ const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { [CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ", [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", + [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", }; /** diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 66b0f4e983..8c2e07aa34 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -75,10 +75,18 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, 0, 0, 0 }, + [TF_TBL_TYPE_METER_DROP_CNT] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, + 0, 0, 0 + }, [TF_TBL_TYPE_MIRROR_CONFIG] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, 0, 0, 0 }, + [TF_TBL_TYPE_METADATA] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, + 0, 0, 0 + }, /* Policy - ARs in bank 1 */ [TF_TBL_TYPE_FULL_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, @@ -194,5 +202,11 @@ struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = { [TF_COUNTER_CFG] = { TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG }, + [TF_METER_CFG] = { + TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_CFG + }, + [TF_METER_INTERVAL_CFG] = { + TF_GLOBAL_CFG_CFG_HCAPI, TF_METER_INTERVAL_CFG + }, }; #endif /* _TF_DEVICE_P58_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index e77399c6bd..7011edcd78 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -374,23 +374,28 @@ tf_tbl_set(struct tf *tfp, } } - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; - aparms.subtype = parms->type; - TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); - - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + /* Do not check meter drop counter because it is not allocated + * resources + */ + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { + /* Verify that the entry has been previously allocated */ + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.subtype = parms->type; + TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); + + aparms.allocated = &allocated; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%d, idx:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - return -EINVAL; + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated index, type:%d, idx:%d\n", + tf_dir_2_str(parms->dir), + parms->type, + parms->idx); + return -EINVAL; + } } /* Set the entry */ @@ -477,23 +482,28 @@ tf_tbl_get(struct tf *tfp, } } - /* Verify that the entry has been previously allocated */ - aparms.rm_db = tbl_db->tbl_db[parms->dir]; - aparms.subtype = parms->type; - TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); - - aparms.allocated = &allocated; - rc = tf_rm_is_allocated(&aparms); - if (rc) - return rc; + /* Do not check meter drop counter because it is not allocated + * resources. + */ + if (parms->type != TF_TBL_TYPE_METER_DROP_CNT) { + /* Verify that the entry has been previously allocated */ + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + aparms.subtype = parms->type; + TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); + + aparms.allocated = &allocated; + rc = tf_rm_is_allocated(&aparms); + if (rc) + return rc; - if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { - TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%d, idx:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); - return -EINVAL; + if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { + TFP_DRV_LOG(ERR, + "%s, Invalid or not allocated index, type:%d, idx:%d\n", + tf_dir_2_str(parms->dir), + parms->type, + parms->idx); + return -EINVAL; + } } /* Set the entry */ diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index e712816209..d100399d0a 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -112,6 +112,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type) return "WC Flexible Key Builder"; case TF_TBL_TYPE_EXT: return "External"; + case TF_TBL_TYPE_METER_DROP_CNT: + return "Meter drop counter"; default: return "Invalid tbl type"; } From patchwork Mon Sep 20 07:42:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 99300 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7CF9A0548; Mon, 20 Sep 2021 09:42:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8B21041102; Mon, 20 Sep 2021 09:42:32 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) by mails.dpdk.org (Postfix) with ESMTP id 010F1410F4 for ; Mon, 20 Sep 2021 09:42:27 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 109FA46C66; Mon, 20 Sep 2021 00:42:24 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 109FA46C66 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1632123746; bh=rMC/w8gheyPMw683XWfWRx+U00GHNxxTJEXuj/ffkwQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e/9dS7bDYQXBn+vJAXx/B79fzUFDiAFc1y8vahh01b/sdCGLSHCSrRG72Qgq54Erz TD8ScN3u3E/9iPCLpESWtdoFr/Yoyrq0jj5LyGMS5PMesBaZY466GkDuIEAmgMzUZK 4atQbu4KqIDFpn9KUh8Qzy5J/IT98ftfNzRN/NU4= From: Venkat Duvvuru To: dev@dpdk.org Cc: Farah Smith Date: Mon, 20 Sep 2021 13:12:05 +0530 Message-Id: <20210920074214.23747-5-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> References: <20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com> <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH v4 04/13] net/bnxt: add SRAM manager model X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith The SRAM manager supports allocation and free of variable sized records within SRAM memory. These record sizes are 8, 16, 32, or 64B. The SRAM manager algorithm will not fragment memory during run time. Previous implementation only included fixed size 64B records regardless of the size required. Signed-off-by: Farah Smith Reviewed-by: Shahaji Bhosle Reviewed-by: Peter Spreadborough Acked-by: Ajit Khaparde --- drivers/net/bnxt/tf_core/ll.c | 3 + drivers/net/bnxt/tf_core/ll.h | 50 +- drivers/net/bnxt/tf_core/meson.build | 2 + drivers/net/bnxt/tf_core/tf_core.c | 104 ++- drivers/net/bnxt/tf_core/tf_core.h | 48 +- drivers/net/bnxt/tf_core/tf_device.c | 40 +- drivers/net/bnxt/tf_core/tf_device.h | 133 ++- drivers/net/bnxt/tf_core/tf_device_p4.c | 75 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 50 +- drivers/net/bnxt/tf_core/tf_device_p58.c | 105 ++- drivers/net/bnxt/tf_core/tf_device_p58.h | 60 +- drivers/net/bnxt/tf_core/tf_msg.c | 2 +- drivers/net/bnxt/tf_core/tf_rm.c | 46 +- drivers/net/bnxt/tf_core/tf_rm.h | 62 +- drivers/net/bnxt/tf_core/tf_session.c | 56 ++ drivers/net/bnxt/tf_core/tf_session.h | 58 +- drivers/net/bnxt/tf_core/tf_sram_mgr.c | 971 ++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_sram_mgr.h | 317 +++++++ drivers/net/bnxt/tf_core/tf_tbl.c | 186 +---- drivers/net/bnxt/tf_core/tf_tbl.h | 15 +- drivers/net/bnxt/tf_core/tf_tbl_sram.c | 713 ++++++++++++++++ drivers/net/bnxt/tf_core/tf_tbl_sram.h | 154 ++++ drivers/net/bnxt/tf_core/tf_tcam.c | 10 +- drivers/net/bnxt/tf_core/tf_tcam.h | 7 + drivers/net/bnxt/tf_core/tf_tcam_shared.c | 28 +- drivers/net/bnxt/tf_core/tf_util.c | 10 + drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 23 + 27 files changed, 2976 insertions(+), 352 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.c create mode 100644 drivers/net/bnxt/tf_core/tf_sram_mgr.h create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.c create mode 100644 drivers/net/bnxt/tf_core/tf_tbl_sram.h diff --git a/drivers/net/bnxt/tf_core/ll.c b/drivers/net/bnxt/tf_core/ll.c index cd168a7970..f2bdff6b9e 100644 --- a/drivers/net/bnxt/tf_core/ll.c +++ b/drivers/net/bnxt/tf_core/ll.c @@ -13,6 +13,7 @@ void ll_init(struct ll *ll) { ll->head = NULL; ll->tail = NULL; + ll->cnt = 0; } /* insert entry in linked list */ @@ -30,6 +31,7 @@ void ll_insert(struct ll *ll, entry->next->prev = entry; ll->head = entry->next->prev; } + ll->cnt++; } /* delete entry from linked list */ @@ -49,4 +51,5 @@ void ll_delete(struct ll *ll, entry->prev->next = entry->next; entry->next->prev = entry->prev; } + ll->cnt--; } diff --git a/drivers/net/bnxt/tf_core/ll.h b/drivers/net/bnxt/tf_core/ll.h index 239478b4f8..9cf8f64ec2 100644 --- a/drivers/net/bnxt/tf_core/ll.h +++ b/drivers/net/bnxt/tf_core/ll.h @@ -8,6 +8,8 @@ #ifndef _LL_H_ #define _LL_H_ +#include + /* linked list entry */ struct ll_entry { struct ll_entry *prev; @@ -18,6 +20,7 @@ struct ll_entry { struct ll { struct ll_entry *head; struct ll_entry *tail; + uint32_t cnt; }; /** @@ -28,7 +31,7 @@ struct ll { void ll_init(struct ll *ll); /** - * Linked list insert + * Linked list insert head * * [in] ll, linked list where element is inserted * [in] entry, entry to be added @@ -43,4 +46,49 @@ void ll_insert(struct ll *ll, struct ll_entry *entry); */ void ll_delete(struct ll *ll, struct ll_entry *entry); +/** + * Linked list return next entry without deleting it + * + * Useful in performing search + * + * [in] Entry in the list + */ +static inline struct ll_entry *ll_next(struct ll_entry *entry) +{ + return entry->next; +} + +/** + * Linked list return the head of the list without removing it + * + * Useful in performing search + * + * [in] ll, linked list + */ +static inline struct ll_entry *ll_head(struct ll *ll) +{ + return ll->head; +} + +/** + * Linked list return the tail of the list without removing it + * + * Useful in performing search + * + * [in] ll, linked list + */ +static inline struct ll_entry *ll_tail(struct ll *ll) +{ + return ll->tail; +} + +/** + * Linked list return the number of entries in the list + * + * [in] ll, linked list + */ +static inline uint32_t ll_cnt(struct ll *ll) +{ + return ll->cnt; +} #endif /* _LL_H_ */ diff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build index f28e77ec2e..206935d18a 100644 --- a/drivers/net/bnxt/tf_core/meson.build +++ b/drivers/net/bnxt/tf_core/meson.build @@ -16,6 +16,8 @@ sources += files( 'stack.c', 'tf_rm.c', 'tf_tbl.c', + 'tf_tbl_sram.c', + 'tf_sram_mgr.c', 'tf_em_common.c', 'tf_em_host.c', 'tf_em_internal.c', diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 5458f76e2d..936102c804 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -1079,17 +1079,16 @@ tf_alloc_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } - - } else { - if (dev->ops->tf_dev_alloc_tbl == NULL) { - rc = -EOPNOTSUPP; + } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) { + rc = dev->ops->tf_dev_alloc_sram_tbl(tfp, &aparms); + if (rc) { TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", + "%s: SRAM table allocation failed, rc:%s\n", tf_dir_2_str(parms->dir), strerror(-rc)); - return -EOPNOTSUPP; + return rc; } - + } else { rc = dev->ops->tf_dev_alloc_tbl(tfp, &aparms); if (rc) { TFP_DRV_LOG(ERR, @@ -1162,15 +1161,16 @@ tf_free_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } - } else { - if (dev->ops->tf_dev_free_tbl == NULL) { - rc = -EOPNOTSUPP; + } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) { + rc = dev->ops->tf_dev_free_sram_tbl(tfp, &fparms); + if (rc) { TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", + "%s: SRAM table free failed, rc:%s\n", tf_dir_2_str(parms->dir), strerror(-rc)); - return -EOPNOTSUPP; + return rc; } + } else { rc = dev->ops->tf_dev_free_tbl(tfp, &fparms); if (rc) { @@ -1181,7 +1181,6 @@ tf_free_tbl_entry(struct tf *tfp, return rc; } } - return 0; } @@ -1244,6 +1243,15 @@ tf_set_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } + } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) { + rc = dev->ops->tf_dev_set_sram_tbl(tfp, &sparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM table set failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } } else { if (dev->ops->tf_dev_set_tbl == NULL) { rc = -EOPNOTSUPP; @@ -1300,28 +1308,39 @@ tf_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } - - if (dev->ops->tf_dev_get_tbl == NULL) { - rc = -EOPNOTSUPP; - TFP_DRV_LOG(ERR, - "%s: Operation not supported, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return -EOPNOTSUPP; - } - gparms.dir = parms->dir; gparms.type = parms->type; gparms.data = parms->data; gparms.data_sz_in_bytes = parms->data_sz_in_bytes; gparms.idx = parms->idx; - rc = dev->ops->tf_dev_get_tbl(tfp, &gparms); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Table get failed, rc:%s\n", - tf_dir_2_str(parms->dir), - strerror(-rc)); - return rc; + + if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) { + rc = dev->ops->tf_dev_get_sram_tbl(tfp, &gparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM table get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } + } else { + if (dev->ops->tf_dev_get_tbl == NULL) { + rc = -EOPNOTSUPP; + TFP_DRV_LOG(ERR, + "%s: Operation not supported, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return -EOPNOTSUPP; + } + + rc = dev->ops->tf_dev_get_tbl(tfp, &gparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Table get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + return rc; + } } return rc; @@ -1361,6 +1380,13 @@ tf_bulk_get_tbl_entry(struct tf *tfp, return rc; } + bparms.dir = parms->dir; + bparms.type = parms->type; + bparms.starting_idx = parms->starting_idx; + bparms.num_entries = parms->num_entries; + bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes; + bparms.physical_mem_addr = parms->physical_mem_addr; + if (parms->type == TF_TBL_TYPE_EXT) { /* Not supported, yet */ rc = -EOPNOTSUPP; @@ -1370,10 +1396,17 @@ tf_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; + } else if (dev->ops->tf_dev_is_sram_managed(tfp, parms->type)) { + rc = dev->ops->tf_dev_get_bulk_sram_tbl(tfp, &bparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: SRAM table bulk get failed, rc:%s\n", + tf_dir_2_str(parms->dir), + strerror(-rc)); + } + return rc; } - /* Internal table type processing */ - if (dev->ops->tf_dev_get_bulk_tbl == NULL) { rc = -EOPNOTSUPP; TFP_DRV_LOG(ERR, @@ -1383,12 +1416,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp, return -EOPNOTSUPP; } - bparms.dir = parms->dir; - bparms.type = parms->type; - bparms.starting_idx = parms->starting_idx; - bparms.num_entries = parms->num_entries; - bparms.entry_sz_in_bytes = parms->entry_sz_in_bytes; - bparms.physical_mem_addr = parms->physical_mem_addr; rc = dev->ops->tf_dev_get_bulk_tbl(tfp, &bparms); if (rc) { TFP_DRV_LOG(ERR, @@ -1397,7 +1424,6 @@ tf_bulk_get_tbl_entry(struct tf *tfp, strerror(-rc)); return rc; } - return rc; } diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index af8d13bd7e..fb02c2b161 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -65,6 +65,16 @@ enum tf_ext_mem_chan_type { TF_EXT_MEM_CHAN_TYPE_MAX }; +/** + * WC TCAM number of slice per row that devices supported + */ +enum tf_wc_num_slice { + TF_WC_TCAM_1_SLICE_PER_ROW = 1, + TF_WC_TCAM_2_SLICE_PER_ROW = 2, + TF_WC_TCAM_4_SLICE_PER_ROW = 4, + TF_WC_TCAM_8_SLICE_PER_ROW = 8, +}; + /** * EEM record AR helper * @@ -670,6 +680,13 @@ struct tf_open_session_parms { */ void *bp; + /** + * [in] + * + * The number of slices per row for WC TCAM entry. + */ + enum tf_wc_num_slice wc_num_slices; + /** * [out] shared_session_creator * @@ -734,8 +751,6 @@ int tf_open_session(struct tf *tfp, /** * General internal resource info * - * TODO: remove tf_rm_new_entry structure and use this structure - * internally. */ struct tf_resource_info { uint16_t start; @@ -1656,12 +1671,7 @@ struct tf_alloc_tbl_entry_parms { * entry of the indicated type for this TruFlow session. * * Allocates an index table record. This function will attempt to - * allocate an entry or search an index table for a matching entry if - * search is enabled (only the shadow copy of the table is accessed). - * - * If search is not enabled, the first available free entry is - * returned. If search is enabled and a matching entry to entry_data - * is found hit is set to TRUE and success is returned. + * allocate an index table entry. * * External types: * @@ -1670,8 +1680,8 @@ struct tf_alloc_tbl_entry_parms { * Allocates an external index table action record. * * NOTE: - * Implementation of the internals of this function will be a stack with push - * and pop. + * Implementation of the internals of the external function will be a stack with + * push and pop. * * Returns success or failure code. */ @@ -1707,20 +1717,15 @@ struct tf_free_tbl_entry_parms { * * Internal types: * - * If session has shadow_copy enabled the shadow DB is searched and if - * found the element ref_cnt is decremented. If ref_cnt goes to - * zero then the element is returned to the session pool. - * - * If the session does not have a shadow DB the element is free'ed and - * given back to the session pool. + * The element is freed and given back to the session pool. * * External types: * - * Free's an external index table action record. + * Frees an external index table action record. * * NOTE: - * Implementation of the internals of this function will be a stack with push - * and pop. + * Implementation of the internals of the external table will be a stack with + * push and pop. * * Returns success or failure code. */ @@ -1764,9 +1769,8 @@ struct tf_set_tbl_entry_parms { /** * set index table entry * - * Used to insert an application programmed index table entry into a - * previous allocated table location. A shadow copy of the table - * is maintained (if enabled) (only for internal objects) + * Used to set an application programmed index table entry into a + * previous allocated table location. * * Returns success or failure code. */ diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 498e668b16..25a7166bbb 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -11,10 +11,14 @@ #include "tf_rm.h" #ifdef TF_TCAM_SHARED #include "tf_tcam_shared.h" +#include "tf_tbl_sram.h" #endif /* TF_TCAM_SHARED */ struct tf; +/* Number of slices per row for WC TCAM */ +uint16_t g_wc_num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW; + /* Forward declarations */ static int tf_dev_unbind_p4(struct tf *tfp); static int tf_dev_unbind_p58(struct tf *tfp); @@ -83,7 +87,8 @@ static int tf_dev_bind_p4(struct tf *tfp, bool shadow_copy, struct tf_session_resources *resources, - struct tf_dev_info *dev_handle) + struct tf_dev_info *dev_handle, + enum tf_wc_num_slice wc_num_slices) { int rc; int frc; @@ -131,7 +136,6 @@ tf_dev_bind_p4(struct tf *tfp, if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; tbl_cfg.cfg = tf_tbl_p4; - tbl_cfg.shadow_copy = shadow_copy; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { @@ -151,6 +155,7 @@ tf_dev_bind_p4(struct tf *tfp, tcam_cfg.cfg = tf_tcam_p4; tcam_cfg.shadow_copy = shadow_copy; tcam_cfg.resources = resources; + tcam_cfg.wc_num_slices = wc_num_slices; #ifdef TF_TCAM_SHARED rc = tf_tcam_shared_bind(tfp, &tcam_cfg); #else /* !TF_TCAM_SHARED */ @@ -369,7 +374,8 @@ static int tf_dev_bind_p58(struct tf *tfp, bool shadow_copy, struct tf_session_resources *resources, - struct tf_dev_info *dev_handle) + struct tf_dev_info *dev_handle, + enum tf_wc_num_slice wc_num_slices) { int rc; int frc; @@ -414,7 +420,6 @@ tf_dev_bind_p58(struct tf *tfp, if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; tbl_cfg.cfg = tf_tbl_p58; - tbl_cfg.shadow_copy = shadow_copy; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { @@ -423,6 +428,13 @@ tf_dev_bind_p58(struct tf *tfp, goto fail; } no_rsv_flag = false; + + rc = tf_tbl_sram_bind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "SRAM table initialization failure\n"); + goto fail; + } } rsv_cnt = tf_dev_reservation_check(TF_TCAM_TBL_TYPE_MAX, @@ -433,6 +445,7 @@ tf_dev_bind_p58(struct tf *tfp, tcam_cfg.cfg = tf_tcam_p58; tcam_cfg.shadow_copy = shadow_copy; tcam_cfg.resources = resources; + tcam_cfg.wc_num_slices = wc_num_slices; #ifdef TF_TCAM_SHARED rc = tf_tcam_shared_bind(tfp, &tcam_cfg); #else /* !TF_TCAM_SHARED */ @@ -565,6 +578,18 @@ tf_dev_unbind_p58(struct tf *tfp) fail = true; } + /* Unbind the SRAM table prior to table as the table manager + * owns and frees the table DB while the SRAM table manager owns + * and manages it's internal data structures. SRAM table manager + * relies on the table rm_db to exist. + */ + rc = tf_tbl_sram_unbind(tfp); + if (rc) { + TFP_DRV_LOG(ERR, + "Device unbind failed, SRAM table\n"); + fail = true; + } + rc = tf_tbl_unbind(tfp); if (rc) { TFP_DRV_LOG(INFO, @@ -606,6 +631,7 @@ tf_dev_bind(struct tf *tfp __rte_unused, enum tf_device_type type, bool shadow_copy, struct tf_session_resources *resources, + uint16_t wc_num_slices, struct tf_dev_info *dev_handle) { switch (type) { @@ -615,13 +641,15 @@ tf_dev_bind(struct tf *tfp __rte_unused, return tf_dev_bind_p4(tfp, shadow_copy, resources, - dev_handle); + dev_handle, + wc_num_slices); case TF_DEVICE_TYPE_THOR: dev_handle->type = type; return tf_dev_bind_p58(tfp, shadow_copy, resources, - dev_handle); + dev_handle, + wc_num_slices); default: TFP_DRV_LOG(ERR, "No such device\n"); diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h index b43cfc6925..9b0c037db0 100644 --- a/drivers/net/bnxt/tf_core/tf_device.h +++ b/drivers/net/bnxt/tf_core/tf_device.h @@ -57,6 +57,9 @@ struct tf_dev_info { * [in] resources * Pointer to resource allocation information * + * [in] wc_num_slices + * Number of slices per row for WC + * * [out] dev_handle * Device handle * @@ -69,6 +72,7 @@ int tf_dev_bind(struct tf *tfp, enum tf_device_type type, bool shadow_copy, struct tf_session_resources *resources, + uint16_t wc_num_slices, struct tf_dev_info *dev_handle); /** @@ -139,6 +143,23 @@ struct tf_dev_ops { uint16_t resource_id, const char **resource_str); + /** + * Set the WC TCAM slice information that the device + * supports. + * + * [in] tfp + * Pointer to TF handle + * + * [in] num_slices_per_row + * Number of slices per row the device supports + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_set_tcam_slice_info)(struct tf *tfp, + enum tf_wc_num_slice num_slices_per_row); + /** * Retrieves the WC TCAM slice information that the device * supports. @@ -241,6 +262,22 @@ struct tf_dev_ops { int (*tf_dev_get_ident_resc_info)(struct tf *tfp, struct tf_identifier_resource_info *parms); + /** + * Indicates whether the index table type is SRAM managed + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD + * + * Returns + * - (0) if the table is not managed by the SRAM manager + * - (1) if the table is managed by the SRAM manager + */ + bool (*tf_dev_is_sram_managed)(struct tf *tfp, + enum tf_tbl_type tbl_type); + /** * Get SRAM table information. * @@ -289,6 +326,25 @@ struct tf_dev_ops { int (*tf_dev_alloc_tbl)(struct tf *tfp, struct tf_tbl_alloc_parms *parms); + /** + * Allocation of an SRAM index table type element. + * + * This API allocates the specified table type element from a + * device specific table type DB. The allocated element is + * returned. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to table allocation parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_alloc_sram_tbl)(struct tf *tfp, + struct tf_tbl_alloc_parms *parms); /** * Allocation of a external table type element. * @@ -327,7 +383,24 @@ struct tf_dev_ops { */ int (*tf_dev_free_tbl)(struct tf *tfp, struct tf_tbl_free_parms *parms); - + /** + * Free of an SRAM table type element. + * + * This API free's a previous allocated table type element from a + * device specific table type DB. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to table free parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_free_sram_tbl)(struct tf *tfp, + struct tf_tbl_free_parms *parms); /** * Free of a external table type element. * @@ -385,6 +458,25 @@ struct tf_dev_ops { int (*tf_dev_set_ext_tbl)(struct tf *tfp, struct tf_tbl_set_parms *parms); + /** + * Sets the specified SRAM table type element. + * + * This API sets the specified element data by invoking the + * firmware. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to table set parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_set_sram_tbl)(struct tf *tfp, + struct tf_tbl_set_parms *parms); + /** * Retrieves the specified table type element. * @@ -404,6 +496,25 @@ struct tf_dev_ops { int (*tf_dev_get_tbl)(struct tf *tfp, struct tf_tbl_get_parms *parms); + /** + * Retrieves the specified SRAM table type element. + * + * This API retrieves the specified element data by invoking the + * firmware. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to table get parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_sram_tbl)(struct tf *tfp, + struct tf_tbl_get_parms *parms); + /** * Retrieves the specified table type element using 'bulk' * mechanism. @@ -424,6 +535,26 @@ struct tf_dev_ops { int (*tf_dev_get_bulk_tbl)(struct tf *tfp, struct tf_tbl_get_bulk_parms *parms); + /** + * Retrieves the specified SRAM table type element using 'bulk' + * mechanism. + * + * This API retrieves the specified element data by invoking the + * firmware. + * + * [in] tfp + * Pointer to TF handle + * + * [in] parms + * Pointer to table get bulk parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ + int (*tf_dev_get_bulk_sram_tbl)(struct tf *tfp, + struct tf_tbl_get_bulk_parms *parms); + /** * Gets the increment value to add to the shared session resource * start offset by for each count in the "stride" diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 2e7ccec123..826cd0cdbc 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -118,14 +118,48 @@ tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused, } /** - * Device specific function that retrieves the WC TCAM slices the + * Device specific function that set the WC TCAM slices the * device supports. * * [in] tfp * Pointer to TF handle * - * [out] slice_size - * Pointer to the WC TCAM slice size + * [in] num_slices_per_row + * The WC TCAM row slice configuration + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int +tf_dev_p4_set_tcam_slice_info(struct tf *tfp __rte_unused, + enum tf_wc_num_slice num_slices_per_row) +{ + switch (num_slices_per_row) { + case TF_WC_TCAM_1_SLICE_PER_ROW: + case TF_WC_TCAM_2_SLICE_PER_ROW: + case TF_WC_TCAM_4_SLICE_PER_ROW: + g_wc_num_slices_per_row = num_slices_per_row; + break; + default: + return -EINVAL; + } + + return 0; +} + +/** + * Device specific function that retrieves the TCAM slices the + * device supports. + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * TF TCAM type + * + * [in] key_sz + * The key size * * [out] num_slices_per_row * Pointer to the WC TCAM row slice configuration @@ -141,11 +175,10 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused, uint16_t *num_slices_per_row) { /* Single slice support */ -#define CFA_P4_WC_TCAM_SLICES_PER_ROW 1 #define CFA_P4_WC_TCAM_SLICE_SIZE 12 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { - *num_slices_per_row = CFA_P4_WC_TCAM_SLICES_PER_ROW; + *num_slices_per_row = g_wc_num_slices_per_row; if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE) return -ENOTSUP; } else { /* for other type of tcam */ @@ -220,26 +253,51 @@ static int tf_dev_p4_word_align(uint16_t size) return ((((size) + 31) >> 5) * 4); } +/** + * Indicates whether the index table type is SRAM managed + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD + * + * Returns + * - (0) if the table is not managed by the SRAM manager + * - (1) if the table is managed by the SRAM manager + */ +static bool tf_dev_p4_is_sram_managed(struct tf *tfp __rte_unused, + enum tf_tbl_type type __rte_unused) +{ + return false; +} /** * Truflow P4 device specific functions */ const struct tf_dev_ops tf_dev_ops_p4_init = { .tf_dev_get_max_types = tf_dev_p4_get_max_types, .tf_dev_get_resource_str = tf_dev_p4_get_resource_str, + .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info, .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info, .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, .tf_dev_search_ident = NULL, .tf_dev_get_ident_resc_info = NULL, .tf_dev_get_tbl_info = NULL, + .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed, .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_tbl = NULL, + .tf_dev_alloc_sram_tbl = NULL, .tf_dev_free_ext_tbl = NULL, .tf_dev_free_tbl = NULL, + .tf_dev_free_sram_tbl = NULL, .tf_dev_set_tbl = NULL, .tf_dev_set_ext_tbl = NULL, + .tf_dev_set_sram_tbl = NULL, .tf_dev_get_tbl = NULL, + .tf_dev_get_sram_tbl = NULL, .tf_dev_get_bulk_tbl = NULL, + .tf_dev_get_bulk_sram_tbl = NULL, .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = NULL, .tf_dev_alloc_tcam = NULL, @@ -271,20 +329,27 @@ const struct tf_dev_ops tf_dev_ops_p4_init = { const struct tf_dev_ops tf_dev_ops_p4 = { .tf_dev_get_max_types = tf_dev_p4_get_max_types, .tf_dev_get_resource_str = tf_dev_p4_get_resource_str, + .tf_dev_set_tcam_slice_info = tf_dev_p4_set_tcam_slice_info, .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info, .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, .tf_dev_search_ident = tf_ident_search, .tf_dev_get_ident_resc_info = tf_ident_get_resc_info, .tf_dev_get_tbl_info = NULL, + .tf_dev_is_sram_managed = tf_dev_p4_is_sram_managed, .tf_dev_alloc_tbl = tf_tbl_alloc, .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, + .tf_dev_alloc_sram_tbl = tf_tbl_alloc, .tf_dev_free_tbl = tf_tbl_free, .tf_dev_free_ext_tbl = tf_tbl_ext_free, + .tf_dev_free_sram_tbl = tf_tbl_free, .tf_dev_set_tbl = tf_tbl_set, .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, + .tf_dev_set_sram_tbl = NULL, .tf_dev_get_tbl = tf_tbl_get, + .tf_dev_get_sram_tbl = NULL, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_get_bulk_sram_tbl = NULL, .tf_dev_get_shared_tbl_increment = tf_dev_p4_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, #ifdef TF_TCAM_SHARED diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index a73ba3cd70..c1357913f1 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -15,101 +15,101 @@ struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_L2_CTXT_LOW] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_PROF_FUNC] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_WC_PROF] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_EM_PROF] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID, - 0, 0, 0 + 0, 0 }, }; struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_PROF_TCAM] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_WC_TCAM] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_SP_TCAM] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM, - 0, 0, 0 + 0, 0 }, }; struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_FULL_ACT_RECORD] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_MCAST_GROUPS] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_ENCAP_8B] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_ENCAP_16B] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_ENCAP_64B] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_SP_SMAC] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_STATS_64] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_METER_PROF] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_METER_INST] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_MIRROR_CONFIG] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, - 0, 0, 0 + 0, 0 }, }; @@ -117,14 +117,14 @@ struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_TBL_SCOPE] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, - 0, 0, 0 + 0, 0 }, }; struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC, - 0, 0, 0 + 0, 0 }, }; diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c index a492c62bff..47d7836a58 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.c +++ b/drivers/net/bnxt/tf_core/tf_device_p58.c @@ -17,6 +17,7 @@ #include "tf_if_tbl.h" #include "tfp.h" #include "tf_msg_common.h" +#include "tf_tbl_sram.h" #define TF_DEV_P58_PARIF_MAX 16 #define TF_DEV_P58_PF_MASK 0xfUL @@ -105,14 +106,48 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused, } /** - * Device specific function that retrieves the WC TCAM slices the + * Device specific function that set the WC TCAM slices the * device supports. * * [in] tfp * Pointer to TF handle * - * [out] slice_size - * Pointer to the WC TCAM slice size + * [in] num_slices_per_row + * The WC TCAM row slice configuration + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +static int +tf_dev_p58_set_tcam_slice_info(struct tf *tfp __rte_unused, + enum tf_wc_num_slice num_slices_per_row) +{ + switch (num_slices_per_row) { + case TF_WC_TCAM_1_SLICE_PER_ROW: + case TF_WC_TCAM_2_SLICE_PER_ROW: + case TF_WC_TCAM_4_SLICE_PER_ROW: + g_wc_num_slices_per_row = num_slices_per_row; + break; + default: + return -EINVAL; + } + + return 0; +} + +/** + * Device specific function that retrieves the TCAM slices the + * device supports. + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * TF TCAM type + * + * [in] key_sz + * The key size * * [out] num_slices_per_row * Pointer to the WC TCAM row slice configuration @@ -123,16 +158,13 @@ tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused, */ static int tf_dev_p58_get_tcam_slice_info(struct tf *tfp __rte_unused, - enum tf_tcam_tbl_type type, - uint16_t key_sz, - uint16_t *num_slices_per_row) + enum tf_tcam_tbl_type type, + uint16_t key_sz, + uint16_t *num_slices_per_row) { -#define CFA_P58_WC_TCAM_SLICES_PER_ROW 1 #define CFA_P58_WC_TCAM_SLICE_SIZE 24 - if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { - /* only support single slice key size now */ - *num_slices_per_row = CFA_P58_WC_TCAM_SLICES_PER_ROW; + *num_slices_per_row = g_wc_num_slices_per_row; if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE) return -ENOTSUP; } else { /* for other type of tcam */ @@ -194,6 +226,44 @@ static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused, return 0; } +/** + * Indicates whether the index table type is SRAM managed + * + * [in] tfp + * Pointer to TF handle + * + * [in] type + * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD + * + * Returns + * - (0) if the table is not managed by the SRAM manager + * - (1) if the table is managed by the SRAM manager + */ +static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused, + enum tf_tbl_type type) +{ + switch (type) { + case TF_TBL_TYPE_FULL_ACT_RECORD: + case TF_TBL_TYPE_COMPACT_ACT_RECORD: + case TF_TBL_TYPE_ACT_ENCAP_8B: + case TF_TBL_TYPE_ACT_ENCAP_16B: + case TF_TBL_TYPE_ACT_ENCAP_32B: + case TF_TBL_TYPE_ACT_ENCAP_64B: + case TF_TBL_TYPE_ACT_SP_SMAC: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: + case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: + case TF_TBL_TYPE_ACT_STATS_64: + case TF_TBL_TYPE_ACT_MODIFY_IPV4: + case TF_TBL_TYPE_ACT_MODIFY_8B: + case TF_TBL_TYPE_ACT_MODIFY_16B: + case TF_TBL_TYPE_ACT_MODIFY_32B: + case TF_TBL_TYPE_ACT_MODIFY_64B: + return true; + default: + return false; + } +} + #define TF_DEV_P58_BANK_SZ_64B 2048 /** * Get SRAM table information. @@ -265,26 +335,34 @@ static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, } return 0; } + /** * Truflow P58 device specific functions */ const struct tf_dev_ops tf_dev_ops_p58_init = { .tf_dev_get_max_types = tf_dev_p58_get_max_types, .tf_dev_get_resource_str = tf_dev_p58_get_resource_str, + .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info, .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info, .tf_dev_alloc_ident = NULL, .tf_dev_free_ident = NULL, .tf_dev_search_ident = NULL, .tf_dev_get_ident_resc_info = NULL, .tf_dev_get_tbl_info = NULL, + .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed, .tf_dev_alloc_ext_tbl = NULL, .tf_dev_alloc_tbl = NULL, + .tf_dev_alloc_sram_tbl = NULL, .tf_dev_free_ext_tbl = NULL, .tf_dev_free_tbl = NULL, + .tf_dev_free_sram_tbl = NULL, .tf_dev_set_tbl = NULL, .tf_dev_set_ext_tbl = NULL, + .tf_dev_set_sram_tbl = NULL, .tf_dev_get_tbl = NULL, + .tf_dev_get_sram_tbl = NULL, .tf_dev_get_bulk_tbl = NULL, + .tf_dev_get_bulk_sram_tbl = NULL, .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = NULL, .tf_dev_alloc_tcam = NULL, @@ -316,20 +394,27 @@ const struct tf_dev_ops tf_dev_ops_p58_init = { const struct tf_dev_ops tf_dev_ops_p58 = { .tf_dev_get_max_types = tf_dev_p58_get_max_types, .tf_dev_get_resource_str = tf_dev_p58_get_resource_str, + .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info, .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info, .tf_dev_alloc_ident = tf_ident_alloc, .tf_dev_free_ident = tf_ident_free, .tf_dev_search_ident = tf_ident_search, .tf_dev_get_ident_resc_info = tf_ident_get_resc_info, + .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed, .tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info, .tf_dev_alloc_tbl = tf_tbl_alloc, + .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc, .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc, .tf_dev_free_tbl = tf_tbl_free, .tf_dev_free_ext_tbl = tf_tbl_ext_free, + .tf_dev_free_sram_tbl = tf_tbl_sram_free, .tf_dev_set_tbl = tf_tbl_set, .tf_dev_set_ext_tbl = tf_tbl_ext_common_set, + .tf_dev_set_sram_tbl = tf_tbl_sram_set, .tf_dev_get_tbl = tf_tbl_get, + .tf_dev_get_sram_tbl = tf_tbl_sram_get, .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, + .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get, .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment, .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, #ifdef TF_TCAM_SHARED diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h index 8c2e07aa34..3e8759f2df 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p58.h +++ b/drivers/net/bnxt/tf_core/tf_device_p58.h @@ -15,107 +15,107 @@ struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_L2_CTXT_LOW] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_PROF_FUNC] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_WC_PROF] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID, - 0, 0, 0 + 0, 0 }, [TF_IDENT_TYPE_EM_PROF] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID, - 0, 0, 0 + 0, 0 }, }; struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = { [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_PROF_TCAM] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_WC_TCAM] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM, - 0, 0, 0 + 0, 0 }, [TF_TCAM_TBL_TYPE_VEB_TCAM] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM, - 0, 0, 0 + 0, 0 }, }; struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_EM_FKB] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_WC_FKB] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_METER_PROF] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_METER_INST] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_METER_DROP_CNT] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_MIRROR_CONFIG] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, - 0, 0, 0 + 0, 0 }, [TF_TBL_TYPE_METADATA] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, - 0, 0, 0 + 0, 0 }, /* Policy - ARs in bank 1 */ [TF_TBL_TYPE_FULL_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 1, + .slices = 4, }, [TF_TBL_TYPE_COMPACT_ACT_RECORD] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, - .slices = 1, + .slices = 8, }, /* Policy - Encaps in bank 2 */ [TF_TBL_TYPE_ACT_ENCAP_8B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 8, }, [TF_TBL_TYPE_ACT_ENCAP_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 4, }, [TF_TBL_TYPE_ACT_ENCAP_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 2, }, [TF_TBL_TYPE_ACT_ENCAP_64B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, @@ -128,19 +128,19 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 8, }, [TF_TBL_TYPE_ACT_MODIFY_16B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 4, }, [TF_TBL_TYPE_ACT_MODIFY_32B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, - .slices = 1, + .slices = 2, }, [TF_TBL_TYPE_ACT_MODIFY_64B] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, @@ -152,32 +152,32 @@ struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = { [TF_TBL_TYPE_ACT_SP_SMAC] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 1, + .slices = 8, }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 1, + .slices = 4, }, [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, - .slices = 1, + .slices = 2, }, /* Policy - Stats in bank 3 */ [TF_TBL_TYPE_ACT_STATS_64] = { .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, - .slices = 1, + .slices = 8, }, }; struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_EM_RECORD] = { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC, - 0, 0, 0 + 0, 0 }, }; diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index e07d9168be..0fbb2fe837 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -2231,7 +2231,7 @@ tf_msg_get_if_tbl_entry(struct tf *tfp, if (rc != 0) return rc; - tfp_memcpy(params->data, resp.data, req.size); + tfp_memcpy(¶ms->data[0], resp.data, req.size); return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c index 0a46e2a343..03c958a7d6 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.c +++ b/drivers/net/bnxt/tf_core/tf_rm.c @@ -34,6 +34,12 @@ struct tf_rm_element { */ uint16_t hcapi_type; + /** + * Resource slices. How many slices will fit in the + * resource pool chunk size. + */ + uint8_t slices; + /** * HCAPI RM allocated range information for the element. */ @@ -356,12 +362,15 @@ tf_rm_check_residuals(struct tf_rm_new_db *rm_db, * - - Failure if negative */ static int -tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg, +tf_rm_update_parent_reservations(struct tf *tfp, + struct tf_dev_info *dev, + struct tf_rm_element_cfg *cfg, uint16_t *alloc_cnt, uint16_t num_elements, uint16_t *req_cnt) { int parent, child; + const char *type_str; /* Search through all the elements */ for (parent = 0; parent < num_elements; parent++) { @@ -377,15 +386,25 @@ tf_rm_update_parent_reservations(struct tf_rm_element_cfg *cfg, if (alloc_cnt[parent] % cfg[parent].slices) combined_cnt++; + if (alloc_cnt[parent]) { + dev->ops->tf_dev_get_resource_str(tfp, + cfg[parent].hcapi_type, + &type_str); + } + /* Search again through all the elements */ for (child = 0; child < num_elements; child++) { /* If this is one of my children */ if (cfg[child].cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD && - cfg[child].parent_subtype == parent) { + cfg[child].parent_subtype == parent && + alloc_cnt[child]) { uint16_t cnt = 0; RTE_ASSERT(cfg[child].slices); + dev->ops->tf_dev_get_resource_str(tfp, + cfg[child].hcapi_type, + &type_str); /* Increment the parents combined count * with each child's count adjusted for * number of slices per RM allocated item. @@ -479,7 +498,7 @@ tf_rm_create_db(struct tf *tfp, /* Update the req_cnt based upon the element configuration */ - tf_rm_update_parent_reservations(parms->cfg, + tf_rm_update_parent_reservations(tfp, dev, parms->cfg, parms->alloc_cnt, parms->num_elements, req_cnt); @@ -594,6 +613,7 @@ tf_rm_create_db(struct tf *tfp, db[i].cfg_type = cfg->cfg_type; db[i].hcapi_type = cfg->hcapi_type; + db[i].slices = cfg->slices; /* Save the parent subtype for later use to find the pool */ @@ -1271,6 +1291,26 @@ tf_rm_get_hcapi_type(struct tf_rm_get_hcapi_parms *parms) return 0; } +int +tf_rm_get_slices(struct tf_rm_get_slices_parms *parms) +{ + struct tf_rm_new_db *rm_db; + enum tf_rm_elem_cfg_type cfg_type; + + TF_CHECK_PARMS2(parms, parms->rm_db); + rm_db = (struct tf_rm_new_db *)parms->rm_db; + TF_CHECK_PARMS1(rm_db->db); + + cfg_type = rm_db->db[parms->subtype].cfg_type; + + /* Bail out if not controlled by HCAPI */ + if (cfg_type == TF_RM_ELEM_CFG_NULL) + return -ENOTSUP; + + *parms->slices = rm_db->db[parms->subtype].slices; + + return 0; +} int tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms) diff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h index 8b984112e8..da7d0c7211 100644 --- a/drivers/net/bnxt/tf_core/tf_rm.h +++ b/drivers/net/bnxt/tf_core/tf_rm.h @@ -43,16 +43,6 @@ struct tf; * support module, not called directly. */ -/** - * Resource reservation single entry result. Used when accessing HCAPI - * RM on the firmware. - */ -struct tf_rm_new_entry { - /** Starting index of the allocated resource */ - uint16_t start; - /** Number of allocated elements */ - uint16_t stride; -}; /** * RM Element configuration enumeration. Used by the Device to @@ -114,10 +104,6 @@ struct tf_rm_element_cfg { */ enum tf_rm_elem_cfg_type cfg_type; - /* If a HCAPI to TF type conversion is required then TF type - * can be added here. - */ - /** * HCAPI RM Type for the element. Used for TF to HCAPI type * conversion. @@ -125,28 +111,19 @@ struct tf_rm_element_cfg { uint16_t hcapi_type; /** - * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD + * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT * * Parent Truflow module subtype associated with this resource type. */ uint16_t parent_subtype; /** - * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD + * if cfg_type == TF_RM_ELEM_CFG_HCAPI_BA_CHILD/PARENT * * Resource slices. How many slices will fit in the * resource pool chunk size. */ uint8_t slices; - - /** - * Pool element divider count - * If 0 or 1, there is 1:1 correspondence between the RM - * BA pool resource element and the HCAPI RM firmware - * resource. If > 1, the RM BA pool element has a 1:n - * correspondence to the HCAPI RM firmware resource. - */ - uint8_t divider; }; /** @@ -160,7 +137,7 @@ struct tf_rm_alloc_info { * In case of dynamic allocation support this would have * to be changed to linked list of tf_rm_entry instead. */ - struct tf_rm_new_entry entry; + struct tf_resource_info entry; }; /** @@ -331,6 +308,25 @@ struct tf_rm_get_hcapi_parms { */ uint16_t *hcapi_type; }; +/** + * Get Slices parameters for a single element + */ +struct tf_rm_get_slices_parms { + /** + * [in] RM DB Handle + */ + void *rm_db; + /** + * [in] TF subtype indicates which DB entry to perform the + * action on. (e.g. TF_TBL_TYPE_FULL_ACTION subtype of module + * TF_MODULE_TYPE_TABLE) + */ + uint16_t subtype; + /** + * [in/out] Pointer to number of slices for the given type + */ + uint16_t *slices; +}; /** * Get InUse count parameters for single element @@ -394,6 +390,8 @@ struct tf_rm_check_indexes_in_range_parms { * @ref tf_rm_get_hcapi_type * * @ref tf_rm_get_inuse_count + * + * @ref tf_rm_get_slice_size */ /** @@ -571,5 +569,17 @@ int tf_rm_get_inuse_count(struct tf_rm_get_inuse_count_parms *parms); int tf_rm_check_indexes_in_range(struct tf_rm_check_indexes_in_range_parms *parms); +/** + * Get the number of slices per resource bit allocator for the resource type + * + * [in] parms + * Pointer to get inuse parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int +tf_rm_get_slices(struct tf_rm_get_slices_parms *parms); #endif /* TF_RM_NEW_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_session.c b/drivers/net/bnxt/tf_core/tf_session.c index 90b65c59e6..3e6664e9f2 100644 --- a/drivers/net/bnxt/tf_core/tf_session.c +++ b/drivers/net/bnxt/tf_core/tf_session.c @@ -202,6 +202,7 @@ tf_session_create(struct tf *tfp, parms->open_cfg->device_type, session->shadow_copy, &parms->open_cfg->resources, + parms->open_cfg->wc_num_slices, &session->dev); /* Logging handled by dev_bind */ @@ -705,6 +706,22 @@ tf_session_get_session(struct tf *tfp, return rc; } +int tf_session_get(struct tf *tfp, + struct tf_session **tfs, + struct tf_dev_info **tfd) +{ + int rc; + rc = tf_session_get_session_internal(tfp, tfs); + + /* Logging done by tf_session_get_session_internal */ + if (rc) + return rc; + + rc = tf_session_get_device(*tfs, tfd); + + return rc; +} + struct tf_session_client * tf_session_get_session_client(struct tf_session *tfs, union tf_session_client_id session_client_id) @@ -1012,4 +1029,43 @@ tf_session_set_tcam_shared_db(struct tf *tfp, tfs->tcam_shared_db_handle = tcam_shared_db_handle; return rc; } + +int +tf_session_get_sram_db(struct tf *tfp, + void **sram_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + *sram_handle = NULL; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + *sram_handle = tfs->sram_handle; + return rc; +} + +int +tf_session_set_sram_db(struct tf *tfp, + void *sram_handle) +{ + struct tf_session *tfs = NULL; + int rc = 0; + + if (tfp == NULL) + return (-EINVAL); + + rc = tf_session_get_session_internal(tfp, &tfs); + if (rc) + return rc; + + tfs->sram_handle = sram_handle; + return rc; +} + #endif /* TF_TCAM_SHARED */ diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h index d68421cd13..c1d7f70060 100644 --- a/drivers/net/bnxt/tf_core/tf_session.h +++ b/drivers/net/bnxt/tf_core/tf_session.h @@ -166,6 +166,10 @@ struct tf_session { */ void *tcam_shared_db_handle; #endif /* TF_TCAM_SHARED */ + /** + * SRAM db reference for the session + */ + void *sram_handle; }; /** @@ -278,6 +282,10 @@ struct tf_session_close_session_parms { * * @ref tf_session_set_tcam_shared_db * #endif + * + * @ref tf_session_get_sram_db + * + * @ref tf_session_set_sram_db */ /** @@ -435,11 +443,11 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs, /** * Looks up the device information from the TF Session. * - * [in] tfp - * Pointer to TF handle + * [in] tfs + * Pointer to session handle * * [out] tfd - * Pointer pointer to the device + * Pointer to the device * * Returns * - (0) if successful. @@ -448,6 +456,26 @@ tf_session_find_session_client_by_fid(struct tf_session *tfs, int tf_session_get_device(struct tf_session *tfs, struct tf_dev_info **tfd); +/** + * Returns the session and the device from the tfp. + * + * [in] tfp + * Pointer to TF handle + * + * [out] tfs + * Pointer to the session + * + * [out] tfd + * Pointer to the device + + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_session_get(struct tf *tfp, + struct tf_session **tfs, + struct tf_dev_info **tfd); + /** * Looks up the FW Session id the requested TF handle. * @@ -614,4 +642,28 @@ int tf_session_get_tcam_shared_db(struct tf *tfp, void **tcam_shared_db_handle); +/** + * Set the pointer to the SRAM database + * + * [in] session, pointer to the session + * + * Returns: + * - the pointer to the parent bnxt struct + */ +int +tf_session_set_sram_db(struct tf *tfp, + void *sram_handle); + +/** + * Get the pointer to the SRAM database + * + * [in] session, pointer to the session + * + * Returns: + * - the pointer to the parent bnxt struct + */ +int +tf_session_get_sram_db(struct tf *tfp, + void **sram_handle); + #endif /* _TF_SESSION_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.c b/drivers/net/bnxt/tf_core/tf_sram_mgr.c new file mode 100644 index 0000000000..f633a78b25 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.c @@ -0,0 +1,971 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ +#include +#include +#include "tf_sram_mgr.h" +#include "tf_core.h" +#include "tf_rm.h" +#include "tf_common.h" +#include "assert.h" +#include "tf_util.h" +#include "tfp.h" +#if (STATS_CLEAR_ON_READ_SUPPORT == 0) +#include "tf_msg.h" +#endif +/*************************** + * Internal Data Structures + ***************************/ + +/** + * TF SRAM block info + * + * Contains all the information about a particular 64B SRAM + * block and the slices within it. + */ +struct tf_sram_block { + /* Previous block + */ + struct tf_sram_block *prev; + /* Next block + */ + struct tf_sram_block *next; + + /** Bitmap indicating which slices are in use + * If a bit is set, it indicates the slice + * in the row is in use. + */ + uint8_t in_use_mask; + + /** Block id - this is a 64B offset + */ + uint16_t block_id; +}; + +/** + * TF SRAM block list + * + * List of 64B SRAM blocks used for fixed size slices (8, 16, 32, 64B) + */ +struct tf_sram_slice_list { + /** Pointer to head of linked list of blocks. + */ + struct tf_sram_block *head; + + /** Pointer to tail of linked list of blocks. + */ + struct tf_sram_block *tail; + + /** Total count of blocks + */ + uint32_t cnt; + + /** First non-full block in the list + */ + struct tf_sram_block *first_not_full_block; + + /** Entry slice size for this list + */ + enum tf_sram_slice_size size; +}; + + +/** + * TF SRAM bank info consists of lists of different slice sizes per bank + */ +struct tf_sram_bank_info { + struct tf_sram_slice_list slice[TF_SRAM_SLICE_SIZE_MAX]; +}; + +/** + * SRAM banks consist of SRAM bank information + */ +struct tf_sram_bank { + struct tf_sram_bank_info bank[TF_SRAM_BANK_ID_MAX]; +}; + +/** + * SRAM banks consist of SRAM bank information + */ +struct tf_sram { + struct tf_sram_bank dir[TF_DIR_MAX]; +}; + +/********************** + * Internal functions + **********************/ + +/** + * Get slice size in string format + */ +const char +*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size) +{ + switch (slice_size) { + case TF_SRAM_SLICE_SIZE_8B: + return "8B slice"; + case TF_SRAM_SLICE_SIZE_16B: + return "16B slice"; + case TF_SRAM_SLICE_SIZE_32B: + return "32B slice"; + case TF_SRAM_SLICE_SIZE_64B: + return "64B slice"; + default: + return "Invalid slice size"; + } +} + +/** + * Get bank in string format + */ +const char +*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id) +{ + switch (bank_id) { + case TF_SRAM_BANK_ID_0: + return "bank_0"; + case TF_SRAM_BANK_ID_1: + return "bank_1"; + case TF_SRAM_BANK_ID_2: + return "bank_2"; + case TF_SRAM_BANK_ID_3: + return "bank_3"; + default: + return "Invalid bank_id"; + } +} + +/** + * TF SRAM get slice list + */ +static int +tf_sram_get_slice_list(struct tf_sram *sram, + struct tf_sram_slice_list **slice_list, + enum tf_sram_slice_size slice_size, + enum tf_dir dir, + enum tf_sram_bank_id bank_id) +{ + int rc = 0; + + TF_CHECK_PARMS2(sram, slice_list); + + *slice_list = &sram->dir[dir].bank[bank_id].slice[slice_size]; + + return rc; +} + +uint16_t tf_sram_bank_2_base_offset[TF_SRAM_BANK_ID_MAX] = { + 0, + 2048, + 4096, + 6144 +}; + +/** + * Translate a block id and bank_id to an 8B offset + */ +static void +tf_sram_block_id_2_offset(enum tf_sram_bank_id bank_id, uint16_t block_id, + uint16_t *offset) +{ + *offset = (block_id + tf_sram_bank_2_base_offset[bank_id]) << 3; +} + +/** + * Translates an 8B offset and bank_id to a block_id + */ +static void +tf_sram_offset_2_block_id(enum tf_sram_bank_id bank_id, uint16_t offset, + uint16_t *block_id, uint16_t *slice_offset) +{ + *slice_offset = offset & 0x7; + *block_id = ((offset & ~0x7) >> 3) - + tf_sram_bank_2_base_offset[bank_id]; +} + +/** + * Find a matching block_id within the slice list + */ +static struct tf_sram_block +*tf_sram_find_block(uint16_t block_id, struct tf_sram_slice_list *slice_list) +{ + uint32_t cnt; + struct tf_sram_block *block; + + cnt = slice_list->cnt; + block = slice_list->head; + + while (cnt > 0 && block) { + if (block->block_id == block_id) + return block; + block = block->next; + cnt--; + } + return NULL; +} + +/** + * Given the current block get the next block within the slice list + * + * List is not changed. + */ +static struct tf_sram_block +*tf_sram_get_next_block(struct tf_sram_block *block) +{ + struct tf_sram_block *nblock; + + if (block != NULL) + nblock = block->next; + else + nblock = NULL; + return nblock; +} + +/** + * Free an allocated slice from a block and if the block is empty, + * return an indication so that the block can be freed. + */ +static int +tf_sram_free_slice(enum tf_sram_slice_size slice_size, + uint16_t slice_offset, struct tf_sram_block *block, + bool *block_is_empty) +{ + int rc = 0; + uint8_t shift; + uint8_t slice_mask = 0; + + TF_CHECK_PARMS2(block, block_is_empty); + + switch (slice_size) { + case TF_SRAM_SLICE_SIZE_8B: + shift = slice_offset >> 0; + assert(shift < 8); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_16B: + shift = slice_offset >> 1; + assert(shift < 4); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_32B: + shift = slice_offset >> 2; + assert(shift < 2); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_64B: + default: + shift = slice_offset >> 0; + assert(shift < 1); + slice_mask = 1 << shift; + break; + } + + if ((block->in_use_mask & slice_mask) == 0) { + rc = -EINVAL; + TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n", + block->block_id, slice_offset); + return rc; + } + + block->in_use_mask &= ~slice_mask; + + if (block->in_use_mask == 0) + *block_is_empty = true; + else + *block_is_empty = false; + + return rc; +} + +/** + * TF SRAM get next slice + * + * Gets the next slice_offset available in the block + * and updates the in_use_mask. + */ +static int +tf_sram_get_next_slice_in_block(struct tf_sram_block *block, + enum tf_sram_slice_size slice_size, + uint16_t *slice_offset, + bool *block_is_full) +{ + int rc, free_id = -1; + uint8_t shift, max_slices, mask, i, full_mask; + + TF_CHECK_PARMS3(block, slice_offset, block_is_full); + + switch (slice_size) { + case TF_SRAM_SLICE_SIZE_8B: + shift = 0; + max_slices = 8; + full_mask = 0xff; + break; + case TF_SRAM_SLICE_SIZE_16B: + shift = 1; + max_slices = 4; + full_mask = 0xf; + break; + case TF_SRAM_SLICE_SIZE_32B: + shift = 2; + max_slices = 2; + full_mask = 0x3; + break; + case TF_SRAM_SLICE_SIZE_64B: + default: + shift = 0; + max_slices = 1; + full_mask = 1; + break; + } + + mask = block->in_use_mask; + + for (i = 0; i < max_slices; i++) { + if ((mask & 1) == 0) { + free_id = i; + block->in_use_mask |= 1 << free_id; + break; + } + mask = mask >> 1; + } + + if (block->in_use_mask == full_mask) + *block_is_full = true; + else + *block_is_full = false; + + + if (free_id >= 0) { + *slice_offset = free_id << shift; + rc = 0; + } else { + *slice_offset = 0; + rc = -ENOMEM; + } + + return rc; +} + +/** + * TF SRAM get indication as to whether the slice offset is + * allocated in the block. + * + */ +static int +tf_sram_is_slice_allocated_in_block(struct tf_sram_block *block, + enum tf_sram_slice_size slice_size, + uint16_t slice_offset, + bool *is_allocated) +{ + int rc = 0; + uint8_t shift; + uint8_t slice_mask = 0; + + TF_CHECK_PARMS2(block, is_allocated); + + *is_allocated = false; + + switch (slice_size) { + case TF_SRAM_SLICE_SIZE_8B: + shift = slice_offset >> 0; + assert(shift < 8); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_16B: + shift = slice_offset >> 1; + assert(shift < 4); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_32B: + shift = slice_offset >> 2; + assert(shift < 2); + slice_mask = 1 << shift; + break; + + case TF_SRAM_SLICE_SIZE_64B: + default: + shift = slice_offset >> 0; + assert(shift < 1); + slice_mask = 1 << shift; + break; + } + + if ((block->in_use_mask & slice_mask) == 0) { + TFP_DRV_LOG(ERR, "block_id(0x%x) slice(%d) was not allocated\n", + block->block_id, slice_offset); + *is_allocated = false; + } else { + *is_allocated = true; + } + + return rc; +} + +/** + * Initialize slice list + */ +static void +tf_sram_init_slice_list(struct tf_sram_slice_list *slice_list, + enum tf_sram_slice_size slice_size) +{ + slice_list->head = NULL; + slice_list->tail = NULL; + slice_list->cnt = 0; + slice_list->size = slice_size; +} + +/** + * Get the block count + */ +static uint32_t +tf_sram_get_block_cnt(struct tf_sram_slice_list *slice_list) +{ + return slice_list->cnt; +} + + +/** + * Free a block data structure - does not free to the RM + */ +static void +tf_sram_free_block(struct tf_sram_slice_list *slice_list, + struct tf_sram_block *block) +{ + if (slice_list->head == block && slice_list->tail == block) { + slice_list->head = NULL; + slice_list->tail = NULL; + } else if (slice_list->head == block) { + slice_list->head = block->next; + slice_list->head->prev = NULL; + } else if (slice_list->tail == block) { + slice_list->tail = block->prev; + slice_list->tail->next = NULL; + } else { + block->prev->next = block->next; + block->next->prev = block->prev; + } + tfp_free(block); + slice_list->cnt--; +} +/** + * Free the entire slice_list + */ +static void +tf_sram_free_slice_list(struct tf_sram_slice_list *slice_list) +{ + uint32_t i, block_cnt; + struct tf_sram_block *nblock, *block; + + block_cnt = tf_sram_get_block_cnt(slice_list); + block = slice_list->head; + + for (i = 0; i < block_cnt; i++) { + nblock = block->next; + tf_sram_free_block(slice_list, block); + block = nblock; + } +} + +/** + * Allocate a single SRAM block from memory and add it to the slice list + */ +static struct tf_sram_block +*tf_sram_alloc_block(struct tf_sram_slice_list *slice_list, + uint16_t block_id) +{ + struct tf_sram_block *block; + struct tfp_calloc_parms cparms; + int rc; + + cparms.nitems = 1; + cparms.size = sizeof(struct tf_sram_block); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate block, rc:%s\n", + strerror(-rc)); + return NULL; + } + block = (struct tf_sram_block *)cparms.mem_va; + block->block_id = block_id; + + if (slice_list->head == NULL) { + slice_list->head = block; + slice_list->tail = block; + block->next = NULL; + block->prev = NULL; + } else { + block->next = slice_list->head; + block->prev = NULL; + block->next->prev = block; + slice_list->head = block->next->prev; + } + slice_list->cnt++; + return block; +} + +/** + * Find the first not full block in the slice list + */ +static void +tf_sram_find_first_not_full_block(struct tf_sram_slice_list *slice_list, + enum tf_sram_slice_size slice_size, + struct tf_sram_block **first_not_full_block) +{ + struct tf_sram_block *block = slice_list->head; + uint8_t slice_mask, mask; + + switch (slice_size) { + case TF_SRAM_SLICE_SIZE_8B: + slice_mask = 0xff; + break; + + case TF_SRAM_SLICE_SIZE_16B: + slice_mask = 0xf; + break; + + case TF_SRAM_SLICE_SIZE_32B: + slice_mask = 0x3; + break; + + case TF_SRAM_SLICE_SIZE_64B: + default: + slice_mask = 0x1; + break; + } + + *first_not_full_block = NULL; + + while (block) { + mask = block->in_use_mask & slice_mask; + if (mask != slice_mask) { + *first_not_full_block = block; + break; + } + block = block->next; + } +} +static void +tf_sram_dump_block(struct tf_sram_block *block) +{ + TFP_DRV_LOG(INFO, "block_id(0x%x) in_use_mask(0x%02x)\n", + block->block_id, + block->in_use_mask); +} + +/********************** + * External functions + **********************/ +int +tf_sram_mgr_bind(void **sram_handle) +{ + int rc = 0; + enum tf_sram_bank_id bank_id; + enum tf_sram_slice_size slice_size; + struct tf_sram *sram; + struct tf_sram_slice_list *slice_list; + enum tf_dir dir; + struct tfp_calloc_parms cparms; + + TF_CHECK_PARMS1(sram_handle); + + cparms.nitems = 1; + cparms.size = sizeof(struct tf_sram); + cparms.alignment = 0; + rc = tfp_calloc(&cparms); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "Failed to allocate SRAM mgmt data, rc:%s\n", + strerror(-rc)); + return rc; + } + sram = (struct tf_sram *)cparms.mem_va; + + /* For each direction + */ + for (dir = 0; dir < TF_DIR_MAX; dir++) { + /* For each bank + */ + for (bank_id = TF_SRAM_BANK_ID_0; + bank_id < TF_SRAM_BANK_ID_MAX; + bank_id++) { + /* Create each sized slice empty list + */ + for (slice_size = TF_SRAM_SLICE_SIZE_8B; + slice_size < TF_SRAM_SLICE_SIZE_MAX; + slice_size++) { + rc = tf_sram_get_slice_list(sram, &slice_list, + slice_size, dir, + bank_id); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "No SRAM slice list, rc:%s\n", + strerror(-rc)); + return rc; + } + tf_sram_init_slice_list(slice_list, slice_size); + } + } + } + + *sram_handle = sram; + + return rc; +} + +int +tf_sram_mgr_unbind(void *sram_handle) +{ + int rc = 0; + struct tf_sram *sram; + enum tf_sram_bank_id bank_id; + enum tf_sram_slice_size slice_size; + enum tf_dir dir; + struct tf_sram_slice_list *slice_list; + + TF_CHECK_PARMS1(sram_handle); + + sram = (struct tf_sram *)sram_handle; + + for (dir = 0; dir < TF_DIR_MAX; dir++) { + /* For each bank + */ + for (bank_id = TF_SRAM_BANK_ID_0; + bank_id < TF_SRAM_BANK_ID_MAX; + bank_id++) { + /* For each slice size + */ + for (slice_size = TF_SRAM_SLICE_SIZE_8B; + slice_size < TF_SRAM_SLICE_SIZE_MAX; + slice_size++) { + rc = tf_sram_get_slice_list(sram, &slice_list, + slice_size, dir, + bank_id); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "No SRAM slice list, rc:%s\n", + strerror(-rc)); + return rc; + } + if (tf_sram_get_block_cnt(slice_list)) + tf_sram_free_slice_list(slice_list); + } + } + } + + tfp_free(sram); + sram_handle = NULL; + + /* Freeing of the RM resources is handled by the table manager */ + return rc; +} + +int tf_sram_mgr_alloc(void *sram_handle, + struct tf_sram_mgr_alloc_parms *parms) +{ + int rc = 0; + struct tf_sram *sram; + struct tf_sram_slice_list *slice_list; + uint16_t block_id, slice_offset = 0; + uint32_t index; + struct tf_sram_block *block; + struct tf_rm_allocate_parms aparms = { 0 }; + bool block_is_full; + uint16_t block_offset; + + TF_CHECK_PARMS3(sram_handle, parms, parms->sram_offset); + + sram = (struct tf_sram *)sram_handle; + + /* Check the current slice list + */ + rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size, + parms->dir, parms->bank_id); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "No SRAM slice list, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* If the list is empty or all entries are full allocate a new block + */ + if (!slice_list->first_not_full_block) { + /* Allocate and insert a new block + */ + aparms.index = &index; + aparms.subtype = parms->tbl_type; + aparms.rm_db = parms->rm_db; + rc = tf_rm_allocate(&aparms); + if (rc) + return rc; + + block_id = index; + block = tf_sram_alloc_block(slice_list, block_id); + } else { + /* Block exists + */ + block = + (struct tf_sram_block *)(slice_list->first_not_full_block); + } + rc = tf_sram_get_next_slice_in_block(block, + parms->slice_size, + &slice_offset, + &block_is_full); + + /* Find the new first non-full block in the list + */ + tf_sram_find_first_not_full_block(slice_list, + parms->slice_size, + &slice_list->first_not_full_block); + + tf_sram_block_id_2_offset(parms->bank_id, block->block_id, + &block_offset); + + *parms->sram_offset = block_offset + slice_offset; + return rc; +} + +int +tf_sram_mgr_free(void *sram_handle, + struct tf_sram_mgr_free_parms *parms) +{ + int rc = 0; + struct tf_sram *sram; + struct tf_sram_slice_list *slice_list; + uint16_t block_id, slice_offset; + struct tf_sram_block *block; + bool block_is_empty; + struct tf_rm_free_parms fparms = { 0 }; + + TF_CHECK_PARMS2(sram_handle, parms); + + sram = (struct tf_sram *)sram_handle; + + /* Check the current slice list + */ + rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size, + parms->dir, parms->bank_id); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "No SRAM slice list, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* Determine the block id and slice offset from the SRAM offset + */ + tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id, + &slice_offset); + + /* Search the list of blocks for the matching block id + */ + block = tf_sram_find_block(block_id, slice_list); + if (block == NULL) { + TFP_DRV_LOG(ERR, "block not found 0x%x\n", block_id); + return rc; + } + + /* If found, search for the matching SRAM slice in use. + */ + rc = tf_sram_free_slice(parms->slice_size, slice_offset, + block, &block_is_empty); + if (rc) { + TFP_DRV_LOG(ERR, "Error freeing slice (%s)\n", strerror(-rc)); + return rc; + } +#if (STATS_CLEAR_ON_READ_SUPPORT == 0) + /* If this is a counter, clear it. In the future we need to switch to + * using the special access registers on Thor to automatically clear on + * read. + */ + /* If this is counter table, clear the entry on free */ + if (parms->tbl_type == TF_TBL_TYPE_ACT_STATS_64) { + uint8_t data[8] = { 0 }; + uint16_t hcapi_type = 0; + struct tf_rm_get_hcapi_parms hparms = { 0 }; + + /* Get the hcapi type */ + hparms.rm_db = parms->rm_db; + hparms.subtype = parms->tbl_type; + hparms.hcapi_type = &hcapi_type; + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Failed type lookup, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->tbl_type), + strerror(-rc)); + return rc; + } + /* Clear the counter + */ + rc = tf_msg_set_tbl_entry(parms->tfp, + parms->dir, + hcapi_type, + sizeof(data), + data, + parms->sram_offset); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Set failed, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->tbl_type), + strerror(-rc)); + return rc; + } + } +#endif + /* If the block is empty, free the block to the RM + */ + if (block_is_empty) { + fparms.rm_db = parms->rm_db; + fparms.subtype = parms->tbl_type; + fparms.index = block_id; + rc = tf_rm_free(&fparms); + + if (rc) { + TFP_DRV_LOG(ERR, "Free block_id(%d) failed error(%s)\n", + block_id, strerror(-rc)); + } + /* Free local entry regardless + */ + tf_sram_free_block(slice_list, block); + + /* Find the next non-full block in the list + */ + tf_sram_find_first_not_full_block(slice_list, + parms->slice_size, + &slice_list->first_not_full_block); + } + + return rc; +} + +int +tf_sram_mgr_dump(void *sram_handle, + struct tf_sram_mgr_dump_parms *parms) +{ + int rc = 0; + struct tf_sram *sram; + struct tf_sram_slice_list *slice_list; + uint32_t block_cnt, i; + struct tf_sram_block *block; + + TF_CHECK_PARMS2(sram_handle, parms); + + sram = (struct tf_sram *)sram_handle; + + rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size, + parms->dir, parms->bank_id); + if (rc) + return rc; + + if (slice_list->cnt || slice_list->first_not_full_block) { + TFP_DRV_LOG(INFO, "\n********** %s: %s: %s ***********\n", + tf_sram_bank_2_str(parms->bank_id), + tf_dir_2_str(parms->dir), + tf_sram_slice_2_str(parms->slice_size)); + + block_cnt = tf_sram_get_block_cnt(slice_list); + TFP_DRV_LOG(INFO, "block_cnt(%d)\n", block_cnt); + if (slice_list->first_not_full_block) + TFP_DRV_LOG(INFO, "first_not_full_block(0x%x)\n", + slice_list->first_not_full_block->block_id); + block = slice_list->head; + for (i = 0; i < block_cnt; i++) { + tf_sram_dump_block(block); + block = tf_sram_get_next_block(block); + } + TFP_DRV_LOG(INFO, "*********************************\n"); + } + return rc; +} +/** + * Validate an SRAM Slice is allocated + * + * Validate whether the SRAM slice is allocated + * + * [in] sram_handle + * Pointer to SRAM handle + * + * [in] parms + * Pointer to the SRAM alloc parameters + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + * + */ +int tf_sram_mgr_is_allocated(void *sram_handle, + struct tf_sram_mgr_is_allocated_parms *parms) +{ + int rc = 0; + struct tf_sram *sram; + struct tf_sram_slice_list *slice_list; + uint16_t block_id, slice_offset; + struct tf_sram_block *block; + + TF_CHECK_PARMS3(sram_handle, parms, parms->is_allocated); + + sram = (struct tf_sram *)sram_handle; + + /* Check the current slice list + */ + rc = tf_sram_get_slice_list(sram, &slice_list, parms->slice_size, + parms->dir, parms->bank_id); + if (rc) { + /* Log error */ + TFP_DRV_LOG(ERR, + "No SRAM slice list, rc:%s\n", + strerror(-rc)); + return rc; + } + + /* If the list is empty, then it cannot be allocated + */ + if (!slice_list->cnt) { + TFP_DRV_LOG(ERR, "List is empty for %s:%s:%s\n", + tf_dir_2_str(parms->dir), + tf_sram_slice_2_str(parms->slice_size), + tf_sram_bank_2_str(parms->bank_id)); + + parms->is_allocated = false; + goto done; + } + + /* Determine the block id and slice offset from the SRAM offset + */ + tf_sram_offset_2_block_id(parms->bank_id, parms->sram_offset, &block_id, + &slice_offset); + + /* Search the list of blocks for the matching block id + */ + block = tf_sram_find_block(block_id, slice_list); + if (block == NULL) { + TFP_DRV_LOG(ERR, "block not found in list 0x%x\n", + parms->sram_offset); + parms->is_allocated = false; + goto done; + } + + rc = tf_sram_is_slice_allocated_in_block(block, + parms->slice_size, + slice_offset, + parms->is_allocated); +done: + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_sram_mgr.h b/drivers/net/bnxt/tf_core/tf_sram_mgr.h new file mode 100644 index 0000000000..4abe3fb468 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_sram_mgr.h @@ -0,0 +1,317 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#ifndef _TF_SRAM_MGR_H_ +#define _TF_SRAM_MGR_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "tf_core.h" +#include "tf_rm.h" + +/* When special access registers are used to access the SRAM, stats can be + * automatically cleared on read by the hardware. This requires additional + * support to be added in the firmware to use these registers for statistics. + * The support entails using the special access registers to read the stats. + * These are stored in bank 3 currently but may move depending upon the + * policy defined in tf_device_p58.h + */ +#define STATS_CLEAR_ON_READ_SUPPORT 0 + +#define TF_SRAM_MGR_BLOCK_SZ_BYTES 64 +#define TF_SRAM_MGR_MIN_SLICE_BYTES 8 +/** + * Bank identifier + */ +enum tf_sram_bank_id { + TF_SRAM_BANK_ID_0, /**< SRAM Bank 0 id */ + TF_SRAM_BANK_ID_1, /**< SRAM Bank 1 id */ + TF_SRAM_BANK_ID_2, /**< SRAM Bank 2 id */ + TF_SRAM_BANK_ID_3, /**< SRAM Bank 3 id */ + TF_SRAM_BANK_ID_MAX /**< SRAM Bank index limit */ +}; + +/** + * TF slice size. + * + * A slice is part of a 64B row + * + * Each slice is a multiple of 8B + */ +enum tf_sram_slice_size { + TF_SRAM_SLICE_SIZE_8B, /**< 8 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_16B, /**< 16 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_32B, /**< 32 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_64B, /**< 64 byte SRAM slice */ + TF_SRAM_SLICE_SIZE_MAX /**< slice limit */ +}; + + +/** Initialize the SRAM slice manager + * + * The SRAM slice manager manages slices within 64B rows. Slices are of size + * tf_sram_slice_size. This function provides a handle to the SRAM manager + * data. + * + * SRAM manager data may dynamically allocate data upon initialization if + * running on the host. + * + * [in/out] sram_handle + * Pointer to SRAM handle + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + * + * Returns the handle for the SRAM slice manager + */ +int tf_sram_mgr_bind(void **sram_handle); + +/** Uninitialize the SRAM slice manager + * + * Frees any dynamically allocated data structures for SRAM slice management. + * + * [in] sram_handle + * Pointer to SRAM handle + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + */ +int tf_sram_mgr_unbind(void *sram_handle); + +/** + * tf_sram_mgr_alloc_parms parameter definition + */ +struct tf_sram_mgr_alloc_parms { + /** + * [in] dir + */ + enum tf_dir dir; + /** + * [in] bank + * + * the SRAM bank to allocate from + */ + enum tf_sram_bank_id bank_id; + /** + * [in] slice_size + * + * the slice size to allocate + */ + enum tf_sram_slice_size slice_size; + /** + * [in/out] sram_slice + * + * A pointer to be filled with an 8B sram slice offset + */ + uint16_t *sram_offset; + /** + * [in] RM DB Handle required for RM allocation + */ + void *rm_db; + /** + * [in] tf table type + */ + enum tf_tbl_type tbl_type; +}; + +/** + * Allocate an SRAM Slice + * + * Allocate an SRAM slice from the indicated bank. If successful an 8B SRAM + * offset will be returned. Slices are variable sized. This may result in + * a row being allocated from the RM SRAM bank pool if required. + * + * [in] sram_handle + * Pointer to SRAM handle + * + * [in] parms + * Pointer to the SRAM alloc parameters + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + * + */ +int tf_sram_mgr_alloc(void *sram_handle, + struct tf_sram_mgr_alloc_parms *parms); +/** + * tf_sram_mgr_free_parms parameter definition + */ +struct tf_sram_mgr_free_parms { + /** + * [in] dir + */ + enum tf_dir dir; + /** + * [in] bank + * + * the SRAM bank to free to + */ + enum tf_sram_bank_id bank_id; + /** + * [in] slice_size + * + * the slice size to be returned + */ + enum tf_sram_slice_size slice_size; + /** + * [in] sram_offset + * + * the SRAM slice offset (8B) to be returned + */ + uint16_t sram_offset; + /** + * [in] RM DB Handle required for RM free + */ + void *rm_db; + /** + * [in] tf table type + */ + enum tf_tbl_type tbl_type; +#if (STATS_CLEAR_ON_READ_SUPPORT == 0) + /** + * [in] tfp + * + * A pointer to the tf handle + */ + void *tfp; +#endif +}; + +/** + * Free an SRAM Slice + * + * Free an SRAM slice to the indicated bank. This may result in a 64B row + * being returned to the RM SRAM bank pool. + * + * [in] sram_handle + * Pointer to SRAM handle + * + * [in] parms + * Pointer to the SRAM free parameters + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + * + */ +int tf_sram_mgr_free(void *sram_handle, + struct tf_sram_mgr_free_parms *parms); + +/** + * tf_sram_mgr_dump_parms parameter definition + */ +struct tf_sram_mgr_dump_parms { + /** + * [in] dir + */ + enum tf_dir dir; + /** + * [in] bank + * + * the SRAM bank to dump + */ + enum tf_sram_bank_id bank_id; + /** + * [in] slice_size + * + * the slice size list to be dumped + */ + enum tf_sram_slice_size slice_size; +}; + +/** + * Dump a slice list + * + * Dump the slice list given the SRAM bank and the slice size + * + * [in] sram_handle + * Pointer to SRAM handle + * + * [in] parms + * Pointer to the SRAM free parameters + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + * + */ +int tf_sram_mgr_dump(void *sram_handle, + struct tf_sram_mgr_dump_parms *parms); + +/** + * tf_sram_mgr_is_allocated_parms parameter definition + */ +struct tf_sram_mgr_is_allocated_parms { + /** + * [in] dir + */ + enum tf_dir dir; + /** + * [in] bank + * + * the SRAM bank to allocate from + */ + enum tf_sram_bank_id bank_id; + /** + * [in] slice_size + * + * the slice size which was allocated + */ + enum tf_sram_slice_size slice_size; + /** + * [in] sram_offset + * + * The sram slice offset to validate + */ + uint16_t sram_offset; + /** + * [in/out] is_allocated + * + * Pointer passed in to be filled with indication of allocation + */ + bool *is_allocated; +}; + +/** + * Validate an SRAM Slice is allocated + * + * Validate whether the SRAM slice is allocated + * + * [in] sram_handle + * Pointer to SRAM handle + * + * [in] parms + * Pointer to the SRAM alloc parameters + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + * + */ +int tf_sram_mgr_is_allocated(void *sram_handle, + struct tf_sram_mgr_is_allocated_parms *parms); + +/** + * Given the slice size, return a char string + */ +const char +*tf_sram_slice_2_str(enum tf_sram_slice_size slice_size); + +/** + * Given the bank_id, return a char string + */ +const char +*tf_sram_bank_2_str(enum tf_sram_bank_id bank_id); + +#endif /* _TF_SRAM_MGR_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c index 7011edcd78..0a8720e7b6 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.c +++ b/drivers/net/bnxt/tf_core/tf_tbl.c @@ -16,20 +16,11 @@ #include "tf_session.h" #include "tf_device.h" -#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \ - *(new_idx) = (((idx) + (base)) << (shift)); \ -} - -#define TF_TBL_PTR_TO_RM(new_idx, idx, base, shift) { \ - *(new_idx) = (((idx) >> (shift)) - (base)); \ -} - struct tf; -/** - * Shadow init flag, set on bind and cleared on unbind - */ -static uint8_t shadow_init; +#define TF_TBL_RM_TO_PTR(new_idx, idx, base, shift) { \ + *(new_idx) = (((idx) + (base)) << (shift)); \ +} int tf_tbl_bind(struct tf *tfp, @@ -121,8 +112,6 @@ tf_tbl_unbind(struct tf *tfp) tbl_db->tbl_db[i] = NULL; } - shadow_init = 0; - return 0; } @@ -135,7 +124,6 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, struct tf_rm_allocate_parms aparms = { 0 }; struct tf_session *tfs; struct tf_dev_info *dev; - uint16_t base = 0, shift = 0; struct tbl_rm_db *tbl_db; void *tbl_db_ptr = NULL; @@ -154,28 +142,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); if (rc) { TFP_DRV_LOG(ERR, - "Failed to get em_ext_db from session, rc:%s\n", + "Failed to get tbl_db from session, rc:%s\n", strerror(-rc)); return rc; } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Only get table info if required for the device */ - if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, - tbl_db->tbl_db[parms->dir], - parms->type, - &base, - &shift); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to get table info:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - } - /* Allocate requested element */ aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; @@ -183,13 +155,12 @@ tf_tbl_alloc(struct tf *tfp __rte_unused, rc = tf_rm_allocate(&aparms); if (rc) { TFP_DRV_LOG(ERR, - "%s: Failed allocate, type:%d\n", + "%s: Failed allocate, type:%s\n", tf_dir_2_str(parms->dir), - parms->type); + tf_tbl_type_2_str(parms->type)); return rc; } - TF_TBL_RM_TO_PTR(&idx, idx, base, shift); *parms->idx = idx; return 0; @@ -205,7 +176,6 @@ tf_tbl_free(struct tf *tfp __rte_unused, int allocated = 0; struct tf_session *tfs; struct tf_dev_info *dev; - uint16_t base = 0, shift = 0; struct tbl_rm_db *tbl_db; void *tbl_db_ptr = NULL; @@ -230,28 +200,10 @@ tf_tbl_free(struct tf *tfp __rte_unused, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Only get table info if required for the device */ - if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, - tbl_db->tbl_db[parms->dir], - parms->type, - &base, - &shift); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to get table info:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - } - /* Check if element is in use */ aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; - - TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); - + aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) @@ -259,9 +211,9 @@ tf_tbl_free(struct tf *tfp __rte_unused, if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { TFP_DRV_LOG(ERR, - "%s: Entry already free, type:%d, index:%d\n", + "%s: Entry already free, type:%s, index:%d\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), parms->idx); return -EINVAL; } @@ -279,9 +231,9 @@ tf_tbl_free(struct tf *tfp __rte_unused, rc = tf_rm_get_hcapi_type(&hparms); if (rc) { TFP_DRV_LOG(ERR, - "%s, Failed type lookup, type:%d, rc:%s\n", + "%s, Failed type lookup, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); return rc; } @@ -295,9 +247,9 @@ tf_tbl_free(struct tf *tfp __rte_unused, parms->idx); if (rc) { TFP_DRV_LOG(ERR, - "%s, Set failed, type:%d, rc:%s\n", + "%s, Set failed, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); return rc; } @@ -306,15 +258,13 @@ tf_tbl_free(struct tf *tfp __rte_unused, /* Free requested element */ fparms.rm_db = tbl_db->tbl_db[parms->dir]; fparms.subtype = parms->type; - - TF_TBL_PTR_TO_RM(&fparms.index, parms->idx, base, shift); - + fparms.index = parms->idx; rc = tf_rm_free(&fparms); if (rc) { TFP_DRV_LOG(ERR, - "%s: Free failed, type:%d, index:%d\n", + "%s: Free failed, type:%s, index:%d\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), parms->idx); return rc; } @@ -333,7 +283,6 @@ tf_tbl_set(struct tf *tfp, struct tf_rm_get_hcapi_parms hparms = { 0 }; struct tf_session *tfs; struct tf_dev_info *dev; - uint16_t base = 0, shift = 0; struct tbl_rm_db *tbl_db; void *tbl_db_ptr = NULL; @@ -358,21 +307,6 @@ tf_tbl_set(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Only get table info if required for the device */ - if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, - tbl_db->tbl_db[parms->dir], - parms->type, - &base, - &shift); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to get table info:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - } /* Do not check meter drop counter because it is not allocated * resources @@ -381,19 +315,18 @@ tf_tbl_set(struct tf *tfp, /* Verify that the entry has been previously allocated */ aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; - TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); - aparms.allocated = &allocated; + aparms.index = parms->idx; rc = tf_rm_is_allocated(&aparms); if (rc) return rc; if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%d, idx:%d\n", - tf_dir_2_str(parms->dir), - parms->type, - parms->idx); + "%s, Invalid or not allocated, type:%s, idx:%d\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); return -EINVAL; } } @@ -405,9 +338,9 @@ tf_tbl_set(struct tf *tfp, rc = tf_rm_get_hcapi_type(&hparms); if (rc) { TFP_DRV_LOG(ERR, - "%s, Failed type lookup, type:%d, rc:%s\n", + "%s, Failed type lookup, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); return rc; } @@ -420,9 +353,9 @@ tf_tbl_set(struct tf *tfp, parms->idx); if (rc) { TFP_DRV_LOG(ERR, - "%s, Set failed, type:%d, rc:%s\n", + "%s, Set failed, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); return rc; } @@ -441,7 +374,6 @@ tf_tbl_get(struct tf *tfp, struct tf_rm_get_hcapi_parms hparms = { 0 }; struct tf_session *tfs; struct tf_dev_info *dev; - uint16_t base = 0, shift = 0; struct tbl_rm_db *tbl_db; void *tbl_db_ptr = NULL; @@ -466,22 +398,6 @@ tf_tbl_get(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Only get table info if required for the device */ - if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, - tbl_db->tbl_db[parms->dir], - parms->type, - &base, - &shift); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to get table info:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - } - /* Do not check meter drop counter because it is not allocated * resources. */ @@ -489,8 +405,7 @@ tf_tbl_get(struct tf *tfp, /* Verify that the entry has been previously allocated */ aparms.rm_db = tbl_db->tbl_db[parms->dir]; aparms.subtype = parms->type; - TF_TBL_PTR_TO_RM(&aparms.index, parms->idx, base, shift); - + aparms.index = parms->idx; aparms.allocated = &allocated; rc = tf_rm_is_allocated(&aparms); if (rc) @@ -498,9 +413,9 @@ tf_tbl_get(struct tf *tfp, if (allocated != TF_RM_ALLOCATED_ENTRY_IN_USE) { TFP_DRV_LOG(ERR, - "%s, Invalid or not allocated index, type:%d, idx:%d\n", + "%s, Invalid or not allocated index, type:%s, idx:%d\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), parms->idx); return -EINVAL; } @@ -513,9 +428,9 @@ tf_tbl_get(struct tf *tfp, rc = tf_rm_get_hcapi_type(&hparms); if (rc) { TFP_DRV_LOG(ERR, - "%s, Failed type lookup, type:%d, rc:%s\n", + "%s, Failed type lookup, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); return rc; } @@ -529,9 +444,9 @@ tf_tbl_get(struct tf *tfp, parms->idx); if (rc) { TFP_DRV_LOG(ERR, - "%s, Get failed, type:%d, rc:%s\n", + "%s, Get failed, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); return rc; } @@ -549,7 +464,6 @@ tf_tbl_bulk_get(struct tf *tfp, struct tf_rm_check_indexes_in_range_parms cparms = { 0 }; struct tf_session *tfs; struct tf_dev_info *dev; - uint16_t base = 0, shift = 0; struct tbl_rm_db *tbl_db; void *tbl_db_ptr = NULL; @@ -574,40 +488,21 @@ tf_tbl_bulk_get(struct tf *tfp, } tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* Only get table info if required for the device */ - if (dev->ops->tf_dev_get_tbl_info) { - rc = dev->ops->tf_dev_get_tbl_info(tfp, - tbl_db->tbl_db[parms->dir], - parms->type, - &base, - &shift); - if (rc) { - TFP_DRV_LOG(ERR, - "%s: Failed to get table info:%d\n", - tf_dir_2_str(parms->dir), - parms->type); - return rc; - } - } - /* Verify that the entries are in the range of reserved resources. */ cparms.rm_db = tbl_db->tbl_db[parms->dir]; cparms.subtype = parms->type; - - TF_TBL_PTR_TO_RM(&cparms.starting_index, parms->starting_idx, - base, shift); - cparms.num_entries = parms->num_entries; + cparms.starting_index = parms->starting_idx; rc = tf_rm_check_indexes_in_range(&cparms); if (rc) { TFP_DRV_LOG(ERR, "%s, Invalid or %d index starting from %d" - " not in range, type:%d", + " not in range, type:%s", tf_dir_2_str(parms->dir), parms->starting_idx, parms->num_entries, - parms->type); + tf_tbl_type_2_str(parms->type)); return rc; } @@ -617,9 +512,9 @@ tf_tbl_bulk_get(struct tf *tfp, rc = tf_rm_get_hcapi_type(&hparms); if (rc) { TFP_DRV_LOG(ERR, - "%s, Failed type lookup, type:%d, rc:%s\n", + "%s, Failed type lookup, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); return rc; } @@ -634,9 +529,9 @@ tf_tbl_bulk_get(struct tf *tfp, parms->physical_mem_addr); if (rc) { TFP_DRV_LOG(ERR, - "%s, Bulk get failed, type:%d, rc:%s\n", + "%s, Bulk get failed, type:%s, rc:%s\n", tf_dir_2_str(parms->dir), - parms->type, + tf_tbl_type_2_str(parms->type), strerror(-rc)); } @@ -653,9 +548,9 @@ tf_tbl_get_resc_info(struct tf *tfp, struct tf_rm_get_alloc_info_parms ainfo; void *tbl_db_ptr = NULL; struct tbl_rm_db *tbl_db; - uint16_t base = 0, shift = 0; struct tf_dev_info *dev; struct tf_session *tfs; + uint16_t base = 0, shift = 0; TF_CHECK_PARMS2(tfp, tbl); @@ -677,7 +572,6 @@ tf_tbl_get_resc_info(struct tf *tfp, tbl_db = (struct tbl_rm_db *)tbl_db_ptr; - /* check if reserved resource for WC is multiple of num_slices */ for (d = 0; d < TF_DIR_MAX; d++) { ainfo.rm_db = tbl_db->tbl_db[d]; dinfo = tbl[d].info; diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h index 7e1107ffe7..2483718e5d 100644 --- a/drivers/net/bnxt/tf_core/tf_tbl.h +++ b/drivers/net/bnxt/tf_core/tf_tbl.h @@ -28,14 +28,6 @@ struct tf_tbl_cfg_parms { * Table Type element configuration array */ struct tf_rm_element_cfg *cfg; - /** - * Shadow table type configuration array - */ - struct tf_shadow_tbl_cfg *shadow_cfg; - /** - * Boolean controlling the request shadow copy. - */ - bool shadow_copy; /** * Session resource allocations */ @@ -197,8 +189,6 @@ struct tbl_rm_db { * * @ref tf_tbl_free * - * @ref tf_tbl_alloc_search - * * @ref tf_tbl_set * * @ref tf_tbl_get @@ -255,10 +245,7 @@ int tf_tbl_alloc(struct tf *tfp, struct tf_tbl_alloc_parms *parms); /** - * Free's the requested table type and returns it to the DB. If shadow - * DB is enabled its searched first and if found the element refcount - * is decremented. If refcount goes to 0 then its returned to the - * table type DB. + * Frees the requested table type and returns it to the DB. * * [in] tfp * Pointer to TF handle, used for HCAPI communication diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.c b/drivers/net/bnxt/tf_core/tf_tbl_sram.c new file mode 100644 index 0000000000..ea10afecb6 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.c @@ -0,0 +1,713 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +/* Truflow Table APIs and supporting code */ + +#include + +#include "tf_tbl.h" +#include "tf_tbl_sram.h" +#include "tf_sram_mgr.h" +#include "tf_common.h" +#include "tf_rm.h" +#include "tf_util.h" +#include "tf_msg.h" +#include "tfp.h" +#include "tf_session.h" +#include "tf_device.h" +#include "cfa_resource_types.h" + +#define DBG_SRAM 0 + +/** + * tf_sram_tbl_get_info_parms parameter definition + */ +struct tf_tbl_sram_get_info_parms { + /** + * [in] table RM database + */ + void *rm_db; + /** + * [in] Receive or transmit direction + */ + enum tf_dir dir; + /** + * [in] table_type + * + * the TF index table type + */ + enum tf_tbl_type tbl_type; + /** + * [out] bank + * + * The SRAM bank associated with the type + */ + enum tf_sram_bank_id bank_id; + /** + * [out] slice_size + * + * the slice size for the indicated table type + */ + enum tf_sram_slice_size slice_size; +}; + +/** + * Translate HCAPI type to SRAM Manager bank + */ +const uint16_t tf_tbl_sram_hcapi_2_bank[CFA_RESOURCE_TYPE_P58_LAST] = { + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = TF_SRAM_BANK_ID_0, + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = TF_SRAM_BANK_ID_1, + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = TF_SRAM_BANK_ID_2, + [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = TF_SRAM_BANK_ID_3 +}; + +#define TF_TBL_SRAM_SLICES_MAX \ + (TF_SRAM_MGR_BLOCK_SZ_BYTES / TF_SRAM_MGR_MIN_SLICE_BYTES) +/** + * Translate HCAPI type to SRAM Manager bank + */ +const uint8_t tf_tbl_sram_slices_2_size[TF_TBL_SRAM_SLICES_MAX + 1] = { + [0] = TF_SRAM_SLICE_SIZE_64B, /* if 0 slices assume 1 64B block */ + [1] = TF_SRAM_SLICE_SIZE_64B, /* 1 slice per 64B block */ + [2] = TF_SRAM_SLICE_SIZE_32B, /* 2 slices per 64B block */ + [4] = TF_SRAM_SLICE_SIZE_16B, /* 4 slices per 64B block */ + [8] = TF_SRAM_SLICE_SIZE_8B /* 8 slices per 64B block */ +}; + +/** + * Get SRAM Table Information for a given index table type + * + * + * [in] sram_handle + * Pointer to SRAM handle + * + * [in] parms + * Pointer to the SRAM get info parameters + * + * Returns + * - (0) if successful + * - (-EINVAL) on failure + * + */ +static int tf_tbl_sram_get_info(struct tf_tbl_sram_get_info_parms *parms) +{ + int rc = 0; + uint16_t hcapi_type; + uint16_t slices; + struct tf_rm_get_hcapi_parms hparms; + struct tf_rm_get_slices_parms sparms; + + hparms.rm_db = parms->rm_db; + hparms.subtype = parms->tbl_type; + hparms.hcapi_type = &hcapi_type; + + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get hcapi_type %s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->tbl_type), + strerror(-rc)); + return rc; + } + parms->bank_id = tf_tbl_sram_hcapi_2_bank[hcapi_type]; + + sparms.rm_db = parms->rm_db; + sparms.subtype = parms->tbl_type; + sparms.slices = &slices; + + rc = tf_rm_get_slices(&sparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get slice cnt %s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->tbl_type), + strerror(-rc)); + return rc; + } + if (slices) + parms->slice_size = tf_tbl_sram_slices_2_size[slices]; + + TFP_DRV_LOG(INFO, + "(%s) bank(%s) slice_size(%s)\n", + tf_tbl_type_2_str(parms->tbl_type), + tf_sram_bank_2_str(parms->bank_id), + tf_sram_slice_2_str(parms->slice_size)); + return rc; +} + +int +tf_tbl_sram_bind(struct tf *tfp __rte_unused) +{ + int rc = 0; + void *sram_handle = NULL; + + TF_CHECK_PARMS1(tfp); + + rc = tf_sram_mgr_bind(&sram_handle); + + tf_session_set_sram_db(tfp, sram_handle); + + TFP_DRV_LOG(INFO, + "SRAM Table - initialized\n"); + + return rc; +} + +int +tf_tbl_sram_unbind(struct tf *tfp __rte_unused) +{ + int rc = 0; + void *sram_handle = NULL; + + TF_CHECK_PARMS1(tfp); + + rc = tf_session_get_sram_db(tfp, &sram_handle); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get sram_handle from session, rc:%s\n", + strerror(-rc)); + return rc; + } + if (sram_handle) + rc = tf_sram_mgr_unbind(sram_handle); + + TFP_DRV_LOG(INFO, + "SRAM Table - deinitialized\n"); + return rc; +} + +int +tf_tbl_sram_alloc(struct tf *tfp, + struct tf_tbl_alloc_parms *parms) +{ + int rc; + uint16_t idx; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tf_tbl_sram_get_info_parms iparms = { 0 }; + struct tf_sram_mgr_alloc_parms aparms = { 0 }; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; + void *sram_handle = NULL; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get(tfp, &tfs, &dev); + if (rc) + return rc; + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get tbl_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + + rc = tf_session_get_sram_db(tfp, &sram_handle); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get sram_handle from session, rc:%s\n", + strerror(-rc)); + return rc; + } + + iparms.rm_db = tbl_db->tbl_db[parms->dir]; + iparms.dir = parms->dir; + iparms.tbl_type = parms->type; + + rc = tf_tbl_sram_get_info(&iparms); + + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get SRAM info %s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type)); + return rc; + } + + aparms.dir = parms->dir; + aparms.bank_id = iparms.bank_id; + aparms.slice_size = iparms.slice_size; + aparms.sram_offset = &idx; + aparms.tbl_type = parms->type; + aparms.rm_db = tbl_db->tbl_db[parms->dir]; + + rc = tf_sram_mgr_alloc(sram_handle, &aparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to allocate SRAM table:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type)); + return rc; + } + *parms->idx = idx; + +#if (DBG_SRAM == 1) + { + struct tf_sram_mgr_dump_parms dparms; + + dparms.dir = parms->dir; + dparms.bank_id = iparms.bank_id; + dparms.slice_size = iparms.slice_size; + + rc = tf_sram_mgr_dump(sram_handle, &dparms); + } +#endif + + return rc; +} + +int +tf_tbl_sram_free(struct tf *tfp __rte_unused, + struct tf_tbl_free_parms *parms) +{ + int rc; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; + struct tf_tbl_sram_get_info_parms iparms = { 0 }; + struct tf_sram_mgr_free_parms fparms = { 0 }; + struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; + bool allocated = false; + void *sram_handle = NULL; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get(tfp, &tfs, &dev); + if (rc) + return rc; + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + + rc = tf_session_get_sram_db(tfp, &sram_handle); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get sram_handle from session, rc:%s\n", + strerror(-rc)); + return rc; + } + + iparms.rm_db = tbl_db->tbl_db[parms->dir]; + iparms.dir = parms->dir; + iparms.tbl_type = parms->type; + + rc = tf_tbl_sram_get_info(&iparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type)); + return rc; + } + +#if (DBG_SRAM == 1) + { + struct tf_sram_mgr_dump_parms dparms; + + printf("%s: %s: %s\n", tf_dir_2_str(parms->dir), + tf_sram_slice_2_str(iparms.slice_size), + tf_sram_bank_2_str(iparms.bank_id)); + + dparms.dir = parms->dir; + dparms.bank_id = iparms.bank_id; + dparms.slice_size = iparms.slice_size; + + rc = tf_sram_mgr_dump(sram_handle, &dparms); + } +#endif + + aparms.sram_offset = parms->idx; + aparms.slice_size = iparms.slice_size; + aparms.bank_id = iparms.bank_id; + aparms.dir = parms->dir; + aparms.is_allocated = &allocated; + + rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); + if (rc || !allocated) { + TFP_DRV_LOG(ERR, + "%s: Free of invalid entry:%s idx(%d):(%s)\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx, + strerror(-rc)); + rc = -ENOMEM; + return rc; + } + + fparms.rm_db = tbl_db->tbl_db[parms->dir]; + fparms.tbl_type = parms->type; + fparms.sram_offset = parms->idx; + fparms.slice_size = iparms.slice_size; + fparms.bank_id = iparms.bank_id; + fparms.dir = parms->dir; +#if (STATS_CLEAR_ON_READ_SUPPORT == 0) + fparms.tfp = tfp; +#endif + rc = tf_sram_mgr_free(sram_handle, &fparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to free entry:%s idx(%d)\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx); + return rc; + } + + +#if (DBG_SRAM == 1) + { + struct tf_sram_mgr_dump_parms dparms; + + printf("%s: %s: %s\n", tf_dir_2_str(parms->dir), + tf_sram_slice_2_str(iparms.slice_size), + tf_sram_bank_2_str(iparms.bank_id)); + + dparms.dir = parms->dir; + dparms.bank_id = iparms.bank_id; + dparms.slice_size = iparms.slice_size; + + rc = tf_sram_mgr_dump(sram_handle, &dparms); + } +#endif + return rc; +} + +int +tf_tbl_sram_set(struct tf *tfp, + struct tf_tbl_set_parms *parms) +{ + int rc; + bool allocated = 0; + uint16_t hcapi_type; + struct tf_rm_get_hcapi_parms hparms = { 0 }; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; + struct tf_tbl_sram_get_info_parms iparms = { 0 }; + struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; + void *sram_handle = NULL; + + + TF_CHECK_PARMS3(tfp, parms, parms->data); + + /* Retrieve the session information */ + rc = tf_session_get(tfp, &tfs, &dev); + if (rc) + return rc; + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + + rc = tf_session_get_sram_db(tfp, &sram_handle); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get sram_handle from session, rc:%s\n", + strerror(-rc)); + return rc; + } + + iparms.rm_db = tbl_db->tbl_db[parms->dir]; + iparms.dir = parms->dir; + iparms.tbl_type = parms->type; + + rc = tf_tbl_sram_get_info(&iparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type)); + return rc; + } + + aparms.sram_offset = parms->idx; + aparms.slice_size = iparms.slice_size; + aparms.bank_id = iparms.bank_id; + aparms.dir = parms->dir; + aparms.is_allocated = &allocated; + rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); + if (rc || !allocated) { + TFP_DRV_LOG(ERR, + "%s: Entry not allocated:%s idx(%d):(%s)\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx, + strerror(-rc)); + rc = -ENOMEM; + return rc; + } + + /* Set the entry */ + hparms.rm_db = tbl_db->tbl_db[parms->dir]; + hparms.subtype = parms->type; + hparms.hcapi_type = &hcapi_type; + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Failed type lookup, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + strerror(-rc)); + return rc; + } + + rc = tf_msg_set_tbl_entry(tfp, + parms->dir, + hcapi_type, + parms->data_sz_in_bytes, + parms->data, + parms->idx); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Set failed, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + strerror(-rc)); + return rc; + } + return rc; +} + +int +tf_tbl_sram_get(struct tf *tfp, + struct tf_tbl_get_parms *parms) +{ + int rc; + uint16_t hcapi_type; + bool allocated = 0; + struct tf_rm_get_hcapi_parms hparms = { 0 }; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; + struct tf_tbl_sram_get_info_parms iparms = { 0 }; + struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; + void *sram_handle = NULL; + + TF_CHECK_PARMS3(tfp, parms, parms->data); + + /* Retrieve the session information */ + rc = tf_session_get(tfp, &tfs, &dev); + if (rc) + return rc; + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + + rc = tf_session_get_sram_db(tfp, &sram_handle); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get sram_handle from session, rc:%s\n", + strerror(-rc)); + return rc; + } + + iparms.rm_db = tbl_db->tbl_db[parms->dir]; + iparms.dir = parms->dir; + iparms.tbl_type = parms->type; + + rc = tf_tbl_sram_get_info(&iparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type)); + return rc; + } + + aparms.sram_offset = parms->idx; + aparms.slice_size = iparms.slice_size; + aparms.bank_id = iparms.bank_id; + aparms.dir = parms->dir; + aparms.is_allocated = &allocated; + + rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); + if (rc || !allocated) { + TFP_DRV_LOG(ERR, + "%s: Entry not allocated:%s idx(%d):(%s)\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->idx, + strerror(-rc)); + rc = -ENOMEM; + return rc; + } + + /* Get the entry */ + hparms.rm_db = tbl_db->tbl_db[parms->dir]; + hparms.subtype = parms->type; + hparms.hcapi_type = &hcapi_type; + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Failed type lookup, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + strerror(-rc)); + return rc; + } + + /* Get the entry */ + rc = tf_msg_get_tbl_entry(tfp, + parms->dir, + hcapi_type, + parms->data_sz_in_bytes, + parms->data, + parms->idx); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Get failed, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + strerror(-rc)); + return rc; + } + return rc; +} + +int +tf_tbl_sram_bulk_get(struct tf *tfp, + struct tf_tbl_get_bulk_parms *parms) +{ + int rc; + uint16_t hcapi_type; + struct tf_rm_get_hcapi_parms hparms = { 0 }; + struct tf_tbl_sram_get_info_parms iparms = { 0 }; + struct tf_session *tfs; + struct tf_dev_info *dev; + struct tbl_rm_db *tbl_db; + void *tbl_db_ptr = NULL; + uint16_t idx; + struct tf_sram_mgr_is_allocated_parms aparms = { 0 }; + bool allocated = false; + void *sram_handle = NULL; + + TF_CHECK_PARMS2(tfp, parms); + + /* Retrieve the session information */ + rc = tf_session_get(tfp, &tfs, &dev); + if (rc) + return rc; + + rc = tf_session_get_db(tfp, TF_MODULE_TYPE_TABLE, &tbl_db_ptr); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get em_ext_db from session, rc:%s\n", + strerror(-rc)); + return rc; + } + tbl_db = (struct tbl_rm_db *)tbl_db_ptr; + + rc = tf_session_get_sram_db(tfp, &sram_handle); + if (rc) { + TFP_DRV_LOG(ERR, + "Failed to get sram_handle from session, rc:%s\n", + strerror(-rc)); + return rc; + } + + iparms.rm_db = tbl_db->tbl_db[parms->dir]; + iparms.dir = parms->dir; + iparms.tbl_type = parms->type; + + rc = tf_tbl_sram_get_info(&iparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s: Failed to get table info:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type)); + return rc; + } + + /* Validate the start offset and the end offset is allocated + * This API is only used for statistics. 8 Byte entry allocation + * is used to verify + */ + aparms.sram_offset = parms->starting_idx; + aparms.slice_size = iparms.slice_size; + aparms.bank_id = iparms.bank_id; + aparms.dir = parms->dir; + aparms.is_allocated = &allocated; + rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); + if (rc || !allocated) { + TFP_DRV_LOG(ERR, + "%s: Entry not allocated:%s starting_idx(%d):(%s)\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + parms->starting_idx, + strerror(-rc)); + rc = -ENOMEM; + return rc; + } + idx = parms->starting_idx + parms->num_entries - 1; + aparms.sram_offset = idx; + rc = tf_sram_mgr_is_allocated(sram_handle, &aparms); + if (rc || !allocated) { + TFP_DRV_LOG(ERR, + "%s: Entry not allocated:%s last_idx(%d):(%s)\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + idx, + strerror(-rc)); + rc = -ENOMEM; + return rc; + } + + hparms.rm_db = tbl_db->tbl_db[parms->dir]; + hparms.subtype = parms->type; + hparms.hcapi_type = &hcapi_type; + rc = tf_rm_get_hcapi_type(&hparms); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Failed type lookup, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + strerror(-rc)); + return rc; + } + + /* Get the entries */ + rc = tf_msg_bulk_get_tbl_entry(tfp, + parms->dir, + hcapi_type, + parms->starting_idx, + parms->num_entries, + parms->entry_sz_in_bytes, + parms->physical_mem_addr); + if (rc) { + TFP_DRV_LOG(ERR, + "%s, Bulk get failed, type:%s, rc:%s\n", + tf_dir_2_str(parms->dir), + tf_tbl_type_2_str(parms->type), + strerror(-rc)); + } + return rc; +} diff --git a/drivers/net/bnxt/tf_core/tf_tbl_sram.h b/drivers/net/bnxt/tf_core/tf_tbl_sram.h new file mode 100644 index 0000000000..32001e34a9 --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_tbl_sram.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2021 Broadcom + * All rights reserved. + */ + +#ifndef TF_TBL_SRAM_H_ +#define TF_TBL_SRAM_H_ + +#include "tf_core.h" +#include "stack.h" + + +/** + * The SRAM Table module provides processing of managed SRAM types. + */ + + +/** + * @page tblsram SRAM Table + * + * @ref tf_tbl_sram_bind + * + * @ref tf_tbl_sram_unbind + * + * @ref tf_tbl_sram_alloc + * + * @ref tf_tbl_sram_free + * + * @ref tf_tbl_sram_set + * + * @ref tf_tbl_sram_get + * + * @ref tf_tbl_sram_bulk_get + */ + +/** + * Initializes the Table module with the requested DBs. Must be + * invoked as the first thing before any of the access functions. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to Table configuration parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tbl_sram_bind(struct tf *tfp); + +/** + * Cleans up the private DBs and releases all the data. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tbl_sram_unbind(struct tf *tfp); + +/** + * Allocates the requested table type from the internal RM DB. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to Table allocation parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tbl_sram_alloc(struct tf *tfp, + struct tf_tbl_alloc_parms *parms); + +/** + * Free's the requested table type and returns it to the DB. If shadow + * DB is enabled its searched first and if found the element refcount + * is decremented. If refcount goes to 0 then its returned to the + * table type DB. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to Table free parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tbl_sram_free(struct tf *tfp, + struct tf_tbl_free_parms *parms); + + +/** + * Configures the requested element by sending a firmware request which + * then installs it into the device internal structures. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to Table set parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tbl_sram_set(struct tf *tfp, + struct tf_tbl_set_parms *parms); + +/** + * Retrieves the requested element by sending a firmware request to get + * the element. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to Table get parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tbl_sram_get(struct tf *tfp, + struct tf_tbl_get_parms *parms); + +/** + * Retrieves bulk block of elements by sending a firmware request to + * get the elements. + * + * [in] tfp + * Pointer to TF handle, used for HCAPI communication + * + * [in] parms + * Pointer to Table get bulk parameters + * + * Returns + * - (0) if successful. + * - (-EINVAL) on failure. + */ +int tf_tbl_sram_bulk_get(struct tf *tfp, + struct tf_tbl_get_bulk_parms *parms); + +#endif /* TF_TBL_SRAM_H */ diff --git a/drivers/net/bnxt/tf_core/tf_tcam.c b/drivers/net/bnxt/tf_core/tf_tcam.c index 45206c5992..806af3070a 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.c +++ b/drivers/net/bnxt/tf_core/tf_tcam.c @@ -43,7 +43,7 @@ tf_tcam_bind(struct tf *tfp, struct tf_shadow_tcam_free_db_parms fshadow; struct tf_shadow_tcam_cfg_parms shadow_cfg; struct tf_shadow_tcam_create_db_parms shadow_cdb; - uint16_t num_slices = 1; + uint16_t num_slices = parms->wc_num_slices; struct tf_session *tfs; struct tf_dev_info *dev; struct tcam_rm_db *tcam_db; @@ -61,7 +61,7 @@ tf_tcam_bind(struct tf *tfp, if (rc) return rc; - if (dev->ops->tf_dev_get_tcam_slice_info == NULL) { + if (dev->ops->tf_dev_set_tcam_slice_info == NULL) { rc = -EOPNOTSUPP; TFP_DRV_LOG(ERR, "Operation not supported, rc:%s\n", @@ -69,10 +69,8 @@ tf_tcam_bind(struct tf *tfp, return rc; } - rc = dev->ops->tf_dev_get_tcam_slice_info(tfp, - TF_TCAM_TBL_TYPE_WC_TCAM, - 0, - &num_slices); + rc = dev->ops->tf_dev_set_tcam_slice_info(tfp, + num_slices); if (rc) return rc; diff --git a/drivers/net/bnxt/tf_core/tf_tcam.h b/drivers/net/bnxt/tf_core/tf_tcam.h index bed17af6ae..b1e7a92b0b 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam.h +++ b/drivers/net/bnxt/tf_core/tf_tcam.h @@ -12,6 +12,9 @@ * The TCAM module provides processing of Internal TCAM types. */ +/* Number of slices per row for WC TCAM */ +extern uint16_t g_wc_num_slices_per_row; + /** * TCAM configuration parameters */ @@ -36,6 +39,10 @@ struct tf_tcam_cfg_parms { * Session resource allocations */ struct tf_session_resources *resources; + /** + * WC number of slices per row. + */ + enum tf_wc_num_slice wc_num_slices; }; /** diff --git a/drivers/net/bnxt/tf_core/tf_tcam_shared.c b/drivers/net/bnxt/tf_core/tf_tcam_shared.c index 83b6fbd5fb..c120c6f577 100644 --- a/drivers/net/bnxt/tf_core/tf_tcam_shared.c +++ b/drivers/net/bnxt/tf_core/tf_tcam_shared.c @@ -279,18 +279,6 @@ tf_tcam_shared_bind(struct tf *tfp, if (rc) return rc; - rc = tf_tcam_shared_get_slices(tfp, - dev, - &num_slices); - if (rc) - return rc; - - if (num_slices > 1) { - TFP_DRV_LOG(ERR, - "Only single slice supported\n"); - return -EOPNOTSUPP; - } - tf_tcam_shared_create_db(&tcam_shared_wc); @@ -330,6 +318,18 @@ tf_tcam_shared_bind(struct tf *tfp, tf_session_set_tcam_shared_db(tfp, (void *)tcam_shared_wc); } + + rc = tf_tcam_shared_get_slices(tfp, + dev, + &num_slices); + if (rc) + return rc; + + if (num_slices > 1) { + TFP_DRV_LOG(ERR, + "Only single slice supported\n"); + return -EOPNOTSUPP; + } } done: return rc; @@ -972,9 +972,9 @@ tf_tcam_shared_move_entry(struct tf *tfp, sparms.idx = dphy_idx; sparms.key = gparms.key; sparms.mask = gparms.mask; - sparms.key_size = gparms.key_size; + sparms.key_size = key_sz_bytes; sparms.result = gparms.result; - sparms.result_size = gparms.result_size; + sparms.result_size = remap_sz_bytes; rc = tf_msg_tcam_entry_set(tfp, dev, &sparms); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index d100399d0a..c1b9be0755 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -76,6 +76,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type) switch (tbl_type) { case TF_TBL_TYPE_FULL_ACT_RECORD: return "Full Action record"; + case TF_TBL_TYPE_COMPACT_ACT_RECORD: + return "Compact Action record"; case TF_TBL_TYPE_MCAST_GROUPS: return "Multicast Groups"; case TF_TBL_TYPE_ACT_ENCAP_8B: @@ -96,6 +98,14 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type) return "Stats 64B"; case TF_TBL_TYPE_ACT_MODIFY_IPV4: return "Modify IPv4"; + case TF_TBL_TYPE_ACT_MODIFY_8B: + return "Modify 8B"; + case TF_TBL_TYPE_ACT_MODIFY_16B: + return "Modify 16B"; + case TF_TBL_TYPE_ACT_MODIFY_32B: + return "Modify 32B"; + case TF_TBL_TYPE_ACT_MODIFY_64B: + return "Modify 64B"; case TF_TBL_TYPE_METER_PROF: return "Meter Profile"; case TF_TBL_TYPE_METER_INST: diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index dbf85e4eda..183bae66c5 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -384,6 +384,7 @@ ulp_ctx_shared_session_open(struct bnxt *bp, size_t copy_nbytes; uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; int32_t rc = 0; + uint8_t app_id; /* only perform this if shared session is enabled. */ if (!bnxt_ulp_cntxt_shared_session_enabled(bp->ulp_ctx)) @@ -422,6 +423,12 @@ ulp_ctx_shared_session_open(struct bnxt *bp, if (rc) return rc; + rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); @@ -445,6 +452,10 @@ ulp_ctx_shared_session_open(struct bnxt *bp, parms.shadow_copy = true; parms.bp = bp; + if (app_id == 0 || app_id == 3) + parms.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; + else + parms.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; /* * Open the session here, but the collect the resources during the @@ -516,6 +527,7 @@ ulp_ctx_session_open(struct bnxt *bp, struct tf_open_session_parms params; struct tf_session_resources *resources; uint32_t ulp_dev_id = BNXT_ULP_DEVICE_ID_LAST; + uint8_t app_id; memset(¶ms, 0, sizeof(params)); @@ -529,6 +541,12 @@ ulp_ctx_session_open(struct bnxt *bp, params.shadow_copy = true; + rc = bnxt_ulp_cntxt_app_id_get(bp->ulp_ctx, &app_id); + if (rc) { + BNXT_TF_DBG(ERR, "Unable to get the app id from ulp.\n"); + return -EINVAL; + } + rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &ulp_dev_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to get device id from ulp.\n"); @@ -556,6 +574,11 @@ ulp_ctx_session_open(struct bnxt *bp, return rc; params.bp = bp; + if (app_id == 0 || app_id == 3) + params.wc_num_slices = TF_WC_TCAM_2_SLICE_PER_ROW; + else + params.wc_num_slices = TF_WC_TCAM_1_SLICE_PER_ROW; + rc = tf_open_session(&bp->tfp, ¶ms); if (rc) { BNXT_TF_DBG(ERR, "Failed to open TF session - %s, rc = %d\n", From patchwork Mon Sep 20 07:42:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 99301 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2EF9BA0548; Mon, 20 Sep 2021 09:42:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E06C34111A; Mon, 20 Sep 2021 09:42:33 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.231]) by mails.dpdk.org (Postfix) with ESMTP id 9862D410F4 for ; Mon, 20 Sep 2021 09:42:28 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id EA17BE5; Mon, 20 Sep 2021 00:42:26 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com EA17BE5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1632123748; bh=jMxmaCd5oh1rC1v6jPwrRLVaUl+9r2KGyO3r+Bn121Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GWrpEALnZ3XiDSluDTOi/oX/rQ7F7RXO7I3Nzpyhni9nNh4PbDMp7F66xxXYx+gLC Y6HZsbw/pYD1ivLQx8S8cb20D+q0VqsbrXoFPCWshHgZ+9NLD0UCdrY1A/9S11jtMk /DMXU6ph+4Z2MfCUbTUE1aUOqOsd88gwryjR4fZw= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Mon, 20 Sep 2021 13:12:06 +0530 Message-Id: <20210920074214.23747-6-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> References: <20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com> <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> Subject: [dpdk-dev] [PATCH v4 05/13] net/bnxt: add flow template support for Thor X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Template adds non-VFR based support for testpmd with: matches to include - DMAC, SIP, DIP, Proto, Sport, Dport - SIP, DIP, Proto, Sport, Dport actions: - count, drop Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Mike Baucom Acked-by: Ajit Khaparde --- drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 6 + drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 36 +++--- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 12 ++ .../bnxt/tf_ulp/generic_templates/meson.build | 3 + .../ulp_template_db_thor_class.c | 1 - drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 120 +++++++++++++++++- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 26 +++- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c | 5 + drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 111 +++++++++++++++- drivers/net/bnxt/tf_ulp/ulp_matcher.c | 13 ++ drivers/net/bnxt/tf_ulp/ulp_port_db.c | 15 ++- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 9 +- drivers/net/bnxt/tf_ulp/ulp_tun.c | 20 +++ drivers/net/bnxt/tf_ulp/ulp_utils.c | 8 +- 16 files changed, 348 insertions(+), 41 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index f59da41e54..e0ebed3fed 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -13,6 +13,12 @@ #define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args) +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#define BNXT_TF_INF(fmt, args...) PMD_DRV_LOG(INFO, fmt, ## args) +#else +#define BNXT_TF_INF(fmt, args...) +#endif + #define BNXT_ULP_EM_FLOWS 8192 #define BNXT_ULP_1M_FLOWS 1000000 #define BNXT_EEM_RX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 183bae66c5..475c7a6cdf 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -698,6 +698,11 @@ ulp_eem_tbl_scope_init(struct bnxt *bp) rc); return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(DEBUG, "TableScope=0x%0x %d\n", + params.tbl_scope_id, + params.tbl_scope_id); +#endif rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to set table scope id\n"); @@ -825,6 +830,8 @@ ulp_ctx_init(struct bnxt *bp, goto error_deinit; } + /* TODO: For now we are overriding to APP:1 on this branch*/ + bp->app_id = 1; rc = bnxt_ulp_cntxt_app_id_set(bp->ulp_ctx, bp->app_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to set app_id for ULP init.\n"); @@ -838,11 +845,6 @@ ulp_ctx_init(struct bnxt *bp, goto error_deinit; } - if (devid == BNXT_ULP_DEVICE_ID_THOR) { - ulp_data->ulp_flags &= ~BNXT_ULP_VF_REP_ENABLED; - BNXT_TF_DBG(ERR, "Enabled non-VFR mode\n"); - } - /* * Shared session must be created before first regular session but after * the ulp_ctx is valid. @@ -902,7 +904,7 @@ ulp_dparms_init(struct bnxt *bp, struct bnxt_ulp_context *ulp_ctx) dparms->ext_flow_db_num_entries = bp->max_num_kflows * 1024; /* GFID = 2 * num_flows */ dparms->mark_db_gfid_entries = dparms->ext_flow_db_num_entries * 2; - BNXT_TF_DBG(DEBUG, "Set the number of flows = %"PRIu64"\n", + BNXT_TF_DBG(DEBUG, "Set the number of flows = %" PRIu64 "\n", dparms->ext_flow_db_num_entries); return 0; @@ -1393,17 +1395,13 @@ bnxt_ulp_port_init(struct bnxt *bp) uint32_t ulp_flags; int32_t rc = 0; + if (!bp || !BNXT_TRUFLOW_EN(bp)) + return rc; + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { BNXT_TF_DBG(ERR, "Skip ulp init for port: %d, not a TVF or PF\n", - bp->eth_dev->data->port_id); - return rc; - } - - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(DEBUG, - "Skip ulp init for port: %d, truflow is not enabled\n", - bp->eth_dev->data->port_id); + bp->eth_dev->data->port_id); return rc; } @@ -1524,6 +1522,9 @@ bnxt_ulp_port_deinit(struct bnxt *bp) struct rte_pci_device *pci_dev; struct rte_pci_addr *pci_addr; + if (!BNXT_TRUFLOW_EN(bp)) + return; + if (!BNXT_PF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { BNXT_TF_DBG(ERR, "Skip ULP deinit port:%d, not a TVF or PF\n", @@ -1531,13 +1532,6 @@ bnxt_ulp_port_deinit(struct bnxt *bp) return; } - if (!BNXT_TRUFLOW_EN(bp)) { - BNXT_TF_DBG(DEBUG, - "Skip ULP deinit for port:%d, truflow is not enabled\n", - bp->eth_dev->data->port_id); - return; - } - if (!bp->ulp_ctx) { BNXT_TF_DBG(DEBUG, "ulp ctx already de-allocated\n"); return; diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 19e9dba356..238b1d9657 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -13,6 +13,9 @@ #include "ulp_port_db.h" #include "ulp_ha_mgr.h" #include +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_template_debug_proto.h" +#endif static int32_t bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr, @@ -222,6 +225,15 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, else if (ret == BNXT_TF_RC_FID) goto return_fid; +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER + /* Dump the rte flow pattern */ + ulp_parser_hdr_info_dump(¶ms); + /* Dump the rte flow action */ + ulp_parser_act_info_dump(¶ms); +#endif +#endif + ret = ulp_matcher_pattern_match(¶ms, ¶ms.class_id); if (ret != BNXT_TF_RC_SUCCESS) goto free_fid; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build index b1e7b8cc32..4ace838a3c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/meson.build +++ b/drivers/net/bnxt/tf_ulp/generic_templates/meson.build @@ -2,7 +2,10 @@ # Copyright(c) 2018 Intel Corporation # Copyright(c) 2020 Broadcom +#Include the folder for headers includes += include_directories('.') + +#Add the source files sources += files( 'ulp_template_db_class.c', 'ulp_template_db_act.c', diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index 83f6152700..e342f340d9 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -6104,4 +6104,3 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { .ident_bit_pos = 29 } }; - diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 13f71ed83b..22c51976ac 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -35,7 +35,7 @@ ulp_fc_mgr_shadow_mem_alloc(struct hw_fc_mem_info *parms, int size) rte_mem_lock_page(parms->mem_va); parms->mem_pa = (void *)(uintptr_t)rte_mem_virt2phy(parms->mem_va); - if (parms->mem_pa == (void *)(uintptr_t)RTE_BAD_IOVA) { + if (parms->mem_pa == (void *)RTE_BAD_IOVA) { BNXT_TF_DBG(ERR, "Allocate failed mem_pa\n"); return -ENOMEM; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c index ab6013f0e3..016c86fb6e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c @@ -116,7 +116,7 @@ ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info) func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >> ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER); - /* The resource func is split into upper and lower */ + /* The reource func is split into upper and lower */ if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) return (func | res_info->resource_func_lower); return func; @@ -654,6 +654,9 @@ ulp_flow_db_fid_alloc(struct bnxt_ulp_context *ulp_ctxt, if (flow_type == BNXT_ULP_FDB_TYPE_REGULAR) ulp_flow_db_func_id_set(flow_db, *fid, func_id); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(ERR, "flow_id = %u:%u allocated\n", flow_type, *fid); +#endif /* return success */ return 0; } @@ -766,7 +769,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt, * flow_type [in] Specify it is regular or default flow * fid [in] The index to the flow entry * params [in/out] The contents to be copied into params. - * Only the critical_resource needs to be set by the caller. + * Onlythe critical_resource needs to be set by the caller. * * Returns 0 on success and negative on failure. */ @@ -937,6 +940,9 @@ ulp_flow_db_fid_free(struct bnxt_ulp_context *ulp_ctxt, ulp_clear_tun_inner_entry(tun_tbl, fid); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(ERR, "flow_id = %u:%u freed\n", flow_type, fid); +#endif /* all good, return success */ return 0; } @@ -1921,3 +1927,113 @@ void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res, if (res && (shared & BNXT_ULP_SHARED_SESSION_YES)) res->fdb_flags |= ULP_FDB_FLAG_SHARED_SESSION; } + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +/* + * Dump the entry details + * + * ulp_ctxt [in] Ptr to ulp_context + * + * returns none + */ +static void ulp_flow_db_res_dump(struct ulp_fdb_resource_info *r, + uint32_t *nxt_res) +{ + uint8_t res_func = ulp_flow_db_resource_func_get(r); + + BNXT_TF_DBG(DEBUG, "Resource func = %x, nxt_resource_idx = %x\n", + res_func, (ULP_FLOW_DB_RES_NXT_MASK & r->nxt_resource_idx)); + if (res_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE) + BNXT_TF_DBG(DEBUG, "EM Handle = 0x%016" PRIX64 "\n", + r->resource_em_handle); + else + BNXT_TF_DBG(DEBUG, "Handle = 0x%08x\n", r->resource_hndl); + + *nxt_res = 0; + ULP_FLOW_DB_RES_NXT_SET(*nxt_res, + r->nxt_resource_idx); +} + +/* + * Dump the flow entry details + * + * flow_db [in] Ptr to flow db + * fid [in] flow id + * + * returns none + */ +void +ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid) +{ + struct ulp_fdb_resource_info *r; + struct bnxt_ulp_flow_tbl *flow_tbl; + uint32_t nxt_res = 0; + uint32_t def_flag = 0, reg_flag = 0; + + flow_tbl = &flow_db->flow_tbl; + if (ulp_flow_db_active_flows_bit_is_set(flow_db, + BNXT_ULP_FDB_TYPE_REGULAR, fid)) + reg_flag = 1; + if (ulp_flow_db_active_flows_bit_is_set(flow_db, + BNXT_ULP_FDB_TYPE_DEFAULT, fid)) + def_flag = 1; + + if (reg_flag && def_flag) + BNXT_TF_DBG(DEBUG, "RID = %u\n", fid); + else if (reg_flag) + BNXT_TF_DBG(DEBUG, "Regular fid = %u and func id = %u\n", + fid, flow_db->func_id_tbl[fid]); + else if (def_flag) + BNXT_TF_DBG(DEBUG, "Default fid = %u\n", fid); + else + return; + /* iterate the resource */ + nxt_res = fid; + do { + r = &flow_tbl->flow_resources[nxt_res]; + ulp_flow_db_res_dump(r, &nxt_res); + } while (nxt_res); +} + +/* + * Dump the flow database entry details + * + * ulp_ctxt [in] Ptr to ulp_context + * flow_id [in] if zero then all fids are dumped. + * + * returns none + */ +int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt, + uint32_t flow_id) +{ + struct bnxt_ulp_flow_db *flow_db; + struct bnxt_ulp_flow_tbl *flow_tbl; + uint32_t fid; + + if (!ulp_ctxt || !ulp_ctxt->cfg_data) { + BNXT_TF_DBG(ERR, "Invalid Arguments\n"); + return -EINVAL; + } + flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt); + if (!flow_db) { + BNXT_TF_DBG(ERR, "Invalid Arguments\n"); + return -EINVAL; + } + + flow_tbl = &flow_db->flow_tbl; + if (flow_id) { + ulp_flow_db_debug_fid_dump(flow_db, flow_id); + return 0; + } + + BNXT_TF_DBG(DEBUG, "Dump flows = %u:%u\n", + flow_tbl->num_flows, + flow_tbl->num_resources); + BNXT_TF_DBG(DEBUG, "Head_index = %u, Tail_index = %u\n", + flow_tbl->head_index, flow_tbl->tail_index); + for (fid = 1; fid < flow_tbl->num_flows; fid++) + ulp_flow_db_debug_fid_dump(flow_db, fid); + BNXT_TF_DBG(DEBUG, "Done.\n"); + return 0; +} +#endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h index 67afca8872..0ddfa6f66d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h +++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h @@ -18,7 +18,7 @@ /* * Structure for the flow database resource information - * The below structure is based on the below partitions + * The below structure is based on the below paritions * nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0] * If resource_func is EM_TBL then use resource_em_handle. * Else the other part of the union is used and @@ -417,4 +417,28 @@ ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt); void ulp_flow_db_shared_session_set(struct ulp_flow_db_res_params *res, enum bnxt_ulp_shared_session shared); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +/* + * Dump the flow entry details + * + * flow_db [in] Ptr to flow db + * fid [in] flow id + * + * returns none + */ +void +ulp_flow_db_debug_fid_dump(struct bnxt_ulp_flow_db *flow_db, uint32_t fid); + +/* + * Dump the flow database entry details + * + * ulp_ctxt [in] Ptr to ulp_context + * flow_id [in] if zero then all fids are dumped. + * + * returns none + */ +int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt, + uint32_t flow_id); +#endif + #endif /* _ULP_FLOW_DB_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c index 3c1af0b007..c6b2b1675d 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c @@ -10,6 +10,11 @@ #include "ulp_mapper.h" #include "ulp_flow_db.h" +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_template_debug_proto.h" +#include "ulp_tf_debug.h" +#endif + /* Retrieve the generic table initialization parameters for the tbl_idx */ static struct bnxt_ulp_generic_tbl_params* ulp_mapper_gen_tbl_params_get(uint32_t tbl_idx) diff --git a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c index 5f5b5d639e..bc5627ec5b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_ha_mgr.c @@ -185,7 +185,7 @@ ulp_ha_mgr_timer_cb(void *arg __rte_unused) rc = ulp_ha_mgr_state_get(ulp_ctx, &curr_state); if (rc) { /* - * This shouldn't happen, if it does, reset the timer + * This shouldn't happen, if it does, resetart the timer * and try again next time. */ BNXT_TF_DBG(ERR, "Failed(%d) to get state.\n", diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index f3a60cc880..7fc3767b33 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -22,6 +22,11 @@ #include "ulp_ha_mgr.h" #include "bnxt_tf_pmd_shim.h" +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_template_debug_proto.h" +#include "ulp_tf_debug.h" +#endif + static uint8_t mapper_fld_zeros[16] = { 0 }; static uint8_t mapper_fld_ones[16] = { @@ -156,6 +161,13 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, tf_free_identifier(tfp, &fparms); return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + BNXT_TF_DBG(DEBUG, "Allocated Glb Res Ident [%s][%d][%d] = 0x%04x\n", + tf_dir_2_str(iparms.dir), + glb_res->glb_regfile_index, iparms.ident_type, iparms.id); +#endif +#endif return rc; } @@ -216,6 +228,13 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, tf_free_tbl_entry(tfp, &free_parms); return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + BNXT_TF_DBG(DEBUG, "Allocated Glb Res Index [%s][%d][%d] = 0x%04x\n", + tf_dir_2_str(aparms.dir), + glb_res->glb_regfile_index, aparms.type, aparms.idx); +#endif +#endif return rc; } @@ -784,6 +803,9 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, tf_ident_2_str(iparms.ident_type)); return rc; } + BNXT_TF_INF("Alloc ident %s:%s.success.\n", + tf_dir_2_str(iparms.dir), + tf_ident_2_str(iparms.ident_type)); id = (uint64_t)tfp_cpu_to_be_64(iparms.id); if (ulp_regfile_write(parms->regfile, idx, id)) { @@ -813,6 +835,11 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, } else { *val = iparms.id; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_ident_field_dump("Ident", ident, tbl, iparms.id); +#endif +#endif return 0; error: @@ -877,6 +904,10 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, sparms.search_id); return rc; } + BNXT_TF_INF("Search ident %s:%s:%x.success.\n", + tf_dir_2_str(sparms.dir), + tf_tbl_type_2_str(sparms.ident_type), + sparms.search_id); /* Write it to the regfile */ id = (uint64_t)tfp_cpu_to_be_64(sparms.search_id); @@ -904,6 +935,11 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, goto error; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_ident_field_dump("Ident", ident, tbl, sparms.search_id); +#endif +#endif return 0; error: @@ -996,7 +1032,7 @@ ulp_mapper_field_src_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; } idx = tfp_be_to_cpu_16(idx); - if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint64_t)) { + if (idx >= BNXT_ULP_CF_IDX_LAST || bytelen > sizeof(uint32_t)) { BNXT_TF_DBG(ERR, "comp field [%d] read oob %d\n", idx, bytelen); return -EINVAL; @@ -1448,7 +1484,16 @@ ulp_mapper_field_opc_process(struct bnxt_ulp_mapper_parms *parms, break; } - return rc; + if (!rc) { +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + if (fld->field_src1 != BNXT_ULP_FIELD_SRC_ZERO) + ulp_mapper_field_dump(name, fld, blob, write_idx, val, + val_len); +#endif +#endif + return rc; + } error: BNXT_TF_DBG(ERR, "Error in %s:%s process %u:%u\n", name, fld->description, (val) ? write_idx : 0, val_len); @@ -1500,8 +1545,15 @@ ulp_mapper_tbl_result_build(struct bnxt_ulp_mapper_parms *parms, } /* if encap bit swap is enabled perform the bit swap */ - if (parms->device_params->encap_byte_swap && encap_flds) + if (parms->device_params->encap_byte_swap && encap_flds) { ulp_blob_perform_encap_swap(data); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + BNXT_TF_DBG(INFO, "Dump after encap swap\n"); + ulp_mapper_blob_dump(data); +#endif +#endif + } return rc; } @@ -1725,6 +1777,9 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, tf_dir_2_str(sparms.dir), sparms.idx); return -EIO; } + BNXT_TF_INF("tcam[%s][%s][%x] write success.\n", + tf_tcam_tbl_2_str(sparms.tcam_tbl_type), + tf_dir_2_str(sparms.dir), sparms.idx); /* Mark action */ rc = ulp_mapper_mark_act_ptr_process(parms, tbl); @@ -1733,6 +1788,11 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_tcam_entry_dump("TCAM", idx, tbl, key, mask, data); +#endif +#endif return rc; } @@ -1838,6 +1898,12 @@ static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob) { ulp_blob_perform_64B_word_swap(blob); ulp_blob_perform_64B_byte_swap(blob); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + BNXT_TF_DBG(INFO, "Dump after wc tcam post process\n"); + ulp_mapper_blob_dump(blob); +#endif +#endif } static int32_t @@ -2134,6 +2200,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "Failed to build the result blob\n"); return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_result_dump("EM Result", tbl, &data); +#endif +#endif if (dparms->dynamic_pad_en) { uint32_t abits = dparms->em_blk_align_bits; @@ -2148,6 +2219,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, ulp_blob_pad_align(&data, abits); ulp_blob_perform_byte_reverse(&data, ULP_BITS_2_BYTE(abits)); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_result_dump("EM Merged Result", tbl, &data); +#endif +#endif } /* do the transpose for the internal EM keys */ @@ -2160,6 +2236,11 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, } tmplen = ulp_blob_data_len_get(&key); ulp_blob_perform_byte_reverse(&key, ULP_BITS_2_BYTE(tmplen)); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_result_dump("EM Key Transpose", tbl, &key); +#endif +#endif } rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, @@ -2190,6 +2271,12 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_em_dump("EM", &key, &data, &iparms); + /* tf_dump_tables(tfp, iparms.tbl_scope_id); */ +#endif +#endif /* Mark action process */ if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT && tbl->resource_type == TF_MEM_EXTERNAL) @@ -2479,6 +2566,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, sparms.idx, rc); goto error; } + BNXT_TF_INF("Index table[%s][%s][%x] write successful.\n", + tf_tbl_type_2_str(sparms.type), + tf_dir_2_str(sparms.dir), sparms.idx); /* Calculate action record size */ if (tbl->resource_type == TF_TBL_TYPE_EXT) { @@ -2635,6 +2725,10 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, iftbl_params.idx, rc); return rc; } + BNXT_TF_INF("Set table[%s][%s][%x] success.\n", + tf_if_tbl_2_str(iftbl_params.type), + tf_dir_2_str(iftbl_params.dir), + iftbl_params.idx); /* * TBD: Need to look at the need to store idx in flow db for restore @@ -2697,6 +2791,12 @@ ulp_mapper_gen_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* The_key is a byte array convert it to a search index */ cache_key = ulp_blob_data_get(&key, &tmplen); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + BNXT_TF_DBG(DEBUG, "The gen_tbl[%u] key\n", tbl_idx); + ulp_mapper_blob_dump(&key); +#endif +#endif /* get the generic table */ gen_tbl_list = &parms->mapper_data->gen_tbl_list[tbl_idx]; @@ -3495,6 +3595,11 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid) for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) { tbl = &tbls[tbl_idx]; cond_goto = tbl->execute_info.cond_true_goto; +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_MAPPER + ulp_mapper_table_dump(tbl, tbl_idx); +#endif +#endif /* Process the conditional func code opcodes */ if (ulp_mapper_func_info_process(parms, tbl)) { BNXT_TF_DBG(ERR, "Failed to process cond update\n"); diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c index 67fa61fc7c..e06d8f6287 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c @@ -6,6 +6,10 @@ #include "ulp_matcher.h" #include "ulp_utils.h" +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_template_debug_proto.h" +#endif + /* Utility function to calculate the class matcher hash */ static uint32_t ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig) @@ -95,6 +99,11 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params, error: BNXT_TF_DBG(DEBUG, "Did not find any matching template\n"); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(DEBUG, "class_hid:0x%x, Hdr:%" PRIX64 " Fld:%" PRIX64 "\n", + class_hid, params->hdr_bitmap.bits, + params->fld_bitmap.bits); +#endif *class_id = 0; return BNXT_TF_RC_ERROR; } @@ -142,6 +151,10 @@ ulp_matcher_action_match(struct ulp_rte_parser_params *params, error: BNXT_TF_DBG(DEBUG, "Did not find any matching action template\n"); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(DEBUG, "act_hid:0x%x, Hdr:%" PRIX64 "\n", + act_hid, params->act_bitmap.bits); +#endif *act_id = 0; return BNXT_TF_RC_ERROR; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 4045473097..7d9865b3e3 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -7,9 +7,13 @@ #include "bnxt.h" #include "bnxt_vnic.h" #include "bnxt_tf_common.h" +#include "bnxt_tf_pmd_shim.h" #include "ulp_port_db.h" #include "tfp.h" -#include "bnxt_tf_pmd_shim.h" + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_tf_debug.h" +#endif static uint32_t ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db) @@ -151,12 +155,12 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt, intf->type = bnxt_pmd_get_interface_type(port_id); intf->drv_func_id = bnxt_pmd_get_fw_func_id(port_id, - BNXT_ULP_INTF_TYPE_INVALID); + BNXT_ULP_INTF_TYPE_INVALID); func = &port_db->ulp_func_id_tbl[intf->drv_func_id]; if (!func->func_valid) { func->func_svif = bnxt_pmd_get_svif(port_id, true, - BNXT_ULP_INTF_TYPE_INVALID); + BNXT_ULP_INTF_TYPE_INVALID); func->func_spif = bnxt_pmd_get_phy_port_id(port_id); func->func_parif = bnxt_pmd_get_parif(port_id, BNXT_ULP_INTF_TYPE_INVALID); @@ -202,6 +206,11 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt, port_data->port_vport = bnxt_pmd_get_vport(port_id); port_data->port_valid = true; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PORT + ulp_port_db_dump(port_db, intf, port_id); +#endif +#endif return 0; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 5fd52b8f36..79b9957781 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -8,6 +8,7 @@ #include "ulp_template_struct.h" #include "bnxt_ulp.h" #include "bnxt_tf_common.h" +#include "bnxt_tf_pmd_shim.h" #include "ulp_rte_parser.h" #include "ulp_matcher.h" #include "ulp_utils.h" @@ -855,7 +856,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, BNXT_ULP_HDR_BIT_II_VLAN); inner_flag = 1; } else { - BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found without eth\n"); + BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n"); return BNXT_TF_RC_ERROR; } /* Update the field protocol hdr bitmap */ @@ -1135,8 +1136,8 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, ulp_rte_prsr_fld_mask(params, &idx, size, &ver_spec, &ver_mask, ULP_PRSR_ACT_DEFAULT); /* - * The TC and flow label field are ignored since OVS is setting - * it for match and it is not supported. + * The TC and flow label field are ignored since OVS is + * setting it for match and it is not supported. * This is a work around and * shall be addressed in the future. */ @@ -2138,7 +2139,7 @@ ulp_rte_vf_act_handler(const struct rte_flow_action *action_item, return BNXT_TF_RC_PARSE_ERR; } - bp = bnxt_get_bp(params->port_id); + bp = bnxt_pmd_get_bp(params->port_id); if (bp == NULL) { BNXT_TF_DBG(ERR, "Invalid bp\n"); return BNXT_TF_RC_ERROR; diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c index cb8530d791..a1dd5b902c 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_tun.c +++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c @@ -3,6 +3,8 @@ * All rights reserved. */ +#include + #include #include "ulp_tun.h" @@ -29,6 +31,15 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params, ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER + /* Dump the rte flow pattern */ + ulp_parser_hdr_info_dump(params); + /* Dump the rte flow action */ + ulp_parser_act_info_dump(params); +#endif +#endif + ret = ulp_matcher_pattern_match(params, ¶ms->class_id); if (ret != BNXT_TF_RC_SUCCESS) goto err; @@ -146,6 +157,15 @@ ulp_post_process_cache_inner_tun_flow(struct ulp_rte_parser_params *params, struct ulp_per_port_flow_info *flow_info; int ret; +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER + /* Dump the rte flow pattern */ + ulp_parser_hdr_info_dump(params); + /* Dump the rte flow action */ + ulp_parser_act_info_dump(params); +#endif +#endif + ret = ulp_matcher_pattern_match(params, ¶ms->class_id); if (ret != BNXT_TF_RC_SUCCESS) return BNXT_TF_RC_ERROR; diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index bafb539c8d..1649e157f2 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -62,7 +62,7 @@ ulp_regfile_read(struct ulp_regfile *regfile, * data [in] The value is written into this variable. It is going to be in the * same byte order as it was written. * - * size [in] The size in bytes of the value being written into this + * size [in] The size in bytes of the value beingritten into this * variable. * * returns 0 on success @@ -295,7 +295,7 @@ ulp_blob_push(struct ulp_blob *blob, datalen, data); if (!rc) { - BNXT_TF_DBG(ERR, "Failed to write blob\n"); + BNXT_TF_DBG(ERR, "Failed ro write blob\n"); return 0; } blob->write_idx += datalen; @@ -355,7 +355,7 @@ ulp_blob_insert(struct ulp_blob *blob, uint32_t offset, datalen, data); if (!rc) { - BNXT_TF_DBG(ERR, "Failed to write blob\n"); + BNXT_TF_DBG(ERR, "Failed ro write blob\n"); return 0; } /* copy the previously stored data */ @@ -409,7 +409,7 @@ ulp_blob_push_64(struct ulp_blob *blob, * * data [in] 32-bit value to be added to the blob. * - * datalen [in] The number of bits to be added to the blob. + * datalen [in] The number of bits to be added ot the blob. * * The offset of the data is updated after each push of data. * NULL returned on error, pointer pushed value otherwise. From patchwork Mon Sep 20 07:42:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Venkat Duvvuru X-Patchwork-Id: 99307 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 95620A0548; Mon, 20 Sep 2021 09:55:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 13DA040DF7; Mon, 20 Sep 2021 09:55:05 +0200 (CEST) Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) by mails.dpdk.org (Postfix) with ESMTP id 4F42F41100 for ; Mon, 20 Sep 2021 09:42:32 +0200 (CEST) Received: from S60.dhcp.broadcom.net (unknown [10.123.66.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id 088AFEA; Mon, 20 Sep 2021 00:42:28 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 088AFEA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1632123751; bh=mNyRZiIoB7Q6s9oNaJ12u9qzZ5+ea6poWcUjlJnyF3Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KYY/Auy4VrJOlIkj2PT87TxLY3ejUu4UNmYeEL73yah7+LfCFkYLQZzfwGnXX6F2/ UbBKehtc1Zv8NjRXQPF3q2LXRiV57XQ0tG2u9VX7RZ2Bl1rryChDWlSgFtaQmfsvOX tTMZbhyvtV8JZw/ny63+6ZEPuHPWhep0InxCnicI= From: Venkat Duvvuru To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru Date: Mon, 20 Sep 2021 13:12:07 +0530 Message-Id: <20210920074214.23747-7-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> References: <20210908050643.9989-1-venkatkumar.duvvuru@broadcom.com> <20210920074214.23747-1-venkatkumar.duvvuru@broadcom.com> X-Mailman-Approved-At: Mon, 20 Sep 2021 09:55:03 +0200 Subject: [dpdk-dev] [PATCH v4 06/13] net/bnxt: add support for tunnel offload API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Add support for tunnel offload APIs. Specifically the following are supported. tunnel_decap_set, tunnel_match, tunnel_action_decap_release, tunnel_item_release. This provides support for VXLAN decap action where two flows can indicate tunnel offload rule. The first flow indicates the tunnel properties and second flow indicates the inner packet structure. The templates are updated to support this feature. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Shahaji Bhosle Acked-by: Ajit Khaparde --- drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 4 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 12 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 20 +- drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 212 +- .../generic_templates/ulp_template_db_act.c | 2 +- .../generic_templates/ulp_template_db_class.c | 8541 +++++++++++----- .../generic_templates/ulp_template_db_enum.h | 210 +- .../generic_templates/ulp_template_db_field.h | 654 +- .../generic_templates/ulp_template_db_tbl.c | 645 +- .../ulp_template_db_thor_class.c | 110 +- .../ulp_template_db_wh_plus_act.c | 2 +- .../ulp_template_db_wh_plus_class.c | 8577 +++++++++++------ drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 46 +- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 8 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 562 +- drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 44 +- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 52 +- drivers/net/bnxt/tf_ulp/ulp_mapper.h | 6 +- drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 31 + drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 134 +- drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 10 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 10 +- drivers/net/bnxt/tf_ulp/ulp_tun.c | 541 +- drivers/net/bnxt/tf_ulp/ulp_tun.h | 89 +- 24 files changed, 13810 insertions(+), 6712 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index e0ebed3fed..6c4bcd2d90 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -37,9 +37,7 @@ enum bnxt_tf_rc { BNXT_TF_RC_PARSE_ERR = -2, BNXT_TF_RC_ERROR = -1, - BNXT_TF_RC_SUCCESS = 0, - BNXT_TF_RC_NORMAL = 1, - BNXT_TF_RC_FID = 2, + BNXT_TF_RC_SUCCESS = 0 }; /* eth IPv4 Type */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 475c7a6cdf..dfafd9ff5b 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -860,8 +860,6 @@ ulp_ctx_init(struct bnxt *bp, if (rc) goto error_deinit; - ulp_tun_tbl_init(ulp_data->tun_tbl); - bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp); return rc; @@ -2064,3 +2062,13 @@ bnxt_ulp_cntxt_entry_release(void) { rte_spinlock_unlock(&bnxt_ulp_ctxt_lock); } + +/* Function to get the app tunnel details from the ulp context. */ +struct bnxt_flow_app_tun_ent * +bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp) +{ + if (!ulp || !ulp->cfg_data) + return NULL; + + return ulp->cfg_data->app_tun; +} diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index 082ca501b6..006df9cbc5 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -47,6 +47,18 @@ enum bnxt_ulp_flow_mem_type { BNXT_ULP_FLOW_MEM_TYPE_LAST = 3 }; +enum bnxt_rte_flow_item_type { + BNXT_RTE_FLOW_ITEM_TYPE_END = (uint32_t)INT_MIN, + BNXT_RTE_FLOW_ITEM_TYPE_VXLAN_DECAP, + BNXT_RTE_FLOW_ITEM_TYPE_LAST +}; + +enum bnxt_rte_flow_action_type { + BNXT_RTE_FLOW_ACTION_TYPE_END = (uint32_t)INT_MIN, + BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP, + BNXT_RTE_FLOW_ACTION_TYPE_LAST +}; + struct bnxt_ulp_df_rule_info { uint32_t def_port_flow_id; uint8_t valid; @@ -79,6 +91,7 @@ struct bnxt_ulp_data { bool accum_stats; uint8_t app_id; uint8_t num_shared_clients; + struct bnxt_flow_app_tun_ent app_tun[BNXT_ULP_MAX_TUN_CACHE_ENTRIES]; }; struct bnxt_ulp_context { @@ -258,9 +271,6 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context *ulp_ctx); void bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context *ulp_ctx); -int32_t -ulp_post_process_tun_flow(struct ulp_rte_parser_params *params); - struct bnxt_ulp_glb_resource_info * bnxt_ulp_app_glb_resource_info_list_get(uint32_t *num_entries); @@ -301,4 +311,8 @@ bnxt_ulp_cntxt_entry_release(void); uint8_t bnxt_ulp_cntxt_num_shared_clients_get(struct bnxt_ulp_context *ulp_ctx); + +struct bnxt_flow_app_tun_ent * +bnxt_ulp_cntxt_ptr2_app_tun_list_get(struct bnxt_ulp_context *ulp); + #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 238b1d9657..3daf5942e8 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -12,6 +12,7 @@ #include "ulp_fc_mgr.h" #include "ulp_port_db.h" #include "ulp_ha_mgr.h" +#include "ulp_tun.h" #include #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG #include "ulp_template_debug_proto.h" @@ -101,12 +102,13 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms, mapper_cparms->act_prop = ¶ms->act_prop; mapper_cparms->flow_id = params->fid; mapper_cparms->parent_flow = params->parent_flow; - mapper_cparms->parent_fid = params->parent_fid; + mapper_cparms->child_flow = params->child_flow; mapper_cparms->fld_bitmap = ¶ms->fld_bitmap; mapper_cparms->flow_pattern_id = params->flow_pattern_id; mapper_cparms->act_pattern_id = params->act_pattern_id; mapper_cparms->app_id = params->app_id; mapper_cparms->port_id = params->port_id; + mapper_cparms->tun_idx = params->tun_idx; /* update the signature fields into the computed field list */ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_HDR_SIG_ID, @@ -218,12 +220,14 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, params.func_id = func_id; params.priority = attr->priority; params.port_id = dev->data->port_id; + /* Perform the rte flow post process */ - ret = bnxt_ulp_rte_parser_post_process(¶ms); + bnxt_ulp_rte_parser_post_process(¶ms); + + /* do the tunnel offload process if any */ + ret = ulp_tunnel_offload_process(¶ms); if (ret == BNXT_TF_RC_ERROR) goto free_fid; - else if (ret == BNXT_TF_RC_FID) - goto return_fid; #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG #ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_PARSER @@ -249,7 +253,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, if (ret) goto free_fid; -return_fid: bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx); flow_id = (struct rte_flow *)((uintptr_t)fid); @@ -314,11 +317,12 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev, goto parse_error; /* Perform the rte flow post process */ - ret = bnxt_ulp_rte_parser_post_process(¶ms); + bnxt_ulp_rte_parser_post_process(¶ms); + + /* do the tunnel offload process if any */ + ret = ulp_tunnel_offload_process(¶ms); if (ret == BNXT_TF_RC_ERROR) goto parse_error; - else if (ret == BNXT_TF_RC_FID) - return 0; ret = ulp_matcher_pattern_match(¶ms, &class_id); @@ -475,11 +479,201 @@ bnxt_ulp_flow_query(struct rte_eth_dev *eth_dev, return rc; } +/* Tunnel offload Apis */ +#define BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS 1 + +static int +bnxt_ulp_tunnel_decap_set(struct rte_eth_dev *eth_dev, + struct rte_flow_tunnel *tunnel, + struct rte_flow_action **pmd_actions, + uint32_t *num_of_actions, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + int32_t rc = 0; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + + if (tunnel == NULL) { + BNXT_TF_DBG(ERR, "No tunnel specified\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "no tunnel specified"); + return -EINVAL; + } + + if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) { + BNXT_TF_DBG(ERR, "Tunnel type unsupported\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel type unsupported"); + return -EINVAL; + } + + rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel decap set failed"); + return -EINVAL; + } + + rc = ulp_app_tun_entry_set_decap_action(tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel decap set failed"); + return -EINVAL; + } + + *pmd_actions = &tun_entry->action; + *num_of_actions = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS; + return 0; +} + +static int +bnxt_ulp_tunnel_match(struct rte_eth_dev *eth_dev, + struct rte_flow_tunnel *tunnel, + struct rte_flow_item **pmd_items, + uint32_t *num_of_items, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + int32_t rc = 0; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + + if (tunnel == NULL) { + BNXT_TF_DBG(ERR, "No tunnel specified\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "no tunnel specified"); + return -EINVAL; + } + + if (tunnel->type != RTE_FLOW_ITEM_TYPE_VXLAN) { + BNXT_TF_DBG(ERR, "Tunnel type unsupported\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "tunnel type unsupported"); + return -EINVAL; + } + + rc = ulp_app_tun_search_entry(ulp_ctx, tunnel, &tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel match set failed"); + return -EINVAL; + } + + rc = ulp_app_tun_entry_set_decap_item(tun_entry); + if (rc < 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "tunnel match set failed"); + return -EINVAL; + } + + *pmd_items = &tun_entry->item; + *num_of_items = BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS; + return 0; +} + +static int +bnxt_ulp_tunnel_decap_release(struct rte_eth_dev *eth_dev, + struct rte_flow_action *pmd_actions, + uint32_t num_actions, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + const struct rte_flow_action *action_item = pmd_actions; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + if (num_actions != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) { + BNXT_TF_DBG(ERR, "num actions is invalid\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "num actions is invalid"); + return -EINVAL; + } + while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) { + if (action_item->type == (typeof(tun_entry->action.type)) + BNXT_RTE_FLOW_ACTION_TYPE_VXLAN_DECAP) { + tun_entry = ulp_app_tun_match_entry(ulp_ctx, + action_item->conf); + ulp_app_tun_entry_delete(tun_entry); + } + action_item++; + } + return 0; +} + +static int +bnxt_ulp_tunnel_item_release(struct rte_eth_dev *eth_dev, + struct rte_flow_item *pmd_items, + uint32_t num_items, + struct rte_flow_error *error) +{ + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_app_tun_ent *tun_entry; + + ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev); + if (ulp_ctx == NULL) { + BNXT_TF_DBG(ERR, "ULP context is not initialized\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "ULP context uninitialized"); + return -EINVAL; + } + if (num_items != BNXT_ULP_TUNNEL_OFFLOAD_NUM_ITEMS) { + BNXT_TF_DBG(ERR, "num items is invalid\n"); + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, NULL, + "num items is invalid"); + return -EINVAL; + } + + tun_entry = ulp_app_tun_match_entry(ulp_ctx, pmd_items->spec); + ulp_app_tun_entry_delete(tun_entry); + return 0; +} + const struct rte_flow_ops bnxt_ulp_rte_flow_ops = { .validate = bnxt_ulp_flow_validate, .create = bnxt_ulp_flow_create, .destroy = bnxt_ulp_flow_destroy, .flush = bnxt_ulp_flow_flush, .query = bnxt_ulp_flow_query, - .isolate = NULL + .isolate = NULL, + /* Tunnel offload callbacks */ + .tunnel_decap_set = bnxt_ulp_tunnel_decap_set, + .tunnel_match = bnxt_ulp_tunnel_match, + .tunnel_action_decap_release = bnxt_ulp_tunnel_decap_release, + .tunnel_item_release = bnxt_ulp_tunnel_item_release, + .get_restore_info = NULL }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c index e18f314856..0da6070d7d 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Mon May 17 15:30:41 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c index 9c419f6a15..f74687acfa 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -360,348 +360,510 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { [BNXT_ULP_CLASS_HID_15db] = 342, [BNXT_ULP_CLASS_HID_1151] = 343, [BNXT_ULP_CLASS_HID_315d] = 344, - [BNXT_ULP_CLASS_HID_34c6] = 345, - [BNXT_ULP_CLASS_HID_0c22] = 346, - [BNXT_ULP_CLASS_HID_1cbe] = 347, - [BNXT_ULP_CLASS_HID_179a] = 348, - [BNXT_ULP_CLASS_HID_59be] = 349, - [BNXT_ULP_CLASS_HID_515a] = 350, - [BNXT_ULP_CLASS_HID_1c72] = 351, - [BNXT_ULP_CLASS_HID_171e] = 352, - [BNXT_ULP_CLASS_HID_19c8] = 353, - [BNXT_ULP_CLASS_HID_112c] = 354, - [BNXT_ULP_CLASS_HID_4d68] = 355, - [BNXT_ULP_CLASS_HID_444c] = 356, - [BNXT_ULP_CLASS_HID_0e8c] = 357, - [BNXT_ULP_CLASS_HID_09e0] = 358, - [BNXT_ULP_CLASS_HID_1af0] = 359, - [BNXT_ULP_CLASS_HID_15d4] = 360, - [BNXT_ULP_CLASS_HID_1dd0] = 361, - [BNXT_ULP_CLASS_HID_14f4] = 362, - [BNXT_ULP_CLASS_HID_70b0] = 363, - [BNXT_ULP_CLASS_HID_4854] = 364, - [BNXT_ULP_CLASS_HID_3dd4] = 365, - [BNXT_ULP_CLASS_HID_34f8] = 366, - [BNXT_ULP_CLASS_HID_09e8] = 367, - [BNXT_ULP_CLASS_HID_008c] = 368, - [BNXT_ULP_CLASS_HID_34e6] = 369, - [BNXT_ULP_CLASS_HID_0c02] = 370, - [BNXT_ULP_CLASS_HID_1c9e] = 371, - [BNXT_ULP_CLASS_HID_17ba] = 372, - [BNXT_ULP_CLASS_HID_429e] = 373, - [BNXT_ULP_CLASS_HID_5dba] = 374, - [BNXT_ULP_CLASS_HID_2a16] = 375, - [BNXT_ULP_CLASS_HID_2532] = 376, - [BNXT_ULP_CLASS_HID_2da2] = 377, - [BNXT_ULP_CLASS_HID_24fe] = 378, - [BNXT_ULP_CLASS_HID_355a] = 379, - [BNXT_ULP_CLASS_HID_0c76] = 380, - [BNXT_ULP_CLASS_HID_13e6] = 381, - [BNXT_ULP_CLASS_HID_7276] = 382, - [BNXT_ULP_CLASS_HID_42d2] = 383, - [BNXT_ULP_CLASS_HID_5dee] = 384, - [BNXT_ULP_CLASS_HID_59de] = 385, - [BNXT_ULP_CLASS_HID_513a] = 386, - [BNXT_ULP_CLASS_HID_1c12] = 387, - [BNXT_ULP_CLASS_HID_177e] = 388, - [BNXT_ULP_CLASS_HID_0e92] = 389, - [BNXT_ULP_CLASS_HID_09fe] = 390, - [BNXT_ULP_CLASS_HID_5c1a] = 391, - [BNXT_ULP_CLASS_HID_5746] = 392, - [BNXT_ULP_CLASS_HID_79da] = 393, - [BNXT_ULP_CLASS_HID_7106] = 394, - [BNXT_ULP_CLASS_HID_3c1e] = 395, - [BNXT_ULP_CLASS_HID_377a] = 396, - [BNXT_ULP_CLASS_HID_2e9e] = 397, - [BNXT_ULP_CLASS_HID_29fa] = 398, - [BNXT_ULP_CLASS_HID_14d2] = 399, - [BNXT_ULP_CLASS_HID_7742] = 400, - [BNXT_ULP_CLASS_HID_3706] = 401, - [BNXT_ULP_CLASS_HID_0fe2] = 402, - [BNXT_ULP_CLASS_HID_1f7e] = 403, - [BNXT_ULP_CLASS_HID_145a] = 404, - [BNXT_ULP_CLASS_HID_417e] = 405, - [BNXT_ULP_CLASS_HID_5e5a] = 406, - [BNXT_ULP_CLASS_HID_29f6] = 407, - [BNXT_ULP_CLASS_HID_26d2] = 408, - [BNXT_ULP_CLASS_HID_2e42] = 409, - [BNXT_ULP_CLASS_HID_271e] = 410, - [BNXT_ULP_CLASS_HID_36ba] = 411, - [BNXT_ULP_CLASS_HID_0f96] = 412, - [BNXT_ULP_CLASS_HID_1006] = 413, - [BNXT_ULP_CLASS_HID_7196] = 414, - [BNXT_ULP_CLASS_HID_4132] = 415, - [BNXT_ULP_CLASS_HID_5e0e] = 416, - [BNXT_ULP_CLASS_HID_59fe] = 417, - [BNXT_ULP_CLASS_HID_511a] = 418, - [BNXT_ULP_CLASS_HID_1c32] = 419, - [BNXT_ULP_CLASS_HID_175e] = 420, - [BNXT_ULP_CLASS_HID_0eb2] = 421, - [BNXT_ULP_CLASS_HID_09de] = 422, - [BNXT_ULP_CLASS_HID_5c3a] = 423, - [BNXT_ULP_CLASS_HID_5766] = 424, - [BNXT_ULP_CLASS_HID_79fa] = 425, - [BNXT_ULP_CLASS_HID_7126] = 426, - [BNXT_ULP_CLASS_HID_3c3e] = 427, - [BNXT_ULP_CLASS_HID_375a] = 428, - [BNXT_ULP_CLASS_HID_2ebe] = 429, - [BNXT_ULP_CLASS_HID_29da] = 430, - [BNXT_ULP_CLASS_HID_14f2] = 431, - [BNXT_ULP_CLASS_HID_7762] = 432, - [BNXT_ULP_CLASS_HID_19e8] = 433, - [BNXT_ULP_CLASS_HID_110c] = 434, - [BNXT_ULP_CLASS_HID_4d48] = 435, - [BNXT_ULP_CLASS_HID_446c] = 436, - [BNXT_ULP_CLASS_HID_0eac] = 437, - [BNXT_ULP_CLASS_HID_09c0] = 438, - [BNXT_ULP_CLASS_HID_1ad0] = 439, - [BNXT_ULP_CLASS_HID_15f4] = 440, - [BNXT_ULP_CLASS_HID_39ec] = 441, - [BNXT_ULP_CLASS_HID_3100] = 442, - [BNXT_ULP_CLASS_HID_0210] = 443, - [BNXT_ULP_CLASS_HID_1d34] = 444, - [BNXT_ULP_CLASS_HID_2ea0] = 445, - [BNXT_ULP_CLASS_HID_29c4] = 446, - [BNXT_ULP_CLASS_HID_3ad4] = 447, - [BNXT_ULP_CLASS_HID_35e8] = 448, - [BNXT_ULP_CLASS_HID_5d80] = 449, - [BNXT_ULP_CLASS_HID_54a4] = 450, - [BNXT_ULP_CLASS_HID_29b4] = 451, - [BNXT_ULP_CLASS_HID_20c8] = 452, - [BNXT_ULP_CLASS_HID_7244] = 453, - [BNXT_ULP_CLASS_HID_4d98] = 454, - [BNXT_ULP_CLASS_HID_5e68] = 455, - [BNXT_ULP_CLASS_HID_598c] = 456, - [BNXT_ULP_CLASS_HID_1248] = 457, - [BNXT_ULP_CLASS_HID_74d8] = 458, - [BNXT_ULP_CLASS_HID_49a8] = 459, - [BNXT_ULP_CLASS_HID_40cc] = 460, - [BNXT_ULP_CLASS_HID_0b0c] = 461, - [BNXT_ULP_CLASS_HID_0220] = 462, - [BNXT_ULP_CLASS_HID_1730] = 463, - [BNXT_ULP_CLASS_HID_7980] = 464, - [BNXT_ULP_CLASS_HID_1db0] = 465, - [BNXT_ULP_CLASS_HID_1494] = 466, - [BNXT_ULP_CLASS_HID_70d0] = 467, - [BNXT_ULP_CLASS_HID_4834] = 468, - [BNXT_ULP_CLASS_HID_3db4] = 469, - [BNXT_ULP_CLASS_HID_3498] = 470, - [BNXT_ULP_CLASS_HID_0988] = 471, - [BNXT_ULP_CLASS_HID_00ec] = 472, - [BNXT_ULP_CLASS_HID_3f44] = 473, - [BNXT_ULP_CLASS_HID_36a8] = 474, - [BNXT_ULP_CLASS_HID_0b58] = 475, - [BNXT_ULP_CLASS_HID_02bc] = 476, - [BNXT_ULP_CLASS_HID_5f48] = 477, - [BNXT_ULP_CLASS_HID_56ac] = 478, - [BNXT_ULP_CLASS_HID_2b5c] = 479, - [BNXT_ULP_CLASS_HID_2280] = 480, - [BNXT_ULP_CLASS_HID_4000] = 481, - [BNXT_ULP_CLASS_HID_5b64] = 482, - [BNXT_ULP_CLASS_HID_2c14] = 483, - [BNXT_ULP_CLASS_HID_2778] = 484, - [BNXT_ULP_CLASS_HID_18f8] = 485, - [BNXT_ULP_CLASS_HID_13dc] = 486, - [BNXT_ULP_CLASS_HID_4c18] = 487, - [BNXT_ULP_CLASS_HID_477c] = 488, - [BNXT_ULP_CLASS_HID_1a88] = 489, - [BNXT_ULP_CLASS_HID_15ec] = 490, - [BNXT_ULP_CLASS_HID_4e28] = 491, - [BNXT_ULP_CLASS_HID_490c] = 492, - [BNXT_ULP_CLASS_HID_3a8c] = 493, - [BNXT_ULP_CLASS_HID_35f0] = 494, - [BNXT_ULP_CLASS_HID_06e0] = 495, - [BNXT_ULP_CLASS_HID_01c4] = 496, - [BNXT_ULP_CLASS_HID_1a08] = 497, - [BNXT_ULP_CLASS_HID_12ec] = 498, - [BNXT_ULP_CLASS_HID_4ea8] = 499, - [BNXT_ULP_CLASS_HID_478c] = 500, - [BNXT_ULP_CLASS_HID_0d4c] = 501, - [BNXT_ULP_CLASS_HID_0a20] = 502, - [BNXT_ULP_CLASS_HID_1930] = 503, - [BNXT_ULP_CLASS_HID_1614] = 504, - [BNXT_ULP_CLASS_HID_3a0c] = 505, - [BNXT_ULP_CLASS_HID_32e0] = 506, - [BNXT_ULP_CLASS_HID_01f0] = 507, - [BNXT_ULP_CLASS_HID_1ed4] = 508, - [BNXT_ULP_CLASS_HID_2d40] = 509, - [BNXT_ULP_CLASS_HID_2a24] = 510, - [BNXT_ULP_CLASS_HID_3934] = 511, - [BNXT_ULP_CLASS_HID_3608] = 512, - [BNXT_ULP_CLASS_HID_5e60] = 513, - [BNXT_ULP_CLASS_HID_5744] = 514, - [BNXT_ULP_CLASS_HID_2a54] = 515, - [BNXT_ULP_CLASS_HID_2328] = 516, - [BNXT_ULP_CLASS_HID_71a4] = 517, - [BNXT_ULP_CLASS_HID_4e78] = 518, - [BNXT_ULP_CLASS_HID_5d88] = 519, - [BNXT_ULP_CLASS_HID_5a6c] = 520, - [BNXT_ULP_CLASS_HID_11a8] = 521, - [BNXT_ULP_CLASS_HID_7738] = 522, - [BNXT_ULP_CLASS_HID_4a48] = 523, - [BNXT_ULP_CLASS_HID_432c] = 524, - [BNXT_ULP_CLASS_HID_08ec] = 525, - [BNXT_ULP_CLASS_HID_01c0] = 526, - [BNXT_ULP_CLASS_HID_14d0] = 527, - [BNXT_ULP_CLASS_HID_7a60] = 528, - [BNXT_ULP_CLASS_HID_1d90] = 529, - [BNXT_ULP_CLASS_HID_14b4] = 530, - [BNXT_ULP_CLASS_HID_70f0] = 531, - [BNXT_ULP_CLASS_HID_4814] = 532, - [BNXT_ULP_CLASS_HID_3d94] = 533, - [BNXT_ULP_CLASS_HID_34b8] = 534, - [BNXT_ULP_CLASS_HID_09a8] = 535, - [BNXT_ULP_CLASS_HID_00cc] = 536, - [BNXT_ULP_CLASS_HID_3f64] = 537, - [BNXT_ULP_CLASS_HID_3688] = 538, - [BNXT_ULP_CLASS_HID_0b78] = 539, - [BNXT_ULP_CLASS_HID_029c] = 540, - [BNXT_ULP_CLASS_HID_5f68] = 541, - [BNXT_ULP_CLASS_HID_568c] = 542, - [BNXT_ULP_CLASS_HID_2b7c] = 543, - [BNXT_ULP_CLASS_HID_22a0] = 544, - [BNXT_ULP_CLASS_HID_4020] = 545, - [BNXT_ULP_CLASS_HID_5b44] = 546, - [BNXT_ULP_CLASS_HID_2c34] = 547, - [BNXT_ULP_CLASS_HID_2758] = 548, - [BNXT_ULP_CLASS_HID_18d8] = 549, - [BNXT_ULP_CLASS_HID_13fc] = 550, - [BNXT_ULP_CLASS_HID_4c38] = 551, - [BNXT_ULP_CLASS_HID_475c] = 552, - [BNXT_ULP_CLASS_HID_1aa8] = 553, - [BNXT_ULP_CLASS_HID_15cc] = 554, - [BNXT_ULP_CLASS_HID_4e08] = 555, - [BNXT_ULP_CLASS_HID_492c] = 556, - [BNXT_ULP_CLASS_HID_3aac] = 557, - [BNXT_ULP_CLASS_HID_35d0] = 558, - [BNXT_ULP_CLASS_HID_06c0] = 559, - [BNXT_ULP_CLASS_HID_01e4] = 560, - [BNXT_ULP_CLASS_HID_4d32] = 561, - [BNXT_ULP_CLASS_HID_54aa] = 562, - [BNXT_ULP_CLASS_HID_0686] = 563, - [BNXT_ULP_CLASS_HID_540e] = 564, - [BNXT_ULP_CLASS_HID_2e3c] = 565, - [BNXT_ULP_CLASS_HID_3a20] = 566, - [BNXT_ULP_CLASS_HID_46f0] = 567, - [BNXT_ULP_CLASS_HID_52e4] = 568, - [BNXT_ULP_CLASS_HID_55e4] = 569, - [BNXT_ULP_CLASS_HID_21f8] = 570, - [BNXT_ULP_CLASS_HID_75e8] = 571, - [BNXT_ULP_CLASS_HID_41fc] = 572, - [BNXT_ULP_CLASS_HID_4d12] = 573, - [BNXT_ULP_CLASS_HID_548a] = 574, - [BNXT_ULP_CLASS_HID_3356] = 575, - [BNXT_ULP_CLASS_HID_1ace] = 576, - [BNXT_ULP_CLASS_HID_1a9a] = 577, - [BNXT_ULP_CLASS_HID_4d46] = 578, - [BNXT_ULP_CLASS_HID_2812] = 579, - [BNXT_ULP_CLASS_HID_338a] = 580, - [BNXT_ULP_CLASS_HID_06e6] = 581, - [BNXT_ULP_CLASS_HID_546e] = 582, - [BNXT_ULP_CLASS_HID_46ee] = 583, - [BNXT_ULP_CLASS_HID_0d22] = 584, - [BNXT_ULP_CLASS_HID_26e2] = 585, - [BNXT_ULP_CLASS_HID_746a] = 586, - [BNXT_ULP_CLASS_HID_1fa6] = 587, - [BNXT_ULP_CLASS_HID_2d2e] = 588, - [BNXT_ULP_CLASS_HID_4ef2] = 589, - [BNXT_ULP_CLASS_HID_576a] = 590, - [BNXT_ULP_CLASS_HID_30b6] = 591, - [BNXT_ULP_CLASS_HID_192e] = 592, - [BNXT_ULP_CLASS_HID_197a] = 593, - [BNXT_ULP_CLASS_HID_4ea6] = 594, - [BNXT_ULP_CLASS_HID_2bf2] = 595, - [BNXT_ULP_CLASS_HID_306a] = 596, - [BNXT_ULP_CLASS_HID_06c6] = 597, - [BNXT_ULP_CLASS_HID_544e] = 598, - [BNXT_ULP_CLASS_HID_46ce] = 599, - [BNXT_ULP_CLASS_HID_0d02] = 600, - [BNXT_ULP_CLASS_HID_26c2] = 601, - [BNXT_ULP_CLASS_HID_744a] = 602, - [BNXT_ULP_CLASS_HID_1f86] = 603, - [BNXT_ULP_CLASS_HID_2d0e] = 604, - [BNXT_ULP_CLASS_HID_2e1c] = 605, - [BNXT_ULP_CLASS_HID_3a00] = 606, - [BNXT_ULP_CLASS_HID_46d0] = 607, - [BNXT_ULP_CLASS_HID_52c4] = 608, - [BNXT_ULP_CLASS_HID_4e10] = 609, - [BNXT_ULP_CLASS_HID_5a04] = 610, - [BNXT_ULP_CLASS_HID_1f98] = 611, - [BNXT_ULP_CLASS_HID_72f8] = 612, - [BNXT_ULP_CLASS_HID_0a78] = 613, - [BNXT_ULP_CLASS_HID_166c] = 614, - [BNXT_ULP_CLASS_HID_233c] = 615, - [BNXT_ULP_CLASS_HID_0f20] = 616, - [BNXT_ULP_CLASS_HID_2a7c] = 617, - [BNXT_ULP_CLASS_HID_3660] = 618, - [BNXT_ULP_CLASS_HID_4330] = 619, - [BNXT_ULP_CLASS_HID_2f24] = 620, - [BNXT_ULP_CLASS_HID_5584] = 621, - [BNXT_ULP_CLASS_HID_2198] = 622, - [BNXT_ULP_CLASS_HID_7588] = 623, - [BNXT_ULP_CLASS_HID_419c] = 624, - [BNXT_ULP_CLASS_HID_7758] = 625, - [BNXT_ULP_CLASS_HID_43ac] = 626, - [BNXT_ULP_CLASS_HID_0c10] = 627, - [BNXT_ULP_CLASS_HID_1864] = 628, - [BNXT_ULP_CLASS_HID_30c8] = 629, - [BNXT_ULP_CLASS_HID_1cdc] = 630, - [BNXT_ULP_CLASS_HID_50cc] = 631, - [BNXT_ULP_CLASS_HID_3d20] = 632, - [BNXT_ULP_CLASS_HID_529c] = 633, - [BNXT_ULP_CLASS_HID_3ef0] = 634, - [BNXT_ULP_CLASS_HID_72e0] = 635, - [BNXT_ULP_CLASS_HID_5ef4] = 636, - [BNXT_ULP_CLASS_HID_2dfc] = 637, - [BNXT_ULP_CLASS_HID_39e0] = 638, - [BNXT_ULP_CLASS_HID_4530] = 639, - [BNXT_ULP_CLASS_HID_5124] = 640, - [BNXT_ULP_CLASS_HID_4df0] = 641, - [BNXT_ULP_CLASS_HID_59e4] = 642, - [BNXT_ULP_CLASS_HID_1c78] = 643, - [BNXT_ULP_CLASS_HID_7118] = 644, - [BNXT_ULP_CLASS_HID_0998] = 645, - [BNXT_ULP_CLASS_HID_158c] = 646, - [BNXT_ULP_CLASS_HID_20dc] = 647, - [BNXT_ULP_CLASS_HID_0cc0] = 648, - [BNXT_ULP_CLASS_HID_299c] = 649, - [BNXT_ULP_CLASS_HID_3580] = 650, - [BNXT_ULP_CLASS_HID_40d0] = 651, - [BNXT_ULP_CLASS_HID_2cc4] = 652, - [BNXT_ULP_CLASS_HID_55a4] = 653, - [BNXT_ULP_CLASS_HID_21b8] = 654, - [BNXT_ULP_CLASS_HID_75a8] = 655, - [BNXT_ULP_CLASS_HID_41bc] = 656, - [BNXT_ULP_CLASS_HID_7778] = 657, - [BNXT_ULP_CLASS_HID_438c] = 658, - [BNXT_ULP_CLASS_HID_0c30] = 659, - [BNXT_ULP_CLASS_HID_1844] = 660, - [BNXT_ULP_CLASS_HID_30e8] = 661, - [BNXT_ULP_CLASS_HID_1cfc] = 662, - [BNXT_ULP_CLASS_HID_50ec] = 663, - [BNXT_ULP_CLASS_HID_3d00] = 664, - [BNXT_ULP_CLASS_HID_52bc] = 665, - [BNXT_ULP_CLASS_HID_3ed0] = 666, - [BNXT_ULP_CLASS_HID_72c0] = 667, - [BNXT_ULP_CLASS_HID_5ed4] = 668, - [BNXT_ULP_CLASS_HID_3866] = 669, - [BNXT_ULP_CLASS_HID_381e] = 670, - [BNXT_ULP_CLASS_HID_3860] = 671, - [BNXT_ULP_CLASS_HID_0454] = 672, - [BNXT_ULP_CLASS_HID_3818] = 673, - [BNXT_ULP_CLASS_HID_042c] = 674, - [BNXT_ULP_CLASS_HID_3846] = 675, - [BNXT_ULP_CLASS_HID_387e] = 676, - [BNXT_ULP_CLASS_HID_3ba6] = 677, - [BNXT_ULP_CLASS_HID_385e] = 678, - [BNXT_ULP_CLASS_HID_3840] = 679, - [BNXT_ULP_CLASS_HID_0474] = 680, - [BNXT_ULP_CLASS_HID_3878] = 681, - [BNXT_ULP_CLASS_HID_044c] = 682, - [BNXT_ULP_CLASS_HID_3ba0] = 683, - [BNXT_ULP_CLASS_HID_0794] = 684, - [BNXT_ULP_CLASS_HID_3858] = 685, - [BNXT_ULP_CLASS_HID_046c] = 686 + [BNXT_ULP_CLASS_HID_3612] = 345, + [BNXT_ULP_CLASS_HID_66da] = 346, + [BNXT_ULP_CLASS_HID_6165] = 347, + [BNXT_ULP_CLASS_HID_2aa1] = 348, + [BNXT_ULP_CLASS_HID_09cd] = 349, + [BNXT_ULP_CLASS_HID_3845] = 350, + [BNXT_ULP_CLASS_HID_11e9] = 351, + [BNXT_ULP_CLASS_HID_4361] = 352, + [BNXT_ULP_CLASS_HID_218d] = 353, + [BNXT_ULP_CLASS_HID_5105] = 354, + [BNXT_ULP_CLASS_HID_0c89] = 355, + [BNXT_ULP_CLASS_HID_3e81] = 356, + [BNXT_ULP_CLASS_HID_1dad] = 357, + [BNXT_ULP_CLASS_HID_4ca5] = 358, + [BNXT_ULP_CLASS_HID_25c9] = 359, + [BNXT_ULP_CLASS_HID_57c1] = 360, + [BNXT_ULP_CLASS_HID_33ed] = 361, + [BNXT_ULP_CLASS_HID_65e5] = 362, + [BNXT_ULP_CLASS_HID_6dd9] = 363, + [BNXT_ULP_CLASS_HID_261d] = 364, + [BNXT_ULP_CLASS_HID_0571] = 365, + [BNXT_ULP_CLASS_HID_34f9] = 366, + [BNXT_ULP_CLASS_HID_1d55] = 367, + [BNXT_ULP_CLASS_HID_4fdd] = 368, + [BNXT_ULP_CLASS_HID_2d31] = 369, + [BNXT_ULP_CLASS_HID_5db9] = 370, + [BNXT_ULP_CLASS_HID_0035] = 371, + [BNXT_ULP_CLASS_HID_323d] = 372, + [BNXT_ULP_CLASS_HID_1111] = 373, + [BNXT_ULP_CLASS_HID_4019] = 374, + [BNXT_ULP_CLASS_HID_2975] = 375, + [BNXT_ULP_CLASS_HID_5b7d] = 376, + [BNXT_ULP_CLASS_HID_3f51] = 377, + [BNXT_ULP_CLASS_HID_6959] = 378, + [BNXT_ULP_CLASS_HID_0e85] = 379, + [BNXT_ULP_CLASS_HID_380d] = 380, + [BNXT_ULP_CLASS_HID_1f21] = 381, + [BNXT_ULP_CLASS_HID_4ea9] = 382, + [BNXT_ULP_CLASS_HID_1705] = 383, + [BNXT_ULP_CLASS_HID_418d] = 384, + [BNXT_ULP_CLASS_HID_2721] = 385, + [BNXT_ULP_CLASS_HID_57a9] = 386, + [BNXT_ULP_CLASS_HID_1a25] = 387, + [BNXT_ULP_CLASS_HID_342d] = 388, + [BNXT_ULP_CLASS_HID_2b01] = 389, + [BNXT_ULP_CLASS_HID_5a09] = 390, + [BNXT_ULP_CLASS_HID_2325] = 391, + [BNXT_ULP_CLASS_HID_5d2d] = 392, + [BNXT_ULP_CLASS_HID_3101] = 393, + [BNXT_ULP_CLASS_HID_6309] = 394, + [BNXT_ULP_CLASS_HID_0bad] = 395, + [BNXT_ULP_CLASS_HID_2535] = 396, + [BNXT_ULP_CLASS_HID_1869] = 397, + [BNXT_ULP_CLASS_HID_4bf1] = 398, + [BNXT_ULP_CLASS_HID_136d] = 399, + [BNXT_ULP_CLASS_HID_43f5] = 400, + [BNXT_ULP_CLASS_HID_2129] = 401, + [BNXT_ULP_CLASS_HID_53b1] = 402, + [BNXT_ULP_CLASS_HID_072d] = 403, + [BNXT_ULP_CLASS_HID_3135] = 404, + [BNXT_ULP_CLASS_HID_1429] = 405, + [BNXT_ULP_CLASS_HID_4731] = 406, + [BNXT_ULP_CLASS_HID_2f6d] = 407, + [BNXT_ULP_CLASS_HID_5f75] = 408, + [BNXT_ULP_CLASS_HID_3d69] = 409, + [BNXT_ULP_CLASS_HID_6f71] = 410, + [BNXT_ULP_CLASS_HID_0dbd] = 411, + [BNXT_ULP_CLASS_HID_3f25] = 412, + [BNXT_ULP_CLASS_HID_1239] = 413, + [BNXT_ULP_CLASS_HID_4da1] = 414, + [BNXT_ULP_CLASS_HID_153d] = 415, + [BNXT_ULP_CLASS_HID_45a5] = 416, + [BNXT_ULP_CLASS_HID_3bb9] = 417, + [BNXT_ULP_CLASS_HID_55a1] = 418, + [BNXT_ULP_CLASS_HID_193d] = 419, + [BNXT_ULP_CLASS_HID_4b25] = 420, + [BNXT_ULP_CLASS_HID_2e39] = 421, + [BNXT_ULP_CLASS_HID_5921] = 422, + [BNXT_ULP_CLASS_HID_213d] = 423, + [BNXT_ULP_CLASS_HID_5125] = 424, + [BNXT_ULP_CLASS_HID_3739] = 425, + [BNXT_ULP_CLASS_HID_093d] = 426, + [BNXT_ULP_CLASS_HID_684d] = 427, + [BNXT_ULP_CLASS_HID_2389] = 428, + [BNXT_ULP_CLASS_HID_00e5] = 429, + [BNXT_ULP_CLASS_HID_316d] = 430, + [BNXT_ULP_CLASS_HID_18c1] = 431, + [BNXT_ULP_CLASS_HID_4a49] = 432, + [BNXT_ULP_CLASS_HID_28a5] = 433, + [BNXT_ULP_CLASS_HID_582d] = 434, + [BNXT_ULP_CLASS_HID_05a1] = 435, + [BNXT_ULP_CLASS_HID_37a9] = 436, + [BNXT_ULP_CLASS_HID_1485] = 437, + [BNXT_ULP_CLASS_HID_458d] = 438, + [BNXT_ULP_CLASS_HID_2ce1] = 439, + [BNXT_ULP_CLASS_HID_5ee9] = 440, + [BNXT_ULP_CLASS_HID_3ac5] = 441, + [BNXT_ULP_CLASS_HID_6ccd] = 442, + [BNXT_ULP_CLASS_HID_0b11] = 443, + [BNXT_ULP_CLASS_HID_3d99] = 444, + [BNXT_ULP_CLASS_HID_1ab5] = 445, + [BNXT_ULP_CLASS_HID_4b3d] = 446, + [BNXT_ULP_CLASS_HID_1291] = 447, + [BNXT_ULP_CLASS_HID_4419] = 448, + [BNXT_ULP_CLASS_HID_22b5] = 449, + [BNXT_ULP_CLASS_HID_523d] = 450, + [BNXT_ULP_CLASS_HID_1fb1] = 451, + [BNXT_ULP_CLASS_HID_31b9] = 452, + [BNXT_ULP_CLASS_HID_2e95] = 453, + [BNXT_ULP_CLASS_HID_5f9d] = 454, + [BNXT_ULP_CLASS_HID_26b1] = 455, + [BNXT_ULP_CLASS_HID_58b9] = 456, + [BNXT_ULP_CLASS_HID_3495] = 457, + [BNXT_ULP_CLASS_HID_669d] = 458, + [BNXT_ULP_CLASS_HID_0e39] = 459, + [BNXT_ULP_CLASS_HID_20a1] = 460, + [BNXT_ULP_CLASS_HID_1dfd] = 461, + [BNXT_ULP_CLASS_HID_4e65] = 462, + [BNXT_ULP_CLASS_HID_16f9] = 463, + [BNXT_ULP_CLASS_HID_4661] = 464, + [BNXT_ULP_CLASS_HID_24bd] = 465, + [BNXT_ULP_CLASS_HID_5625] = 466, + [BNXT_ULP_CLASS_HID_02b9] = 467, + [BNXT_ULP_CLASS_HID_34a1] = 468, + [BNXT_ULP_CLASS_HID_11bd] = 469, + [BNXT_ULP_CLASS_HID_42a5] = 470, + [BNXT_ULP_CLASS_HID_2af9] = 471, + [BNXT_ULP_CLASS_HID_5ae1] = 472, + [BNXT_ULP_CLASS_HID_38fd] = 473, + [BNXT_ULP_CLASS_HID_6ae5] = 474, + [BNXT_ULP_CLASS_HID_0829] = 475, + [BNXT_ULP_CLASS_HID_3ab1] = 476, + [BNXT_ULP_CLASS_HID_17ad] = 477, + [BNXT_ULP_CLASS_HID_4835] = 478, + [BNXT_ULP_CLASS_HID_10a9] = 479, + [BNXT_ULP_CLASS_HID_4031] = 480, + [BNXT_ULP_CLASS_HID_3e2d] = 481, + [BNXT_ULP_CLASS_HID_5035] = 482, + [BNXT_ULP_CLASS_HID_1ca9] = 483, + [BNXT_ULP_CLASS_HID_4eb1] = 484, + [BNXT_ULP_CLASS_HID_2bad] = 485, + [BNXT_ULP_CLASS_HID_5cb5] = 486, + [BNXT_ULP_CLASS_HID_24a9] = 487, + [BNXT_ULP_CLASS_HID_54b1] = 488, + [BNXT_ULP_CLASS_HID_32ad] = 489, + [BNXT_ULP_CLASS_HID_0ca9] = 490, + [BNXT_ULP_CLASS_HID_7f35] = 491, + [BNXT_ULP_CLASS_HID_34f1] = 492, + [BNXT_ULP_CLASS_HID_179d] = 493, + [BNXT_ULP_CLASS_HID_2615] = 494, + [BNXT_ULP_CLASS_HID_0fb9] = 495, + [BNXT_ULP_CLASS_HID_5d31] = 496, + [BNXT_ULP_CLASS_HID_3fdd] = 497, + [BNXT_ULP_CLASS_HID_4f55] = 498, + [BNXT_ULP_CLASS_HID_12d9] = 499, + [BNXT_ULP_CLASS_HID_20d1] = 500, + [BNXT_ULP_CLASS_HID_03fd] = 501, + [BNXT_ULP_CLASS_HID_52f5] = 502, + [BNXT_ULP_CLASS_HID_3b99] = 503, + [BNXT_ULP_CLASS_HID_4991] = 504, + [BNXT_ULP_CLASS_HID_2dbd] = 505, + [BNXT_ULP_CLASS_HID_7bb5] = 506, + [BNXT_ULP_CLASS_HID_34c6] = 507, + [BNXT_ULP_CLASS_HID_0c22] = 508, + [BNXT_ULP_CLASS_HID_1cbe] = 509, + [BNXT_ULP_CLASS_HID_179a] = 510, + [BNXT_ULP_CLASS_HID_59be] = 511, + [BNXT_ULP_CLASS_HID_515a] = 512, + [BNXT_ULP_CLASS_HID_1c72] = 513, + [BNXT_ULP_CLASS_HID_171e] = 514, + [BNXT_ULP_CLASS_HID_19c8] = 515, + [BNXT_ULP_CLASS_HID_112c] = 516, + [BNXT_ULP_CLASS_HID_4d68] = 517, + [BNXT_ULP_CLASS_HID_444c] = 518, + [BNXT_ULP_CLASS_HID_0e8c] = 519, + [BNXT_ULP_CLASS_HID_09e0] = 520, + [BNXT_ULP_CLASS_HID_1af0] = 521, + [BNXT_ULP_CLASS_HID_15d4] = 522, + [BNXT_ULP_CLASS_HID_1dd0] = 523, + [BNXT_ULP_CLASS_HID_14f4] = 524, + [BNXT_ULP_CLASS_HID_70b0] = 525, + [BNXT_ULP_CLASS_HID_4854] = 526, + [BNXT_ULP_CLASS_HID_3dd4] = 527, + [BNXT_ULP_CLASS_HID_34f8] = 528, + [BNXT_ULP_CLASS_HID_09e8] = 529, + [BNXT_ULP_CLASS_HID_008c] = 530, + [BNXT_ULP_CLASS_HID_34e6] = 531, + [BNXT_ULP_CLASS_HID_0c02] = 532, + [BNXT_ULP_CLASS_HID_1c9e] = 533, + [BNXT_ULP_CLASS_HID_17ba] = 534, + [BNXT_ULP_CLASS_HID_429e] = 535, + [BNXT_ULP_CLASS_HID_5dba] = 536, + [BNXT_ULP_CLASS_HID_2a16] = 537, + [BNXT_ULP_CLASS_HID_2532] = 538, + [BNXT_ULP_CLASS_HID_2da2] = 539, + [BNXT_ULP_CLASS_HID_24fe] = 540, + [BNXT_ULP_CLASS_HID_355a] = 541, + [BNXT_ULP_CLASS_HID_0c76] = 542, + [BNXT_ULP_CLASS_HID_13e6] = 543, + [BNXT_ULP_CLASS_HID_7276] = 544, + [BNXT_ULP_CLASS_HID_42d2] = 545, + [BNXT_ULP_CLASS_HID_5dee] = 546, + [BNXT_ULP_CLASS_HID_59de] = 547, + [BNXT_ULP_CLASS_HID_513a] = 548, + [BNXT_ULP_CLASS_HID_1c12] = 549, + [BNXT_ULP_CLASS_HID_177e] = 550, + [BNXT_ULP_CLASS_HID_0e92] = 551, + [BNXT_ULP_CLASS_HID_09fe] = 552, + [BNXT_ULP_CLASS_HID_5c1a] = 553, + [BNXT_ULP_CLASS_HID_5746] = 554, + [BNXT_ULP_CLASS_HID_79da] = 555, + [BNXT_ULP_CLASS_HID_7106] = 556, + [BNXT_ULP_CLASS_HID_3c1e] = 557, + [BNXT_ULP_CLASS_HID_377a] = 558, + [BNXT_ULP_CLASS_HID_2e9e] = 559, + [BNXT_ULP_CLASS_HID_29fa] = 560, + [BNXT_ULP_CLASS_HID_14d2] = 561, + [BNXT_ULP_CLASS_HID_7742] = 562, + [BNXT_ULP_CLASS_HID_3706] = 563, + [BNXT_ULP_CLASS_HID_0fe2] = 564, + [BNXT_ULP_CLASS_HID_1f7e] = 565, + [BNXT_ULP_CLASS_HID_145a] = 566, + [BNXT_ULP_CLASS_HID_417e] = 567, + [BNXT_ULP_CLASS_HID_5e5a] = 568, + [BNXT_ULP_CLASS_HID_29f6] = 569, + [BNXT_ULP_CLASS_HID_26d2] = 570, + [BNXT_ULP_CLASS_HID_2e42] = 571, + [BNXT_ULP_CLASS_HID_271e] = 572, + [BNXT_ULP_CLASS_HID_36ba] = 573, + [BNXT_ULP_CLASS_HID_0f96] = 574, + [BNXT_ULP_CLASS_HID_1006] = 575, + [BNXT_ULP_CLASS_HID_7196] = 576, + [BNXT_ULP_CLASS_HID_4132] = 577, + [BNXT_ULP_CLASS_HID_5e0e] = 578, + [BNXT_ULP_CLASS_HID_59fe] = 579, + [BNXT_ULP_CLASS_HID_511a] = 580, + [BNXT_ULP_CLASS_HID_1c32] = 581, + [BNXT_ULP_CLASS_HID_175e] = 582, + [BNXT_ULP_CLASS_HID_0eb2] = 583, + [BNXT_ULP_CLASS_HID_09de] = 584, + [BNXT_ULP_CLASS_HID_5c3a] = 585, + [BNXT_ULP_CLASS_HID_5766] = 586, + [BNXT_ULP_CLASS_HID_79fa] = 587, + [BNXT_ULP_CLASS_HID_7126] = 588, + [BNXT_ULP_CLASS_HID_3c3e] = 589, + [BNXT_ULP_CLASS_HID_375a] = 590, + [BNXT_ULP_CLASS_HID_2ebe] = 591, + [BNXT_ULP_CLASS_HID_29da] = 592, + [BNXT_ULP_CLASS_HID_14f2] = 593, + [BNXT_ULP_CLASS_HID_7762] = 594, + [BNXT_ULP_CLASS_HID_19e8] = 595, + [BNXT_ULP_CLASS_HID_110c] = 596, + [BNXT_ULP_CLASS_HID_4d48] = 597, + [BNXT_ULP_CLASS_HID_446c] = 598, + [BNXT_ULP_CLASS_HID_0eac] = 599, + [BNXT_ULP_CLASS_HID_09c0] = 600, + [BNXT_ULP_CLASS_HID_1ad0] = 601, + [BNXT_ULP_CLASS_HID_15f4] = 602, + [BNXT_ULP_CLASS_HID_39ec] = 603, + [BNXT_ULP_CLASS_HID_3100] = 604, + [BNXT_ULP_CLASS_HID_0210] = 605, + [BNXT_ULP_CLASS_HID_1d34] = 606, + [BNXT_ULP_CLASS_HID_2ea0] = 607, + [BNXT_ULP_CLASS_HID_29c4] = 608, + [BNXT_ULP_CLASS_HID_3ad4] = 609, + [BNXT_ULP_CLASS_HID_35e8] = 610, + [BNXT_ULP_CLASS_HID_5d80] = 611, + [BNXT_ULP_CLASS_HID_54a4] = 612, + [BNXT_ULP_CLASS_HID_29b4] = 613, + [BNXT_ULP_CLASS_HID_20c8] = 614, + [BNXT_ULP_CLASS_HID_7244] = 615, + [BNXT_ULP_CLASS_HID_4d98] = 616, + [BNXT_ULP_CLASS_HID_5e68] = 617, + [BNXT_ULP_CLASS_HID_598c] = 618, + [BNXT_ULP_CLASS_HID_1248] = 619, + [BNXT_ULP_CLASS_HID_74d8] = 620, + [BNXT_ULP_CLASS_HID_49a8] = 621, + [BNXT_ULP_CLASS_HID_40cc] = 622, + [BNXT_ULP_CLASS_HID_0b0c] = 623, + [BNXT_ULP_CLASS_HID_0220] = 624, + [BNXT_ULP_CLASS_HID_1730] = 625, + [BNXT_ULP_CLASS_HID_7980] = 626, + [BNXT_ULP_CLASS_HID_1db0] = 627, + [BNXT_ULP_CLASS_HID_1494] = 628, + [BNXT_ULP_CLASS_HID_70d0] = 629, + [BNXT_ULP_CLASS_HID_4834] = 630, + [BNXT_ULP_CLASS_HID_3db4] = 631, + [BNXT_ULP_CLASS_HID_3498] = 632, + [BNXT_ULP_CLASS_HID_0988] = 633, + [BNXT_ULP_CLASS_HID_00ec] = 634, + [BNXT_ULP_CLASS_HID_3f44] = 635, + [BNXT_ULP_CLASS_HID_36a8] = 636, + [BNXT_ULP_CLASS_HID_0b58] = 637, + [BNXT_ULP_CLASS_HID_02bc] = 638, + [BNXT_ULP_CLASS_HID_5f48] = 639, + [BNXT_ULP_CLASS_HID_56ac] = 640, + [BNXT_ULP_CLASS_HID_2b5c] = 641, + [BNXT_ULP_CLASS_HID_2280] = 642, + [BNXT_ULP_CLASS_HID_4000] = 643, + [BNXT_ULP_CLASS_HID_5b64] = 644, + [BNXT_ULP_CLASS_HID_2c14] = 645, + [BNXT_ULP_CLASS_HID_2778] = 646, + [BNXT_ULP_CLASS_HID_18f8] = 647, + [BNXT_ULP_CLASS_HID_13dc] = 648, + [BNXT_ULP_CLASS_HID_4c18] = 649, + [BNXT_ULP_CLASS_HID_477c] = 650, + [BNXT_ULP_CLASS_HID_1a88] = 651, + [BNXT_ULP_CLASS_HID_15ec] = 652, + [BNXT_ULP_CLASS_HID_4e28] = 653, + [BNXT_ULP_CLASS_HID_490c] = 654, + [BNXT_ULP_CLASS_HID_3a8c] = 655, + [BNXT_ULP_CLASS_HID_35f0] = 656, + [BNXT_ULP_CLASS_HID_06e0] = 657, + [BNXT_ULP_CLASS_HID_01c4] = 658, + [BNXT_ULP_CLASS_HID_1a08] = 659, + [BNXT_ULP_CLASS_HID_12ec] = 660, + [BNXT_ULP_CLASS_HID_4ea8] = 661, + [BNXT_ULP_CLASS_HID_478c] = 662, + [BNXT_ULP_CLASS_HID_0d4c] = 663, + [BNXT_ULP_CLASS_HID_0a20] = 664, + [BNXT_ULP_CLASS_HID_1930] = 665, + [BNXT_ULP_CLASS_HID_1614] = 666, + [BNXT_ULP_CLASS_HID_3a0c] = 667, + [BNXT_ULP_CLASS_HID_32e0] = 668, + [BNXT_ULP_CLASS_HID_01f0] = 669, + [BNXT_ULP_CLASS_HID_1ed4] = 670, + [BNXT_ULP_CLASS_HID_2d40] = 671, + [BNXT_ULP_CLASS_HID_2a24] = 672, + [BNXT_ULP_CLASS_HID_3934] = 673, + [BNXT_ULP_CLASS_HID_3608] = 674, + [BNXT_ULP_CLASS_HID_5e60] = 675, + [BNXT_ULP_CLASS_HID_5744] = 676, + [BNXT_ULP_CLASS_HID_2a54] = 677, + [BNXT_ULP_CLASS_HID_2328] = 678, + [BNXT_ULP_CLASS_HID_71a4] = 679, + [BNXT_ULP_CLASS_HID_4e78] = 680, + [BNXT_ULP_CLASS_HID_5d88] = 681, + [BNXT_ULP_CLASS_HID_5a6c] = 682, + [BNXT_ULP_CLASS_HID_11a8] = 683, + [BNXT_ULP_CLASS_HID_7738] = 684, + [BNXT_ULP_CLASS_HID_4a48] = 685, + [BNXT_ULP_CLASS_HID_432c] = 686, + [BNXT_ULP_CLASS_HID_08ec] = 687, + [BNXT_ULP_CLASS_HID_01c0] = 688, + [BNXT_ULP_CLASS_HID_14d0] = 689, + [BNXT_ULP_CLASS_HID_7a60] = 690, + [BNXT_ULP_CLASS_HID_1d90] = 691, + [BNXT_ULP_CLASS_HID_14b4] = 692, + [BNXT_ULP_CLASS_HID_70f0] = 693, + [BNXT_ULP_CLASS_HID_4814] = 694, + [BNXT_ULP_CLASS_HID_3d94] = 695, + [BNXT_ULP_CLASS_HID_34b8] = 696, + [BNXT_ULP_CLASS_HID_09a8] = 697, + [BNXT_ULP_CLASS_HID_00cc] = 698, + [BNXT_ULP_CLASS_HID_3f64] = 699, + [BNXT_ULP_CLASS_HID_3688] = 700, + [BNXT_ULP_CLASS_HID_0b78] = 701, + [BNXT_ULP_CLASS_HID_029c] = 702, + [BNXT_ULP_CLASS_HID_5f68] = 703, + [BNXT_ULP_CLASS_HID_568c] = 704, + [BNXT_ULP_CLASS_HID_2b7c] = 705, + [BNXT_ULP_CLASS_HID_22a0] = 706, + [BNXT_ULP_CLASS_HID_4020] = 707, + [BNXT_ULP_CLASS_HID_5b44] = 708, + [BNXT_ULP_CLASS_HID_2c34] = 709, + [BNXT_ULP_CLASS_HID_2758] = 710, + [BNXT_ULP_CLASS_HID_18d8] = 711, + [BNXT_ULP_CLASS_HID_13fc] = 712, + [BNXT_ULP_CLASS_HID_4c38] = 713, + [BNXT_ULP_CLASS_HID_475c] = 714, + [BNXT_ULP_CLASS_HID_1aa8] = 715, + [BNXT_ULP_CLASS_HID_15cc] = 716, + [BNXT_ULP_CLASS_HID_4e08] = 717, + [BNXT_ULP_CLASS_HID_492c] = 718, + [BNXT_ULP_CLASS_HID_3aac] = 719, + [BNXT_ULP_CLASS_HID_35d0] = 720, + [BNXT_ULP_CLASS_HID_06c0] = 721, + [BNXT_ULP_CLASS_HID_01e4] = 722, + [BNXT_ULP_CLASS_HID_4d32] = 723, + [BNXT_ULP_CLASS_HID_54aa] = 724, + [BNXT_ULP_CLASS_HID_0686] = 725, + [BNXT_ULP_CLASS_HID_540e] = 726, + [BNXT_ULP_CLASS_HID_2e3c] = 727, + [BNXT_ULP_CLASS_HID_3a20] = 728, + [BNXT_ULP_CLASS_HID_46f0] = 729, + [BNXT_ULP_CLASS_HID_52e4] = 730, + [BNXT_ULP_CLASS_HID_55e4] = 731, + [BNXT_ULP_CLASS_HID_21f8] = 732, + [BNXT_ULP_CLASS_HID_75e8] = 733, + [BNXT_ULP_CLASS_HID_41fc] = 734, + [BNXT_ULP_CLASS_HID_4d12] = 735, + [BNXT_ULP_CLASS_HID_548a] = 736, + [BNXT_ULP_CLASS_HID_3356] = 737, + [BNXT_ULP_CLASS_HID_1ace] = 738, + [BNXT_ULP_CLASS_HID_1a9a] = 739, + [BNXT_ULP_CLASS_HID_4d46] = 740, + [BNXT_ULP_CLASS_HID_2812] = 741, + [BNXT_ULP_CLASS_HID_338a] = 742, + [BNXT_ULP_CLASS_HID_06e6] = 743, + [BNXT_ULP_CLASS_HID_546e] = 744, + [BNXT_ULP_CLASS_HID_46ee] = 745, + [BNXT_ULP_CLASS_HID_0d22] = 746, + [BNXT_ULP_CLASS_HID_26e2] = 747, + [BNXT_ULP_CLASS_HID_746a] = 748, + [BNXT_ULP_CLASS_HID_1fa6] = 749, + [BNXT_ULP_CLASS_HID_2d2e] = 750, + [BNXT_ULP_CLASS_HID_4ef2] = 751, + [BNXT_ULP_CLASS_HID_576a] = 752, + [BNXT_ULP_CLASS_HID_30b6] = 753, + [BNXT_ULP_CLASS_HID_192e] = 754, + [BNXT_ULP_CLASS_HID_197a] = 755, + [BNXT_ULP_CLASS_HID_4ea6] = 756, + [BNXT_ULP_CLASS_HID_2bf2] = 757, + [BNXT_ULP_CLASS_HID_306a] = 758, + [BNXT_ULP_CLASS_HID_06c6] = 759, + [BNXT_ULP_CLASS_HID_544e] = 760, + [BNXT_ULP_CLASS_HID_46ce] = 761, + [BNXT_ULP_CLASS_HID_0d02] = 762, + [BNXT_ULP_CLASS_HID_26c2] = 763, + [BNXT_ULP_CLASS_HID_744a] = 764, + [BNXT_ULP_CLASS_HID_1f86] = 765, + [BNXT_ULP_CLASS_HID_2d0e] = 766, + [BNXT_ULP_CLASS_HID_2e1c] = 767, + [BNXT_ULP_CLASS_HID_3a00] = 768, + [BNXT_ULP_CLASS_HID_46d0] = 769, + [BNXT_ULP_CLASS_HID_52c4] = 770, + [BNXT_ULP_CLASS_HID_4e10] = 771, + [BNXT_ULP_CLASS_HID_5a04] = 772, + [BNXT_ULP_CLASS_HID_1f98] = 773, + [BNXT_ULP_CLASS_HID_72f8] = 774, + [BNXT_ULP_CLASS_HID_0a78] = 775, + [BNXT_ULP_CLASS_HID_166c] = 776, + [BNXT_ULP_CLASS_HID_233c] = 777, + [BNXT_ULP_CLASS_HID_0f20] = 778, + [BNXT_ULP_CLASS_HID_2a7c] = 779, + [BNXT_ULP_CLASS_HID_3660] = 780, + [BNXT_ULP_CLASS_HID_4330] = 781, + [BNXT_ULP_CLASS_HID_2f24] = 782, + [BNXT_ULP_CLASS_HID_5584] = 783, + [BNXT_ULP_CLASS_HID_2198] = 784, + [BNXT_ULP_CLASS_HID_7588] = 785, + [BNXT_ULP_CLASS_HID_419c] = 786, + [BNXT_ULP_CLASS_HID_7758] = 787, + [BNXT_ULP_CLASS_HID_43ac] = 788, + [BNXT_ULP_CLASS_HID_0c10] = 789, + [BNXT_ULP_CLASS_HID_1864] = 790, + [BNXT_ULP_CLASS_HID_30c8] = 791, + [BNXT_ULP_CLASS_HID_1cdc] = 792, + [BNXT_ULP_CLASS_HID_50cc] = 793, + [BNXT_ULP_CLASS_HID_3d20] = 794, + [BNXT_ULP_CLASS_HID_529c] = 795, + [BNXT_ULP_CLASS_HID_3ef0] = 796, + [BNXT_ULP_CLASS_HID_72e0] = 797, + [BNXT_ULP_CLASS_HID_5ef4] = 798, + [BNXT_ULP_CLASS_HID_2dfc] = 799, + [BNXT_ULP_CLASS_HID_39e0] = 800, + [BNXT_ULP_CLASS_HID_4530] = 801, + [BNXT_ULP_CLASS_HID_5124] = 802, + [BNXT_ULP_CLASS_HID_4df0] = 803, + [BNXT_ULP_CLASS_HID_59e4] = 804, + [BNXT_ULP_CLASS_HID_1c78] = 805, + [BNXT_ULP_CLASS_HID_7118] = 806, + [BNXT_ULP_CLASS_HID_0998] = 807, + [BNXT_ULP_CLASS_HID_158c] = 808, + [BNXT_ULP_CLASS_HID_20dc] = 809, + [BNXT_ULP_CLASS_HID_0cc0] = 810, + [BNXT_ULP_CLASS_HID_299c] = 811, + [BNXT_ULP_CLASS_HID_3580] = 812, + [BNXT_ULP_CLASS_HID_40d0] = 813, + [BNXT_ULP_CLASS_HID_2cc4] = 814, + [BNXT_ULP_CLASS_HID_55a4] = 815, + [BNXT_ULP_CLASS_HID_21b8] = 816, + [BNXT_ULP_CLASS_HID_75a8] = 817, + [BNXT_ULP_CLASS_HID_41bc] = 818, + [BNXT_ULP_CLASS_HID_7778] = 819, + [BNXT_ULP_CLASS_HID_438c] = 820, + [BNXT_ULP_CLASS_HID_0c30] = 821, + [BNXT_ULP_CLASS_HID_1844] = 822, + [BNXT_ULP_CLASS_HID_30e8] = 823, + [BNXT_ULP_CLASS_HID_1cfc] = 824, + [BNXT_ULP_CLASS_HID_50ec] = 825, + [BNXT_ULP_CLASS_HID_3d00] = 826, + [BNXT_ULP_CLASS_HID_52bc] = 827, + [BNXT_ULP_CLASS_HID_3ed0] = 828, + [BNXT_ULP_CLASS_HID_72c0] = 829, + [BNXT_ULP_CLASS_HID_5ed4] = 830, + [BNXT_ULP_CLASS_HID_3866] = 831, + [BNXT_ULP_CLASS_HID_381e] = 832, + [BNXT_ULP_CLASS_HID_3860] = 833, + [BNXT_ULP_CLASS_HID_0454] = 834, + [BNXT_ULP_CLASS_HID_3818] = 835, + [BNXT_ULP_CLASS_HID_042c] = 836, + [BNXT_ULP_CLASS_HID_3846] = 837, + [BNXT_ULP_CLASS_HID_387e] = 838, + [BNXT_ULP_CLASS_HID_3ba6] = 839, + [BNXT_ULP_CLASS_HID_385e] = 840, + [BNXT_ULP_CLASS_HID_3840] = 841, + [BNXT_ULP_CLASS_HID_0474] = 842, + [BNXT_ULP_CLASS_HID_3878] = 843, + [BNXT_ULP_CLASS_HID_044c] = 844, + [BNXT_ULP_CLASS_HID_3ba0] = 845, + [BNXT_ULP_CLASS_HID_0794] = 846, + [BNXT_ULP_CLASS_HID_3858] = 847, + [BNXT_ULP_CLASS_HID_046c] = 848 }; /* Array for the proto matcher list */ @@ -6964,8 +7126,3839 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HF_0_1_12_BITMASK_O_UDP_DST_PORT } }, [345] = { - .class_hid = BNXT_ULP_CLASS_HID_34c6, + .class_hid = BNXT_ULP_CLASS_HID_3612, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 81920, + .flow_pattern_id = 0, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_F1 | + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT } + }, + [346] = { + .class_hid = BNXT_ULP_CLASS_HID_66da, + .class_tid = 2, + .hdr_sig_id = 0, + .flow_sig_id = 81928, + .flow_pattern_id = 0, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_F1 | + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT } + }, + [347] = { + .class_hid = BNXT_ULP_CLASS_HID_6165, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 1313792, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC } + }, + [348] = { + .class_hid = BNXT_ULP_CLASS_HID_2aa1, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 1321984, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC } + }, + [349] = { + .class_hid = BNXT_ULP_CLASS_HID_09cd, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 3410944, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC } + }, + [350] = { + .class_hid = BNXT_ULP_CLASS_HID_3845, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 3419136, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC } + }, + [351] = { + .class_hid = BNXT_ULP_CLASS_HID_11e9, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2148797440, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [352] = { + .class_hid = BNXT_ULP_CLASS_HID_4361, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2148805632, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [353] = { + .class_hid = BNXT_ULP_CLASS_HID_218d, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2150894592, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [354] = { + .class_hid = BNXT_ULP_CLASS_HID_5105, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 2150902784, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR } + }, + [355] = { + .class_hid = BNXT_ULP_CLASS_HID_0c89, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4296281088, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [356] = { + .class_hid = BNXT_ULP_CLASS_HID_3e81, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4296289280, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [357] = { + .class_hid = BNXT_ULP_CLASS_HID_1dad, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4298378240, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [358] = { + .class_hid = BNXT_ULP_CLASS_HID_4ca5, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 4298386432, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [359] = { + .class_hid = BNXT_ULP_CLASS_HID_25c9, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6443764736, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [360] = { + .class_hid = BNXT_ULP_CLASS_HID_57c1, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6443772928, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [361] = { + .class_hid = BNXT_ULP_CLASS_HID_33ed, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6445861888, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [362] = { + .class_hid = BNXT_ULP_CLASS_HID_65e5, + .class_tid = 2, + .hdr_sig_id = 1, + .flow_sig_id = 6445870080, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR } + }, + [363] = { + .class_hid = BNXT_ULP_CLASS_HID_6dd9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 1313792, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC } + }, + [364] = { + .class_hid = BNXT_ULP_CLASS_HID_261d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 1321984, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC } + }, + [365] = { + .class_hid = BNXT_ULP_CLASS_HID_0571, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 3410944, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC } + }, + [366] = { + .class_hid = BNXT_ULP_CLASS_HID_34f9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 3419136, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC } + }, + [367] = { + .class_hid = BNXT_ULP_CLASS_HID_1d55, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2148797440, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [368] = { + .class_hid = BNXT_ULP_CLASS_HID_4fdd, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2148805632, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [369] = { + .class_hid = BNXT_ULP_CLASS_HID_2d31, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2150894592, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [370] = { + .class_hid = BNXT_ULP_CLASS_HID_5db9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 2150902784, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR } + }, + [371] = { + .class_hid = BNXT_ULP_CLASS_HID_0035, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4296281088, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [372] = { + .class_hid = BNXT_ULP_CLASS_HID_323d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4296289280, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [373] = { + .class_hid = BNXT_ULP_CLASS_HID_1111, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4298378240, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [374] = { + .class_hid = BNXT_ULP_CLASS_HID_4019, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 4298386432, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [375] = { + .class_hid = BNXT_ULP_CLASS_HID_2975, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6443764736, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [376] = { + .class_hid = BNXT_ULP_CLASS_HID_5b7d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6443772928, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [377] = { + .class_hid = BNXT_ULP_CLASS_HID_3f51, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6445861888, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [378] = { + .class_hid = BNXT_ULP_CLASS_HID_6959, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 6445870080, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR } + }, + [379] = { + .class_hid = BNXT_ULP_CLASS_HID_0e85, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8591248384, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [380] = { + .class_hid = BNXT_ULP_CLASS_HID_380d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8591256576, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [381] = { + .class_hid = BNXT_ULP_CLASS_HID_1f21, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8593345536, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [382] = { + .class_hid = BNXT_ULP_CLASS_HID_4ea9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 8593353728, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [383] = { + .class_hid = BNXT_ULP_CLASS_HID_1705, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10738732032, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [384] = { + .class_hid = BNXT_ULP_CLASS_HID_418d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10738740224, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [385] = { + .class_hid = BNXT_ULP_CLASS_HID_2721, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10740829184, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [386] = { + .class_hid = BNXT_ULP_CLASS_HID_57a9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 10740837376, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [387] = { + .class_hid = BNXT_ULP_CLASS_HID_1a25, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12886215680, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [388] = { + .class_hid = BNXT_ULP_CLASS_HID_342d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12886223872, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [389] = { + .class_hid = BNXT_ULP_CLASS_HID_2b01, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12888312832, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [390] = { + .class_hid = BNXT_ULP_CLASS_HID_5a09, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 12888321024, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [391] = { + .class_hid = BNXT_ULP_CLASS_HID_2325, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15033699328, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [392] = { + .class_hid = BNXT_ULP_CLASS_HID_5d2d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15033707520, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [393] = { + .class_hid = BNXT_ULP_CLASS_HID_3101, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15035796480, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [394] = { + .class_hid = BNXT_ULP_CLASS_HID_6309, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 15035804672, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT } + }, + [395] = { + .class_hid = BNXT_ULP_CLASS_HID_0bad, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17181182976, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [396] = { + .class_hid = BNXT_ULP_CLASS_HID_2535, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17181191168, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [397] = { + .class_hid = BNXT_ULP_CLASS_HID_1869, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17183280128, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [398] = { + .class_hid = BNXT_ULP_CLASS_HID_4bf1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 17183288320, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [399] = { + .class_hid = BNXT_ULP_CLASS_HID_136d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19328666624, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [400] = { + .class_hid = BNXT_ULP_CLASS_HID_43f5, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19328674816, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [401] = { + .class_hid = BNXT_ULP_CLASS_HID_2129, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19330763776, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [402] = { + .class_hid = BNXT_ULP_CLASS_HID_53b1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 19330771968, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [403] = { + .class_hid = BNXT_ULP_CLASS_HID_072d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21476150272, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [404] = { + .class_hid = BNXT_ULP_CLASS_HID_3135, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21476158464, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [405] = { + .class_hid = BNXT_ULP_CLASS_HID_1429, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21478247424, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [406] = { + .class_hid = BNXT_ULP_CLASS_HID_4731, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 21478255616, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [407] = { + .class_hid = BNXT_ULP_CLASS_HID_2f6d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23623633920, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [408] = { + .class_hid = BNXT_ULP_CLASS_HID_5f75, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23623642112, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [409] = { + .class_hid = BNXT_ULP_CLASS_HID_3d69, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23625731072, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [410] = { + .class_hid = BNXT_ULP_CLASS_HID_6f71, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 23625739264, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [411] = { + .class_hid = BNXT_ULP_CLASS_HID_0dbd, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25771117568, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [412] = { + .class_hid = BNXT_ULP_CLASS_HID_3f25, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25771125760, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [413] = { + .class_hid = BNXT_ULP_CLASS_HID_1239, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25773214720, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [414] = { + .class_hid = BNXT_ULP_CLASS_HID_4da1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 25773222912, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [415] = { + .class_hid = BNXT_ULP_CLASS_HID_153d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27918601216, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [416] = { + .class_hid = BNXT_ULP_CLASS_HID_45a5, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27918609408, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [417] = { + .class_hid = BNXT_ULP_CLASS_HID_3bb9, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27920698368, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [418] = { + .class_hid = BNXT_ULP_CLASS_HID_55a1, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 27920706560, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [419] = { + .class_hid = BNXT_ULP_CLASS_HID_193d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30066084864, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [420] = { + .class_hid = BNXT_ULP_CLASS_HID_4b25, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30066093056, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [421] = { + .class_hid = BNXT_ULP_CLASS_HID_2e39, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30068182016, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [422] = { + .class_hid = BNXT_ULP_CLASS_HID_5921, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 30068190208, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [423] = { + .class_hid = BNXT_ULP_CLASS_HID_213d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32213568512, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [424] = { + .class_hid = BNXT_ULP_CLASS_HID_5125, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32213576704, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [425] = { + .class_hid = BNXT_ULP_CLASS_HID_3739, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32215665664, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [426] = { + .class_hid = BNXT_ULP_CLASS_HID_093d, + .class_tid = 2, + .hdr_sig_id = 2, + .flow_sig_id = 32215673856, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT | + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT } + }, + [427] = { + .class_hid = BNXT_ULP_CLASS_HID_684d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 1313792, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC } + }, + [428] = { + .class_hid = BNXT_ULP_CLASS_HID_2389, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 1321984, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC } + }, + [429] = { + .class_hid = BNXT_ULP_CLASS_HID_00e5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 3410944, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC } + }, + [430] = { + .class_hid = BNXT_ULP_CLASS_HID_316d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 3419136, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC } + }, + [431] = { + .class_hid = BNXT_ULP_CLASS_HID_18c1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2148797440, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [432] = { + .class_hid = BNXT_ULP_CLASS_HID_4a49, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2148805632, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [433] = { + .class_hid = BNXT_ULP_CLASS_HID_28a5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2150894592, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [434] = { + .class_hid = BNXT_ULP_CLASS_HID_582d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 2150902784, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR } + }, + [435] = { + .class_hid = BNXT_ULP_CLASS_HID_05a1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4296281088, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [436] = { + .class_hid = BNXT_ULP_CLASS_HID_37a9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4296289280, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [437] = { + .class_hid = BNXT_ULP_CLASS_HID_1485, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4298378240, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [438] = { + .class_hid = BNXT_ULP_CLASS_HID_458d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 4298386432, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [439] = { + .class_hid = BNXT_ULP_CLASS_HID_2ce1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6443764736, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [440] = { + .class_hid = BNXT_ULP_CLASS_HID_5ee9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6443772928, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [441] = { + .class_hid = BNXT_ULP_CLASS_HID_3ac5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6445861888, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [442] = { + .class_hid = BNXT_ULP_CLASS_HID_6ccd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 6445870080, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR } + }, + [443] = { + .class_hid = BNXT_ULP_CLASS_HID_0b11, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8591248384, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [444] = { + .class_hid = BNXT_ULP_CLASS_HID_3d99, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8591256576, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [445] = { + .class_hid = BNXT_ULP_CLASS_HID_1ab5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8593345536, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [446] = { + .class_hid = BNXT_ULP_CLASS_HID_4b3d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 8593353728, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [447] = { + .class_hid = BNXT_ULP_CLASS_HID_1291, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10738732032, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [448] = { + .class_hid = BNXT_ULP_CLASS_HID_4419, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10738740224, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [449] = { + .class_hid = BNXT_ULP_CLASS_HID_22b5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10740829184, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [450] = { + .class_hid = BNXT_ULP_CLASS_HID_523d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 10740837376, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [451] = { + .class_hid = BNXT_ULP_CLASS_HID_1fb1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12886215680, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [452] = { + .class_hid = BNXT_ULP_CLASS_HID_31b9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12886223872, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [453] = { + .class_hid = BNXT_ULP_CLASS_HID_2e95, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12888312832, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [454] = { + .class_hid = BNXT_ULP_CLASS_HID_5f9d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 12888321024, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [455] = { + .class_hid = BNXT_ULP_CLASS_HID_26b1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15033699328, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [456] = { + .class_hid = BNXT_ULP_CLASS_HID_58b9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15033707520, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [457] = { + .class_hid = BNXT_ULP_CLASS_HID_3495, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15035796480, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [458] = { + .class_hid = BNXT_ULP_CLASS_HID_669d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 15035804672, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT } + }, + [459] = { + .class_hid = BNXT_ULP_CLASS_HID_0e39, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17181182976, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [460] = { + .class_hid = BNXT_ULP_CLASS_HID_20a1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17181191168, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [461] = { + .class_hid = BNXT_ULP_CLASS_HID_1dfd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17183280128, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [462] = { + .class_hid = BNXT_ULP_CLASS_HID_4e65, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 17183288320, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [463] = { + .class_hid = BNXT_ULP_CLASS_HID_16f9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19328666624, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [464] = { + .class_hid = BNXT_ULP_CLASS_HID_4661, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19328674816, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [465] = { + .class_hid = BNXT_ULP_CLASS_HID_24bd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19330763776, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [466] = { + .class_hid = BNXT_ULP_CLASS_HID_5625, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 19330771968, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [467] = { + .class_hid = BNXT_ULP_CLASS_HID_02b9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21476150272, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [468] = { + .class_hid = BNXT_ULP_CLASS_HID_34a1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21476158464, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [469] = { + .class_hid = BNXT_ULP_CLASS_HID_11bd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21478247424, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [470] = { + .class_hid = BNXT_ULP_CLASS_HID_42a5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 21478255616, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [471] = { + .class_hid = BNXT_ULP_CLASS_HID_2af9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23623633920, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [472] = { + .class_hid = BNXT_ULP_CLASS_HID_5ae1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23623642112, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [473] = { + .class_hid = BNXT_ULP_CLASS_HID_38fd, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23625731072, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [474] = { + .class_hid = BNXT_ULP_CLASS_HID_6ae5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 23625739264, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [475] = { + .class_hid = BNXT_ULP_CLASS_HID_0829, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25771117568, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [476] = { + .class_hid = BNXT_ULP_CLASS_HID_3ab1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25771125760, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [477] = { + .class_hid = BNXT_ULP_CLASS_HID_17ad, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25773214720, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [478] = { + .class_hid = BNXT_ULP_CLASS_HID_4835, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 25773222912, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [479] = { + .class_hid = BNXT_ULP_CLASS_HID_10a9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27918601216, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [480] = { + .class_hid = BNXT_ULP_CLASS_HID_4031, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27918609408, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [481] = { + .class_hid = BNXT_ULP_CLASS_HID_3e2d, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27920698368, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [482] = { + .class_hid = BNXT_ULP_CLASS_HID_5035, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 27920706560, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [483] = { + .class_hid = BNXT_ULP_CLASS_HID_1ca9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30066084864, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [484] = { + .class_hid = BNXT_ULP_CLASS_HID_4eb1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30066093056, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [485] = { + .class_hid = BNXT_ULP_CLASS_HID_2bad, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30068182016, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [486] = { + .class_hid = BNXT_ULP_CLASS_HID_5cb5, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 30068190208, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [487] = { + .class_hid = BNXT_ULP_CLASS_HID_24a9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32213568512, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [488] = { + .class_hid = BNXT_ULP_CLASS_HID_54b1, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32213576704, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [489] = { + .class_hid = BNXT_ULP_CLASS_HID_32ad, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32215665664, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [490] = { + .class_hid = BNXT_ULP_CLASS_HID_0ca9, + .class_tid = 2, + .hdr_sig_id = 3, + .flow_sig_id = 32215673856, + .flow_pattern_id = 1, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT } + }, + [491] = { + .class_hid = BNXT_ULP_CLASS_HID_7f35, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 1313792, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC } + }, + [492] = { + .class_hid = BNXT_ULP_CLASS_HID_34f1, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 1321984, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC } + }, + [493] = { + .class_hid = BNXT_ULP_CLASS_HID_179d, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 3410944, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC } + }, + [494] = { + .class_hid = BNXT_ULP_CLASS_HID_2615, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 3419136, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC } + }, + [495] = { + .class_hid = BNXT_ULP_CLASS_HID_0fb9, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2148797440, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [496] = { + .class_hid = BNXT_ULP_CLASS_HID_5d31, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2148805632, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [497] = { + .class_hid = BNXT_ULP_CLASS_HID_3fdd, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2150894592, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [498] = { + .class_hid = BNXT_ULP_CLASS_HID_4f55, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 2150902784, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR } + }, + [499] = { + .class_hid = BNXT_ULP_CLASS_HID_12d9, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4296281088, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [500] = { + .class_hid = BNXT_ULP_CLASS_HID_20d1, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4296289280, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [501] = { + .class_hid = BNXT_ULP_CLASS_HID_03fd, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4298378240, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [502] = { + .class_hid = BNXT_ULP_CLASS_HID_52f5, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 4298386432, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [503] = { + .class_hid = BNXT_ULP_CLASS_HID_3b99, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6443764736, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [504] = { + .class_hid = BNXT_ULP_CLASS_HID_4991, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6443772928, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [505] = { + .class_hid = BNXT_ULP_CLASS_HID_2dbd, + .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6445861888, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [506] = { + .class_hid = BNXT_ULP_CLASS_HID_7bb5, .class_tid = 2, + .hdr_sig_id = 4, + .flow_sig_id = 6445870080, + .flow_pattern_id = 2, + .app_sig = 0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_ICMP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR } + }, + [507] = { + .class_hid = BNXT_ULP_CLASS_HID_34c6, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 0, @@ -6975,12 +10968,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [346] = { + [508] = { .class_hid = BNXT_ULP_CLASS_HID_0c22, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4100, .flow_pattern_id = 0, @@ -6990,13 +10983,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [347] = { + [509] = { .class_hid = BNXT_ULP_CLASS_HID_1cbe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 0, @@ -7006,13 +10999,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [348] = { + [510] = { .class_hid = BNXT_ULP_CLASS_HID_179a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 6148, .flow_pattern_id = 0, @@ -7022,14 +11015,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [349] = { + [511] = { .class_hid = BNXT_ULP_CLASS_HID_59be, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 0, @@ -7039,12 +11032,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [350] = { + [512] = { .class_hid = BNXT_ULP_CLASS_HID_515a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 16388, .flow_pattern_id = 0, @@ -7054,13 +11047,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [351] = { + [513] = { .class_hid = BNXT_ULP_CLASS_HID_1c72, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 0, @@ -7070,13 +11063,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [352] = { + [514] = { .class_hid = BNXT_ULP_CLASS_HID_171e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 24580, .flow_pattern_id = 0, @@ -7086,14 +11079,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [353] = { + [515] = { .class_hid = BNXT_ULP_CLASS_HID_19c8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 0, @@ -7104,12 +11097,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [354] = { + [516] = { .class_hid = BNXT_ULP_CLASS_HID_112c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32772, .flow_pattern_id = 0, @@ -7120,13 +11113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [355] = { + [517] = { .class_hid = BNXT_ULP_CLASS_HID_4d68, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 0, @@ -7137,13 +11130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [356] = { + [518] = { .class_hid = BNXT_ULP_CLASS_HID_444c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32836, .flow_pattern_id = 0, @@ -7154,14 +11147,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [357] = { + [519] = { .class_hid = BNXT_ULP_CLASS_HID_0e8c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -7172,13 +11165,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [358] = { + [520] = { .class_hid = BNXT_ULP_CLASS_HID_09e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -7189,14 +11182,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [359] = { + [521] = { .class_hid = BNXT_ULP_CLASS_HID_1af0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 0, @@ -7207,14 +11200,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [360] = { + [522] = { .class_hid = BNXT_ULP_CLASS_HID_15d4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49220, .flow_pattern_id = 0, @@ -7225,15 +11218,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [361] = { + [523] = { .class_hid = BNXT_ULP_CLASS_HID_1dd0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 0, @@ -7244,12 +11237,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [362] = { + [524] = { .class_hid = BNXT_ULP_CLASS_HID_14f4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131076, .flow_pattern_id = 0, @@ -7260,13 +11253,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [363] = { + [525] = { .class_hid = BNXT_ULP_CLASS_HID_70b0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 0, @@ -7277,13 +11270,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [364] = { + [526] = { .class_hid = BNXT_ULP_CLASS_HID_4854, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131140, .flow_pattern_id = 0, @@ -7294,14 +11287,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [365] = { + [527] = { .class_hid = BNXT_ULP_CLASS_HID_3dd4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 0, @@ -7312,13 +11305,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [366] = { + [528] = { .class_hid = BNXT_ULP_CLASS_HID_34f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196612, .flow_pattern_id = 0, @@ -7329,14 +11322,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [367] = { + [529] = { .class_hid = BNXT_ULP_CLASS_HID_09e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 0, @@ -7347,14 +11340,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [368] = { + [530] = { .class_hid = BNXT_ULP_CLASS_HID_008c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196676, .flow_pattern_id = 0, @@ -7365,15 +11358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [369] = { + [531] = { .class_hid = BNXT_ULP_CLASS_HID_34e6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 0, @@ -7384,12 +11377,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [370] = { + [532] = { .class_hid = BNXT_ULP_CLASS_HID_0c02, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4100, .flow_pattern_id = 0, @@ -7400,13 +11393,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [371] = { + [533] = { .class_hid = BNXT_ULP_CLASS_HID_1c9e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 0, @@ -7417,13 +11410,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [372] = { + [534] = { .class_hid = BNXT_ULP_CLASS_HID_17ba, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 6148, .flow_pattern_id = 0, @@ -7434,14 +11427,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [373] = { + [535] = { .class_hid = BNXT_ULP_CLASS_HID_429e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 0, @@ -7452,13 +11445,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [374] = { + [536] = { .class_hid = BNXT_ULP_CLASS_HID_5dba, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 12292, .flow_pattern_id = 0, @@ -7469,14 +11462,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [375] = { + [537] = { .class_hid = BNXT_ULP_CLASS_HID_2a16, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 0, @@ -7487,14 +11480,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [376] = { + [538] = { .class_hid = BNXT_ULP_CLASS_HID_2532, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 14340, .flow_pattern_id = 0, @@ -7505,15 +11498,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [377] = { + [539] = { .class_hid = BNXT_ULP_CLASS_HID_2da2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 0, @@ -7524,13 +11517,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [378] = { + [540] = { .class_hid = BNXT_ULP_CLASS_HID_24fe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 20484, .flow_pattern_id = 0, @@ -7541,14 +11534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [379] = { + [541] = { .class_hid = BNXT_ULP_CLASS_HID_355a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 0, @@ -7559,14 +11552,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [380] = { + [542] = { .class_hid = BNXT_ULP_CLASS_HID_0c76, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 22532, .flow_pattern_id = 0, @@ -7577,15 +11570,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [381] = { + [543] = { .class_hid = BNXT_ULP_CLASS_HID_13e6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 0, @@ -7596,14 +11589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [382] = { + [544] = { .class_hid = BNXT_ULP_CLASS_HID_7276, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 28676, .flow_pattern_id = 0, @@ -7614,15 +11607,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [383] = { + [545] = { .class_hid = BNXT_ULP_CLASS_HID_42d2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 0, @@ -7633,15 +11626,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [384] = { + [546] = { .class_hid = BNXT_ULP_CLASS_HID_5dee, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 30724, .flow_pattern_id = 0, @@ -7652,16 +11645,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [385] = { + [547] = { .class_hid = BNXT_ULP_CLASS_HID_59de, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 0, @@ -7672,12 +11665,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [386] = { + [548] = { .class_hid = BNXT_ULP_CLASS_HID_513a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 16388, .flow_pattern_id = 0, @@ -7688,13 +11681,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [387] = { + [549] = { .class_hid = BNXT_ULP_CLASS_HID_1c12, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 0, @@ -7705,13 +11698,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [388] = { + [550] = { .class_hid = BNXT_ULP_CLASS_HID_177e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 24580, .flow_pattern_id = 0, @@ -7722,14 +11715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [389] = { + [551] = { .class_hid = BNXT_ULP_CLASS_HID_0e92, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -7740,13 +11733,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [390] = { + [552] = { .class_hid = BNXT_ULP_CLASS_HID_09fe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -7757,14 +11750,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [391] = { + [553] = { .class_hid = BNXT_ULP_CLASS_HID_5c1a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 0, @@ -7775,14 +11768,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [392] = { + [554] = { .class_hid = BNXT_ULP_CLASS_HID_5746, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 57348, .flow_pattern_id = 0, @@ -7793,15 +11786,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [393] = { + [555] = { .class_hid = BNXT_ULP_CLASS_HID_79da, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 0, @@ -7812,13 +11805,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [394] = { + [556] = { .class_hid = BNXT_ULP_CLASS_HID_7106, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 81924, .flow_pattern_id = 0, @@ -7829,14 +11822,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [395] = { + [557] = { .class_hid = BNXT_ULP_CLASS_HID_3c1e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 0, @@ -7847,14 +11840,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [396] = { + [558] = { .class_hid = BNXT_ULP_CLASS_HID_377a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 90116, .flow_pattern_id = 0, @@ -7865,15 +11858,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [397] = { + [559] = { .class_hid = BNXT_ULP_CLASS_HID_2e9e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -7884,14 +11877,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [398] = { + [560] = { .class_hid = BNXT_ULP_CLASS_HID_29fa, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -7902,15 +11895,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [399] = { + [561] = { .class_hid = BNXT_ULP_CLASS_HID_14d2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 0, @@ -7921,15 +11914,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [400] = { + [562] = { .class_hid = BNXT_ULP_CLASS_HID_7742, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 122884, .flow_pattern_id = 0, @@ -7940,16 +11933,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [401] = { + [563] = { .class_hid = BNXT_ULP_CLASS_HID_3706, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 0, @@ -7960,12 +11953,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [402] = { + [564] = { .class_hid = BNXT_ULP_CLASS_HID_0fe2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4100, .flow_pattern_id = 0, @@ -7976,13 +11969,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [403] = { + [565] = { .class_hid = BNXT_ULP_CLASS_HID_1f7e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 0, @@ -7993,13 +11986,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [404] = { + [566] = { .class_hid = BNXT_ULP_CLASS_HID_145a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 6148, .flow_pattern_id = 0, @@ -8010,14 +12003,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [405] = { + [567] = { .class_hid = BNXT_ULP_CLASS_HID_417e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 0, @@ -8028,13 +12021,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [406] = { + [568] = { .class_hid = BNXT_ULP_CLASS_HID_5e5a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 12292, .flow_pattern_id = 0, @@ -8045,14 +12038,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [407] = { + [569] = { .class_hid = BNXT_ULP_CLASS_HID_29f6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 0, @@ -8063,14 +12056,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [408] = { + [570] = { .class_hid = BNXT_ULP_CLASS_HID_26d2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 14340, .flow_pattern_id = 0, @@ -8081,15 +12074,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [409] = { + [571] = { .class_hid = BNXT_ULP_CLASS_HID_2e42, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 0, @@ -8100,13 +12093,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [410] = { + [572] = { .class_hid = BNXT_ULP_CLASS_HID_271e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 20484, .flow_pattern_id = 0, @@ -8117,14 +12110,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [411] = { + [573] = { .class_hid = BNXT_ULP_CLASS_HID_36ba, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 0, @@ -8135,14 +12128,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [412] = { + [574] = { .class_hid = BNXT_ULP_CLASS_HID_0f96, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 22532, .flow_pattern_id = 0, @@ -8153,15 +12146,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [413] = { + [575] = { .class_hid = BNXT_ULP_CLASS_HID_1006, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 0, @@ -8172,14 +12165,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [414] = { + [576] = { .class_hid = BNXT_ULP_CLASS_HID_7196, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 28676, .flow_pattern_id = 0, @@ -8190,15 +12183,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [415] = { + [577] = { .class_hid = BNXT_ULP_CLASS_HID_4132, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 0, @@ -8209,15 +12202,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [416] = { + [578] = { .class_hid = BNXT_ULP_CLASS_HID_5e0e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 30724, .flow_pattern_id = 0, @@ -8228,16 +12221,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [417] = { + [579] = { .class_hid = BNXT_ULP_CLASS_HID_59fe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 0, @@ -8248,12 +12241,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [418] = { + [580] = { .class_hid = BNXT_ULP_CLASS_HID_511a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 16388, .flow_pattern_id = 0, @@ -8264,13 +12257,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [419] = { + [581] = { .class_hid = BNXT_ULP_CLASS_HID_1c32, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 0, @@ -8281,13 +12274,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [420] = { + [582] = { .class_hid = BNXT_ULP_CLASS_HID_175e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 24580, .flow_pattern_id = 0, @@ -8298,14 +12291,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [421] = { + [583] = { .class_hid = BNXT_ULP_CLASS_HID_0eb2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -8316,13 +12309,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [422] = { + [584] = { .class_hid = BNXT_ULP_CLASS_HID_09de, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -8333,14 +12326,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [423] = { + [585] = { .class_hid = BNXT_ULP_CLASS_HID_5c3a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 0, @@ -8351,14 +12344,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [424] = { + [586] = { .class_hid = BNXT_ULP_CLASS_HID_5766, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 57348, .flow_pattern_id = 0, @@ -8369,15 +12362,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [425] = { + [587] = { .class_hid = BNXT_ULP_CLASS_HID_79fa, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 0, @@ -8388,13 +12381,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [426] = { + [588] = { .class_hid = BNXT_ULP_CLASS_HID_7126, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 81924, .flow_pattern_id = 0, @@ -8405,14 +12398,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [427] = { + [589] = { .class_hid = BNXT_ULP_CLASS_HID_3c3e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 0, @@ -8423,14 +12416,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [428] = { + [590] = { .class_hid = BNXT_ULP_CLASS_HID_375a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 90116, .flow_pattern_id = 0, @@ -8441,15 +12434,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [429] = { + [591] = { .class_hid = BNXT_ULP_CLASS_HID_2ebe, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -8460,14 +12453,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [430] = { + [592] = { .class_hid = BNXT_ULP_CLASS_HID_29da, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -8478,15 +12471,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [431] = { + [593] = { .class_hid = BNXT_ULP_CLASS_HID_14f2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 0, @@ -8497,15 +12490,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [432] = { + [594] = { .class_hid = BNXT_ULP_CLASS_HID_7762, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 122884, .flow_pattern_id = 0, @@ -8516,16 +12509,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [433] = { + [595] = { .class_hid = BNXT_ULP_CLASS_HID_19e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 0, @@ -8537,12 +12530,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [434] = { + [596] = { .class_hid = BNXT_ULP_CLASS_HID_110c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32772, .flow_pattern_id = 0, @@ -8554,13 +12547,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [435] = { + [597] = { .class_hid = BNXT_ULP_CLASS_HID_4d48, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 0, @@ -8572,13 +12565,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [436] = { + [598] = { .class_hid = BNXT_ULP_CLASS_HID_446c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32836, .flow_pattern_id = 0, @@ -8590,14 +12583,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [437] = { + [599] = { .class_hid = BNXT_ULP_CLASS_HID_0eac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -8609,13 +12602,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [438] = { + [600] = { .class_hid = BNXT_ULP_CLASS_HID_09c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -8627,14 +12620,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [439] = { + [601] = { .class_hid = BNXT_ULP_CLASS_HID_1ad0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 0, @@ -8646,14 +12639,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [440] = { + [602] = { .class_hid = BNXT_ULP_CLASS_HID_15f4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49220, .flow_pattern_id = 0, @@ -8665,15 +12658,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [441] = { + [603] = { .class_hid = BNXT_ULP_CLASS_HID_39ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 0, @@ -8685,13 +12678,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [442] = { + [604] = { .class_hid = BNXT_ULP_CLASS_HID_3100, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98308, .flow_pattern_id = 0, @@ -8703,14 +12696,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [443] = { + [605] = { .class_hid = BNXT_ULP_CLASS_HID_0210, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 0, @@ -8722,14 +12715,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [444] = { + [606] = { .class_hid = BNXT_ULP_CLASS_HID_1d34, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98372, .flow_pattern_id = 0, @@ -8741,15 +12734,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [445] = { + [607] = { .class_hid = BNXT_ULP_CLASS_HID_2ea0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -8761,14 +12754,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [446] = { + [608] = { .class_hid = BNXT_ULP_CLASS_HID_29c4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -8780,15 +12773,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [447] = { + [609] = { .class_hid = BNXT_ULP_CLASS_HID_3ad4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 0, @@ -8800,15 +12793,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [448] = { + [610] = { .class_hid = BNXT_ULP_CLASS_HID_35e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114756, .flow_pattern_id = 0, @@ -8820,16 +12813,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [449] = { + [611] = { .class_hid = BNXT_ULP_CLASS_HID_5d80, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 0, @@ -8841,13 +12834,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [450] = { + [612] = { .class_hid = BNXT_ULP_CLASS_HID_54a4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163844, .flow_pattern_id = 0, @@ -8859,14 +12852,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [451] = { + [613] = { .class_hid = BNXT_ULP_CLASS_HID_29b4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 0, @@ -8878,14 +12871,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [452] = { + [614] = { .class_hid = BNXT_ULP_CLASS_HID_20c8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163908, .flow_pattern_id = 0, @@ -8897,15 +12890,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [453] = { + [615] = { .class_hid = BNXT_ULP_CLASS_HID_7244, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 0, @@ -8917,14 +12910,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [454] = { + [616] = { .class_hid = BNXT_ULP_CLASS_HID_4d98, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180228, .flow_pattern_id = 0, @@ -8936,15 +12929,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [455] = { + [617] = { .class_hid = BNXT_ULP_CLASS_HID_5e68, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 0, @@ -8956,15 +12949,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [456] = { + [618] = { .class_hid = BNXT_ULP_CLASS_HID_598c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180292, .flow_pattern_id = 0, @@ -8976,16 +12969,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [457] = { + [619] = { .class_hid = BNXT_ULP_CLASS_HID_1248, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 0, @@ -8997,14 +12990,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [458] = { + [620] = { .class_hid = BNXT_ULP_CLASS_HID_74d8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229380, .flow_pattern_id = 0, @@ -9016,15 +13009,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [459] = { + [621] = { .class_hid = BNXT_ULP_CLASS_HID_49a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 0, @@ -9036,15 +13029,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [460] = { + [622] = { .class_hid = BNXT_ULP_CLASS_HID_40cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229444, .flow_pattern_id = 0, @@ -9056,16 +13049,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [461] = { + [623] = { .class_hid = BNXT_ULP_CLASS_HID_0b0c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 0, @@ -9077,15 +13070,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [462] = { + [624] = { .class_hid = BNXT_ULP_CLASS_HID_0220, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245764, .flow_pattern_id = 0, @@ -9097,16 +13090,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [463] = { + [625] = { .class_hid = BNXT_ULP_CLASS_HID_1730, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 0, @@ -9118,16 +13111,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [464] = { + [626] = { .class_hid = BNXT_ULP_CLASS_HID_7980, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245828, .flow_pattern_id = 0, @@ -9139,17 +13132,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [465] = { + [627] = { .class_hid = BNXT_ULP_CLASS_HID_1db0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 0, @@ -9161,12 +13154,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [466] = { + [628] = { .class_hid = BNXT_ULP_CLASS_HID_1494, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131076, .flow_pattern_id = 0, @@ -9178,13 +13171,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [467] = { + [629] = { .class_hid = BNXT_ULP_CLASS_HID_70d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 0, @@ -9196,13 +13189,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [468] = { + [630] = { .class_hid = BNXT_ULP_CLASS_HID_4834, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131140, .flow_pattern_id = 0, @@ -9214,14 +13207,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [469] = { + [631] = { .class_hid = BNXT_ULP_CLASS_HID_3db4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 0, @@ -9233,13 +13226,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [470] = { + [632] = { .class_hid = BNXT_ULP_CLASS_HID_3498, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196612, .flow_pattern_id = 0, @@ -9251,14 +13244,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [471] = { + [633] = { .class_hid = BNXT_ULP_CLASS_HID_0988, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 0, @@ -9270,14 +13263,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [472] = { + [634] = { .class_hid = BNXT_ULP_CLASS_HID_00ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196676, .flow_pattern_id = 0, @@ -9289,15 +13282,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [473] = { + [635] = { .class_hid = BNXT_ULP_CLASS_HID_3f44, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 0, @@ -9309,13 +13302,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [474] = { + [636] = { .class_hid = BNXT_ULP_CLASS_HID_36a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393220, .flow_pattern_id = 0, @@ -9327,14 +13320,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [475] = { + [637] = { .class_hid = BNXT_ULP_CLASS_HID_0b58, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 0, @@ -9346,14 +13339,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [476] = { + [638] = { .class_hid = BNXT_ULP_CLASS_HID_02bc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393284, .flow_pattern_id = 0, @@ -9365,15 +13358,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [477] = { + [639] = { .class_hid = BNXT_ULP_CLASS_HID_5f48, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 0, @@ -9385,14 +13378,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [478] = { + [640] = { .class_hid = BNXT_ULP_CLASS_HID_56ac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458756, .flow_pattern_id = 0, @@ -9404,15 +13397,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [479] = { + [641] = { .class_hid = BNXT_ULP_CLASS_HID_2b5c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 0, @@ -9424,15 +13417,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [480] = { + [642] = { .class_hid = BNXT_ULP_CLASS_HID_2280, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458820, .flow_pattern_id = 0, @@ -9444,16 +13437,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [481] = { + [643] = { .class_hid = BNXT_ULP_CLASS_HID_4000, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 0, @@ -9465,13 +13458,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [482] = { + [644] = { .class_hid = BNXT_ULP_CLASS_HID_5b64, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655364, .flow_pattern_id = 0, @@ -9483,14 +13476,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [483] = { + [645] = { .class_hid = BNXT_ULP_CLASS_HID_2c14, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 0, @@ -9502,14 +13495,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [484] = { + [646] = { .class_hid = BNXT_ULP_CLASS_HID_2778, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655428, .flow_pattern_id = 0, @@ -9521,15 +13514,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [485] = { + [647] = { .class_hid = BNXT_ULP_CLASS_HID_18f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 0, @@ -9541,14 +13534,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [486] = { + [648] = { .class_hid = BNXT_ULP_CLASS_HID_13dc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720900, .flow_pattern_id = 0, @@ -9560,15 +13553,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [487] = { + [649] = { .class_hid = BNXT_ULP_CLASS_HID_4c18, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 0, @@ -9580,15 +13573,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [488] = { + [650] = { .class_hid = BNXT_ULP_CLASS_HID_477c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720964, .flow_pattern_id = 0, @@ -9600,16 +13593,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [489] = { + [651] = { .class_hid = BNXT_ULP_CLASS_HID_1a88, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 0, @@ -9621,14 +13614,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [490] = { + [652] = { .class_hid = BNXT_ULP_CLASS_HID_15ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917508, .flow_pattern_id = 0, @@ -9640,15 +13633,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [491] = { + [653] = { .class_hid = BNXT_ULP_CLASS_HID_4e28, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 0, @@ -9660,15 +13653,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [492] = { + [654] = { .class_hid = BNXT_ULP_CLASS_HID_490c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917572, .flow_pattern_id = 0, @@ -9680,16 +13673,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [493] = { + [655] = { .class_hid = BNXT_ULP_CLASS_HID_3a8c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 0, @@ -9701,15 +13694,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [494] = { + [656] = { .class_hid = BNXT_ULP_CLASS_HID_35f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983044, .flow_pattern_id = 0, @@ -9721,16 +13714,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [495] = { + [657] = { .class_hid = BNXT_ULP_CLASS_HID_06e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 0, @@ -9742,16 +13735,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [496] = { + [658] = { .class_hid = BNXT_ULP_CLASS_HID_01c4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983108, .flow_pattern_id = 0, @@ -9763,17 +13756,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [497] = { + [659] = { .class_hid = BNXT_ULP_CLASS_HID_1a08, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 0, @@ -9785,12 +13778,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [498] = { + [660] = { .class_hid = BNXT_ULP_CLASS_HID_12ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32772, .flow_pattern_id = 0, @@ -9802,13 +13795,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [499] = { + [661] = { .class_hid = BNXT_ULP_CLASS_HID_4ea8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 0, @@ -9820,13 +13813,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [500] = { + [662] = { .class_hid = BNXT_ULP_CLASS_HID_478c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32836, .flow_pattern_id = 0, @@ -9838,14 +13831,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [501] = { + [663] = { .class_hid = BNXT_ULP_CLASS_HID_0d4c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 0, @@ -9857,13 +13850,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [502] = { + [664] = { .class_hid = BNXT_ULP_CLASS_HID_0a20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49156, .flow_pattern_id = 0, @@ -9875,14 +13868,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [503] = { + [665] = { .class_hid = BNXT_ULP_CLASS_HID_1930, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 0, @@ -9894,14 +13887,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [504] = { + [666] = { .class_hid = BNXT_ULP_CLASS_HID_1614, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49220, .flow_pattern_id = 0, @@ -9913,15 +13906,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [505] = { + [667] = { .class_hid = BNXT_ULP_CLASS_HID_3a0c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 0, @@ -9933,13 +13926,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [506] = { + [668] = { .class_hid = BNXT_ULP_CLASS_HID_32e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98308, .flow_pattern_id = 0, @@ -9951,14 +13944,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [507] = { + [669] = { .class_hid = BNXT_ULP_CLASS_HID_01f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 0, @@ -9970,14 +13963,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [508] = { + [670] = { .class_hid = BNXT_ULP_CLASS_HID_1ed4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98372, .flow_pattern_id = 0, @@ -9989,15 +13982,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [509] = { + [671] = { .class_hid = BNXT_ULP_CLASS_HID_2d40, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 0, @@ -10009,14 +14002,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [510] = { + [672] = { .class_hid = BNXT_ULP_CLASS_HID_2a24, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114692, .flow_pattern_id = 0, @@ -10028,15 +14021,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [511] = { + [673] = { .class_hid = BNXT_ULP_CLASS_HID_3934, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 0, @@ -10048,15 +14041,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [512] = { + [674] = { .class_hid = BNXT_ULP_CLASS_HID_3608, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114756, .flow_pattern_id = 0, @@ -10068,16 +14061,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [513] = { + [675] = { .class_hid = BNXT_ULP_CLASS_HID_5e60, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 0, @@ -10089,13 +14082,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [514] = { + [676] = { .class_hid = BNXT_ULP_CLASS_HID_5744, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163844, .flow_pattern_id = 0, @@ -10107,14 +14100,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [515] = { + [677] = { .class_hid = BNXT_ULP_CLASS_HID_2a54, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 0, @@ -10126,14 +14119,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [516] = { + [678] = { .class_hid = BNXT_ULP_CLASS_HID_2328, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163908, .flow_pattern_id = 0, @@ -10145,15 +14138,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [517] = { + [679] = { .class_hid = BNXT_ULP_CLASS_HID_71a4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 0, @@ -10165,14 +14158,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [518] = { + [680] = { .class_hid = BNXT_ULP_CLASS_HID_4e78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180228, .flow_pattern_id = 0, @@ -10184,15 +14177,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [519] = { + [681] = { .class_hid = BNXT_ULP_CLASS_HID_5d88, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 0, @@ -10204,15 +14197,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [520] = { + [682] = { .class_hid = BNXT_ULP_CLASS_HID_5a6c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180292, .flow_pattern_id = 0, @@ -10224,16 +14217,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [521] = { + [683] = { .class_hid = BNXT_ULP_CLASS_HID_11a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 0, @@ -10245,14 +14238,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [522] = { + [684] = { .class_hid = BNXT_ULP_CLASS_HID_7738, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229380, .flow_pattern_id = 0, @@ -10264,15 +14257,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [523] = { + [685] = { .class_hid = BNXT_ULP_CLASS_HID_4a48, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 0, @@ -10284,15 +14277,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [524] = { + [686] = { .class_hid = BNXT_ULP_CLASS_HID_432c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229444, .flow_pattern_id = 0, @@ -10304,16 +14297,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [525] = { + [687] = { .class_hid = BNXT_ULP_CLASS_HID_08ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 0, @@ -10325,15 +14318,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [526] = { + [688] = { .class_hid = BNXT_ULP_CLASS_HID_01c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245764, .flow_pattern_id = 0, @@ -10345,16 +14338,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [527] = { + [689] = { .class_hid = BNXT_ULP_CLASS_HID_14d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 0, @@ -10366,16 +14359,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [528] = { + [690] = { .class_hid = BNXT_ULP_CLASS_HID_7a60, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245828, .flow_pattern_id = 0, @@ -10387,17 +14380,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [529] = { + [691] = { .class_hid = BNXT_ULP_CLASS_HID_1d90, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 0, @@ -10409,12 +14402,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [530] = { + [692] = { .class_hid = BNXT_ULP_CLASS_HID_14b4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131076, .flow_pattern_id = 0, @@ -10426,13 +14419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [531] = { + [693] = { .class_hid = BNXT_ULP_CLASS_HID_70f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 0, @@ -10444,13 +14437,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [532] = { + [694] = { .class_hid = BNXT_ULP_CLASS_HID_4814, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131140, .flow_pattern_id = 0, @@ -10462,14 +14455,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [533] = { + [695] = { .class_hid = BNXT_ULP_CLASS_HID_3d94, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 0, @@ -10481,13 +14474,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [534] = { + [696] = { .class_hid = BNXT_ULP_CLASS_HID_34b8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196612, .flow_pattern_id = 0, @@ -10499,14 +14492,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [535] = { + [697] = { .class_hid = BNXT_ULP_CLASS_HID_09a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 0, @@ -10518,14 +14511,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [536] = { + [698] = { .class_hid = BNXT_ULP_CLASS_HID_00cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196676, .flow_pattern_id = 0, @@ -10537,15 +14530,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [537] = { + [699] = { .class_hid = BNXT_ULP_CLASS_HID_3f64, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 0, @@ -10557,13 +14550,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [538] = { + [700] = { .class_hid = BNXT_ULP_CLASS_HID_3688, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393220, .flow_pattern_id = 0, @@ -10575,14 +14568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [539] = { + [701] = { .class_hid = BNXT_ULP_CLASS_HID_0b78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 0, @@ -10594,14 +14587,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [540] = { + [702] = { .class_hid = BNXT_ULP_CLASS_HID_029c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393284, .flow_pattern_id = 0, @@ -10613,15 +14606,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [541] = { + [703] = { .class_hid = BNXT_ULP_CLASS_HID_5f68, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 0, @@ -10633,14 +14626,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [542] = { + [704] = { .class_hid = BNXT_ULP_CLASS_HID_568c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458756, .flow_pattern_id = 0, @@ -10652,15 +14645,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [543] = { + [705] = { .class_hid = BNXT_ULP_CLASS_HID_2b7c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 0, @@ -10672,15 +14665,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [544] = { + [706] = { .class_hid = BNXT_ULP_CLASS_HID_22a0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458820, .flow_pattern_id = 0, @@ -10692,16 +14685,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [545] = { + [707] = { .class_hid = BNXT_ULP_CLASS_HID_4020, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 0, @@ -10713,13 +14706,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [546] = { + [708] = { .class_hid = BNXT_ULP_CLASS_HID_5b44, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655364, .flow_pattern_id = 0, @@ -10731,14 +14724,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [547] = { + [709] = { .class_hid = BNXT_ULP_CLASS_HID_2c34, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 0, @@ -10750,14 +14743,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [548] = { + [710] = { .class_hid = BNXT_ULP_CLASS_HID_2758, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655428, .flow_pattern_id = 0, @@ -10769,15 +14762,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [549] = { + [711] = { .class_hid = BNXT_ULP_CLASS_HID_18d8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 0, @@ -10789,14 +14782,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [550] = { + [712] = { .class_hid = BNXT_ULP_CLASS_HID_13fc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720900, .flow_pattern_id = 0, @@ -10808,15 +14801,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [551] = { + [713] = { .class_hid = BNXT_ULP_CLASS_HID_4c38, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 0, @@ -10828,15 +14821,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [552] = { + [714] = { .class_hid = BNXT_ULP_CLASS_HID_475c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720964, .flow_pattern_id = 0, @@ -10848,16 +14841,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [553] = { + [715] = { .class_hid = BNXT_ULP_CLASS_HID_1aa8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 0, @@ -10869,14 +14862,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [554] = { + [716] = { .class_hid = BNXT_ULP_CLASS_HID_15cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917508, .flow_pattern_id = 0, @@ -10888,15 +14881,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [555] = { + [717] = { .class_hid = BNXT_ULP_CLASS_HID_4e08, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 0, @@ -10908,15 +14901,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [556] = { + [718] = { .class_hid = BNXT_ULP_CLASS_HID_492c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917572, .flow_pattern_id = 0, @@ -10928,16 +14921,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [557] = { + [719] = { .class_hid = BNXT_ULP_CLASS_HID_3aac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 0, @@ -10949,15 +14942,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [558] = { + [720] = { .class_hid = BNXT_ULP_CLASS_HID_35d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983044, .flow_pattern_id = 0, @@ -10969,16 +14962,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [559] = { + [721] = { .class_hid = BNXT_ULP_CLASS_HID_06c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 0, @@ -10990,16 +14983,16 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [560] = { + [722] = { .class_hid = BNXT_ULP_CLASS_HID_01e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983108, .flow_pattern_id = 0, @@ -11011,17 +15004,17 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [561] = { + [723] = { .class_hid = BNXT_ULP_CLASS_HID_4d32, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4096, .flow_pattern_id = 1, @@ -11031,11 +15024,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [562] = { + [724] = { .class_hid = BNXT_ULP_CLASS_HID_54aa, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 6144, .flow_pattern_id = 1, @@ -11045,12 +15038,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR } }, - [563] = { + [725] = { .class_hid = BNXT_ULP_CLASS_HID_0686, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 16384, .flow_pattern_id = 1, @@ -11060,11 +15053,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [564] = { + [726] = { .class_hid = BNXT_ULP_CLASS_HID_540e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 24576, .flow_pattern_id = 1, @@ -11074,12 +15067,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR } }, - [565] = { + [727] = { .class_hid = BNXT_ULP_CLASS_HID_2e3c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32768, .flow_pattern_id = 1, @@ -11090,11 +15083,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [566] = { + [728] = { .class_hid = BNXT_ULP_CLASS_HID_3a20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 32832, .flow_pattern_id = 1, @@ -11105,12 +15098,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [567] = { + [729] = { .class_hid = BNXT_ULP_CLASS_HID_46f0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11121,12 +15114,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [568] = { + [730] = { .class_hid = BNXT_ULP_CLASS_HID_52e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 49216, .flow_pattern_id = 1, @@ -11137,13 +15130,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR } }, - [569] = { + [731] = { .class_hid = BNXT_ULP_CLASS_HID_55e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131072, .flow_pattern_id = 1, @@ -11154,11 +15147,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [570] = { + [732] = { .class_hid = BNXT_ULP_CLASS_HID_21f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 131136, .flow_pattern_id = 1, @@ -11169,12 +15162,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [571] = { + [733] = { .class_hid = BNXT_ULP_CLASS_HID_75e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196608, .flow_pattern_id = 1, @@ -11185,12 +15178,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [572] = { + [734] = { .class_hid = BNXT_ULP_CLASS_HID_41fc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 196672, .flow_pattern_id = 1, @@ -11201,13 +15194,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR } }, - [573] = { + [735] = { .class_hid = BNXT_ULP_CLASS_HID_4d12, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4096, .flow_pattern_id = 1, @@ -11218,11 +15211,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [574] = { + [736] = { .class_hid = BNXT_ULP_CLASS_HID_548a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 6144, .flow_pattern_id = 1, @@ -11233,12 +15226,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR } }, - [575] = { + [737] = { .class_hid = BNXT_ULP_CLASS_HID_3356, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 12288, .flow_pattern_id = 1, @@ -11249,12 +15242,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [576] = { + [738] = { .class_hid = BNXT_ULP_CLASS_HID_1ace, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 14336, .flow_pattern_id = 1, @@ -11265,13 +15258,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT } }, - [577] = { + [739] = { .class_hid = BNXT_ULP_CLASS_HID_1a9a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 20480, .flow_pattern_id = 1, @@ -11282,12 +15275,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [578] = { + [740] = { .class_hid = BNXT_ULP_CLASS_HID_4d46, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 22528, .flow_pattern_id = 1, @@ -11298,13 +15291,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [579] = { + [741] = { .class_hid = BNXT_ULP_CLASS_HID_2812, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 28672, .flow_pattern_id = 1, @@ -11315,13 +15308,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [580] = { + [742] = { .class_hid = BNXT_ULP_CLASS_HID_338a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 30720, .flow_pattern_id = 1, @@ -11332,14 +15325,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT } }, - [581] = { + [743] = { .class_hid = BNXT_ULP_CLASS_HID_06e6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 16384, .flow_pattern_id = 1, @@ -11350,11 +15343,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [582] = { + [744] = { .class_hid = BNXT_ULP_CLASS_HID_546e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 24576, .flow_pattern_id = 1, @@ -11365,12 +15358,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR } }, - [583] = { + [745] = { .class_hid = BNXT_ULP_CLASS_HID_46ee, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11381,12 +15374,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [584] = { + [746] = { .class_hid = BNXT_ULP_CLASS_HID_0d22, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 57344, .flow_pattern_id = 1, @@ -11397,13 +15390,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT } }, - [585] = { + [747] = { .class_hid = BNXT_ULP_CLASS_HID_26e2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 81920, .flow_pattern_id = 1, @@ -11414,12 +15407,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [586] = { + [748] = { .class_hid = BNXT_ULP_CLASS_HID_746a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 90112, .flow_pattern_id = 1, @@ -11430,13 +15423,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [587] = { + [749] = { .class_hid = BNXT_ULP_CLASS_HID_1fa6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -11447,13 +15440,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [588] = { + [750] = { .class_hid = BNXT_ULP_CLASS_HID_2d2e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 122880, .flow_pattern_id = 1, @@ -11464,14 +15457,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT } }, - [589] = { + [751] = { .class_hid = BNXT_ULP_CLASS_HID_4ef2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4096, .flow_pattern_id = 1, @@ -11482,11 +15475,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [590] = { + [752] = { .class_hid = BNXT_ULP_CLASS_HID_576a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 6144, .flow_pattern_id = 1, @@ -11497,12 +15490,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR } }, - [591] = { + [753] = { .class_hid = BNXT_ULP_CLASS_HID_30b6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 12288, .flow_pattern_id = 1, @@ -11513,12 +15506,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [592] = { + [754] = { .class_hid = BNXT_ULP_CLASS_HID_192e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 14336, .flow_pattern_id = 1, @@ -11529,13 +15522,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT } }, - [593] = { + [755] = { .class_hid = BNXT_ULP_CLASS_HID_197a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 20480, .flow_pattern_id = 1, @@ -11546,12 +15539,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [594] = { + [756] = { .class_hid = BNXT_ULP_CLASS_HID_4ea6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 22528, .flow_pattern_id = 1, @@ -11562,13 +15555,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [595] = { + [757] = { .class_hid = BNXT_ULP_CLASS_HID_2bf2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 28672, .flow_pattern_id = 1, @@ -11579,13 +15572,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [596] = { + [758] = { .class_hid = BNXT_ULP_CLASS_HID_306a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 30720, .flow_pattern_id = 1, @@ -11596,14 +15589,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT } }, - [597] = { + [759] = { .class_hid = BNXT_ULP_CLASS_HID_06c6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 16384, .flow_pattern_id = 1, @@ -11614,11 +15607,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [598] = { + [760] = { .class_hid = BNXT_ULP_CLASS_HID_544e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 24576, .flow_pattern_id = 1, @@ -11629,12 +15622,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR } }, - [599] = { + [761] = { .class_hid = BNXT_ULP_CLASS_HID_46ce, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11645,12 +15638,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [600] = { + [762] = { .class_hid = BNXT_ULP_CLASS_HID_0d02, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 57344, .flow_pattern_id = 1, @@ -11661,13 +15654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT } }, - [601] = { + [763] = { .class_hid = BNXT_ULP_CLASS_HID_26c2, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 81920, .flow_pattern_id = 1, @@ -11678,12 +15671,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [602] = { + [764] = { .class_hid = BNXT_ULP_CLASS_HID_744a, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 90112, .flow_pattern_id = 1, @@ -11694,13 +15687,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [603] = { + [765] = { .class_hid = BNXT_ULP_CLASS_HID_1f86, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -11711,13 +15704,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [604] = { + [766] = { .class_hid = BNXT_ULP_CLASS_HID_2d0e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 122880, .flow_pattern_id = 1, @@ -11728,14 +15721,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT } }, - [605] = { + [767] = { .class_hid = BNXT_ULP_CLASS_HID_2e1c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32768, .flow_pattern_id = 1, @@ -11747,11 +15740,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [606] = { + [768] = { .class_hid = BNXT_ULP_CLASS_HID_3a00, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 32832, .flow_pattern_id = 1, @@ -11763,12 +15756,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [607] = { + [769] = { .class_hid = BNXT_ULP_CLASS_HID_46d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -11780,12 +15773,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [608] = { + [770] = { .class_hid = BNXT_ULP_CLASS_HID_52c4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 49216, .flow_pattern_id = 1, @@ -11797,13 +15790,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR } }, - [609] = { + [771] = { .class_hid = BNXT_ULP_CLASS_HID_4e10, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98304, .flow_pattern_id = 1, @@ -11815,12 +15808,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [610] = { + [772] = { .class_hid = BNXT_ULP_CLASS_HID_5a04, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 98368, .flow_pattern_id = 1, @@ -11832,13 +15825,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [611] = { + [773] = { .class_hid = BNXT_ULP_CLASS_HID_1f98, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -11850,13 +15843,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [612] = { + [774] = { .class_hid = BNXT_ULP_CLASS_HID_72f8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 114752, .flow_pattern_id = 1, @@ -11868,14 +15861,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT } }, - [613] = { + [775] = { .class_hid = BNXT_ULP_CLASS_HID_0a78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163840, .flow_pattern_id = 1, @@ -11887,12 +15880,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [614] = { + [776] = { .class_hid = BNXT_ULP_CLASS_HID_166c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 163904, .flow_pattern_id = 1, @@ -11904,13 +15897,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [615] = { + [777] = { .class_hid = BNXT_ULP_CLASS_HID_233c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180224, .flow_pattern_id = 1, @@ -11922,13 +15915,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [616] = { + [778] = { .class_hid = BNXT_ULP_CLASS_HID_0f20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 180288, .flow_pattern_id = 1, @@ -11940,14 +15933,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [617] = { + [779] = { .class_hid = BNXT_ULP_CLASS_HID_2a7c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229376, .flow_pattern_id = 1, @@ -11959,13 +15952,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [618] = { + [780] = { .class_hid = BNXT_ULP_CLASS_HID_3660, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 229440, .flow_pattern_id = 1, @@ -11977,14 +15970,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [619] = { + [781] = { .class_hid = BNXT_ULP_CLASS_HID_4330, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245760, .flow_pattern_id = 1, @@ -11996,14 +15989,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [620] = { + [782] = { .class_hid = BNXT_ULP_CLASS_HID_2f24, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 245824, .flow_pattern_id = 1, @@ -12015,15 +16008,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT } }, - [621] = { + [783] = { .class_hid = BNXT_ULP_CLASS_HID_5584, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131072, .flow_pattern_id = 1, @@ -12035,11 +16028,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [622] = { + [784] = { .class_hid = BNXT_ULP_CLASS_HID_2198, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 131136, .flow_pattern_id = 1, @@ -12051,12 +16044,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [623] = { + [785] = { .class_hid = BNXT_ULP_CLASS_HID_7588, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196608, .flow_pattern_id = 1, @@ -12068,12 +16061,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [624] = { + [786] = { .class_hid = BNXT_ULP_CLASS_HID_419c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 196672, .flow_pattern_id = 1, @@ -12085,13 +16078,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR } }, - [625] = { + [787] = { .class_hid = BNXT_ULP_CLASS_HID_7758, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393216, .flow_pattern_id = 1, @@ -12103,12 +16096,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [626] = { + [788] = { .class_hid = BNXT_ULP_CLASS_HID_43ac, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 393280, .flow_pattern_id = 1, @@ -12120,13 +16113,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [627] = { + [789] = { .class_hid = BNXT_ULP_CLASS_HID_0c10, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458752, .flow_pattern_id = 1, @@ -12138,13 +16131,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [628] = { + [790] = { .class_hid = BNXT_ULP_CLASS_HID_1864, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 458816, .flow_pattern_id = 1, @@ -12156,14 +16149,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT } }, - [629] = { + [791] = { .class_hid = BNXT_ULP_CLASS_HID_30c8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655360, .flow_pattern_id = 1, @@ -12175,12 +16168,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [630] = { + [792] = { .class_hid = BNXT_ULP_CLASS_HID_1cdc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 655424, .flow_pattern_id = 1, @@ -12192,13 +16185,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [631] = { + [793] = { .class_hid = BNXT_ULP_CLASS_HID_50cc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720896, .flow_pattern_id = 1, @@ -12210,13 +16203,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [632] = { + [794] = { .class_hid = BNXT_ULP_CLASS_HID_3d20, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 720960, .flow_pattern_id = 1, @@ -12228,14 +16221,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [633] = { + [795] = { .class_hid = BNXT_ULP_CLASS_HID_529c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917504, .flow_pattern_id = 1, @@ -12247,13 +16240,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [634] = { + [796] = { .class_hid = BNXT_ULP_CLASS_HID_3ef0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 917568, .flow_pattern_id = 1, @@ -12265,14 +16258,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [635] = { + [797] = { .class_hid = BNXT_ULP_CLASS_HID_72e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983040, .flow_pattern_id = 1, @@ -12284,14 +16277,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [636] = { + [798] = { .class_hid = BNXT_ULP_CLASS_HID_5ef4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 983104, .flow_pattern_id = 1, @@ -12303,15 +16296,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT | - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT } + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT } }, - [637] = { + [799] = { .class_hid = BNXT_ULP_CLASS_HID_2dfc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32768, .flow_pattern_id = 1, @@ -12323,11 +16316,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [638] = { + [800] = { .class_hid = BNXT_ULP_CLASS_HID_39e0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 32832, .flow_pattern_id = 1, @@ -12339,12 +16332,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [639] = { + [801] = { .class_hid = BNXT_ULP_CLASS_HID_4530, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49152, .flow_pattern_id = 1, @@ -12356,12 +16349,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [640] = { + [802] = { .class_hid = BNXT_ULP_CLASS_HID_5124, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 49216, .flow_pattern_id = 1, @@ -12373,13 +16366,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR } }, - [641] = { + [803] = { .class_hid = BNXT_ULP_CLASS_HID_4df0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98304, .flow_pattern_id = 1, @@ -12391,12 +16384,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [642] = { + [804] = { .class_hid = BNXT_ULP_CLASS_HID_59e4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 98368, .flow_pattern_id = 1, @@ -12408,13 +16401,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [643] = { + [805] = { .class_hid = BNXT_ULP_CLASS_HID_1c78, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114688, .flow_pattern_id = 1, @@ -12426,13 +16419,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [644] = { + [806] = { .class_hid = BNXT_ULP_CLASS_HID_7118, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 114752, .flow_pattern_id = 1, @@ -12444,14 +16437,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT } }, - [645] = { + [807] = { .class_hid = BNXT_ULP_CLASS_HID_0998, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163840, .flow_pattern_id = 1, @@ -12463,12 +16456,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [646] = { + [808] = { .class_hid = BNXT_ULP_CLASS_HID_158c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 163904, .flow_pattern_id = 1, @@ -12480,13 +16473,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [647] = { + [809] = { .class_hid = BNXT_ULP_CLASS_HID_20dc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180224, .flow_pattern_id = 1, @@ -12498,13 +16491,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [648] = { + [810] = { .class_hid = BNXT_ULP_CLASS_HID_0cc0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 180288, .flow_pattern_id = 1, @@ -12516,14 +16509,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [649] = { + [811] = { .class_hid = BNXT_ULP_CLASS_HID_299c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229376, .flow_pattern_id = 1, @@ -12535,13 +16528,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [650] = { + [812] = { .class_hid = BNXT_ULP_CLASS_HID_3580, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 229440, .flow_pattern_id = 1, @@ -12553,14 +16546,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [651] = { + [813] = { .class_hid = BNXT_ULP_CLASS_HID_40d0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245760, .flow_pattern_id = 1, @@ -12572,14 +16565,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [652] = { + [814] = { .class_hid = BNXT_ULP_CLASS_HID_2cc4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 245824, .flow_pattern_id = 1, @@ -12591,15 +16584,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT } }, - [653] = { + [815] = { .class_hid = BNXT_ULP_CLASS_HID_55a4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131072, .flow_pattern_id = 1, @@ -12611,11 +16604,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [654] = { + [816] = { .class_hid = BNXT_ULP_CLASS_HID_21b8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 131136, .flow_pattern_id = 1, @@ -12627,12 +16620,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [655] = { + [817] = { .class_hid = BNXT_ULP_CLASS_HID_75a8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196608, .flow_pattern_id = 1, @@ -12644,12 +16637,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [656] = { + [818] = { .class_hid = BNXT_ULP_CLASS_HID_41bc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 196672, .flow_pattern_id = 1, @@ -12661,13 +16654,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR } }, - [657] = { + [819] = { .class_hid = BNXT_ULP_CLASS_HID_7778, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393216, .flow_pattern_id = 1, @@ -12679,12 +16672,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [658] = { + [820] = { .class_hid = BNXT_ULP_CLASS_HID_438c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 393280, .flow_pattern_id = 1, @@ -12696,13 +16689,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [659] = { + [821] = { .class_hid = BNXT_ULP_CLASS_HID_0c30, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458752, .flow_pattern_id = 1, @@ -12714,13 +16707,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [660] = { + [822] = { .class_hid = BNXT_ULP_CLASS_HID_1844, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 458816, .flow_pattern_id = 1, @@ -12732,14 +16725,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT } }, - [661] = { + [823] = { .class_hid = BNXT_ULP_CLASS_HID_30e8, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655360, .flow_pattern_id = 1, @@ -12751,12 +16744,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [662] = { + [824] = { .class_hid = BNXT_ULP_CLASS_HID_1cfc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 655424, .flow_pattern_id = 1, @@ -12768,13 +16761,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [663] = { + [825] = { .class_hid = BNXT_ULP_CLASS_HID_50ec, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720896, .flow_pattern_id = 1, @@ -12786,13 +16779,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [664] = { + [826] = { .class_hid = BNXT_ULP_CLASS_HID_3d00, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 720960, .flow_pattern_id = 1, @@ -12804,14 +16797,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [665] = { + [827] = { .class_hid = BNXT_ULP_CLASS_HID_52bc, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917504, .flow_pattern_id = 1, @@ -12823,13 +16816,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [666] = { + [828] = { .class_hid = BNXT_ULP_CLASS_HID_3ed0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 917568, .flow_pattern_id = 1, @@ -12841,14 +16834,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [667] = { + [829] = { .class_hid = BNXT_ULP_CLASS_HID_72c0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983040, .flow_pattern_id = 1, @@ -12860,14 +16853,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [668] = { + [830] = { .class_hid = BNXT_ULP_CLASS_HID_5ed4, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 983104, .flow_pattern_id = 1, @@ -12879,15 +16872,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT } + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT } }, - [669] = { + [831] = { .class_hid = BNXT_ULP_CLASS_HID_3866, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 0, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12897,12 +16890,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC } }, - [670] = { + [832] = { .class_hid = BNXT_ULP_CLASS_HID_381e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 1, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12912,12 +16905,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC } }, - [671] = { + [833] = { .class_hid = BNXT_ULP_CLASS_HID_3860, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12928,12 +16921,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC } }, - [672] = { + [834] = { .class_hid = BNXT_ULP_CLASS_HID_0454, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 2, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -12944,13 +16937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV6 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID } }, - [673] = { + [835] = { .class_hid = BNXT_ULP_CLASS_HID_3818, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12961,12 +16954,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC } }, - [674] = { + [836] = { .class_hid = BNXT_ULP_CLASS_HID_042c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 3, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -12977,13 +16970,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_IPV4 | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID } }, - [675] = { + [837] = { .class_hid = BNXT_ULP_CLASS_HID_3846, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 4, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -12994,12 +16987,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC } }, - [676] = { + [838] = { .class_hid = BNXT_ULP_CLASS_HID_387e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 5, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13010,12 +17003,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC } }, - [677] = { + [839] = { .class_hid = BNXT_ULP_CLASS_HID_3ba6, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 6, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13026,12 +17019,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC } }, - [678] = { + [840] = { .class_hid = BNXT_ULP_CLASS_HID_385e, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 7, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13042,12 +17035,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC } }, - [679] = { + [841] = { .class_hid = BNXT_ULP_CLASS_HID_3840, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13059,12 +17052,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC } }, - [680] = { + [842] = { .class_hid = BNXT_ULP_CLASS_HID_0474, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 8, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13076,13 +17069,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID } }, - [681] = { + [843] = { .class_hid = BNXT_ULP_CLASS_HID_3878, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13094,12 +17087,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC } }, - [682] = { + [844] = { .class_hid = BNXT_ULP_CLASS_HID_044c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 9, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13111,13 +17104,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_TCP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID } }, - [683] = { + [845] = { .class_hid = BNXT_ULP_CLASS_HID_3ba0, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13129,12 +17122,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC } }, - [684] = { + [846] = { .class_hid = BNXT_ULP_CLASS_HID_0794, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 10, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13146,13 +17139,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID } }, - [685] = { + [847] = { .class_hid = BNXT_ULP_CLASS_HID_3858, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 4, .flow_pattern_id = 2, @@ -13164,12 +17157,12 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC } }, - [686] = { + [848] = { .class_hid = BNXT_ULP_CLASS_HID_046c, - .class_tid = 2, + .class_tid = 3, .hdr_sig_id = 11, .flow_sig_id = 68, .flow_pattern_id = 2, @@ -13181,8 +17174,8 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = { BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_EGR }, .field_sig = { .bits = - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC | - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC | - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID } + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID } } }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h index b6db49cc5d..e55d0923a5 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #ifndef ULP_TEMPLATE_DB_H_ #define ULP_TEMPLATE_DB_H_ @@ -11,13 +11,13 @@ #define BNXT_ULP_REGFILE_MAX_SZ 40 #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 -#define BNXT_ULP_GEN_TBL_MAX_SZ 10 +#define BNXT_ULP_GEN_TBL_MAX_SZ 12 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 32768 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 687 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 849 #define BNXT_ULP_CLASS_HID_LOW_PRIME 6701 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 -#define BNXT_ULP_CLASS_HID_SHFTR 23 -#define BNXT_ULP_CLASS_HID_SHFTL 23 +#define BNXT_ULP_CLASS_HID_SHFTR 24 +#define BNXT_ULP_CLASS_HID_SHFTL 24 #define BNXT_ULP_CLASS_HID_MASK 32767 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86 @@ -36,14 +36,14 @@ #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4 #define BNXT_ULP_APP_ID_SHIFT 4 -#define BNXT_ULP_GLB_FIELD_TBL_SIZE 5595 -#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 5 -#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 74 -#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 495 -#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 20 -#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 546 -#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 43 -#define ULP_THOR_CLASS_TMPL_LIST_SIZE 5 +#define BNXT_ULP_GLB_FIELD_TBL_SIZE 7643 +#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 6 +#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 89 +#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 600 +#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 26 +#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 619 +#define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 49 +#define ULP_THOR_CLASS_TMPL_LIST_SIZE 6 #define ULP_THOR_CLASS_TBL_LIST_SIZE 33 #define ULP_THOR_CLASS_KEY_INFO_LIST_SIZE 242 #define ULP_THOR_CLASS_IDENT_LIST_SIZE 8 @@ -113,7 +113,8 @@ enum bnxt_ulp_hdr_bit { BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000, BNXT_ULP_HDR_BIT_I_ICMP = 0x0000000000020000, BNXT_ULP_HDR_BIT_F1 = 0x0000000000040000, - BNXT_ULP_HDR_BIT_LAST = 0x0000000000080000 + BNXT_ULP_HDR_BIT_F2 = 0x0000000000080000, + BNXT_ULP_HDR_BIT_LAST = 0x0000000000100000 }; enum bnxt_ulp_accept_opc { @@ -199,8 +200,10 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_FLOW_SIG_ID = 60, BNXT_ULP_CF_IDX_WC_MATCH = 61, BNXT_ULP_CF_IDX_WC_IS_HA_HIGH_REG = 62, - BNXT_ULP_CF_IDX_F1_DMAC = 63, - BNXT_ULP_CF_IDX_LAST = 64 + BNXT_ULP_CF_IDX_TUNNEL_ID = 63, + BNXT_ULP_CF_IDX_TUN_OFF_DIP_ID = 64, + BNXT_ULP_CF_IDX_TUN_OFF_DMAC_ID = 65, + BNXT_ULP_CF_IDX_LAST = 66 }; enum bnxt_ulp_cond_list_opc { @@ -315,7 +318,8 @@ enum bnxt_ulp_func_opc { BNXT_ULP_FUNC_OPC_COPY_SRC1_TO_RF = 7, BNXT_ULP_FUNC_OPC_RSS_CONFIG = 8, BNXT_ULP_FUNC_OPC_GET_PARENT_MAC_ADDR = 9, - BNXT_ULP_FUNC_OPC_LAST = 10 + BNXT_ULP_FUNC_OPC_ALLOC_L2_CTX_ID = 10, + BNXT_ULP_FUNC_OPC_LAST = 11 }; enum bnxt_ulp_func_src { @@ -497,7 +501,8 @@ enum bnxt_ulp_tcam_tbl_opc { BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE = 2, BNXT_ULP_TCAM_TBL_OPC_ALLOC_REGFILE = 3, BNXT_ULP_TCAM_TBL_OPC_WR_REGFILE = 4, - BNXT_ULP_TCAM_TBL_OPC_LAST = 5 + BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT = 5, + BNXT_ULP_TCAM_TBL_OPC_LAST = 6 }; enum bnxt_ulp_template_type { @@ -549,7 +554,8 @@ enum bnxt_ulp_resource_sub_type { BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM = 1, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR = 2, BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE = 3, - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4 + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE = 4, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE = 5 }; enum bnxt_ulp_act_prop_sz { @@ -1443,6 +1449,168 @@ enum bnxt_ulp_class_hid { BNXT_ULP_CLASS_HID_15db = 0x15db, BNXT_ULP_CLASS_HID_1151 = 0x1151, BNXT_ULP_CLASS_HID_315d = 0x315d, + BNXT_ULP_CLASS_HID_3612 = 0x3612, + BNXT_ULP_CLASS_HID_66da = 0x66da, + BNXT_ULP_CLASS_HID_6165 = 0x6165, + BNXT_ULP_CLASS_HID_2aa1 = 0x2aa1, + BNXT_ULP_CLASS_HID_09cd = 0x09cd, + BNXT_ULP_CLASS_HID_3845 = 0x3845, + BNXT_ULP_CLASS_HID_11e9 = 0x11e9, + BNXT_ULP_CLASS_HID_4361 = 0x4361, + BNXT_ULP_CLASS_HID_218d = 0x218d, + BNXT_ULP_CLASS_HID_5105 = 0x5105, + BNXT_ULP_CLASS_HID_0c89 = 0x0c89, + BNXT_ULP_CLASS_HID_3e81 = 0x3e81, + BNXT_ULP_CLASS_HID_1dad = 0x1dad, + BNXT_ULP_CLASS_HID_4ca5 = 0x4ca5, + BNXT_ULP_CLASS_HID_25c9 = 0x25c9, + BNXT_ULP_CLASS_HID_57c1 = 0x57c1, + BNXT_ULP_CLASS_HID_33ed = 0x33ed, + BNXT_ULP_CLASS_HID_65e5 = 0x65e5, + BNXT_ULP_CLASS_HID_6dd9 = 0x6dd9, + BNXT_ULP_CLASS_HID_261d = 0x261d, + BNXT_ULP_CLASS_HID_0571 = 0x0571, + BNXT_ULP_CLASS_HID_34f9 = 0x34f9, + BNXT_ULP_CLASS_HID_1d55 = 0x1d55, + BNXT_ULP_CLASS_HID_4fdd = 0x4fdd, + BNXT_ULP_CLASS_HID_2d31 = 0x2d31, + BNXT_ULP_CLASS_HID_5db9 = 0x5db9, + BNXT_ULP_CLASS_HID_0035 = 0x0035, + BNXT_ULP_CLASS_HID_323d = 0x323d, + BNXT_ULP_CLASS_HID_1111 = 0x1111, + BNXT_ULP_CLASS_HID_4019 = 0x4019, + BNXT_ULP_CLASS_HID_2975 = 0x2975, + BNXT_ULP_CLASS_HID_5b7d = 0x5b7d, + BNXT_ULP_CLASS_HID_3f51 = 0x3f51, + BNXT_ULP_CLASS_HID_6959 = 0x6959, + BNXT_ULP_CLASS_HID_0e85 = 0x0e85, + BNXT_ULP_CLASS_HID_380d = 0x380d, + BNXT_ULP_CLASS_HID_1f21 = 0x1f21, + BNXT_ULP_CLASS_HID_4ea9 = 0x4ea9, + BNXT_ULP_CLASS_HID_1705 = 0x1705, + BNXT_ULP_CLASS_HID_418d = 0x418d, + BNXT_ULP_CLASS_HID_2721 = 0x2721, + BNXT_ULP_CLASS_HID_57a9 = 0x57a9, + BNXT_ULP_CLASS_HID_1a25 = 0x1a25, + BNXT_ULP_CLASS_HID_342d = 0x342d, + BNXT_ULP_CLASS_HID_2b01 = 0x2b01, + BNXT_ULP_CLASS_HID_5a09 = 0x5a09, + BNXT_ULP_CLASS_HID_2325 = 0x2325, + BNXT_ULP_CLASS_HID_5d2d = 0x5d2d, + BNXT_ULP_CLASS_HID_3101 = 0x3101, + BNXT_ULP_CLASS_HID_6309 = 0x6309, + BNXT_ULP_CLASS_HID_0bad = 0x0bad, + BNXT_ULP_CLASS_HID_2535 = 0x2535, + BNXT_ULP_CLASS_HID_1869 = 0x1869, + BNXT_ULP_CLASS_HID_4bf1 = 0x4bf1, + BNXT_ULP_CLASS_HID_136d = 0x136d, + BNXT_ULP_CLASS_HID_43f5 = 0x43f5, + BNXT_ULP_CLASS_HID_2129 = 0x2129, + BNXT_ULP_CLASS_HID_53b1 = 0x53b1, + BNXT_ULP_CLASS_HID_072d = 0x072d, + BNXT_ULP_CLASS_HID_3135 = 0x3135, + BNXT_ULP_CLASS_HID_1429 = 0x1429, + BNXT_ULP_CLASS_HID_4731 = 0x4731, + BNXT_ULP_CLASS_HID_2f6d = 0x2f6d, + BNXT_ULP_CLASS_HID_5f75 = 0x5f75, + BNXT_ULP_CLASS_HID_3d69 = 0x3d69, + BNXT_ULP_CLASS_HID_6f71 = 0x6f71, + BNXT_ULP_CLASS_HID_0dbd = 0x0dbd, + BNXT_ULP_CLASS_HID_3f25 = 0x3f25, + BNXT_ULP_CLASS_HID_1239 = 0x1239, + BNXT_ULP_CLASS_HID_4da1 = 0x4da1, + BNXT_ULP_CLASS_HID_153d = 0x153d, + BNXT_ULP_CLASS_HID_45a5 = 0x45a5, + BNXT_ULP_CLASS_HID_3bb9 = 0x3bb9, + BNXT_ULP_CLASS_HID_55a1 = 0x55a1, + BNXT_ULP_CLASS_HID_193d = 0x193d, + BNXT_ULP_CLASS_HID_4b25 = 0x4b25, + BNXT_ULP_CLASS_HID_2e39 = 0x2e39, + BNXT_ULP_CLASS_HID_5921 = 0x5921, + BNXT_ULP_CLASS_HID_213d = 0x213d, + BNXT_ULP_CLASS_HID_5125 = 0x5125, + BNXT_ULP_CLASS_HID_3739 = 0x3739, + BNXT_ULP_CLASS_HID_093d = 0x093d, + BNXT_ULP_CLASS_HID_684d = 0x684d, + BNXT_ULP_CLASS_HID_2389 = 0x2389, + BNXT_ULP_CLASS_HID_00e5 = 0x00e5, + BNXT_ULP_CLASS_HID_316d = 0x316d, + BNXT_ULP_CLASS_HID_18c1 = 0x18c1, + BNXT_ULP_CLASS_HID_4a49 = 0x4a49, + BNXT_ULP_CLASS_HID_28a5 = 0x28a5, + BNXT_ULP_CLASS_HID_582d = 0x582d, + BNXT_ULP_CLASS_HID_05a1 = 0x05a1, + BNXT_ULP_CLASS_HID_37a9 = 0x37a9, + BNXT_ULP_CLASS_HID_1485 = 0x1485, + BNXT_ULP_CLASS_HID_458d = 0x458d, + BNXT_ULP_CLASS_HID_2ce1 = 0x2ce1, + BNXT_ULP_CLASS_HID_5ee9 = 0x5ee9, + BNXT_ULP_CLASS_HID_3ac5 = 0x3ac5, + BNXT_ULP_CLASS_HID_6ccd = 0x6ccd, + BNXT_ULP_CLASS_HID_0b11 = 0x0b11, + BNXT_ULP_CLASS_HID_3d99 = 0x3d99, + BNXT_ULP_CLASS_HID_1ab5 = 0x1ab5, + BNXT_ULP_CLASS_HID_4b3d = 0x4b3d, + BNXT_ULP_CLASS_HID_1291 = 0x1291, + BNXT_ULP_CLASS_HID_4419 = 0x4419, + BNXT_ULP_CLASS_HID_22b5 = 0x22b5, + BNXT_ULP_CLASS_HID_523d = 0x523d, + BNXT_ULP_CLASS_HID_1fb1 = 0x1fb1, + BNXT_ULP_CLASS_HID_31b9 = 0x31b9, + BNXT_ULP_CLASS_HID_2e95 = 0x2e95, + BNXT_ULP_CLASS_HID_5f9d = 0x5f9d, + BNXT_ULP_CLASS_HID_26b1 = 0x26b1, + BNXT_ULP_CLASS_HID_58b9 = 0x58b9, + BNXT_ULP_CLASS_HID_3495 = 0x3495, + BNXT_ULP_CLASS_HID_669d = 0x669d, + BNXT_ULP_CLASS_HID_0e39 = 0x0e39, + BNXT_ULP_CLASS_HID_20a1 = 0x20a1, + BNXT_ULP_CLASS_HID_1dfd = 0x1dfd, + BNXT_ULP_CLASS_HID_4e65 = 0x4e65, + BNXT_ULP_CLASS_HID_16f9 = 0x16f9, + BNXT_ULP_CLASS_HID_4661 = 0x4661, + BNXT_ULP_CLASS_HID_24bd = 0x24bd, + BNXT_ULP_CLASS_HID_5625 = 0x5625, + BNXT_ULP_CLASS_HID_02b9 = 0x02b9, + BNXT_ULP_CLASS_HID_34a1 = 0x34a1, + BNXT_ULP_CLASS_HID_11bd = 0x11bd, + BNXT_ULP_CLASS_HID_42a5 = 0x42a5, + BNXT_ULP_CLASS_HID_2af9 = 0x2af9, + BNXT_ULP_CLASS_HID_5ae1 = 0x5ae1, + BNXT_ULP_CLASS_HID_38fd = 0x38fd, + BNXT_ULP_CLASS_HID_6ae5 = 0x6ae5, + BNXT_ULP_CLASS_HID_0829 = 0x0829, + BNXT_ULP_CLASS_HID_3ab1 = 0x3ab1, + BNXT_ULP_CLASS_HID_17ad = 0x17ad, + BNXT_ULP_CLASS_HID_4835 = 0x4835, + BNXT_ULP_CLASS_HID_10a9 = 0x10a9, + BNXT_ULP_CLASS_HID_4031 = 0x4031, + BNXT_ULP_CLASS_HID_3e2d = 0x3e2d, + BNXT_ULP_CLASS_HID_5035 = 0x5035, + BNXT_ULP_CLASS_HID_1ca9 = 0x1ca9, + BNXT_ULP_CLASS_HID_4eb1 = 0x4eb1, + BNXT_ULP_CLASS_HID_2bad = 0x2bad, + BNXT_ULP_CLASS_HID_5cb5 = 0x5cb5, + BNXT_ULP_CLASS_HID_24a9 = 0x24a9, + BNXT_ULP_CLASS_HID_54b1 = 0x54b1, + BNXT_ULP_CLASS_HID_32ad = 0x32ad, + BNXT_ULP_CLASS_HID_0ca9 = 0x0ca9, + BNXT_ULP_CLASS_HID_7f35 = 0x7f35, + BNXT_ULP_CLASS_HID_34f1 = 0x34f1, + BNXT_ULP_CLASS_HID_179d = 0x179d, + BNXT_ULP_CLASS_HID_2615 = 0x2615, + BNXT_ULP_CLASS_HID_0fb9 = 0x0fb9, + BNXT_ULP_CLASS_HID_5d31 = 0x5d31, + BNXT_ULP_CLASS_HID_3fdd = 0x3fdd, + BNXT_ULP_CLASS_HID_4f55 = 0x4f55, + BNXT_ULP_CLASS_HID_12d9 = 0x12d9, + BNXT_ULP_CLASS_HID_20d1 = 0x20d1, + BNXT_ULP_CLASS_HID_03fd = 0x03fd, + BNXT_ULP_CLASS_HID_52f5 = 0x52f5, + BNXT_ULP_CLASS_HID_3b99 = 0x3b99, + BNXT_ULP_CLASS_HID_4991 = 0x4991, + BNXT_ULP_CLASS_HID_2dbd = 0x2dbd, + BNXT_ULP_CLASS_HID_7bb5 = 0x7bb5, BNXT_ULP_CLASS_HID_34c6 = 0x34c6, BNXT_ULP_CLASS_HID_0c22 = 0x0c22, BNXT_ULP_CLASS_HID_1cbe = 0x1cbe, @@ -1876,8 +2044,8 @@ enum bnxt_ulp_act_hid { }; enum bnxt_ulp_df_tpl { - BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 3, - BNXT_ULP_DF_TPL_DEFAULT_VFR = 4 + BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT = 4, + BNXT_ULP_DF_TPL_DEFAULT_VFR = 5 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h index 115bdc644c..1d7bbfe2cc 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_field.h @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Wed Mar 17 11:31:19 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #ifndef ULP_HDR_FIELD_ENUMS_H_ #define ULP_HDR_FIELD_ENUMS_H_ @@ -415,272 +415,460 @@ enum bnxt_ulp_hf_0_2_0_bitmask { BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, BNXT_ULP_HF_0_2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF_0_2_0_BITMASK_O_UDP_CSUM = 0x0000200000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_VNI = 0x0000040000000000, + BNXT_ULP_HF_0_2_0_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000 }; enum bnxt_ulp_hf_0_2_1_bitmask { BNXT_ULP_HF_0_2_1_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_1_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_1_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_1_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000 }; enum bnxt_ulp_hf_0_2_2_bitmask { BNXT_ULP_HF_0_2_2_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_2_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_2_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SRC_PORT = 0x0000000040000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DST_PORT = 0x0000000020000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_SENT_SEQ = 0x0000000010000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RECV_ACK = 0x0000000008000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_DATA_OFF = 0x0000000004000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_TCP_FLAGS = 0x0000000002000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_RX_WIN = 0x0000000001000000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_CSUM = 0x0000000000800000, + BNXT_ULP_HF_0_2_2_BITMASK_I_TCP_URP = 0x0000000000400000 }; enum bnxt_ulp_hf_0_2_3_bitmask { BNXT_ULP_HF_0_2_3_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_3_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_3_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_SRC_PORT = 0x0000000040000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_DST_PORT = 0x0000000020000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_LENGTH = 0x0000000010000000, + BNXT_ULP_HF_0_2_3_BITMASK_I_UDP_CSUM = 0x0000000008000000 }; enum bnxt_ulp_hf_0_2_4_bitmask { BNXT_ULP_HF_0_2_4_BITMASK_WM = 0x8000000000000000, BNXT_ULP_HF_0_2_4_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, - BNXT_ULP_HF_0_2_4_BITMASK_O_TCP_URP = 0x0000040000000000 + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_VER = 0x2000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TOS = 0x1000000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_LEN = 0x0800000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_ID = 0x0400000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_FRAG_OFF = 0x0200000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_TTL = 0x0100000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_PROTO_ID = 0x0080000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_CSUM = 0x0040000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_SRC_ADDR = 0x0020000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_IPV4_DST_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_SRC_PORT = 0x0008000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_DST_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_LENGTH = 0x0002000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_O_UDP_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_FLAGS = 0x0000800000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD0 = 0x0000400000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_VNI = 0x0000200000000000, + BNXT_ULP_HF_0_2_4_BITMASK_T_VXLAN_RSVD1 = 0x0000100000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_DMAC = 0x0000080000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_SMAC = 0x0000040000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ETH_TYPE = 0x0000020000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_VER = 0x0000010000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TOS = 0x0000008000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_LEN = 0x0000004000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_ID = 0x0000002000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_FRAG_OFF = 0x0000001000000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_TTL = 0x0000000800000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_PROTO_ID = 0x0000000400000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_CSUM = 0x0000000200000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_SRC_ADDR = 0x0000000100000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_IPV4_DST_ADDR = 0x0000000080000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_TYPE = 0x0000000040000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CODE = 0x0000000020000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_CSUM = 0x0000000010000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_IDENT = 0x0000000008000000, + BNXT_ULP_HF_0_2_4_BITMASK_I_ICMP_SEQ_NUM = 0x0000000004000000 }; -enum bnxt_ulp_hf_0_2_5_bitmask { - BNXT_ULP_HF_0_2_5_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, - BNXT_ULP_HF_0_2_5_BITMASK_O_TCP_URP = 0x0000010000000000 +enum bnxt_ulp_hf_0_3_0_bitmask { + BNXT_ULP_HF_0_3_0_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_3_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000 }; -enum bnxt_ulp_hf_0_2_6_bitmask { - BNXT_ULP_HF_0_2_6_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TC = 0x0200000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, - BNXT_ULP_HF_0_2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 +enum bnxt_ulp_hf_0_3_1_bitmask { + BNXT_ULP_HF_0_3_1_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_3_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000 }; -enum bnxt_ulp_hf_0_2_7_bitmask { - BNXT_ULP_HF_0_2_7_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_VER = 0x0400000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, - BNXT_ULP_HF_0_2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 +enum bnxt_ulp_hf_0_3_2_bitmask { + BNXT_ULP_HF_0_3_2_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000 }; -enum bnxt_ulp_hf_0_2_8_bitmask { - BNXT_ULP_HF_0_2_8_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, - BNXT_ULP_HF_0_2_8_BITMASK_O_TCP_URP = 0x0000008000000000 +enum bnxt_ulp_hf_0_3_3_bitmask { + BNXT_ULP_HF_0_3_3_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_3_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000 }; -enum bnxt_ulp_hf_0_2_9_bitmask { - BNXT_ULP_HF_0_2_9_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, - BNXT_ULP_HF_0_2_9_BITMASK_O_TCP_URP = 0x0000002000000000 +enum bnxt_ulp_hf_0_3_4_bitmask { + BNXT_ULP_HF_0_3_4_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_SENT_SEQ = 0x0001000000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RECV_ACK = 0x0000800000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_DATA_OFF = 0x0000400000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_TCP_FLAGS = 0x0000200000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_RX_WIN = 0x0000100000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_CSUM = 0x0000080000000000, + BNXT_ULP_HF_0_3_4_BITMASK_O_TCP_URP = 0x0000040000000000 }; -enum bnxt_ulp_hf_0_2_10_bitmask { - BNXT_ULP_HF_0_2_10_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TC = 0x0040000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, - BNXT_ULP_HF_0_2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 +enum bnxt_ulp_hf_0_3_5_bitmask { + BNXT_ULP_HF_0_3_5_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_CSUM = 0x0000020000000000, + BNXT_ULP_HF_0_3_5_BITMASK_O_TCP_URP = 0x0000010000000000 }; -enum bnxt_ulp_hf_0_2_11_bitmask { - BNXT_ULP_HF_0_2_11_BITMASK_WM = 0x8000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_SVIF_INDEX = 0x4000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_VER = 0x0080000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, - BNXT_ULP_HF_0_2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 +enum bnxt_ulp_hf_0_3_6_bitmask { + BNXT_ULP_HF_0_3_6_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TC = 0x0200000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000, + BNXT_ULP_HF_0_3_6_BITMASK_O_UDP_CSUM = 0x0000800000000000 +}; + +enum bnxt_ulp_hf_0_3_7_bitmask { + BNXT_ULP_HF_0_3_7_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_VER = 0x0400000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TOS = 0x0200000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_LEN = 0x0100000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_TTL = 0x0020000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000, + BNXT_ULP_HF_0_3_7_BITMASK_O_UDP_CSUM = 0x0000200000000000 +}; + +enum bnxt_ulp_hf_0_3_8_bitmask { + BNXT_ULP_HF_0_3_8_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_CSUM = 0x0000010000000000, + BNXT_ULP_HF_0_3_8_BITMASK_O_TCP_URP = 0x0000008000000000 +}; + +enum bnxt_ulp_hf_0_3_9_bitmask { + BNXT_ULP_HF_0_3_9_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF_0_3_9_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf_0_3_10_bitmask { + BNXT_ULP_HF_0_3_10_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TC = 0x0040000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000, + BNXT_ULP_HF_0_3_10_BITMASK_O_UDP_CSUM = 0x0000100000000000 +}; + +enum bnxt_ulp_hf_0_3_11_bitmask { + BNXT_ULP_HF_0_3_11_BITMASK_WM = 0x8000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_SVIF_INDEX = 0x4000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_DMAC = 0x2000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_SMAC = 0x1000000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_ETH_TYPE = 0x0800000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_VID = 0x0200000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_VER = 0x0080000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TOS = 0x0040000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_LEN = 0x0020000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_TTL = 0x0004000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF_0_3_11_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c index 2debaea0ca..58b4dba63c 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -111,6 +111,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = { .num_buckets = 0, .hash_tbl_entries = 0, .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_INGRESS] = { + .name = "INGRESS GENERIC_TABLE_TUNNEL_CACHE", + .result_num_entries = 256, + .result_num_bytes = 7, + .key_num_bytes = 2, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE << 1 | + BNXT_ULP_DIRECTION_EGRESS] = { + .name = "EGRESS GENERIC_TABLE_TUNNEL_CACHE", + .result_num_entries = 256, + .result_num_bytes = 7, + .key_num_bytes = 2, + .num_buckets = 8, + .hash_tbl_entries = 1024, + .result_byte_order = BNXT_ULP_BYTE_ORDER_LE } }; @@ -3098,238 +3118,411 @@ uint8_t ulp_glb_field_tbl[] = { [4098] = 2, [4100] = 3, [4102] = 4, - [4136] = 5, - [4138] = 6, - [4140] = 7, - [4142] = 8, - [4144] = 9, - [4146] = 10, - [4148] = 11, - [4150] = 12, + [4116] = 5, + [4118] = 6, + [4120] = 7, + [4122] = 8, + [4124] = 9, + [4126] = 10, + [4128] = 11, + [4130] = 12, + [4132] = 13, + [4134] = 14, + [4170] = 15, + [4172] = 16, + [4174] = 17, + [4176] = 18, + [4190] = 19, + [4191] = 20, + [4192] = 21, + [4193] = 22, [4224] = 0, [4225] = 1, - [4226] = 2, - [4228] = 3, - [4230] = 4, - [4244] = 5, - [4246] = 6, - [4248] = 7, - [4250] = 8, - [4252] = 9, - [4254] = 10, - [4256] = 11, - [4258] = 12, - [4260] = 13, - [4262] = 14, + [4227] = 20, + [4229] = 21, + [4231] = 22, + [4244] = 2, + [4245] = 23, + [4246] = 3, + [4247] = 24, + [4248] = 4, + [4249] = 25, + [4250] = 5, + [4251] = 26, + [4252] = 6, + [4253] = 27, + [4254] = 7, + [4255] = 28, + [4256] = 8, + [4257] = 29, + [4258] = 9, + [4259] = 30, + [4260] = 10, + [4261] = 31, + [4262] = 11, + [4263] = 32, + [4298] = 12, + [4300] = 13, + [4302] = 14, + [4304] = 15, + [4318] = 16, + [4319] = 17, + [4320] = 18, + [4321] = 19, [4352] = 0, [4353] = 1, - [4354] = 2, - [4356] = 3, - [4358] = 4, - [4392] = 8, - [4394] = 9, - [4396] = 10, - [4398] = 11, - [4400] = 12, - [4402] = 13, - [4404] = 14, - [4406] = 15, - [4434] = 5, - [4438] = 6, - [4442] = 7, + [4355] = 20, + [4357] = 21, + [4359] = 22, + [4372] = 2, + [4373] = 23, + [4374] = 3, + [4375] = 24, + [4376] = 4, + [4377] = 25, + [4378] = 5, + [4379] = 26, + [4380] = 6, + [4381] = 27, + [4382] = 7, + [4383] = 28, + [4384] = 8, + [4385] = 29, + [4386] = 9, + [4387] = 30, + [4388] = 10, + [4389] = 31, + [4390] = 11, + [4391] = 32, + [4409] = 33, + [4411] = 34, + [4413] = 35, + [4415] = 36, + [4417] = 37, + [4419] = 38, + [4421] = 39, + [4423] = 40, + [4425] = 41, + [4426] = 12, + [4428] = 13, + [4430] = 14, + [4432] = 15, + [4446] = 16, + [4447] = 17, + [4448] = 18, + [4449] = 19, [4480] = 0, [4481] = 1, - [4482] = 2, - [4484] = 3, - [4486] = 4, - [4500] = 8, - [4502] = 9, - [4504] = 10, - [4506] = 11, - [4508] = 12, - [4510] = 13, - [4512] = 14, - [4514] = 15, - [4516] = 16, - [4518] = 17, - [4562] = 5, - [4566] = 6, - [4570] = 7, + [4483] = 20, + [4485] = 21, + [4487] = 22, + [4500] = 2, + [4501] = 23, + [4502] = 3, + [4503] = 24, + [4504] = 4, + [4505] = 25, + [4506] = 5, + [4507] = 26, + [4508] = 6, + [4509] = 27, + [4510] = 7, + [4511] = 28, + [4512] = 8, + [4513] = 29, + [4514] = 9, + [4515] = 30, + [4516] = 10, + [4517] = 31, + [4518] = 11, + [4519] = 32, + [4554] = 12, + [4555] = 33, + [4556] = 13, + [4557] = 34, + [4558] = 14, + [4559] = 35, + [4560] = 15, + [4561] = 36, + [4574] = 16, + [4575] = 17, + [4576] = 18, + [4577] = 19, [4608] = 0, [4609] = 1, - [4610] = 2, - [4612] = 3, - [4614] = 4, - [4648] = 5, - [4650] = 6, - [4652] = 7, - [4654] = 8, - [4656] = 9, - [4658] = 10, - [4660] = 11, - [4662] = 12, - [4664] = 13, - [4666] = 14, - [4668] = 15, - [4670] = 16, - [4672] = 17, - [4674] = 18, - [4676] = 19, - [4678] = 20, - [4680] = 21, - [4736] = 0, - [4737] = 1, - [4738] = 2, - [4740] = 3, - [4742] = 4, - [4756] = 5, - [4758] = 6, - [4760] = 7, - [4762] = 8, - [4764] = 9, - [4766] = 10, - [4768] = 11, - [4770] = 12, - [4772] = 13, - [4774] = 14, - [4792] = 15, - [4794] = 16, - [4796] = 17, - [4798] = 18, - [4800] = 19, - [4802] = 20, - [4804] = 21, - [4806] = 22, - [4808] = 23, - [4864] = 0, - [4865] = 1, - [4866] = 2, - [4868] = 3, - [4870] = 4, - [4904] = 5, - [4906] = 6, - [4908] = 7, - [4910] = 8, - [4912] = 9, - [4914] = 10, - [4916] = 11, - [4918] = 12, - [4938] = 13, - [4940] = 14, - [4942] = 15, - [4944] = 16, - [4992] = 0, - [4993] = 1, - [4994] = 2, - [4996] = 3, - [4998] = 4, - [5012] = 5, - [5014] = 6, - [5016] = 7, - [5018] = 8, - [5020] = 9, - [5022] = 10, - [5024] = 11, - [5026] = 12, - [5028] = 13, - [5030] = 14, - [5066] = 15, - [5068] = 16, - [5070] = 17, - [5072] = 18, - [5120] = 0, - [5121] = 1, - [5122] = 2, - [5124] = 3, - [5126] = 4, - [5160] = 8, - [5162] = 9, - [5164] = 10, - [5166] = 11, - [5168] = 12, - [5170] = 13, - [5172] = 14, - [5174] = 15, - [5176] = 16, - [5178] = 17, - [5180] = 18, - [5182] = 19, - [5184] = 20, - [5186] = 21, - [5188] = 22, - [5190] = 23, - [5192] = 24, - [5202] = 5, - [5206] = 6, - [5210] = 7, - [5248] = 0, - [5249] = 1, - [5250] = 2, - [5252] = 3, - [5254] = 4, - [5268] = 8, - [5270] = 9, - [5272] = 10, - [5274] = 11, - [5276] = 12, - [5278] = 13, - [5280] = 14, - [5282] = 15, - [5284] = 16, - [5286] = 17, - [5304] = 18, - [5306] = 19, - [5308] = 20, - [5310] = 21, - [5312] = 22, - [5314] = 23, - [5316] = 24, - [5318] = 25, - [5320] = 26, - [5330] = 5, - [5334] = 6, - [5338] = 7, - [5376] = 0, - [5377] = 1, - [5378] = 2, - [5380] = 3, - [5382] = 4, - [5416] = 8, - [5418] = 9, - [5420] = 10, - [5422] = 11, - [5424] = 12, - [5426] = 13, - [5428] = 14, - [5430] = 15, - [5450] = 16, - [5452] = 17, - [5454] = 18, - [5456] = 19, - [5458] = 5, - [5462] = 6, - [5466] = 7, - [5504] = 0, - [5505] = 1, - [5506] = 2, - [5508] = 3, - [5510] = 4, - [5524] = 8, - [5526] = 9, - [5528] = 10, - [5530] = 11, - [5532] = 12, - [5534] = 13, - [5536] = 14, - [5538] = 15, - [5540] = 16, - [5542] = 17, - [5578] = 18, - [5580] = 19, - [5582] = 20, - [5584] = 21, - [5586] = 5, - [5590] = 6, - [5594] = 7 + [4611] = 20, + [4613] = 21, + [4615] = 22, + [4619] = 33, + [4621] = 34, + [4623] = 35, + [4625] = 36, + [4627] = 37, + [4628] = 2, + [4629] = 23, + [4630] = 3, + [4631] = 24, + [4632] = 4, + [4633] = 25, + [4634] = 5, + [4635] = 26, + [4636] = 6, + [4637] = 27, + [4638] = 7, + [4639] = 28, + [4640] = 8, + [4641] = 29, + [4642] = 9, + [4643] = 30, + [4644] = 10, + [4645] = 31, + [4646] = 11, + [4647] = 32, + [4682] = 12, + [4684] = 13, + [4686] = 14, + [4688] = 15, + [4702] = 16, + [4703] = 17, + [4704] = 18, + [4705] = 19, + [6144] = 0, + [6145] = 1, + [6146] = 2, + [6148] = 3, + [6150] = 4, + [6184] = 5, + [6186] = 6, + [6188] = 7, + [6190] = 8, + [6192] = 9, + [6194] = 10, + [6196] = 11, + [6198] = 12, + [6272] = 0, + [6273] = 1, + [6274] = 2, + [6276] = 3, + [6278] = 4, + [6292] = 5, + [6294] = 6, + [6296] = 7, + [6298] = 8, + [6300] = 9, + [6302] = 10, + [6304] = 11, + [6306] = 12, + [6308] = 13, + [6310] = 14, + [6400] = 0, + [6401] = 1, + [6402] = 2, + [6404] = 3, + [6406] = 4, + [6440] = 8, + [6442] = 9, + [6444] = 10, + [6446] = 11, + [6448] = 12, + [6450] = 13, + [6452] = 14, + [6454] = 15, + [6482] = 5, + [6486] = 6, + [6490] = 7, + [6528] = 0, + [6529] = 1, + [6530] = 2, + [6532] = 3, + [6534] = 4, + [6548] = 8, + [6550] = 9, + [6552] = 10, + [6554] = 11, + [6556] = 12, + [6558] = 13, + [6560] = 14, + [6562] = 15, + [6564] = 16, + [6566] = 17, + [6610] = 5, + [6614] = 6, + [6618] = 7, + [6656] = 0, + [6657] = 1, + [6658] = 2, + [6660] = 3, + [6662] = 4, + [6696] = 5, + [6698] = 6, + [6700] = 7, + [6702] = 8, + [6704] = 9, + [6706] = 10, + [6708] = 11, + [6710] = 12, + [6712] = 13, + [6714] = 14, + [6716] = 15, + [6718] = 16, + [6720] = 17, + [6722] = 18, + [6724] = 19, + [6726] = 20, + [6728] = 21, + [6784] = 0, + [6785] = 1, + [6786] = 2, + [6788] = 3, + [6790] = 4, + [6804] = 5, + [6806] = 6, + [6808] = 7, + [6810] = 8, + [6812] = 9, + [6814] = 10, + [6816] = 11, + [6818] = 12, + [6820] = 13, + [6822] = 14, + [6840] = 15, + [6842] = 16, + [6844] = 17, + [6846] = 18, + [6848] = 19, + [6850] = 20, + [6852] = 21, + [6854] = 22, + [6856] = 23, + [6912] = 0, + [6913] = 1, + [6914] = 2, + [6916] = 3, + [6918] = 4, + [6952] = 5, + [6954] = 6, + [6956] = 7, + [6958] = 8, + [6960] = 9, + [6962] = 10, + [6964] = 11, + [6966] = 12, + [6986] = 13, + [6988] = 14, + [6990] = 15, + [6992] = 16, + [7040] = 0, + [7041] = 1, + [7042] = 2, + [7044] = 3, + [7046] = 4, + [7060] = 5, + [7062] = 6, + [7064] = 7, + [7066] = 8, + [7068] = 9, + [7070] = 10, + [7072] = 11, + [7074] = 12, + [7076] = 13, + [7078] = 14, + [7114] = 15, + [7116] = 16, + [7118] = 17, + [7120] = 18, + [7168] = 0, + [7169] = 1, + [7170] = 2, + [7172] = 3, + [7174] = 4, + [7208] = 8, + [7210] = 9, + [7212] = 10, + [7214] = 11, + [7216] = 12, + [7218] = 13, + [7220] = 14, + [7222] = 15, + [7224] = 16, + [7226] = 17, + [7228] = 18, + [7230] = 19, + [7232] = 20, + [7234] = 21, + [7236] = 22, + [7238] = 23, + [7240] = 24, + [7250] = 5, + [7254] = 6, + [7258] = 7, + [7296] = 0, + [7297] = 1, + [7298] = 2, + [7300] = 3, + [7302] = 4, + [7316] = 8, + [7318] = 9, + [7320] = 10, + [7322] = 11, + [7324] = 12, + [7326] = 13, + [7328] = 14, + [7330] = 15, + [7332] = 16, + [7334] = 17, + [7352] = 18, + [7354] = 19, + [7356] = 20, + [7358] = 21, + [7360] = 22, + [7362] = 23, + [7364] = 24, + [7366] = 25, + [7368] = 26, + [7378] = 5, + [7382] = 6, + [7386] = 7, + [7424] = 0, + [7425] = 1, + [7426] = 2, + [7428] = 3, + [7430] = 4, + [7464] = 8, + [7466] = 9, + [7468] = 10, + [7470] = 11, + [7472] = 12, + [7474] = 13, + [7476] = 14, + [7478] = 15, + [7498] = 16, + [7500] = 17, + [7502] = 18, + [7504] = 19, + [7506] = 5, + [7510] = 6, + [7514] = 7, + [7552] = 0, + [7553] = 1, + [7554] = 2, + [7556] = 3, + [7558] = 4, + [7572] = 8, + [7574] = 9, + [7576] = 10, + [7578] = 11, + [7580] = 12, + [7582] = 13, + [7584] = 14, + [7586] = 15, + [7588] = 16, + [7590] = 17, + [7626] = 18, + [7628] = 19, + [7630] = 20, + [7632] = 21, + [7634] = 5, + [7638] = 6, + [7642] = 7 }; diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c index e342f340d9..d20c4197fa 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Thu May 20 11:56:39 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -22,8 +22,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .cond_start_idx = 0, .cond_nums = 4 } }, - /* class_tid: 3, ingress */ - [3] = { + /* class_tid: 4, ingress */ + [4] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 15, .start_tbl_idx = 12, @@ -32,8 +32,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[] = { .cond_start_idx = 8, .cond_nums = 1 } }, - /* class_tid: 4, egress */ - [4] = { + /* class_tid: 5, egress */ + [5] = { .device_name = BNXT_ULP_DEVICE_ID_THOR, .num_tbls = 6, .start_tbl_idx = 27, @@ -306,7 +306,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 38, .result_num_fields = 5 }, - { /* class_tid: 3, , table: int_full_act_record.0 */ + { /* class_tid: 4, , table: int_full_act_record.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -327,7 +327,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 128, .result_num_fields = 17 }, - { /* class_tid: 3, , table: port_table.wr_0 */ + { /* class_tid: 4, , table: port_table.wr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE, @@ -350,7 +350,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 152, .result_num_fields = 5 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -372,7 +372,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 6, .ident_nums = 0 }, - { /* class_tid: 3, , table: control.ing_0 */ + { /* class_tid: 4, , table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -385,7 +385,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_RX, @@ -414,7 +414,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 6, .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ + { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -455,7 +455,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_RX, @@ -473,7 +473,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, , table: control.egr_0 */ + { /* class_tid: 4, , table: control.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -485,7 +485,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: int_full_act_record.egr_0 */ + { /* class_tid: 4, , table: int_full_act_record.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -507,7 +507,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -529,7 +529,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 0 }, - { /* class_tid: 3, , table: control.egr_1 */ + { /* class_tid: 4, , table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, .direction = TF_DIR_RX, .execute_info = { @@ -542,7 +542,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -569,7 +569,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .ident_start_idx = 7, .ident_nums = 1 }, - { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ + { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -605,7 +605,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.loopback */ + { /* class_tid: 5, , table: int_full_act_record.loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -627,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -645,7 +645,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, .direction = TF_DIR_TX, @@ -663,7 +663,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.vf_ing */ + { /* class_tid: 5, , table: int_full_act_record.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -685,7 +685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 17, .encap_num_fields = 0 }, - { /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */ + { /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, .resource_sub_type = @@ -707,7 +707,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[] = { .result_num_fields = 0, .encap_num_fields = 11 }, - { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ + { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = @@ -768,27 +768,27 @@ struct bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_O_L4 }, - /* cond_reject: thor, class_tid: 3 */ + /* cond_reject: thor, class_tid: 4 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* cond_execute: class_tid: 3, control.ing_0 */ + /* cond_execute: class_tid: 4, control.ing_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, control.egr_0 */ + /* cond_execute: class_tid: 4, control.egr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* cond_execute: class_tid: 3, control.egr_1 */ + /* cond_execute: class_tid: 4, control.egr_1 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_reject: thor, class_tid: 4 */ + /* cond_reject: thor, class_tid: 5 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE @@ -3612,7 +3612,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SKIP } }, - /* class_tid: 3, , table: port_table.wr_0 */ + /* class_tid: 4, , table: port_table.wr_0 */ { .field_info_mask = { .description = "dev.port_id", @@ -3633,7 +3633,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ { .field_info_mask = { .description = "svif", @@ -3653,7 +3653,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .field_info_mask = { .description = "etype", @@ -3958,7 +3958,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { 1} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { .field_info_mask = { .description = "svif", @@ -3978,7 +3978,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd */ { .field_info_mask = { .description = "svif", @@ -3998,7 +3998,7 @@ struct bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[] = { BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .field_info_mask = { .description = "etype", @@ -5187,7 +5187,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: int_full_act_record.0 */ + /* class_tid: 4, , table: int_full_act_record.0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: port_table.wr_0 */ + /* class_tid: 4, , table: port_table.wr_0 */ { .description = "rid", .field_bit_size = 32, @@ -5329,7 +5329,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "prof_func_id", .field_bit_size = 7, @@ -5380,7 +5380,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { .description = "rid", .field_bit_size = 32, @@ -5414,7 +5414,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5434,7 +5434,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_DEFAULT_AREC_PTR & 0xff} }, - /* class_tid: 3, , table: int_full_act_record.egr_0 */ + /* class_tid: 4, , table: int_full_act_record.egr_0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5542,7 +5542,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "prof_func_id", .field_bit_size = 7, @@ -5593,7 +5593,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff} }, - /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5603,7 +5603,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5613,7 +5613,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.loopback */ + /* class_tid: 5, , table: int_full_act_record.loopback */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5721,7 +5721,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5731,7 +5731,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -5741,7 +5741,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.vf_ing */ + /* class_tid: 5, , table: int_full_act_record.vf_ing */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -5849,7 +5849,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 4, , table: vtag_encap_record.vfr_egr0 */ + /* class_tid: 5, , table: vtag_encap_record.vfr_egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -5929,7 +5929,7 @@ struct bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[] = { (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ + /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ { .description = "sp_rec_ptr", .field_bit_size = 16, @@ -6085,7 +6085,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 29 }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -6094,7 +6094,7 @@ struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 29 }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c index b6d2afd55b..de924fe81a 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Thu May 13 18:15:56 2021 */ +/* date: Mon May 17 15:54:03 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c index 85b8950e49..7b6ee03a4b 100644 --- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c +++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_class.c @@ -3,7 +3,7 @@ * All rights reserved. */ -/* date: Fri May 14 10:26:31 2021 */ +/* date: Mon May 17 15:54:03 2021 */ #include "ulp_template_db_enum.h" #include "ulp_template_db_field.h" @@ -22,7 +22,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 0, .cond_nums = 1 } }, - /* class_tid: 2, egress */ + /* class_tid: 2, ingress */ [2] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 15, @@ -32,24 +32,34 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = { .cond_start_idx = 24, .cond_nums = 1 } }, - /* class_tid: 3, ingress */ + /* class_tid: 3, egress */ [3] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 22, + .num_tbls = 15, .start_tbl_idx = 33, + .reject_info = { + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 30, + .cond_nums = 1 } + }, + /* class_tid: 4, ingress */ + [4] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 22, + .start_tbl_idx = 48, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 35, + .cond_start_idx = 41, .cond_nums = 0 } }, - /* class_tid: 4, egress */ - [4] = { + /* class_tid: 5, egress */ + [5] = { .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, .num_tbls = 19, - .start_tbl_idx = 55, + .start_tbl_idx = 70, .reject_info = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE, - .cond_start_idx = 41, + .cond_start_idx = 47, .cond_nums = 0 } } }; @@ -455,58 +465,133 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ + { /* class_tid: 2, , table: tunnel_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 5, + .cond_true_goto = 1, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 25, - .cond_nums = 1 }, + .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, .key_start_idx = 223, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 2, .ident_start_idx = 9, .ident_nums = 1 }, + { /* class_tid: 2, , table: control.tunnel_cache_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 25, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 2, , table: l2_cntxt_tcam.1 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 26, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_IDENT, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 225, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 127, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 10, + .ident_nums = 1 + }, + { /* class_tid: 2, , table: tunnel_cache.wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_TUNNEL_CACHE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 26, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 238, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 2, + .result_start_idx = 140, + .result_bit_size = 52, + .result_num_fields = 3 + }, + { /* class_tid: 2, , table: control.flow_type_check */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 5, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 26, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, { /* class_tid: 2, , table: mac_addr_cache.rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 224, + .key_start_idx = 240, .blob_key_bit_size = 73, .key_bit_size = 73, .key_num_fields = 5, - .ident_start_idx = 10, + .ident_start_idx = 11, .ident_nums = 1 }, - { /* class_tid: 2, , table: control.0 */ + { /* class_tid: 2, , table: control.mac_addr_cache_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 26, + .cond_start_idx = 27, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, @@ -515,12 +600,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { { /* class_tid: 2, , table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -529,323 +614,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 229, + .key_start_idx = 245, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 127, + .result_start_idx = 143, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 11, - .ident_nums = 1 + .ident_start_idx = 12, + .ident_nums = 0 }, { /* class_tid: 2, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 242, + .key_start_idx = 258, .blob_key_bit_size = 73, .key_bit_size = 73, .key_num_fields = 5, - .result_start_idx = 140, + .result_start_idx = 156, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 2, , table: profile_tcam_cache.rd */ + { /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 247, + .key_start_idx = 263, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, .ident_start_idx = 12, .ident_nums = 3 }, - { /* class_tid: 2, , table: control.gen_tbl_miss */ + { /* class_tid: 2, , table: control.profile_tcam_cache.f2_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, + .cond_true_goto = 1, + .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 27, + .cond_start_idx = 28, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 2, , table: control.conflict_check */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 4, - .cond_false_goto = 1023, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 28, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, - .func_info = { - .func_opc = BNXT_ULP_FUNC_OPC_EQ, - .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, - .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, - .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, - .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, - .func_dst_opr = BNXT_ULP_RF_IDX_CC }, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 2, , table: profile_tcam.ipv4 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 2, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 29, - .cond_nums = 1 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 250, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 43, - .result_start_idx = 144, - .result_bit_size = 38, - .result_num_fields = 17, - .ident_start_idx = 15, - .ident_nums = 1 - }, - { /* class_tid: 2, , table: profile_tcam.ipv6 */ + { /* class_tid: 2, , table: profile_tcam.f2 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 1, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 293, + .key_start_idx = 266, .blob_key_bit_size = 81, .key_bit_size = 81, .key_num_fields = 43, - .result_start_idx = 161, + .result_start_idx = 160, .result_bit_size = 38, - .result_num_fields = 17, - .ident_start_idx = 16, - .ident_nums = 1 + .result_num_fields = 17 }, - { /* class_tid: 2, , table: profile_tcam_cache.wr */ + { /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 30, + .cond_start_idx = 29, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 336, + .key_start_idx = 309, .blob_key_bit_size = 14, .key_bit_size = 14, .key_num_fields = 3, - .result_start_idx = 178, + .result_start_idx = 177, .result_bit_size = 122, .result_num_fields = 5 }, - { /* class_tid: 2, , table: em.ipv4 */ + { /* class_tid: 2, , table: em.tun */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_INTERNAL, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 30, - .cond_nums = 2 }, + .cond_start_idx = 29, + .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 339, - .blob_key_bit_size = 176, - .key_bit_size = 176, - .key_num_fields = 10, - .result_start_idx = 183, + .key_start_idx = 312, + .blob_key_bit_size = 112, + .key_bit_size = 112, + .key_num_fields = 8, + .result_start_idx = 182, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, , table: eem.ipv4 */ + { /* class_tid: 2, , table: eem.tun */ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, .resource_type = TF_MEM_EXTERNAL, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 0, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 32, - .cond_nums = 2 }, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 30, + .cond_nums = 0 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 349, + .key_start_idx = 320, .blob_key_bit_size = 448, .key_bit_size = 448, - .key_num_fields = 10, - .result_start_idx = 192, + .key_num_fields = 8, + .result_start_idx = 191, .result_bit_size = 64, .result_num_fields = 9 }, - { /* class_tid: 2, , table: em.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_INTERNAL, + { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 5, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 34, + .cond_start_idx = 31, .cond_nums = 1 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 359, - .blob_key_bit_size = 416, - .key_bit_size = 416, - .key_num_fields = 11, - .result_start_idx = 201, - .result_bit_size = 64, - .result_num_fields = 9 + .key_start_idx = 328, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 15, + .ident_nums = 1 }, - { /* class_tid: 2, , table: eem.ipv6 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, + { /* class_tid: 3, , table: mac_addr_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, + .cond_start_idx = 32, .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 370, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 210, - .result_bit_size = 64, - .result_num_fields = 9 + .key_start_idx = 329, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .ident_start_idx = 16, + .ident_nums = 1 }, - { /* class_tid: 3, , table: int_full_act_record.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 219, - .result_bit_size = 128, - .result_num_fields = 26 - }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 35, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 381, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 17, - .ident_nums = 0 - }, - { /* class_tid: 3, , table: control.ing_0 */ + { /* class_tid: 3, , table: control.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 35, + .cond_start_idx = 32, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + { /* class_tid: 3, , table: l2_cntxt_tcam.0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_RX, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -853,361 +851,240 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 382, + .key_start_idx = 334, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 245, + .result_start_idx = 200, .result_bit_size = 64, .result_num_fields = 13, .ident_start_idx = 17, .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + { /* class_tid: 3, , table: mac_addr_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MAC_ADDR_CACHE, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 33, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_HASH, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 395, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 258, + .key_start_idx = 347, + .blob_key_bit_size = 73, + .key_bit_size = 73, + .key_num_fields = 5, + .result_start_idx = 213, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 262, - .result_bit_size = 32, - .result_num_fields = 1 - }, - { /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, + { /* class_tid: 3, , table: profile_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, + .cond_start_idx = 33, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 263, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 352, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .ident_start_idx = 18, + .ident_nums = 3 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_RX, + { /* class_tid: 3, , table: control.gen_tbl_miss */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 2, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 36, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 264, - .result_bit_size = 32, - .result_num_fields = 1 + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 33, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: control.egr_0 */ + { /* class_tid: 3, , table: control.conflict_check */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, + .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 6, + .cond_true_goto = 4, + .cond_false_goto = 1023, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 36, + .cond_start_idx = 34, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .func_info = { + .func_opc = BNXT_ULP_FUNC_OPC_EQ, + .func_src1 = BNXT_ULP_FUNC_SRC_REGFILE, + .func_opr1 = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .func_src2 = BNXT_ULP_FUNC_SRC_COMP_FIELD, + .func_opr2 = BNXT_ULP_CF_IDX_FLOW_SIG_ID, + .func_dst_opr = BNXT_ULP_RF_IDX_CC }, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 3, , table: int_full_act_record.egr_vfr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 37, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 265, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + { /* class_tid: 3, , table: profile_tcam.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 2, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 37, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 396, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 18, - .ident_nums = 0 - }, - { /* class_tid: 3, , table: control.egr_1 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 37, + .cond_start_idx = 35, .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 355, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 217, + .result_bit_size = 38, + .result_num_fields = 17, + .ident_start_idx = 21, + .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ + { /* class_tid: 3, , table: profile_tcam.ipv6 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 397, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 291, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 18, - .ident_nums = 0 + .key_start_idx = 398, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 43, + .result_start_idx = 234, + .result_bit_size = 38, + .result_num_fields = 17, + .ident_start_idx = 22, + .ident_nums = 1 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ + { /* class_tid: 3, , table: profile_tcam_cache.wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 0, + .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, + .cond_start_idx = 36, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 410, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 304, - .result_bit_size = 62, - .result_num_fields = 4 + .key_start_idx = 441, + .blob_key_bit_size = 14, + .key_bit_size = 14, + .key_num_fields = 3, + .result_start_idx = 251, + .result_bit_size = 122, + .result_num_fields = 5 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + { /* class_tid: 3, , table: em.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 38, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 36, + .cond_nums = 2 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 411, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .ident_start_idx = 18, - .ident_nums = 0 - }, - { /* class_tid: 3, , table: control.egr_2 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 3, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 38, - .cond_nums = 1 }, - .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE - }, - { /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 39, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, - .fdb_operand = BNXT_ULP_RF_IDX_RID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 412, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 308, + .key_start_idx = 444, + .blob_key_bit_size = 176, + .key_bit_size = 176, + .key_num_fields = 10, + .result_start_idx = 256, .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 18, - .ident_nums = 1 + .result_num_fields = 9 }, - { /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + { /* class_tid: 3, , table: eem.ipv4 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 39, + .cond_start_idx = 38, .cond_nums = 2 }, - .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, - .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 425, - .blob_key_bit_size = 8, - .key_bit_size = 8, - .key_num_fields = 1, - .result_start_idx = 321, - .result_bit_size = 62, - .result_num_fields = 4 - }, - { /* class_tid: 3, , table: int_full_act_record.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 325, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 - }, - { /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 351, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 454, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 10, + .result_start_idx = 265, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + { /* class_tid: 3, , table: em.ipv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 41, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 40, + .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 352, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 464, + .blob_key_bit_size = 416, + .key_bit_size = 416, + .key_num_fields = 11, + .result_start_idx = 274, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + { /* class_tid: 3, , table: eem.ipv6 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE, + .resource_type = TF_MEM_EXTERNAL, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 0, @@ -1215,41 +1092,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 41, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, - .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 353, - .result_bit_size = 32, - .result_num_fields = 1 + .key_start_idx = 475, + .blob_key_bit_size = 448, + .key_bit_size = 448, + .key_num_fields = 11, + .result_start_idx = 283, + .result_bit_size = 64, + .result_num_fields = 9 }, - { /* class_tid: 4, , table: int_full_act_record.loopback */ + { /* class_tid: 4, , table: int_full_act_record.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 41, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, - .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 354, + .result_start_idx = 292, .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0 + .result_num_fields = 26 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, @@ -1260,16 +1140,16 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 426, + .key_start_idx = 486, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 19, + .ident_start_idx = 23, .ident_nums = 0 }, - { /* class_tid: 4, , table: control.vf_0 */ + { /* class_tid: 4, , table: control.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 3, @@ -1280,10 +1160,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ + { /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, @@ -1296,22 +1176,24 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 427, + .key_start_idx = 487, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 380, + .result_start_idx = 318, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 19, + .ident_start_idx = 23, .ident_nums = 1 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, @@ -1322,119 +1204,103 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 440, + .key_start_idx = 500, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 393, + .result_start_idx = 331, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 42, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 397, + .result_start_idx = 335, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 42, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 398, + .result_start_idx = 336, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + { /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, .cond_start_idx = 42, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, - .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 399, + .result_start_idx = 337, .result_bit_size = 32, .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.vf_ing */ + { /* class_tid: 4, , table: control.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 6, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 42, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 4, , table: int_full_act_record.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 400, + .result_start_idx = 338, .result_bit_size = 128, .result_num_fields = 26, .encap_num_fields = 0 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .execute_info = { - .cond_true_goto = 1, - .cond_false_goto = 1, - .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, - .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .pri_opcode = BNXT_ULP_PRI_OPC_CONST, - .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 441, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 426, - .result_bit_size = 64, - .result_num_fields = 13, - .ident_start_idx = 20, - .ident_nums = 0 - }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, @@ -1443,33 +1309,33 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 42, + .cond_start_idx = 43, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 454, + .key_start_idx = 501, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .ident_start_idx = 20, + .ident_start_idx = 24, .ident_nums = 0 }, - { /* class_tid: 4, , table: control.vfr_0 */ + { /* class_tid: 4, , table: control.egr_1 */ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, - .direction = TF_DIR_TX, + .direction = TF_DIR_RX, .execute_info = { .cond_true_goto = 1, - .cond_false_goto = 3, + .cond_false_goto = 0, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, - .cond_start_idx = 42, + .cond_start_idx = 43, .cond_nums = 1 }, .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, .fdb_operand = BNXT_ULP_RF_IDX_RID, .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, .direction = TF_DIR_TX, @@ -1477,7 +1343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1486,140 +1352,392 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 455, + .key_start_idx = 502, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 439, + .result_start_idx = 364, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 20, + .ident_start_idx = 24, .ident_nums = 0 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { - .cond_true_goto = 1, + .cond_true_goto = 0, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 44, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 468, + .key_start_idx = 515, .blob_key_bit_size = 8, .key_bit_size = 8, .key_num_fields = 1, - .result_start_idx = 452, + .result_start_idx = 377, .result_bit_size = 62, .result_num_fields = 4 }, - { /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 44, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 456, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12 + .key_start_idx = 516, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 24, + .ident_nums = 0 }, - { /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .execute_info = { + { /* class_tid: 4, , table: control.egr_2 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 44, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 45, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 517, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 381, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 24, + .ident_nums = 1 + }, + { /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 45, + .cond_nums = 2 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 530, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 394, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 4, , table: int_full_act_record.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 468, + .result_start_idx = 398, .result_bit_size = 128, - .result_num_fields = 26 + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 424, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 425, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_COMP_FIELD, + .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 426, + .result_bit_size = 32, + .result_num_fields = 1 }, - { /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */ + { /* class_tid: 5, , table: int_full_act_record.loopback */ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, - .direction = TF_DIR_RX, + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 47, .cond_nums = 0 }, - .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, - .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE, + .tbl_operand = BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_NOP, .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .result_start_idx = 494, + .result_start_idx = 427, .result_bit_size = 128, - .result_num_fields = 26 + .result_num_fields = 26, + .encap_num_fields = 0 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 47, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 531, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 25, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: control.vf_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 47, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + { /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, .execute_info = { .cond_true_goto = 1, .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, - .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, .pri_opcode = BNXT_ULP_PRI_OPC_CONST, .pri_operand = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 469, + .key_start_idx = 532, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 520, + .result_start_idx = 453, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 20, - .ident_nums = 0 + .ident_start_idx = 25, + .ident_nums = 1 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 545, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 466, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 470, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 471, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_IF_TBL_OPC_WR_CONST, + .tbl_operand = ULP_WP_SYM_LOOPBACK_PARIF, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 472, + .result_bit_size = 32, + .result_num_fields = 1 + }, + { /* class_tid: 5, , table: int_full_act_record.vf_ing */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 473, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0 }, - { /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .execute_info = { - .cond_true_goto = 0, - .cond_false_goto = 0, + .cond_true_goto = 1, + .cond_false_goto = 1, .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, - .cond_start_idx = 43, + .cond_start_idx = 48, .cond_nums = 0 }, .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, @@ -1629,19 +1747,224 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = { .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .key_start_idx = 482, + .key_start_idx = 546, .blob_key_bit_size = 167, .key_bit_size = 167, .key_num_fields = 13, - .result_start_idx = 533, + .result_start_idx = 499, .result_bit_size = 64, .result_num_fields = 13, - .ident_start_idx = 20, + .ident_start_idx = 26, .ident_nums = 0 - } -}; - -struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 48, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 559, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .ident_start_idx = 26, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: control.vfr_0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 3, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND, + .cond_start_idx = 48, + .cond_nums = 1 }, + .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE, + .fdb_operand = BNXT_ULP_RF_IDX_RID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 560, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 512, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 26, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE, + .gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 573, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 525, + .result_bit_size = 62, + .result_num_fields = 4 + }, + { /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 529, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12 + }, + { /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 541, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .result_start_idx = 567, + .result_bit_size = 128, + .result_num_fields = 26 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 1, + .cond_false_goto = 1, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 574, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 593, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 26, + .ident_nums = 0 + }, + { /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .execute_info = { + .cond_true_goto = 0, + .cond_false_goto = 0, + .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE, + .cond_start_idx = 49, + .cond_nums = 0 }, + .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE, + .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0, + .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID, + .pri_opcode = BNXT_ULP_PRI_OPC_CONST, + .pri_operand = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .key_start_idx = 587, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 606, + .result_bit_size = 64, + .result_num_fields = 13, + .ident_start_idx = 26, + .ident_nums = 0 + } +}; + +struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { /* cond_reject: wh_plus, class_tid: 1 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, @@ -1751,32 +2074,61 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH }, - /* cond_execute: class_tid: 2, l2_cntxt_tcam_cache.rd */ + /* cond_execute: class_tid: 2, control.tunnel_cache_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.flow_type_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, + .cond_operand = BNXT_ULP_HDR_BIT_F1 + }, + /* cond_execute: class_tid: 2, control.mac_addr_cache_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, control.profile_tcam_cache.f2_check */ + { + .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, + .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS + }, + /* cond_execute: class_tid: 2, em.tun */ + { + .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, + }, + /* cond_reject: wh_plus, class_tid: 3 */ + { + .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_WC_MATCH + }, + /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.rd */ { .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET, .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_SMAC }, - /* cond_execute: class_tid: 2, control.0 */ + /* cond_execute: class_tid: 3, control.0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 2, control.gen_tbl_miss */ + /* cond_execute: class_tid: 3, control.gen_tbl_miss */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 2, control.conflict_check */ + /* cond_execute: class_tid: 3, control.conflict_check */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_CC }, - /* cond_execute: class_tid: 2, profile_tcam.ipv4 */ + /* cond_execute: class_tid: 3, profile_tcam.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 2, em.ipv4 */ + /* cond_execute: class_tid: 3, em.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, }, @@ -1784,7 +2136,7 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 2, eem.ipv4 */ + /* cond_execute: class_tid: 3, eem.ipv4 */ { .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_IS_SET, }, @@ -1792,31 +2144,31 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET, .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4 }, - /* cond_execute: class_tid: 2, em.ipv6 */ + /* cond_execute: class_tid: 3, em.ipv6 */ { .cond_opcode = BNXT_ULP_COND_OPC_EXT_MEM_NOT_SET, }, - /* cond_execute: class_tid: 3, control.ing_0 */ + /* cond_execute: class_tid: 4, control.ing_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, control.egr_0 */ + /* cond_execute: class_tid: 4, control.egr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE }, - /* cond_execute: class_tid: 3, control.egr_1 */ + /* cond_execute: class_tid: 4, control.egr_1 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, control.egr_2 */ + /* cond_execute: class_tid: 4, control.egr_2 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 3, l2_cntxt_tcam_cache.egr_wr */ + /* cond_execute: class_tid: 4, l2_cntxt_tcam_cache.egr_wr */ { .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET, .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE @@ -1825,12 +2177,12 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 4, control.vf_0 */ + /* cond_execute: class_tid: 5, control.vf_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS }, - /* cond_execute: class_tid: 4, control.vfr_0 */ + /* cond_execute: class_tid: 5, control.vfr_0 */ { .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET, .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS @@ -5669,7 +6021,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 2, , table: tunnel_cache.rd */ { .field_info_mask = { .description = "svif", @@ -5690,181 +6042,52 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, - /* class_tid: 2, , table: mac_addr_cache.rd */ { .field_info_mask = { - .description = "svif", + .description = "tunnel_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + 0xff} }, .field_info_spec = { - .description = "svif", + .description = "tunnel_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} } }, + /* class_tid: 2, , table: l2_cntxt_tcam.1 */ { .field_info_mask = { - .description = "tun_hdr", - .field_bit_size = 4, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr", - .field_bit_size = 4, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "one_tag", - .field_bit_size = 1, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "one_tag", - .field_bit_size = 1, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} - } - }, - { - .field_info_mask = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} - }, - .field_info_spec = { - .description = "mac_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} - } - }, - /* class_tid: 2, , table: l2_cntxt_tcam.0 */ - { - .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -5872,19 +6095,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "mac0_addr", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "mac0_addr", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -5892,19 +6109,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "svif", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "svif", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -5968,18 +6179,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -6046,7 +6252,47 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 1} } }, - /* class_tid: 2, , table: mac_addr_cache.wr */ + /* class_tid: 2, , table: tunnel_cache.wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "tunnel_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_TUNNEL_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_TUNNEL_ID & 0xff} + } + }, + /* class_tid: 2, , table: mac_addr_cache.rd */ { .field_info_mask = { .description = "svif", @@ -6072,17 +6318,15 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "tun_hdr", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + 0xff} }, .field_info_spec = { .description = "tun_hdr", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_TUN_HDR_TYPE_NONE} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -6090,60 +6334,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { .description = "vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "vid", .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_HF, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -6153,8 +6364,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { .description = "mac_addr", @@ -6162,204 +6373,166 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 2, , table: profile_tcam_cache.rd */ + /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "l2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 2, , table: profile_tcam.ipv4 */ { .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "l4_hdr_type", + .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_type", + .description = "sparif", .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_error", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_error", - .field_bit_size = 1, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_valid", - .field_bit_size = 1, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_type", + .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -6367,7 +6540,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l3_hdr_type", + .description = "tun_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6375,162 +6548,200 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_error", - .field_bit_size = 1, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "l3_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + 1} } }, + /* class_tid: 2, , table: mac_addr_cache.wr */ { .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} + } + }, + { + .field_info_mask = { + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_vtag_present", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_vtag_present", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, + .description = "vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_uc_mc_bc", - .field_bit_size = 2, + .description = "vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_hdr_type", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "l2_hdr_type", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, + /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ { .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_hdr_valid", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_hdr_valid", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + } + }, + /* class_tid: 2, , table: profile_tcam.f2 */ + { + .field_info_mask = { + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", + .description = "l4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", + .description = "l4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6538,13 +6749,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_err", + .description = "l4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_err", + .description = "l4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6552,15 +6763,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tun_hdr_valid", + .description = "l4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_valid", + .description = "l4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6568,13 +6777,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", + .description = "l3_ipv6_cmp_dst", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6582,27 +6791,27 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl4_hdr_error", + .description = "l3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_error", + .description = "l3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6610,29 +6819,44 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "l3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV4}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", + .description = "l3_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", + .description = "l3_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6640,27 +6864,31 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_src", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_ipv6_cmp_src", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "tl3_hdr_isIP", + .description = "l2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_isIP", + .description = "l2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6668,57 +6896,55 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_two_vtags", + .description = "l2_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_two_vtags", + .description = "l2_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6726,13 +6952,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_vtag_present", + .description = "l2_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_vtag_present", + .description = "l2_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6740,35 +6966,37 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_hdr_valid", + .description = "tun_hdr_err", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -6776,7 +7004,7 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "tl2_hdr_valid", + .description = "tun_hdr_err", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6784,68 +7012,65 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "hrec_next", + .description = "tun_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "hrec_next", + .description = "tun_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TUN_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tl4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "tl4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + ULP_WP_SYM_TL4_HDR_TYPE_UDP} } }, { .field_info_mask = { - .description = "agg_error", + .description = "tl4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "agg_error", + .description = "tl4_hdr_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -6853,159 +7078,137 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TL4_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", + .description = "tl3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "valid", + .description = "tl3_hdr_isIP", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 2, , table: profile_tcam.ipv6 */ { .field_info_mask = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_ONES, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + 0xff} }, .field_info_spec = { - .description = "l4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, - .field_opr1 = { - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, - (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr2 = { - ULP_WP_SYM_L4_HDR_TYPE_TCP}, - .field_src3 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr3 = { - ULP_WP_SYM_L4_HDR_TYPE_UDP} + .description = "tl3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4_hdr_error", + .description = "tl3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + 0xff} }, .field_info_spec = { - .description = "l4_hdr_error", + .description = "tl3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_TL3_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "l4_hdr_valid", + .description = "tl2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4_hdr_valid", + .description = "tl2_two_vtags", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_ipv6_cmp_dst", + .description = "tl2_vtag_present", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_ipv6_cmp_dst", + .description = "tl2_vtag_present", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7013,61 +7216,61 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_isIP", - .field_bit_size = 1, + .description = "tl2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3_hdr_type", - .field_bit_size = 4, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3_hdr_type", - .field_bit_size = 4, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L3_HDR_TYPE_IPV6} + ULP_WP_SYM_TL2_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "l3_hdr_error", + .description = "hrec_next", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_error", + .description = "hrec_next", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7075,68 +7278,60 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3_hdr_valid", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - ULP_WP_SYM_L3_HDR_VALID_YES} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l2_two_vtags", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "l2_vtag_present", + .description = "agg_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_vtag_present", + .description = "agg_error", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_uc_mc_bc", + .description = "recycle_cnt", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_uc_mc_bc", + .description = "recycle_cnt", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7144,15 +7339,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_type", + .description = "pkt_type_0", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_hdr_type", + .description = "pkt_type_0", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -7160,1487 +7353,1459 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_hdr_error", - .field_bit_size = 1, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "l2_hdr_valid", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - ULP_WP_SYM_L2_HDR_VALID_YES} + 1} } }, + /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ { .field_info_mask = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_flags", - .field_bit_size = 3, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_err", - .field_bit_size = 1, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, + /* class_tid: 2, , table: em.tun */ { .field_info_mask = { - .description = "tun_hdr_valid", - .field_bit_size = 1, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_valid", - .field_bit_size = 1, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_is_udp_tcp", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl4_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "tl4_hdr_type", - .field_bit_size = 4, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} }, .field_info_spec = { - .description = "tl4_hdr_error", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} } }, { .field_info_mask = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl4_hdr_valid", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_ipv6_cmp_dst", - .field_bit_size = 1, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl3_ipv6_cmp_src", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl3_hdr_isIP", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 2, , table: eem.tun */ { .field_info_mask = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 339, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 339, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl3_hdr_error", - .field_bit_size = 1, + .description = "l2.ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "tl3_hdr_valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_I_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_I_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "tl2_two_vtags", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} }, .field_info_spec = { - .description = "tl2_two_vtags", - .field_bit_size = 1, + .description = "tun_id", + .field_bit_size = 24, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI & 0xff} } }, { .field_info_mask = { - .description = "tl2_vtag_present", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_vtag_present", - .field_bit_size = 1, + .description = "tun_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_uc_mc_bc", - .field_bit_size = 2, + .description = "tun_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_hdr_type", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "tl2_hdr_valid", - .field_bit_size = 1, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "hrec_next", - .field_bit_size = 1, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, + /* class_tid: 3, , table: mac_addr_cache.rd */ { .field_info_mask = { - .description = "reserved", - .field_bit_size = 9, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "reserved", - .field_bit_size = 9, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "tun_hdr", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "agg_error", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "agg_error", + .description = "one_tag", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { - .description = "pkt_type_0", - .field_bit_size = 2, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, + /* class_tid: 3, , table: l2_cntxt_tcam.0 */ { .field_info_mask = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "pkt_type_1", - .field_bit_size = 2, + .description = "l2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "mac0_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, - /* class_tid: 2, , table: profile_tcam_cache.wr */ { .field_info_mask = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "recycle_cnt", - .field_bit_size = 2, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "prof_func_id", - .field_bit_size = 7, + .description = "sparif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr2 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr3 = { - (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "hdr_sig_id", - .field_bit_size = 5, + .description = "tl2_ivlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 2, , table: em.ipv4 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "tl2_ovlan_vid", + .field_bit_size = 12, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac1_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "l2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff} } }, { .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "tl2_num_vtags", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "key_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 32, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + 1} }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 32, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + 1} } }, + /* class_tid: 3, , table: mac_addr_cache.wr */ { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff} } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff, - 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tun_hdr", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + ULP_WP_SYM_TUN_HDR_TYPE_NONE} } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "one_tag", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "one_tag", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, - /* class_tid: 2, , table: eem.ipv4 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 275, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_OO_VLAN & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_HF, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "mac_addr", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} } }, + /* class_tid: 3, , table: profile_tcam_cache.rd */ { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "recycle_cnt", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "hdr_sig_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, + /* class_tid: 3, , table: profile_tcam.ipv4 */ { .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 32, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 32, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} } }, { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - 0xff, - 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 2, , table: em.ipv6 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 3, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "l3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3_hdr_error", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "l3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .description = "l3_hdr_valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + ULP_WP_SYM_L3_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 128, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 128, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 128, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + 0xff} }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 128, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, { .field_info_mask = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + 0xff} }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + ULP_WP_SYM_L2_HDR_VALID_YES} } }, - /* class_tid: 2, , table: eem.ipv6 */ { .field_info_mask = { - .description = "spare", - .field_bit_size = 35, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "spare", - .field_bit_size = 35, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "local_cos", - .field_bit_size = 3, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l4.dst", - .field_bit_size = 16, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l4.dst", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l4.src", - .field_bit_size = 16, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff, - 0xff} - }, - .field_info_spec = { - .description = "l4.src", - .field_bit_size = 16, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.prot", - .field_bit_size = 8, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "l3.prot", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_CF, - .field_opr2 = { - (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l3.dst", - .field_bit_size = 128, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} - }, - .field_info_spec = { - .description = "l3.dst", - .field_bit_size = 128, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l3.src", - .field_bit_size = 128, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l3.src", - .field_bit_size = 128, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "tl4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2.smac", - .field_bit_size = 48, + .description = "tl4_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2.dmac", - .field_bit_size = 48, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_HF, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 0xff, 0xff} }, .field_info_spec = { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "tl4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_rd */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -8648,491 +8813,511 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - } - }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ - { - .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + 1} } }, + /* class_tid: 3, , table: profile_tcam.ipv6 */ { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_ONES, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l4_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_HDR_BIT, + .field_opr1 = { + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff, + (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr2 = { + ULP_WP_SYM_L4_HDR_TYPE_TCP}, + .field_src3 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr3 = { + ULP_WP_SYM_L4_HDR_TYPE_UDP} + } + }, + { + .field_info_mask = { + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l4_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff} } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", + .description = "l3_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", + .description = "l3_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + ULP_WP_SYM_L3_HDR_TYPE_IPV6} } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff} }, .field_info_spec = { - .description = "valid", + .description = "l3_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + ULP_WP_SYM_L3_HDR_VALID_YES} } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff} } }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l2_hdr_type", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l2_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} - } - }, - { - .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + ULP_WP_SYM_L2_HDR_VALID_YES} } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_flags", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tun_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tun_hdr_err", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "tun_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl4_hdr_is_udp_tcp", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", + .description = "tl4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", + .description = "tl4_hdr_type", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -9140,203 +9325,171 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "tl4_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", + .description = "tl4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff} }, .field_info_spec = { - .description = "valid", + .description = "tl4_hdr_valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_dst", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_rd_egr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_ipv6_cmp_src", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_isIP", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "tl3_hdr_type", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "tl3_hdr_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "tl3_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "tl2_two_vtags", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "tl2_vtag_present", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "tl2_uc_mc_bc", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", + .description = "tl2_hdr_type", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO @@ -9344,280 +9497,294 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "tl2_hdr_valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "hrec_next", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "reserved", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "agg_error", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "pkt_type_0", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "pkt_type_1", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 0xff} + 1} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + 1} } }, + /* class_tid: 3, , table: profile_tcam_cache.wr */ { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "recycle_cnt", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr2 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr3 = { + (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff} } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "hdr_sig_id", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff} } }, + /* class_tid: 3, , table: em.ipv4 */ { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - }, - .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO - } - }, - { - .field_info_mask = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} - }, - .field_info_spec = { - .description = "valid", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - 1} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ { .field_info_mask = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -9625,211 +9792,305 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "mac0_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "mac0_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "svif", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 3, , table: eem.ipv4 */ { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 275, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", - .field_bit_size = 48, + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac1_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "l3.prot", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "l3.src", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "l2.dmac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, .field_opr1 = { - 1} + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .field_info_mask = { - .description = "svif", + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -9837,34 +10098,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "svif", + .description = "em_profile_id", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + /* class_tid: 3, , table: em.ipv6 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "spare", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "local_cos", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -9872,32 +10147,48 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_ovlan_vid", - .field_bit_size = 12, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac0_addr", - .field_bit_size = 48, + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} }, .field_info_spec = { - .description = "mac0_addr", - .field_bit_size = 48, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, @@ -9905,154 +10196,314 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "svif", + .description = "l3.prot", .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} }, .field_info_spec = { - .description = "sparif", - .field_bit_size = 4, + .description = "l3.dst", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} } }, { .field_info_mask = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, .field_info_spec = { - .description = "tl2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.src", + .field_bit_size = 128, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} } }, { .field_info_mask = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l2.smac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tl2_ovlan_vid", - .field_bit_size = 12, + .description = "l2.smac", + .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "mac1_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} }, .field_info_spec = { - .description = "mac1_addr", + .description = "l2.dmac", .field_bit_size = 48, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} } }, { .field_info_mask = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { + 0xff, 0xff} }, .field_info_spec = { - .description = "l2_num_vtags", - .field_bit_size = 2, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 2} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} } }, { .field_info_mask = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} }, .field_info_spec = { - .description = "tl2_num_vtags", - .field_bit_size = 2, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} } }, + /* class_tid: 3, , table: eem.ipv6 */ { .field_info_mask = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 35, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "tun_hdr_type", - .field_bit_size = 4, + .description = "spare", + .field_bit_size = 35, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "key_type", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { - .description = "key_type", - .field_bit_size = 2, + .description = "local_cos", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { .field_info_mask = { - .description = "valid", - .field_bit_size = 1, + .description = "l4.dst", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff, + 0xff} }, .field_info_spec = { - .description = "valid", - .field_bit_size = 1, + .description = "l4.dst", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_DST_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l4.src", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { - 1} + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l4.src", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L4_SRC_PORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO } }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .field_info_mask = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l3.prot", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_THEN_SRC2_ELSE_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_CF, + .field_opr2 = { + (BNXT_ULP_CF_IDX_O_L3_PROTO_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L3_PROTO_ID & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l3.dst", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + .field_info_spec = { + .description = "l3.dst", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "l3.src", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + }, + .field_info_spec = { + .description = "l3.src", + .field_bit_size = 128, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2.smac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + }, + .field_info_spec = { + .description = "l2.dmac", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_HF, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ONES, .field_opr1 = { @@ -10060,13 +10511,67 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { 0xff} }, .field_info_spec = { - .description = "l2_ivlan_vid", - .field_bit_size = 12, + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + } + }, + { + .field_info_mask = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -10112,8 +10617,8 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} } }, { @@ -10177,17 +10682,13 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ONES, - .field_opr1 = { - 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, .field_info_spec = { .description = "l2_num_vtags", .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO } }, { @@ -10249,529 +10750,2581 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = { .field_opr1 = { 1} } - } -}; - -struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { - /* class_tid: 1, , table: l2_cntxt_tcam.0 */ - { - .description = "l2_cntxt_id", - .field_bit_size = 10, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { - .description = "prof_func_id", - .field_bit_size = 7, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, - .field_opr1 = { - (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff} + } }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_rd_vfr */ { - .description = "l2_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.rd */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_rd_egr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_rd_egr0 */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 2} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + { + .field_info_mask = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff, + 0xff} + }, + .field_info_spec = { + .description = "l2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff} + } + }, + { + .field_info_mask = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "l2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac0_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "svif", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff} + } + }, + { + .field_info_mask = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "sparif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ivlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_ovlan_vid", + .field_bit_size = 12, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "mac1_addr", + .field_bit_size = 48, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ONES, + .field_opr1 = { + 0xff} + }, + .field_info_spec = { + .description = "l2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + }, + { + .field_info_mask = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tl2_num_vtags", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "tun_hdr_type", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + .field_info_spec = { + .description = "key_type", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + } + }, + { + .field_info_mask = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + .field_info_spec = { + .description = "valid", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + } + } +}; + +struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { + /* class_tid: 1, , table: l2_cntxt_tcam.0 */ + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "prof_func_id", + .field_bit_size = 7, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, + .field_opr1 = { + (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff} + }, + { + .description = "l2_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + { + .description = "allowed_pri", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_pri", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "allowed_tpid", + .field_bit_size = 6, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "default_tpid", + .field_bit_size = 3, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "bd_act_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "sp_rec_ptr", + .field_bit_size = 16, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "byp_sp_lkup", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "l2_cntxt_id", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + }, + { + .description = "src_property_ptr", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam.ipv4 */ + { + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + }, + { + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam.ipv6 */ + { + .description = "wc_key_id", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} }, { - .description = "parif", + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr1 = { + (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_L4 & 0xff}, + .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr2 = { + (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, + .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_opr3 = { + (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 7} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ + { + .description = "wc_key_id", .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "wc_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.0", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.1", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.2", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.3", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.4", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.5", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.6", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "em_key_mask.7", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.8", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_mask.9", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 20} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "em_search_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} + }, + { + .description = "pl_byp_lkup_en", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 1, , table: profile_tcam_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, + { + .description = "profile_tcam_index", + .field_bit_size = 10, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + }, + { + .description = "em_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + }, + { + .description = "wc_profile_id", + .field_bit_size = 8, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "flow_sig_id", + .field_bit_size = 64, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, + /* class_tid: 1, , table: em.ipv4 */ { - .description = "allowed_pri", - .field_bit_size = 8, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "default_pri", - .field_bit_size = 3, + .description = "ext_flow_cntr", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "allowed_tpid", - .field_bit_size = 6, + .description = "act_rec_int", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "default_tpid", - .field_bit_size = 3, + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "bd_act_en", - .field_bit_size = 1, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "sp_rec_ptr", - .field_bit_size = 16, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "byp_sp_lkup", - .field_bit_size = 1, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 3} }, { - .description = "pri_anti_spoof_ctl", - .field_bit_size = 2, + .description = "l1_cacheable", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "tpid_anti_spoof_ctl", - .field_bit_size = 2, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, - /* class_tid: 1, , table: mac_addr_cache.wr */ + /* class_tid: 1, , table: eem.ipv4 */ { - .description = "rid", - .field_bit_size = 32, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, - BNXT_ULP_RF_IDX_RID & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "l2_cntxt_tcam_index", - .field_bit_size = 10, + .description = "ext_flow_cntr", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l2_cntxt_id", - .field_bit_size = 10, + .description = "act_rec_int", + .field_bit_size = 1, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .description = "src_property_ptr", - .field_bit_size = 10, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + (173 >> 8) & 0xff, + 173 & 0xff} }, - /* class_tid: 1, , table: profile_tcam.ipv4 */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .description = "wc_search_en", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.0", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, + /* class_tid: 1, , table: em.ipv6 */ { - .description = "em_key_mask.1", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "em_key_mask.2", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.3", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.4", - .field_bit_size = 1, + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "key_size", + .field_bit_size = 9, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID & 0xff} + 3} }, { - .description = "em_key_mask.5", + .description = "l1_cacheable", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, - .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.6", + .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + 1} }, + /* class_tid: 1, , table: eem.ipv6 */ { - .description = "em_key_mask.7", - .field_bit_size = 1, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "em_key_mask.8", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.9", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", + .description = "act_rec_size", .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 3} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (413 >> 8) & 0xff, + 413 & 0xff} }, { - .description = "em_search_en", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 11, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 3} }, { - .description = "pl_byp_lkup_en", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, , table: profile_tcam.ipv6 */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "valid", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, + /* class_tid: 1, , table: em.vxlan */ { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "act_rec_ptr", + .field_bit_size = 33, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "wc_search_en", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.0", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.1", - .field_bit_size = 1, + .description = "act_rec_size", + .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.2", - .field_bit_size = 1, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_ETH_SMAC >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_ETH_SMAC & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.3", - .field_bit_size = 1, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.4", - .field_bit_size = 1, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR & 0xff} + 3} }, { - .description = "em_key_mask.5", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr1 = { - (BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.6", + .description = "valid", .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff} + 1} }, + /* class_tid: 1, , table: eem.vxlan */ { - .description = "em_key_mask.7", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1_AND_SRC2_OR_SRC3, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .description = "act_rec_ptr", + .field_bit_size = 33, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_O_L4 >> 8) & 0xff, - BNXT_ULP_CF_IDX_O_L4 & 0xff}, - .field_src2 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr2 = { - (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}, - .field_src3 = BNXT_ULP_FIELD_SRC_FIELD_BIT, - .field_opr3 = { - (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff, - BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff} + (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, { - .description = "em_key_mask.8", + .description = "ext_flow_cntr", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.9", + .description = "act_rec_int", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", + .description = "act_rec_size", .field_bit_size = 5, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 7} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, + BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} }, { - .description = "em_search_en", - .field_bit_size = 1, + .description = "key_size", + .field_bit_size = 9, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} - }, - { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (197 >> 8) & 0xff, + 197 & 0xff} }, - /* class_tid: 1, , table: profile_tcam.ipv4_vxlan */ { - .description = "wc_key_id", - .field_bit_size = 4, + .description = "reserved", + .field_bit_size = 11, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "wc_profile_id", - .field_bit_size = 8, + .description = "strength", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 3} }, { - .description = "wc_search_en", + .description = "l1_cacheable", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.0", + .description = "valid", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, + /* class_tid: 2, , table: l2_cntxt_tcam.1 */ { - .description = "em_key_mask.1", - .field_bit_size = 1, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.2", - .field_bit_size = 1, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.3", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.4", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.5", - .field_bit_size = 1, + .description = "allowed_pri", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.6", - .field_bit_size = 1, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 1} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.7", - .field_bit_size = 1, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.8", - .field_bit_size = 1, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_mask.9", + .description = "bd_act_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_key_id", - .field_bit_size = 5, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 20} - }, - { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_search_en", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, @@ -10779,12 +13332,18 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { 1} }, { - .description = "pl_byp_lkup_en", - .field_bit_size = 1, + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 1, , table: profile_tcam_cache.wr */ + { + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + /* class_tid: 2, , table: tunnel_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -10795,299 +13354,303 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "profile_tcam_index", + .description = "l2_cntxt_tcam_index", .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "em_profile_id", - .field_bit_size = 8, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} - }, - { - .description = "wc_profile_id", - .field_bit_size = 8, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, + /* class_tid: 2, , table: l2_cntxt_tcam.0 */ { - .description = "flow_sig_id", - .field_bit_size = 64, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, - /* class_tid: 1, , table: em.ipv4 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "prof_func_id", + .field_bit_size = 7, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_RF_IDX_VXLAN_PROF_FUNC_ID & 0xff} }, { - .description = "ext_flow_cntr", + .description = "l2_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_int", - .field_bit_size = 1, + .description = "parif", + .field_bit_size = 4, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, + .field_opr1 = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff} + }, + { + .description = "allowed_pri", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "default_pri", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "key_size", - .field_bit_size = 9, + .description = "allowed_tpid", + .field_bit_size = 6, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", - .field_bit_size = 11, + .description = "default_tpid", + .field_bit_size = 3, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "bd_act_en", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", - .field_bit_size = 1, + .description = "sp_rec_ptr", + .field_bit_size = 16, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "byp_sp_lkup", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, - /* class_tid: 1, , table: eem.ipv4 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "pri_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, - .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "ext_flow_cntr", - .field_bit_size = 1, + .description = "tpid_anti_spoof_ctl", + .field_bit_size = 2, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, , table: mac_addr_cache.wr */ + { + .description = "rid", + .field_bit_size = 32, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_opr1 = { + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} + }, { - .description = "act_rec_int", - .field_bit_size = 1, + .description = "l2_cntxt_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "l2_cntxt_id", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff} }, { - .description = "key_size", - .field_bit_size = 9, + .description = "src_property_ptr", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - (173 >> 8) & 0xff, - 173 & 0xff} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, , table: profile_tcam.f2 */ { - .description = "reserved", - .field_bit_size = 11, + .description = "wc_key_id", + .field_bit_size = 4, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "wc_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", + .description = "wc_search_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "em_key_mask.0", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { 1} }, - /* class_tid: 1, , table: em.ipv6 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "em_key_mask.1", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_RF, + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + 1} }, { - .description = "ext_flow_cntr", + .description = "em_key_mask.2", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "act_rec_int", + .description = "em_key_mask.3", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "em_key_mask.4", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "key_size", - .field_bit_size = 9, + .description = "em_key_mask.5", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "reserved", - .field_bit_size = 11, + .description = "em_key_mask.6", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "strength", - .field_bit_size = 2, + .description = "em_key_mask.7", + .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, - .field_opr1 = { - 3} + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "l1_cacheable", + .description = "em_key_mask.8", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", + .description = "em_key_mask.9", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, + .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + }, + { + .description = "em_key_id", + .field_bit_size = 5, + .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - 1} + 8} }, - /* class_tid: 1, , table: eem.ipv6 */ { - .description = "act_rec_ptr", - .field_bit_size = 33, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "ext_flow_cntr", + .description = "em_search_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_opr1 = { + 1} }, { - .description = "act_rec_int", + .description = "pl_byp_lkup_en", .field_bit_size = 1, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, + /* class_tid: 2, , table: profile_tcam_cache.f2_wr */ { - .description = "act_rec_size", - .field_bit_size = 5, + .description = "rid", + .field_bit_size = 32, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff, - BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff} + (BNXT_ULP_RF_IDX_RID >> 8) & 0xff, + BNXT_ULP_RF_IDX_RID & 0xff} }, { - .description = "key_size", - .field_bit_size = 9, + .description = "profile_tcam_index", + .field_bit_size = 10, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - (413 >> 8) & 0xff, - 413 & 0xff} - }, - { - .description = "reserved", - .field_bit_size = 11, - .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_ZERO + (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff} }, { - .description = "strength", - .field_bit_size = 2, + .description = "em_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_RF, .field_opr1 = { - 3} + (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff} }, { - .description = "l1_cacheable", - .field_bit_size = 1, + .description = "wc_profile_id", + .field_bit_size = 8, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, { - .description = "valid", - .field_bit_size = 1, + .description = "flow_sig_id", + .field_bit_size = 64, .field_opc = BNXT_ULP_FIELD_OPC_SRC1, - .field_src1 = BNXT_ULP_FIELD_SRC_CONST, + .field_src1 = BNXT_ULP_FIELD_SRC_CF, .field_opr1 = { - 1} + (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, - /* class_tid: 1, , table: em.vxlan */ + /* class_tid: 2, , table: em.tun */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11149,7 +13712,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 1, , table: eem.vxlan */ + /* class_tid: 2, , table: eem.tun */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11186,8 +13749,8 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_CONST, .field_opr1 = { - (197 >> 8) & 0xff, - 197 & 0xff} + (109 >> 8) & 0xff, + 109 & 0xff} }, { .description = "reserved", @@ -11217,7 +13780,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: l2_cntxt_tcam.0 */ + /* class_tid: 3, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -11317,7 +13880,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: mac_addr_cache.wr */ + /* class_tid: 3, , table: mac_addr_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -11351,7 +13914,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: profile_tcam.ipv4 */ + /* class_tid: 3, , table: profile_tcam.ipv4 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -11497,7 +14060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: profile_tcam.ipv6 */ + /* class_tid: 3, , table: profile_tcam.ipv6 */ { .description = "wc_key_id", .field_bit_size = 4, @@ -11643,7 +14206,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 2, , table: profile_tcam_cache.wr */ + /* class_tid: 3, , table: profile_tcam_cache.wr */ { .description = "rid", .field_bit_size = 32, @@ -11686,7 +14249,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff, BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff} }, - /* class_tid: 2, , table: em.ipv4 */ + /* class_tid: 3, , table: em.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11748,7 +14311,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: eem.ipv4 */ + /* class_tid: 3, , table: eem.ipv4 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11816,7 +14379,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: em.ipv6 */ + /* class_tid: 3, , table: em.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11878,7 +14441,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 2, , table: eem.ipv6 */ + /* class_tid: 3, , table: eem.ipv6 */ { .description = "act_rec_ptr", .field_bit_size = 33, @@ -11946,7 +14509,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opr1 = { 1} }, - /* class_tid: 3, , table: int_full_act_record.ing_0 */ + /* class_tid: 4, , table: int_full_act_record.ing_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12106,7 +14669,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -12196,7 +14759,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.ing_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.ing_wr */ { .description = "rid", .field_bit_size = 32, @@ -12230,7 +14793,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: parif_def_lkup_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_lkup_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12240,7 +14803,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12250,7 +14813,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.ing_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.ing_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12260,7 +14823,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: int_full_act_record.egr_vfr */ + /* class_tid: 4, , table: int_full_act_record.egr_vfr */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12420,7 +14983,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_bypass.egr_vfr */ + /* class_tid: 4, , table: l2_cntxt_tcam_bypass.egr_vfr */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -12508,7 +15071,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr_vfr */ { .description = "rid", .field_bit_size = 32, @@ -12539,7 +15102,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -12629,7 +15192,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: l2_cntxt_tcam_cache.egr_wr */ + /* class_tid: 4, , table: l2_cntxt_tcam_cache.egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -12663,7 +15226,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: int_full_act_record.egr_0 */ + /* class_tid: 4, , table: int_full_act_record.egr_0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -12823,7 +15386,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 3, , table: parif_def_lkup_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_lkup_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12833,7 +15396,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12843,7 +15406,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 3, , table: parif_def_err_arec_ptr.egr_0 */ + /* class_tid: 4, , table: parif_def_err_arec_ptr.egr_0 */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -12853,7 +15416,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff, BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.loopback */ + /* class_tid: 5, , table: int_full_act_record.loopback */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13013,7 +15576,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ + /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .field_bit_size = 10, @@ -13102,7 +15665,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vf_egr_wr */ + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vf_egr_wr */ { .description = "rid", .field_bit_size = 32, @@ -13136,7 +15699,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: parif_def_lkup_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_lkup_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13146,7 +15709,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: parif_def_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13156,7 +15719,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: parif_def_err_arec_ptr.vf_egr */ + /* class_tid: 5, , table: parif_def_err_arec_ptr.vf_egr */ { .description = "act_rec_ptr", .field_bit_size = 32, @@ -13166,7 +15729,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff, BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff} }, - /* class_tid: 4, , table: int_full_act_record.vf_ing */ + /* class_tid: 5, , table: int_full_act_record.vf_ing */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13326,7 +15889,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vf_ing */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vf_ing */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13412,7 +15975,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_egr0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -13497,7 +16060,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_cache.vfr_wr_egr0 */ { .description = "rid", .field_bit_size = 32, @@ -13528,7 +16091,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: int_vtag_encap_record.vfr_egr0 */ + /* class_tid: 5, , table: int_vtag_encap_record.vfr_egr0 */ { .description = "ecv_tun_type", .field_bit_size = 3, @@ -13611,7 +16174,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: int_full_act_record.vfr_egr0 */ + /* class_tid: 5, , table: int_full_act_record.vfr_egr0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13774,7 +16337,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: int_full_act_record.vfr_ing0 */ + /* class_tid: 5, , table: int_full_act_record.vfr_ing0 */ { .description = "flow_cntr_ptr", .field_bit_size = 14, @@ -13936,7 +16499,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_dtagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -14022,7 +16585,7 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = { .field_opc = BNXT_ULP_FIELD_OPC_SRC1, .field_src1 = BNXT_ULP_FIELD_SRC_ZERO }, - /* class_tid: 4, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ + /* class_tid: 5, , table: l2_cntxt_tcam_bypass.vfr_stagged_ing0 */ { .description = "act_record_ptr", .field_bit_size = 16, @@ -14180,13 +16743,22 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 2, , table: l2_cntxt_tcam_cache.rd */ + /* class_tid: 2, , table: tunnel_cache.rd */ { .description = "l2_cntxt_id", .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 42 }, + /* class_tid: 2, , table: l2_cntxt_tcam.1 */ + { + .description = "l2_cntxt_id", + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, /* class_tid: 2, , table: mac_addr_cache.rd */ { .description = "l2_cntxt_id", @@ -14194,7 +16766,40 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 42 }, - /* class_tid: 2, , table: l2_cntxt_tcam.0 */ + /* class_tid: 2, , table: profile_tcam_cache.f2_rd */ + { + .description = "em_profile_id", + .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, + .ident_bit_size = 8, + .ident_bit_pos = 42 + }, + { + .description = "flow_sig_id", + .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID, + .ident_bit_size = 64, + .ident_bit_pos = 58 + }, + { + .description = "profile_tcam_index", + .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0, + .ident_bit_size = 10, + .ident_bit_pos = 32 + }, + /* class_tid: 3, , table: l2_cntxt_tcam_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + /* class_tid: 3, , table: mac_addr_cache.rd */ + { + .description = "l2_cntxt_id", + .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 42 + }, + /* class_tid: 3, , table: l2_cntxt_tcam.0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14203,7 +16808,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 2, , table: profile_tcam_cache.rd */ + /* class_tid: 3, , table: profile_tcam_cache.rd */ { .description = "em_profile_id", .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0, @@ -14222,7 +16827,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 32 }, - /* class_tid: 2, , table: profile_tcam.ipv4 */ + /* class_tid: 3, , table: profile_tcam.ipv4 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14231,7 +16836,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 2, , table: profile_tcam.ipv6 */ + /* class_tid: 3, , table: profile_tcam.ipv6 */ { .description = "em_profile_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14240,7 +16845,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 8, .ident_bit_pos = 28 }, - /* class_tid: 3, , table: l2_cntxt_tcam.ing_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.ing_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14249,7 +16854,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 3, , table: l2_cntxt_tcam.egr_0 */ + /* class_tid: 4, , table: l2_cntxt_tcam.egr_0 */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, @@ -14258,7 +16863,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = { .ident_bit_size = 10, .ident_bit_pos = 0 }, - /* class_tid: 4, , table: l2_cntxt_tcam.vf_egr */ + /* class_tid: 5, , table: l2_cntxt_tcam.vf_egr */ { .description = "l2_cntxt_id", .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 22c51976ac..d6b4f93d31 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -413,11 +413,13 @@ static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt, } /* Update the parent counters if it is child flow */ - if (sw_acc_tbl_entry->parent_flow_id) { + if (sw_acc_tbl_entry->pc_flow_idx & FLOW_CNTR_PC_FLOW_VALID) { + uint32_t pc_idx; + /* Update the parent counters */ t_sw = sw_acc_tbl_entry; - if (ulp_flow_db_parent_flow_count_update(ctxt, - t_sw->parent_flow_id, + pc_idx = t_sw->pc_flow_idx & ~FLOW_CNTR_PC_FLOW_VALID; + if (ulp_flow_db_parent_flow_count_update(ctxt, pc_idx, t_sw->pkt_count, t_sw->byte_count)) { PMD_DRV_LOG(ERR, "Error updating parent counters\n"); @@ -658,6 +660,7 @@ int32_t ulp_fc_mgr_cntr_reset(struct bnxt_ulp_context *ctxt, enum tf_dir dir, ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].hw_cntr_id = 0; ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pkt_count = 0; ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].byte_count = 0; + ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = 0; ulp_fc_info->num_entries--; pthread_mutex_unlock(&ulp_fc_info->fc_lock); @@ -688,6 +691,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, uint32_t hw_cntr_id = 0, sw_cntr_idx = 0; struct sw_acc_counter *sw_acc_tbl_entry; bool found_cntr_resource = false; + bool found_parent_flow = false; + uint32_t pc_idx = 0; ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt); if (!ulp_fc_info) @@ -707,12 +712,16 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, (params.resource_sub_type == BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT || params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT || - params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC)) { + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_EXT_COUNT)) { found_cntr_resource = true; break; } + if (params.resource_func == + BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) { + found_parent_flow = true; + pc_idx = params.resource_hndl; + } + } while (!rc && nxt_resource_index); bnxt_ulp_cntxt_release_fdb_lock(ctxt); @@ -722,7 +731,8 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, dir = params.direction; hw_cntr_id = params.resource_hndl; - if (params.resource_sub_type == + if (!found_parent_flow && + params.resource_sub_type == BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { if (!ulp_fc_info->num_counters) return ulp_fc_tf_flow_stat_get(ctxt, ¶ms, count); @@ -745,14 +755,17 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, sw_acc_tbl_entry->byte_count = 0; } pthread_mutex_unlock(&ulp_fc_info->fc_lock); - } else if (params.resource_sub_type == - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT_ACC) { + } else if (found_parent_flow && + params.resource_sub_type == + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) { /* Get stats from the parent child table */ - ulp_flow_db_parent_flow_count_get(ctxt, flow_id, + ulp_flow_db_parent_flow_count_get(ctxt, pc_idx, &count->hits, &count->bytes, count->reset); - count->hits_set = 1; - count->bytes_set = 1; + if (count->hits) + count->hits_set = 1; + if (count->bytes) + count->bytes_set = 1; } else { /* TBD: Handle External counters */ rc = -EINVAL; @@ -770,13 +783,13 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt, * * hw_cntr_id [in] The HW flow counter ID * - * fid [in] parent flow id + * pc_idx [in] parent child db index * */ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir, uint32_t hw_cntr_id, - uint32_t fid) + uint32_t pc_idx) { struct bnxt_ulp_fc_info *ulp_fc_info; uint32_t sw_cntr_idx; @@ -789,10 +802,11 @@ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt, pthread_mutex_lock(&ulp_fc_info->fc_lock); sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx; if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) { - ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid; + pc_idx |= FLOW_CNTR_PC_FLOW_VALID; + ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].pc_flow_idx = pc_idx; } else { BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n", - hw_cntr_id, fid); + hw_cntr_id, pc_idx); rc = -ENOENT; } pthread_mutex_unlock(&ulp_fc_info->fc_lock); diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h index 448d05c118..9825ed2a27 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h @@ -21,12 +21,14 @@ #define FLOW_CNTR_BYTES(v, d) (((v) & (d)->byte_count_mask) >> \ (d)->byte_count_shift) +#define FLOW_CNTR_PC_FLOW_VALID 0x1000000 + struct sw_acc_counter { uint64_t pkt_count; uint64_t byte_count; bool valid; uint32_t hw_cntr_id; - uint32_t parent_flow_id; + uint32_t pc_flow_idx; }; struct hw_fc_mem_info { @@ -175,12 +177,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx, * * hw_cntr_id [in] The HW flow counter ID * - * fid [in] parent flow id + * pc_idx [in] parent child db index * */ int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt, enum tf_dir dir, uint32_t hw_cntr_id, - uint32_