From patchwork Sat Sep 18 14:31:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99287 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E265CA0C45; Sat, 18 Sep 2021 16:32:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C59AC410E9; Sat, 18 Sep 2021 16:32:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 898C54003D for ; Sat, 18 Sep 2021 16:32:15 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18I9QY9O021367 for ; Sat, 18 Sep 2021 07:32:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=K3PocWc05IjvXBcvXpOb8oNDUlA22E+JrQ+yfjCKEMQ=; b=Rnsg7aKytxZOREZyuSp6Wrd0PWLPD9HuYS4rov4B0vRFiaeIfcAjNnCochLBB7IFqoSn hNfGGOnRx/oR1iH61o93thKMal5tCjjWAnLQ/9eFNuB0RTrVSCx1yLjLmru1bxWedAwd goPjBUbi+SOstn4Z2OmeSYq/gYgUWBRyfnY4Iq1Yh4NEmwtq5rtoBewIlTP61frgeSWn 1tr1wy1wY+qXKfl04z3zrPCd7Dzpswpyd/2BooicNgtAZCsAiweq1pOyYU8p3zQ+NVzj RmDSpeMDcVijCSFuNSnGvKWoeO9zWhmItoUrCZpg3ur6tIzYvqBp9L9DaSiuxrBFqonv XQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3b5dfp0hne-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 18 Sep 2021 07:32:14 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 18 Sep 2021 07:32:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:13 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id BDBFC3F7057; Sat, 18 Sep 2021 07:32:11 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Sat, 18 Sep 2021 10:31:51 -0400 Message-ID: <1631975519-30924-2-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 3_oqWOFLKKWWwO9zceA-TVRoVBMMuZD2 X-Proofpoint-GUID: 3_oqWOFLKKWWwO9zceA-TVRoVBMMuZD2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 1/8] common/cnxk: use different macros for sdp and lbk max frames X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao For SDP interface all platforms supports up to 65535 frame size. Updated api with new check for SDP interface. Signed-off-by: Satha Rao --- drivers/common/cnxk/hw/nix.h | 1 + drivers/common/cnxk/roc_nix.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index 6b86002..a0ffd25 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2102,6 +2102,7 @@ struct nix_lso_format { #define NIX_CN9K_MAX_HW_FRS 9212UL #define NIX_LBK_MAX_HW_FRS 65535UL +#define NIX_SDP_MAX_HW_FRS 65535UL #define NIX_RPM_MAX_HW_FRS 16380UL #define NIX_MIN_HW_FRS 60UL diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 23d508b..d1e8c2d 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -113,10 +113,13 @@ { struct nix *nix = roc_nix_to_nix_priv(roc_nix); + if (roc_nix_is_sdp(roc_nix)) + return NIX_SDP_MAX_HW_FRS; + if (roc_model_is_cn9k()) return NIX_CN9K_MAX_HW_FRS; - if (nix->lbk_link || roc_nix_is_sdp(roc_nix)) + if (nix->lbk_link) return NIX_LBK_MAX_HW_FRS; return NIX_RPM_MAX_HW_FRS; From patchwork Sat Sep 18 14:31:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99289 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C059A0C45; Sat, 18 Sep 2021 16:32:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 873BE410F4; Sat, 18 Sep 2021 16:32:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3D00B410E0 for ; Sat, 18 Sep 2021 16:32:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18IEBL4u016135; Sat, 18 Sep 2021 07:32:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=gw4bdnuY3gukOr9nMMJ7li/3EmSu9TABffuFC/6n8rQ=; b=AkM29xO2z0lzbW8izHHKziWpge1gKJOGg+SwPLKj3UtsXLBYywBD+Q88sCaX7/ccoSlf Fwq3RsdaCFi7gJIK46P0LhL8Os+kdfoDU5bYfqDNEP6PFN7t8oyoKvSASCIVcDpdtSVa jaYhE6oqemKrg5rqmuRiEqYKjMG5EV6ukCtuSP2/1fRLdMHa2mOsNBwVakNcVKgiPpnf wTZcwuamH/9ppowxISV9ylG5tAjn7eqcUzxYPr/MT/WWvAN3HFIG2klmT4QpObS1Q3ph hPHWmNYmKE+DOp+58giIhlp/F82YOwIrP7c/3dZSLzu9ckC9Lv+JzK/9XcaW0LPWdrTy Qw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3b5fmm08ys-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 18 Sep 2021 07:32:17 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 18 Sep 2021 07:32:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:15 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id 0B3CE3F705D; Sat, 18 Sep 2021 07:32:13 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Sat, 18 Sep 2021 10:31:52 -0400 Message-ID: <1631975519-30924-3-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 6cGjVIC-Hyb8OUKi-13FPVKnYrh5jdmx X-Proofpoint-GUID: 6cGjVIC-Hyb8OUKi-13FPVKnYrh5jdmx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 2/8] common/cnxk: flush smq X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Added new API to flush all SMQs related nix interface Signed-off-by: Satha Rao --- drivers/common/cnxk/hw/nix.h | 6 +++++ drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_tm_ops.c | 50 ++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 58 insertions(+) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index a0ffd25..bc908c2 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2189,4 +2189,10 @@ struct nix_lso_format { #define NIX_LSO_FORMAT_IDX_TSOV4 0 #define NIX_LSO_FORMAT_IDX_TSOV6 1 +/* [CN10K, .) */ +#define NIX_SENDSTATALG_MASK 0x7 +#define NIX_SENDSTATALG_SEL_MASK 0x8 +#define NIX_SENDSTAT_IOFFSET_MASK 0xFFF +#define NIX_SENDSTAT_OOFFSET_MASK 0xFFF + #endif /* __NIX_HW_H__ */ diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index b0e6fab..ac7bd7e 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -468,6 +468,7 @@ int __roc_api roc_nix_tm_rsrc_count(struct roc_nix *roc_nix, int __roc_api roc_nix_tm_node_name_get(struct roc_nix *roc_nix, uint32_t node_id, char *buf, size_t buflen); +int __roc_api roc_nix_smq_flush(struct roc_nix *roc_nix); /* MAC */ int __roc_api roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start); diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index ed244d4..d9741f5 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -311,6 +311,56 @@ } int +roc_nix_smq_flush(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_tm_node_list *list; + enum roc_nix_tm_tree tree; + struct nix_tm_node *node; + int rc = 0; + + if (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA)) + return 0; + + tree = nix->tm_tree; + list = nix_tm_node_list(nix, tree); + + /* XOFF & Flush all SMQ's. HRM mandates + * all SQ's empty before SMQ flush is issued. + */ + TAILQ_FOREACH(node, list, node) { + if (node->hw_lvl != NIX_TXSCH_LVL_SMQ) + continue; + if (!(node->flags & NIX_TM_NODE_HWRES)) + continue; + + rc = nix_tm_smq_xoff(nix, node, true); + if (rc) { + plt_err("Failed to enable smq %u, rc=%d", node->hw_id, + rc); + goto exit; + } + } + + /* XON all SMQ's */ + TAILQ_FOREACH(node, list, node) { + if (node->hw_lvl != NIX_TXSCH_LVL_SMQ) + continue; + if (!(node->flags & NIX_TM_NODE_HWRES)) + continue; + + rc = nix_tm_smq_xoff(nix, node, false); + if (rc) { + plt_err("Failed to enable smq %u, rc=%d", node->hw_id, + rc); + goto exit; + } + } +exit: + return rc; +} + +int roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 5df2e56..388f938 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -170,6 +170,7 @@ INTERNAL { roc_nix_xstats_names_get; roc_nix_switch_hdr_set; roc_nix_eeprom_info_get; + roc_nix_smq_flush; roc_nix_tm_dump; roc_nix_tm_fini; roc_nix_tm_free_resources; From patchwork Sat Sep 18 14:31:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99288 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DF36AA0C45; Sat, 18 Sep 2021 16:32:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 697F7410F7; Sat, 18 Sep 2021 16:32:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E7E38410EF for ; Sat, 18 Sep 2021 16:32:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18IDnd02010787 for ; Sat, 18 Sep 2021 07:32:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=EbkKlXRxuqJnc32rEeYtlivPPgsx4+ET29QgKXF1/9g=; b=IPK7i7ywkQ0GPvMZXsLdhRakT1i9y6eO6VblInFcAWQHFnQwPyXmj8ve1vhIIZMbpzzU 0l1oCNWLgyXvV+S6gUUv/doax2rSWjRRjoNnDJ63lwCAKhgmSSM+33+xoMX0sqLqpJJg fLi1DDklNjcKnXZUBtMuoMN6Z/BFsc/3pWYq6OgFAj5BUYPwy/95maEdwEzMIdq6WMLb oQ98FE6FlUhM/zJc176E3uNdN2+7D4Zj7hf81BlGE6EQlDnJ//sEJMWDkfKxu0kHW5Ob UT9h/PW5lCk3MWfpArgLVInP6q3lmE4KuKVM3L0Oh5fRG8JE3rPAD7jFG1/HJPnCVS+I Rw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3b5fmm08yy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 18 Sep 2021 07:32:20 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 18 Sep 2021 07:32:17 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:17 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id 8FFF13F705E; Sat, 18 Sep 2021 07:32:16 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Sat, 18 Sep 2021 10:31:53 -0400 Message-ID: <1631975519-30924-4-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NGdukiRHNlBdI5CevzQXMVe-gkklszr8 X-Proofpoint-GUID: NGdukiRHNlBdI5CevzQXMVe-gkklszr8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 3/8] common/cnxk: increase sched weight and shaper burst limit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nithin Dabilpuram Increase sched weight and shaper burst limit for cn10k. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/hw/nix.h | 13 +++++++---- drivers/common/cnxk/roc_nix.h | 23 ++++++++++++++++++- drivers/common/cnxk/roc_nix_priv.h | 11 ++++++---- drivers/common/cnxk/roc_nix_tm.c | 2 +- drivers/common/cnxk/roc_nix_tm_ops.c | 10 +++++---- drivers/common/cnxk/roc_nix_tm_utils.c | 40 +++++++++++++++++++++++++--------- 6 files changed, 75 insertions(+), 24 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index bc908c2..d205438 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2134,8 +2134,9 @@ struct nix_lso_format { 0) /* NIX burst limits */ -#define NIX_TM_MAX_BURST_EXPONENT 0xf -#define NIX_TM_MAX_BURST_MANTISSA 0xff +#define NIX_TM_MAX_BURST_EXPONENT 0xful +#define NIX_TM_MAX_BURST_MANTISSA 0x7ffful +#define NIX_CN9K_TM_MAX_BURST_MANTISSA 0xfful /* NIX burst calculation * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA]) @@ -2147,7 +2148,7 @@ struct nix_lso_format { * / 256 */ #define NIX_TM_SHAPER_BURST(exponent, mantissa) \ - (((256 + (mantissa)) << ((exponent) + 1)) / 256) + (((256ul + (mantissa)) << ((exponent) + 1)) / 256ul) /* Burst limit in Bytes */ #define NIX_TM_MIN_SHAPER_BURST NIX_TM_SHAPER_BURST(0, 0) @@ -2156,13 +2157,17 @@ struct nix_lso_format { NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT, \ NIX_TM_MAX_BURST_MANTISSA) +#define NIX_CN9K_TM_MAX_SHAPER_BURST \ + NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT, \ + NIX_CN9K_TM_MAX_BURST_MANTISSA) + /* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */ #define NIX_TM_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1) #define NIX_TM_LENGTH_ADJUST_MAX 255 #define NIX_TM_TLX_SP_PRIO_MAX 10 #define NIX_CN9K_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1) -#define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(14) - 1) +#define NIX_TM_RR_WEIGHT_MAX (BIT_ULL(14) - 1) /* [CN9K, CN10K) */ #define NIX_CN9K_TXSCH_LVL_SMQ_MAX 512 diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index ac7bd7e..90dc413 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -277,6 +277,28 @@ enum roc_nix_lso_tun_type { ROC_NIX_LSO_TUN_MAX, }; +/* Restrict CN9K sched weight to have a minimum quantum */ +#define ROC_NIX_CN9K_TM_RR_WEIGHT_MAX 255u + +/* NIX TM Inlines */ +static inline uint64_t +roc_nix_tm_max_sched_wt_get(void) +{ + if (roc_model_is_cn9k()) + return ROC_NIX_CN9K_TM_RR_WEIGHT_MAX; + else + return NIX_TM_RR_WEIGHT_MAX; +} + +static inline uint64_t +roc_nix_tm_max_shaper_burst_get(void) +{ + if (roc_model_is_cn9k()) + return NIX_CN9K_TM_MAX_SHAPER_BURST; + else + return NIX_TM_MAX_SHAPER_BURST; +} + /* Dev */ int __roc_api roc_nix_dev_init(struct roc_nix *roc_nix); int __roc_api roc_nix_dev_fini(struct roc_nix *roc_nix); @@ -324,7 +346,6 @@ void __roc_api roc_nix_rx_queue_intr_disable(struct roc_nix *roc_nix, void __roc_api roc_nix_unregister_cq_irqs(struct roc_nix *roc_nix); /* Traffic Management */ -#define ROC_NIX_TM_MAX_SCHED_WT ((uint8_t)~0) #define ROC_NIX_TM_SHAPER_PROFILE_NONE UINT32_MAX #define ROC_NIX_TM_NODE_ID_INVALID UINT32_MAX diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 9dc0c88..cc8e822 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -256,11 +256,14 @@ struct nix_tm_shaper_data { static inline uint64_t nix_tm_weight_to_rr_quantum(uint64_t weight) { - uint64_t max = (roc_model_is_cn9k() ? NIX_CN9K_TM_RR_QUANTUM_MAX : - NIX_TM_RR_QUANTUM_MAX); + uint64_t max = NIX_CN9K_TM_RR_QUANTUM_MAX; - weight &= (uint64_t)ROC_NIX_TM_MAX_SCHED_WT; - return (weight * max) / ROC_NIX_TM_MAX_SCHED_WT; + /* From CN10K onwards, we only configure RR weight */ + if (!roc_model_is_cn9k()) + return weight; + + weight &= (uint64_t)max; + return (weight * max) / ROC_NIX_CN9K_TM_RR_WEIGHT_MAX; } static inline bool diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index ad54e17..947320a 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -223,7 +223,7 @@ if (rc) return rc; - if (node->weight > ROC_NIX_TM_MAX_SCHED_WT) + if (node->weight > roc_nix_tm_max_sched_wt_get()) return NIX_ERR_TM_WEIGHT_EXCEED; /* Maintain minimum weight */ diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index d9741f5..a313023 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -83,6 +83,7 @@ { struct nix *nix = roc_nix_to_nix_priv(roc_nix); uint64_t commit_rate, commit_sz; + uint64_t min_burst, max_burst; uint64_t peak_rate, peak_sz; uint32_t id; @@ -92,6 +93,9 @@ peak_rate = profile->peak.rate; peak_sz = profile->peak.size; + min_burst = NIX_TM_MIN_SHAPER_BURST; + max_burst = roc_nix_tm_max_shaper_burst_get(); + if (nix_tm_shaper_profile_search(nix, id) && !skip_ins) return NIX_ERR_TM_SHAPER_PROFILE_EXISTS; @@ -105,8 +109,7 @@ /* commit rate and burst size can be enabled/disabled */ if (commit_rate || commit_sz) { - if (commit_sz < NIX_TM_MIN_SHAPER_BURST || - commit_sz > NIX_TM_MAX_SHAPER_BURST) + if (commit_sz < min_burst || commit_sz > max_burst) return NIX_ERR_TM_INVALID_COMMIT_SZ; else if (!nix_tm_shaper_rate_conv(commit_rate, NULL, NULL, NULL)) @@ -115,8 +118,7 @@ /* Peak rate and burst size can be enabled/disabled */ if (peak_sz || peak_rate) { - if (peak_sz < NIX_TM_MIN_SHAPER_BURST || - peak_sz > NIX_TM_MAX_SHAPER_BURST) + if (peak_sz < min_burst || peak_sz > max_burst) return NIX_ERR_TM_INVALID_PEAK_SZ; else if (!nix_tm_shaper_rate_conv(peak_rate, NULL, NULL, NULL)) return NIX_ERR_TM_INVALID_PEAK_RATE; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 6b9543e..00604b1 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -8,9 +8,23 @@ static inline uint64_t nix_tm_shaper2regval(struct nix_tm_shaper_data *shaper) { - return (shaper->burst_exponent << 37) | (shaper->burst_mantissa << 29) | - (shaper->div_exp << 13) | (shaper->exponent << 9) | - (shaper->mantissa << 1); + uint64_t regval; + + if (roc_model_is_cn9k()) { + regval = (shaper->burst_exponent << 37); + regval |= (shaper->burst_mantissa << 29); + regval |= (shaper->div_exp << 13); + regval |= (shaper->exponent << 9); + regval |= (shaper->mantissa << 1); + return regval; + } + + regval = (shaper->burst_exponent << 44); + regval |= (shaper->burst_mantissa << 29); + regval |= (shaper->div_exp << 13); + regval |= (shaper->exponent << 9); + regval |= (shaper->mantissa << 1); + return regval; } uint16_t @@ -178,20 +192,26 @@ struct nix_tm_node * nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p, uint64_t *mantissa_p) { + uint64_t min_burst, max_burst; uint64_t exponent, mantissa; + uint32_t max_mantissa; + + min_burst = NIX_TM_MIN_SHAPER_BURST; + max_burst = roc_nix_tm_max_shaper_burst_get(); - if (value < NIX_TM_MIN_SHAPER_BURST || value > NIX_TM_MAX_SHAPER_BURST) + if (value < min_burst || value > max_burst) return 0; + max_mantissa = (roc_model_is_cn9k() ? NIX_CN9K_TM_MAX_BURST_MANTISSA : + NIX_TM_MAX_BURST_MANTISSA); /* Calculate burst exponent and mantissa using * the following formula: * - * value = (((256 + mantissa) << (exponent + 1) - / 256) + * value = (((256 + mantissa) << (exponent + 1) / 256) * */ exponent = NIX_TM_MAX_BURST_EXPONENT; - mantissa = NIX_TM_MAX_BURST_MANTISSA; + mantissa = max_mantissa; while (value < (1ull << (exponent + 1))) exponent -= 1; @@ -199,8 +219,7 @@ struct nix_tm_node * while (value < ((256 + mantissa) << (exponent + 1)) / 256) mantissa -= 1; - if (exponent > NIX_TM_MAX_BURST_EXPONENT || - mantissa > NIX_TM_MAX_BURST_MANTISSA) + if (exponent > NIX_TM_MAX_BURST_EXPONENT || mantissa > max_mantissa) return 0; if (exponent_p) @@ -544,6 +563,7 @@ struct nix_tm_node * uint64_t rr_quantum; uint8_t k = 0; + /* For CN9K, weight needs to be converted to quantum */ rr_quantum = nix_tm_weight_to_rr_quantum(node->weight); /* For children to root, strict prio is default if either @@ -554,7 +574,7 @@ struct nix_tm_node * strict_prio = NIX_TM_TL1_DFLT_RR_PRIO; plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, " - "prio 0x%" PRIx64 ", rr_quantum 0x%" PRIx64 " (%p)", + "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)", nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, strict_prio, rr_quantum, node); From patchwork Sat Sep 18 14:31:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99290 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00114A0C45; Sat, 18 Sep 2021 16:32:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AE6EE410E0; Sat, 18 Sep 2021 16:32:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C3EB7406B4 for ; Sat, 18 Sep 2021 16:32:22 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18ICxoJ9015955 for ; Sat, 18 Sep 2021 07:32:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=WjccEyblx1APgB0iwrBT8KAsd+okwNms9xE2j3Zw9bk=; b=E7rgI0YedWAmf+hmsE+1Y3sN1C2zesU//kmkG5yG5xfsFT90WfEiuKOu44RWflRTjrky 8M5Cmzsat4bidiR42fmtQU7E1pT3DietfXvVXjom9ICx4K9LNxX0t7aJaL/izOya0+5g g94DUh9HRRQNKZxVoXfF3UUVvWgx9OfYd43+GyigaWheyDVja7no5X0WHMczfokZJkk9 YSNMuvW9KeEgbsnpsZPzZZ9jcw5X899tZjmE2mETfunq1buF/ysn+dA6kU+eyhHh5jwk jNL7KcZeaR+JNizHaKAlUALAJWQUE1HM2o0G7lpL0UUe+fpsjNZaE1nEL7XOdW43nc/Z RA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3b5fmm0901-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 18 Sep 2021 07:32:22 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 18 Sep 2021 07:32:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:20 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id D169B3F708C; Sat, 18 Sep 2021 07:32:18 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Sat, 18 Sep 2021 10:31:54 -0400 Message-ID: <1631975519-30924-5-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: pkTpbI-a64vzKb-qAOjs2GlswhjJHdv8 X-Proofpoint-GUID: pkTpbI-a64vzKb-qAOjs2GlswhjJHdv8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 4/8] common/cnxk: handle packet mode shaper limits X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Add new macros to reflect HW shaper PPS limits. New API to validate input rates for packet mode. Increase adjust value to support lesser PPS (<61). Signed-off-by: Satha Rao --- drivers/common/cnxk/hw/nix.h | 3 ++ drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/roc_nix_tm_ops.c | 76 ++++++++++++++++++++++++---------- drivers/common/cnxk/roc_nix_tm_utils.c | 4 +- 4 files changed, 60 insertions(+), 24 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index d205438..6a0eb01 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2133,6 +2133,9 @@ struct nix_lso_format { NIX_TM_SHAPER_RATE(NIX_TM_MAX_RATE_EXPONENT, NIX_TM_MAX_RATE_MANTISSA, \ 0) +#define NIX_TM_MIN_SHAPER_PPS_RATE 25 +#define NIX_TM_MAX_SHAPER_PPS_RATE (100ul << 20) + /* NIX burst limits */ #define NIX_TM_MAX_BURST_EXPONENT 0xful #define NIX_TM_MAX_BURST_MANTISSA 0x7ffful diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index cc8e822..3412bf2 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -90,6 +90,7 @@ struct nix_tm_shaper_profile { struct nix_tm_tb commit; struct nix_tm_tb peak; int32_t pkt_len_adj; + int32_t pkt_mode_adj; bool pkt_mode; uint32_t id; void (*free_fn)(void *profile); diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index a313023..69d5837 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -78,6 +78,51 @@ } static int +nix_tm_adjust_shaper_pps_rate(struct nix_tm_shaper_profile *profile) +{ + uint64_t min_rate = profile->commit.rate; + + if (!profile->pkt_mode) + return 0; + + profile->pkt_mode_adj = 1; + + if (profile->commit.rate && + (profile->commit.rate < NIX_TM_MIN_SHAPER_PPS_RATE || + profile->commit.rate > NIX_TM_MAX_SHAPER_PPS_RATE)) + return NIX_ERR_TM_INVALID_COMMIT_RATE; + + if (profile->peak.rate && + (profile->peak.rate < NIX_TM_MIN_SHAPER_PPS_RATE || + profile->peak.rate > NIX_TM_MAX_SHAPER_PPS_RATE)) + return NIX_ERR_TM_INVALID_PEAK_RATE; + + if (profile->peak.rate && min_rate > profile->peak.rate) + min_rate = profile->peak.rate; + + /* Each packet accomulate single count, whereas HW + * considers each unit as Byte, so we need convert + * user pps to bps + */ + profile->commit.rate = profile->commit.rate * 8; + profile->peak.rate = profile->peak.rate * 8; + min_rate = min_rate * 8; + + if (min_rate && (min_rate < NIX_TM_MIN_SHAPER_RATE)) { + int adjust = NIX_TM_MIN_SHAPER_RATE / min_rate; + + if (adjust > NIX_TM_LENGTH_ADJUST_MAX) + return NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST; + + profile->pkt_mode_adj += adjust; + profile->commit.rate += (adjust * profile->commit.rate); + profile->peak.rate += (adjust * profile->peak.rate); + } + + return 0; +} + +static int nix_tm_shaper_profile_add(struct roc_nix *roc_nix, struct nix_tm_shaper_profile *profile, int skip_ins) { @@ -86,8 +131,13 @@ uint64_t min_burst, max_burst; uint64_t peak_rate, peak_sz; uint32_t id; + int rc; id = profile->id; + rc = nix_tm_adjust_shaper_pps_rate(profile); + if (rc) + return rc; + commit_rate = profile->commit.rate; commit_sz = profile->commit.size; peak_rate = profile->peak.rate; @@ -157,17 +207,8 @@ profile->ref_cnt = 0; profile->id = roc_profile->id; - if (roc_profile->pkt_mode) { - /* Each packet accomulate single count, whereas HW - * considers each unit as Byte, so we need convert - * user pps to bps - */ - profile->commit.rate = roc_profile->commit_rate * 8; - profile->peak.rate = roc_profile->peak_rate * 8; - } else { - profile->commit.rate = roc_profile->commit_rate; - profile->peak.rate = roc_profile->peak_rate; - } + profile->commit.rate = roc_profile->commit_rate; + profile->peak.rate = roc_profile->peak_rate; profile->commit.size = roc_profile->commit_sz; profile->peak.size = roc_profile->peak_sz; profile->pkt_len_adj = roc_profile->pkt_len_adj; @@ -185,17 +226,8 @@ profile = (struct nix_tm_shaper_profile *)roc_profile->reserved; - if (roc_profile->pkt_mode) { - /* Each packet accomulate single count, whereas HW - * considers each unit as Byte, so we need convert - * user pps to bps - */ - profile->commit.rate = roc_profile->commit_rate * 8; - profile->peak.rate = roc_profile->peak_rate * 8; - } else { - profile->commit.rate = roc_profile->commit_rate; - profile->peak.rate = roc_profile->peak_rate; - } + profile->commit.rate = roc_profile->commit_rate; + profile->peak.rate = roc_profile->peak_rate; profile->commit.size = roc_profile->commit_sz; profile->peak.size = roc_profile->peak_sz; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 00604b1..8330624 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -628,8 +628,8 @@ struct nix_tm_node * memset(&pir, 0, sizeof(pir)); nix_tm_shaper_conf_get(profile, &cir, &pir); - if (node->pkt_mode) - adjust = 1; + if (profile && node->pkt_mode) + adjust = profile->pkt_mode_adj; else if (profile) adjust = profile->pkt_len_adj; From patchwork Sat Sep 18 14:31:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99291 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A617EA0C45; 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Sat, 18 Sep 2021 07:32:25 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 18 Sep 2021 07:32:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:22 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id 280733F7068; Sat, 18 Sep 2021 07:32:20 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Sat, 18 Sep 2021 10:31:55 -0400 Message-ID: <1631975519-30924-6-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: jdmneZvbTvY1G-_qN2NrMoj1o90mWA1H X-Proofpoint-GUID: jdmneZvbTvY1G-_qN2NrMoj1o90mWA1H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 5/8] common/cnxk: handler to get rte tm error type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Different TM handlers returns various platform specific errors, this patch introduces new API to convert these internal error types to RTE_TM* error types. Also updated error message API with missed TM error types. Signed-off-by: Satha Rao --- drivers/common/cnxk/cnxk_utils.c | 68 ++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/cnxk_utils.h | 11 +++++++ drivers/common/cnxk/meson.build | 5 +++ drivers/common/cnxk/roc_utils.c | 6 ++++ drivers/common/cnxk/version.map | 1 + 5 files changed, 91 insertions(+) create mode 100644 drivers/common/cnxk/cnxk_utils.c create mode 100644 drivers/common/cnxk/cnxk_utils.h diff --git a/drivers/common/cnxk/cnxk_utils.c b/drivers/common/cnxk/cnxk_utils.c new file mode 100644 index 0000000..4e56adc --- /dev/null +++ b/drivers/common/cnxk/cnxk_utils.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#include +#include + +#include "roc_api.h" +#include "roc_priv.h" + +#include "cnxk_utils.h" + +int +roc_nix_tm_err_to_rte_err(int errorcode) +{ + int err_type; + + switch (errorcode) { + case NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN; + break; + case NIX_ERR_TM_INVALID_COMMIT_SZ: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE; + break; + case NIX_ERR_TM_INVALID_COMMIT_RATE: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_RATE; + break; + case NIX_ERR_TM_INVALID_PEAK_SZ: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE; + break; + case NIX_ERR_TM_INVALID_PEAK_RATE: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_RATE; + break; + case NIX_ERR_TM_INVALID_SHAPER_PROFILE: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + break; + case NIX_ERR_TM_SHAPER_PROFILE_IN_USE: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE; + break; + case NIX_ERR_TM_INVALID_NODE: + err_type = RTE_TM_ERROR_TYPE_NODE_ID; + break; + case NIX_ERR_TM_PKT_MODE_MISMATCH: + err_type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + break; + case NIX_ERR_TM_INVALID_PARENT: + case NIX_ERR_TM_PARENT_PRIO_UPDATE: + err_type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + break; + case NIX_ERR_TM_PRIO_ORDER: + case NIX_ERR_TM_MULTIPLE_RR_GROUPS: + err_type = RTE_TM_ERROR_TYPE_NODE_PRIORITY; + break; + case NIX_ERR_TM_PRIO_EXCEEDED: + err_type = RTE_TM_ERROR_TYPE_CAPABILITIES; + break; + default: + /** + * Handle general error (as defined in linux errno.h) + */ + if (abs(errorcode) < 300) + err_type = errorcode; + else + err_type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + break; + } + + return err_type; +} diff --git a/drivers/common/cnxk/cnxk_utils.h b/drivers/common/cnxk/cnxk_utils.h new file mode 100644 index 0000000..5463cd4 --- /dev/null +++ b/drivers/common/cnxk/cnxk_utils.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#ifndef _CNXK_UTILS_H_ +#define _CNXK_UTILS_H_ + +#include "roc_platform.h" + +int __roc_api roc_nix_tm_err_to_rte_err(int errorcode); + +#endif /* _CNXK_UTILS_H_ */ diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 8a551d1..258429d 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -61,5 +61,10 @@ sources = files( # Security common code sources += files('cnxk_security.c') +# common DPDK utilities code +sources += files('cnxk_utils.c') + includes += include_directories('../../bus/pci') includes += include_directories('../../../lib/net') +includes += include_directories('../../../lib/ethdev') +includes += include_directories('../../../lib/meter') diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c index 9cb8708..751486f 100644 --- a/drivers/common/cnxk/roc_utils.c +++ b/drivers/common/cnxk/roc_utils.c @@ -64,6 +64,9 @@ case NIX_ERR_TM_INVALID_SHAPER_PROFILE: err_msg = "TM shaper profile invalid"; break; + case NIX_ERR_TM_PKT_MODE_MISMATCH: + err_msg = "shaper profile pkt mode mismatch"; + break; case NIX_ERR_TM_WEIGHT_EXCEED: err_msg = "TM DWRR weight exceeded"; break; @@ -88,6 +91,9 @@ case NIX_ERR_TM_SHAPER_PROFILE_EXISTS: err_msg = "TM shaper profile exists"; break; + case NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST: + err_msg = "length adjust invalid"; + break; case NIX_ERR_TM_INVALID_TREE: err_msg = "TM tree invalid"; break; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 388f938..776cabb 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -172,6 +172,7 @@ INTERNAL { roc_nix_eeprom_info_get; roc_nix_smq_flush; roc_nix_tm_dump; + roc_nix_tm_err_to_rte_err; roc_nix_tm_fini; roc_nix_tm_free_resources; roc_nix_tm_hierarchy_disable; From patchwork Sat Sep 18 14:31:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99292 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2AC36A0C45; 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Sat, 18 Sep 2021 07:32:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 18 Sep 2021 07:32:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:25 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id B1F8A3F7057; Sat, 18 Sep 2021 07:32:23 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: Date: Sat, 18 Sep 2021 10:31:56 -0400 Message-ID: <1631975519-30924-7-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: z9vxktviJ9nbNARSgUX8jDaIS97UglG0 X-Proofpoint-GUID: z9vxktviJ9nbNARSgUX8jDaIS97UglG0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 6/8] common/cnxk: set of handlers to get tm hierarchy internals X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Platform specific TM tree hierarchy details are part of common cnxk driver. This patch introduces missing HAL apis to return state of TM hierarchy required to support ethdev TM operations inside cnxk PMD. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_model.h | 6 +++ drivers/common/cnxk/roc_nix.h | 10 ++++ drivers/common/cnxk/roc_nix_priv.h | 1 - drivers/common/cnxk/roc_nix_tm.c | 22 ++++++++- drivers/common/cnxk/roc_nix_tm_ops.c | 11 +---- drivers/common/cnxk/roc_nix_tm_utils.c | 86 ++++++++++++++++++++++++++++++++-- drivers/common/cnxk/version.map | 8 ++++ 7 files changed, 127 insertions(+), 17 deletions(-) diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index c1d11b7..856a570 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -106,6 +106,12 @@ struct roc_model { } static inline uint64_t +roc_model_is_cn96_cx(void) +{ + return (roc_model->flag & ROC_MODEL_CN96xx_C0); +} + +static inline uint64_t roc_model_is_cn95_a0(void) { return roc_model->flag & ROC_MODEL_CNF95xx_A0; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 90dc413..d9a4613 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -490,6 +490,16 @@ int __roc_api roc_nix_tm_node_name_get(struct roc_nix *roc_nix, uint32_t node_id, char *buf, size_t buflen); int __roc_api roc_nix_smq_flush(struct roc_nix *roc_nix); +int __roc_api roc_nix_tm_max_prio(struct roc_nix *roc_nix, int lvl); +int __roc_api roc_nix_tm_lvl_is_leaf(struct roc_nix *roc_nix, int lvl); +void __roc_api +roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node, + struct roc_nix_tm_shaper_profile *profile); +int __roc_api roc_nix_tm_lvl_cnt_get(struct roc_nix *roc_nix); +int __roc_api roc_nix_tm_lvl_have_link_access(struct roc_nix *roc_nix, int lvl); +int __roc_api roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix); +bool __roc_api roc_nix_tm_is_user_hierarchy_enabled(struct roc_nix *nix); +int __roc_api roc_nix_tm_tree_type_get(struct roc_nix *nix); /* MAC */ int __roc_api roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start); diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 3412bf2..b67f648 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -350,7 +350,6 @@ int nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig, int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree); int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node, bool rr_quantum_only); -int nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix); /* * TM priv utils. diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index 947320a..08d6e86 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -155,6 +155,20 @@ return 0; } +static int +nix_tm_root_node_get(struct nix *nix, int tree) +{ + struct nix_tm_node_list *list = nix_tm_node_list(nix, tree); + struct nix_tm_node *tm_node; + + TAILQ_FOREACH(tm_node, list, node) { + if (tm_node->hw_lvl == nix->tm_root_lvl) + return 1; + } + + return 0; +} + int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node) { @@ -207,6 +221,10 @@ if (nix_tm_node_search(nix, node_id, tree)) return NIX_ERR_TM_NODE_EXISTS; + /* Check if root node exists */ + if (hw_lvl == nix->tm_root_lvl && nix_tm_root_node_get(nix, tree)) + return NIX_ERR_TM_NODE_EXISTS; + profile = nix_tm_shaper_profile_search(nix, profile_id); if (!nix_tm_is_leaf(nix, lvl)) { /* Check if shaper profile exists for non leaf node */ @@ -1157,7 +1175,7 @@ } int -nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix) +roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); uint32_t nonleaf_id = nix->nb_tx_queues; @@ -1227,7 +1245,7 @@ goto error; node->id = i; - node->parent_id = parent; + node->parent_id = parent + i; node->priority = 0; node->weight = NIX_TM_DFLT_RR_WT; node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE; diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index 69d5837..29f276a 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -927,13 +927,6 @@ return rc; } - /* Prepare rlimit tree */ - rc = nix_tm_prepare_rate_limited_tree(roc_nix); - if (rc) { - plt_err("failed to prepare rlimit tm tree, rc=%d", rc); - return rc; - } - return rc; } @@ -951,11 +944,11 @@ uint8_t k = 0; int rc; - if (nix->tm_tree != ROC_NIX_TM_RLIMIT || + if ((nix->tm_tree == ROC_NIX_TM_USER) || !(nix->tm_flags & NIX_TM_HIERARCHY_ENA)) return NIX_ERR_TM_INVALID_TREE; - node = nix_tm_node_search(nix, qid, ROC_NIX_TM_RLIMIT); + node = nix_tm_node_search(nix, qid, nix->tm_tree); /* check if we found a valid leaf node */ if (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent || diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 8330624..a135454 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -235,6 +235,9 @@ struct nix_tm_node * struct nix_tm_shaper_data *cir, struct nix_tm_shaper_data *pir) { + memset(cir, 0, sizeof(*cir)); + memset(pir, 0, sizeof(*pir)); + if (!profile) return; @@ -624,8 +627,6 @@ struct nix_tm_node * uint64_t adjust = 0; uint8_t k = 0; - memset(&cir, 0, sizeof(cir)); - memset(&pir, 0, sizeof(pir)); nix_tm_shaper_conf_get(profile, &cir, &pir); if (profile && node->pkt_mode) @@ -1043,15 +1044,16 @@ struct nix_tm_shaper_profile * if (node->hw_lvl != NIX_TXSCH_LVL_TL1) return NIX_ERR_OP_NOTSUP; + /* Check if node has HW resource */ + if (!(node->flags & NIX_TM_NODE_HWRES)) + return 0; + schq = node->hw_id; /* Skip fetch if not requested */ if (!n_stats) goto clear_stats; memset(n_stats, 0, sizeof(struct roc_nix_tm_node_stats)); - /* Check if node has HW resource */ - if (!(node->flags & NIX_TM_NODE_HWRES)) - return 0; req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->read = 1; @@ -1102,3 +1104,77 @@ struct nix_tm_shaper_profile * return mbox_process_msg(mbox, (void **)&rsp); } + +bool +roc_nix_tm_is_user_hierarchy_enabled(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + if ((nix->tm_flags & NIX_TM_HIERARCHY_ENA) && + (nix->tm_tree == ROC_NIX_TM_USER)) + return true; + return false; +} + +int +roc_nix_tm_tree_type_get(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + return nix->tm_tree; +} + +int +roc_nix_tm_max_prio(struct roc_nix *roc_nix, int lvl) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + int hw_lvl = nix_tm_lvl2nix(nix, lvl); + + return nix_tm_max_prio(nix, hw_lvl); +} + +int +roc_nix_tm_lvl_is_leaf(struct roc_nix *roc_nix, int lvl) +{ + return nix_tm_is_leaf(roc_nix_to_nix_priv(roc_nix), lvl); +} + +void +roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node, + struct roc_nix_tm_shaper_profile *roc_prof) +{ + struct nix_tm_node *tm_node = (struct nix_tm_node *)node; + struct nix_tm_shaper_profile *profile; + struct nix_tm_shaper_data cir, pir; + + profile = (struct nix_tm_shaper_profile *)roc_prof->reserved; + tm_node->red_algo = NIX_REDALG_STD; + + /* C0 doesn't support STALL when both PIR & CIR are enabled */ + if (profile && roc_model_is_cn96_cx()) { + nix_tm_shaper_conf_get(profile, &cir, &pir); + + if (pir.rate && cir.rate) + tm_node->red_algo = NIX_REDALG_DISCARD; + } +} + +int +roc_nix_tm_lvl_cnt_get(struct roc_nix *roc_nix) +{ + if (nix_tm_have_tl1_access(roc_nix_to_nix_priv(roc_nix))) + return NIX_TXSCH_LVL_CNT; + + return (NIX_TXSCH_LVL_CNT - 1); +} + +int +roc_nix_tm_lvl_have_link_access(struct roc_nix *roc_nix, int lvl) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + if (nix_tm_lvl2nix(nix, lvl) == NIX_TXSCH_LVL_TL1) + return 1; + + return 0; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 776cabb..9b7cbf6 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -175,10 +175,16 @@ INTERNAL { roc_nix_tm_err_to_rte_err; roc_nix_tm_fini; roc_nix_tm_free_resources; + roc_nix_tm_lvl_cnt_get; + roc_nix_tm_tree_type_get; roc_nix_tm_hierarchy_disable; roc_nix_tm_hierarchy_enable; roc_nix_tm_init; + roc_nix_tm_is_user_hierarchy_enabled; roc_nix_tm_leaf_cnt; + roc_nix_tm_lvl_have_link_access; + roc_nix_tm_lvl_is_leaf; + roc_nix_tm_max_prio; roc_nix_tm_node_add; roc_nix_tm_node_delete; roc_nix_tm_node_get; @@ -191,10 +197,12 @@ INTERNAL { roc_nix_tm_node_stats_get; roc_nix_tm_node_suspend_resume; roc_nix_tm_prealloc_res; + roc_nix_tm_prepare_rate_limited_tree; roc_nix_tm_rlimit_sq; roc_nix_tm_root_has_sp; roc_nix_tm_rsrc_count; roc_nix_tm_rsrc_max; + roc_nix_tm_shaper_default_red_algo; roc_nix_tm_shaper_profile_add; roc_nix_tm_shaper_profile_delete; roc_nix_tm_shaper_profile_get; From patchwork Sat Sep 18 14:31:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99293 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4C677A0C45; Sat, 18 Sep 2021 16:32:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4ECAC41134; Sat, 18 Sep 2021 16:32:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 85B4E4111D for ; Sat, 18 Sep 2021 16:32:30 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18IBsqLS022054 for ; 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Sat, 18 Sep 2021 07:32:27 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id 48C2D3F705E; Sat, 18 Sep 2021 07:32:26 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Sat, 18 Sep 2021 10:31:57 -0400 Message-ID: <1631975519-30924-8-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: aGhlFt-sZ3b1XP60Szw4fjgjmDOxJN-U X-Proofpoint-GUID: aGhlFt-sZ3b1XP60Szw4fjgjmDOxJN-U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 7/8] net/cnxk: tm capabilities and queue rate limit handlers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Initial version of TM implementation added basic infrastructure, tm node_get, capabilities operations and rate limit queue operation. Signed-off-by: Satha Rao --- drivers/net/cnxk/cnxk_ethdev.c | 2 + drivers/net/cnxk/cnxk_ethdev.h | 3 + drivers/net/cnxk/cnxk_tm.c | 322 +++++++++++++++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_tm.h | 18 +++ drivers/net/cnxk/meson.build | 1 + 5 files changed, 346 insertions(+) create mode 100644 drivers/net/cnxk/cnxk_tm.c create mode 100644 drivers/net/cnxk/cnxk_tm.h diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 7152dcd..8629193 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1276,6 +1276,8 @@ struct eth_dev_ops cnxk_eth_dev_ops = { .rss_hash_update = cnxk_nix_rss_hash_update, .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get, .set_mc_addr_list = cnxk_nix_mc_addr_list_configure, + .set_queue_rate_limit = cnxk_nix_tm_set_queue_rate_limit, + .tm_ops_get = cnxk_nix_tm_ops_get, }; static int diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 27920c8..10e05e6 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -330,6 +330,9 @@ int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev, int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock); uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); +int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops); +int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev, + uint16_t queue_idx, uint16_t tx_rate); /* RSS */ uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss, diff --git a/drivers/net/cnxk/cnxk_tm.c b/drivers/net/cnxk/cnxk_tm.c new file mode 100644 index 0000000..87fd8be --- /dev/null +++ b/drivers/net/cnxk/cnxk_tm.c @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#include +#include +#include + +static int +cnxk_nix_tm_node_type_get(struct rte_eth_dev *eth_dev, uint32_t node_id, + int *is_leaf, struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + struct roc_nix_tm_node *node; + + if (is_leaf == NULL) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + return -EINVAL; + } + + node = roc_nix_tm_node_get(nix, node_id); + if (node_id == RTE_TM_NODE_ID_NULL || !node) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + return -EINVAL; + } + + if (roc_nix_tm_lvl_is_leaf(nix, node->lvl)) + *is_leaf = true; + else + *is_leaf = false; + + return 0; +} + +static int +cnxk_nix_tm_capa_get(struct rte_eth_dev *eth_dev, + struct rte_tm_capabilities *cap, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + int rc, max_nr_nodes = 0, i, n_lvl; + struct roc_nix *nix = &dev->nix; + uint16_t schq[ROC_TM_LVL_MAX]; + + memset(cap, 0, sizeof(*cap)); + + rc = roc_nix_tm_rsrc_count(nix, schq); + if (rc) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message = "unexpected fatal error"; + return rc; + } + + for (i = 0; i < NIX_TXSCH_LVL_TL1; i++) + max_nr_nodes += schq[i]; + + cap->n_nodes_max = max_nr_nodes + dev->nb_txq; + + n_lvl = roc_nix_tm_lvl_cnt_get(nix); + /* Consider leaf level */ + cap->n_levels_max = n_lvl + 1; + cap->non_leaf_nodes_identical = 1; + cap->leaf_nodes_identical = 1; + + /* Shaper Capabilities */ + cap->shaper_private_n_max = max_nr_nodes; + cap->shaper_n_max = max_nr_nodes; + cap->shaper_private_dual_rate_n_max = max_nr_nodes; + cap->shaper_private_rate_min = NIX_TM_MIN_SHAPER_RATE / 8; + cap->shaper_private_rate_max = NIX_TM_MAX_SHAPER_RATE / 8; + cap->shaper_private_packet_mode_supported = 1; + cap->shaper_private_byte_mode_supported = 1; + cap->shaper_pkt_length_adjust_min = NIX_TM_LENGTH_ADJUST_MIN; + cap->shaper_pkt_length_adjust_max = NIX_TM_LENGTH_ADJUST_MAX; + + /* Schedule Capabilities */ + cap->sched_n_children_max = schq[n_lvl - 1]; + cap->sched_sp_n_priorities_max = NIX_TM_TLX_SP_PRIO_MAX; + cap->sched_wfq_n_children_per_group_max = cap->sched_n_children_max; + cap->sched_wfq_n_groups_max = 1; + cap->sched_wfq_weight_max = roc_nix_tm_max_sched_wt_get(); + cap->sched_wfq_packet_mode_supported = 1; + cap->sched_wfq_byte_mode_supported = 1; + + cap->dynamic_update_mask = RTE_TM_UPDATE_NODE_PARENT_KEEP_LEVEL | + RTE_TM_UPDATE_NODE_SUSPEND_RESUME; + cap->stats_mask = RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_BYTES | + RTE_TM_STATS_N_PKTS_RED_DROPPED | + RTE_TM_STATS_N_BYTES_RED_DROPPED; + + for (i = 0; i < RTE_COLORS; i++) { + cap->mark_vlan_dei_supported[i] = false; + cap->mark_ip_ecn_tcp_supported[i] = false; + cap->mark_ip_dscp_supported[i] = false; + } + + return 0; +} + +static int +cnxk_nix_tm_level_capa_get(struct rte_eth_dev *eth_dev, uint32_t lvl, + struct rte_tm_level_capabilities *cap, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + uint16_t schq[ROC_TM_LVL_MAX]; + int rc, n_lvl; + + memset(cap, 0, sizeof(*cap)); + + rc = roc_nix_tm_rsrc_count(nix, schq); + if (rc) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message = "unexpected fatal error"; + return rc; + } + + n_lvl = roc_nix_tm_lvl_cnt_get(nix); + + if (roc_nix_tm_lvl_is_leaf(nix, lvl)) { + /* Leaf */ + cap->n_nodes_max = dev->nb_txq; + cap->n_nodes_leaf_max = dev->nb_txq; + cap->leaf_nodes_identical = 1; + cap->leaf.stats_mask = + RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_BYTES; + + } else if (lvl == ROC_TM_LVL_ROOT) { + /* Root node, a.k.a. TL2(vf)/TL1(pf) */ + cap->n_nodes_max = 1; + cap->n_nodes_nonleaf_max = 1; + cap->non_leaf_nodes_identical = 1; + + cap->nonleaf.shaper_private_supported = true; + cap->nonleaf.shaper_private_dual_rate_supported = + roc_nix_tm_lvl_have_link_access(nix, lvl) ? false : + true; + cap->nonleaf.shaper_private_rate_min = + NIX_TM_MIN_SHAPER_RATE / 8; + cap->nonleaf.shaper_private_rate_max = + NIX_TM_MAX_SHAPER_RATE / 8; + cap->nonleaf.shaper_private_packet_mode_supported = 1; + cap->nonleaf.shaper_private_byte_mode_supported = 1; + + cap->nonleaf.sched_n_children_max = schq[lvl]; + cap->nonleaf.sched_sp_n_priorities_max = + roc_nix_tm_max_prio(nix, lvl) + 1; + cap->nonleaf.sched_wfq_n_groups_max = 1; + cap->nonleaf.sched_wfq_weight_max = + roc_nix_tm_max_sched_wt_get(); + cap->nonleaf.sched_wfq_packet_mode_supported = 1; + cap->nonleaf.sched_wfq_byte_mode_supported = 1; + + if (roc_nix_tm_lvl_have_link_access(nix, lvl)) + cap->nonleaf.stats_mask = + RTE_TM_STATS_N_PKTS_RED_DROPPED | + RTE_TM_STATS_N_BYTES_RED_DROPPED; + } else if (lvl < ROC_TM_LVL_MAX) { + /* TL2, TL3, TL4, MDQ */ + cap->n_nodes_max = schq[lvl]; + cap->n_nodes_nonleaf_max = cap->n_nodes_max; + cap->non_leaf_nodes_identical = 1; + + cap->nonleaf.shaper_private_supported = true; + cap->nonleaf.shaper_private_dual_rate_supported = true; + cap->nonleaf.shaper_private_rate_min = + NIX_TM_MIN_SHAPER_RATE / 8; + cap->nonleaf.shaper_private_rate_max = + NIX_TM_MAX_SHAPER_RATE / 8; + cap->nonleaf.shaper_private_packet_mode_supported = 1; + cap->nonleaf.shaper_private_byte_mode_supported = 1; + + /* MDQ doesn't support Strict Priority */ + if ((int)lvl == (n_lvl - 1)) + cap->nonleaf.sched_n_children_max = dev->nb_txq; + else + cap->nonleaf.sched_n_children_max = schq[lvl - 1]; + cap->nonleaf.sched_sp_n_priorities_max = + roc_nix_tm_max_prio(nix, lvl) + 1; + cap->nonleaf.sched_wfq_n_groups_max = 1; + cap->nonleaf.sched_wfq_weight_max = + roc_nix_tm_max_sched_wt_get(); + cap->nonleaf.sched_wfq_packet_mode_supported = 1; + cap->nonleaf.sched_wfq_byte_mode_supported = 1; + } else { + /* unsupported level */ + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + return rc; + } + return 0; +} + +static int +cnxk_nix_tm_node_capa_get(struct rte_eth_dev *eth_dev, uint32_t node_id, + struct rte_tm_node_capabilities *cap, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_nix_tm_node *tm_node; + struct roc_nix *nix = &dev->nix; + uint16_t schq[ROC_TM_LVL_MAX]; + int rc, n_lvl, lvl; + + memset(cap, 0, sizeof(*cap)); + + tm_node = (struct cnxk_nix_tm_node *)roc_nix_tm_node_get(nix, node_id); + if (!tm_node) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "no such node"; + return -EINVAL; + } + + lvl = tm_node->nix_node.lvl; + n_lvl = roc_nix_tm_lvl_cnt_get(nix); + + /* Leaf node */ + if (roc_nix_tm_lvl_is_leaf(nix, lvl)) { + cap->stats_mask = RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_BYTES; + return 0; + } + + rc = roc_nix_tm_rsrc_count(nix, schq); + if (rc) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message = "unexpected fatal error"; + return rc; + } + + /* Non Leaf Shaper */ + cap->shaper_private_supported = true; + cap->shaper_private_rate_min = NIX_TM_MIN_SHAPER_RATE / 8; + cap->shaper_private_rate_max = NIX_TM_MAX_SHAPER_RATE / 8; + cap->shaper_private_packet_mode_supported = 1; + cap->shaper_private_byte_mode_supported = 1; + + /* Non Leaf Scheduler */ + if (lvl == (n_lvl - 1)) + cap->nonleaf.sched_n_children_max = dev->nb_txq; + else + cap->nonleaf.sched_n_children_max = schq[lvl - 1]; + + cap->nonleaf.sched_sp_n_priorities_max = + roc_nix_tm_max_prio(nix, lvl) + 1; + cap->nonleaf.sched_wfq_n_children_per_group_max = + cap->nonleaf.sched_n_children_max; + cap->nonleaf.sched_wfq_n_groups_max = 1; + cap->nonleaf.sched_wfq_weight_max = roc_nix_tm_max_sched_wt_get(); + cap->nonleaf.sched_wfq_packet_mode_supported = 1; + cap->nonleaf.sched_wfq_byte_mode_supported = 1; + + cap->shaper_private_dual_rate_supported = true; + if (roc_nix_tm_lvl_have_link_access(nix, lvl)) { + cap->shaper_private_dual_rate_supported = false; + cap->stats_mask = RTE_TM_STATS_N_PKTS_RED_DROPPED | + RTE_TM_STATS_N_BYTES_RED_DROPPED; + } + + return 0; +} + +const struct rte_tm_ops cnxk_tm_ops = { + .node_type_get = cnxk_nix_tm_node_type_get, + .capabilities_get = cnxk_nix_tm_capa_get, + .level_capabilities_get = cnxk_nix_tm_level_capa_get, + .node_capabilities_get = cnxk_nix_tm_node_capa_get, +}; + +int +cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev __rte_unused, void *arg) +{ + if (!arg) + return -EINVAL; + + /* Check for supported revisions */ + if (roc_model_is_cn96_ax() || roc_model_is_cn95_a0()) + return -EINVAL; + + *(const void **)arg = &cnxk_tm_ops; + + return 0; +} + +int +cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev, + uint16_t queue_idx, uint16_t tx_rate_mbps) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint64_t tx_rate = tx_rate_mbps * (uint64_t)1E6; + struct roc_nix *nix = &dev->nix; + int rc = -EINVAL; + + /* Check for supported revisions */ + if (roc_model_is_cn96_ax() || roc_model_is_cn95_a0()) + goto exit; + + if (queue_idx >= eth_dev->data->nb_tx_queues) + goto exit; + + if ((roc_nix_tm_tree_type_get(nix) != ROC_NIX_TM_RLIMIT) && + eth_dev->data->nb_tx_queues > 1) { + /* + * Disable xmit will be enabled when + * new topology is available. + */ + rc = roc_nix_tm_hierarchy_disable(nix); + if (rc) + goto exit; + + rc = roc_nix_tm_prepare_rate_limited_tree(nix); + if (rc) + goto exit; + + rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_RLIMIT, true); + if (rc) + goto exit; + } + + return roc_nix_tm_rlimit_sq(nix, queue_idx, tx_rate); +exit: + return rc; +} diff --git a/drivers/net/cnxk/cnxk_tm.h b/drivers/net/cnxk/cnxk_tm.h new file mode 100644 index 0000000..f7470c2 --- /dev/null +++ b/drivers/net/cnxk/cnxk_tm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#ifndef __CNXK_TM_H__ +#define __CNXK_TM_H__ + +#include + +#include + +#include "roc_api.h" + +struct cnxk_nix_tm_node { + struct roc_nix_tm_node nix_node; + struct rte_tm_node_params params; +}; + +#endif /* __CNXK_TM_H__ */ diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build index d4cdd17..1e86144 100644 --- a/drivers/net/cnxk/meson.build +++ b/drivers/net/cnxk/meson.build @@ -17,6 +17,7 @@ sources = files( 'cnxk_ptp.c', 'cnxk_rte_flow.c', 'cnxk_stats.c', + 'cnxk_tm.c', ) # CN9K From patchwork Sat Sep 18 14:31:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satha Koteswara Rao Kottidi X-Patchwork-Id: 99294 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EEE64A0C45; Sat, 18 Sep 2021 16:33:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 69BA24111E; Sat, 18 Sep 2021 16:32:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B77C6410ED for ; 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Sat, 18 Sep 2021 07:32:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 18 Sep 2021 07:32:29 -0700 Received: from cavium.marvell.com (unknown [10.28.34.244]) by maili.marvell.com (Postfix) with ESMTP id 87B183F7057; Sat, 18 Sep 2021 07:32:28 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Sat, 18 Sep 2021 10:31:58 -0400 Message-ID: <1631975519-30924-9-git-send-email-skoteshwar@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 3ZfGLEZ-XRLiF8X0e_eI6F1TcNIicmX7 X-Proofpoint-GUID: 3ZfGLEZ-XRLiF8X0e_eI6F1TcNIicmX7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-18_05,2021-09-17_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 8/8] net/cnxk: tm shaper and node operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao Implemented TM node, shaper profile, hierarchy_commit and statistic operations. Signed-off-by: Satha Rao --- doc/guides/rel_notes/release_21_11.rst | 1 + drivers/net/cnxk/cnxk_tm.c | 353 +++++++++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_tm.h | 5 + 3 files changed, 359 insertions(+) diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index df4ffc3..36b1f65 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -85,6 +85,7 @@ New Features * **Updated Marvell cnxk ethdev driver.** * Added rte_flow support for dual VLAN insert and strip actions + * Added rte_tm support * **Added multi-process support for testpmd.** diff --git a/drivers/net/cnxk/cnxk_tm.c b/drivers/net/cnxk/cnxk_tm.c index 87fd8be..9015a45 100644 --- a/drivers/net/cnxk/cnxk_tm.c +++ b/drivers/net/cnxk/cnxk_tm.c @@ -259,11 +259,364 @@ return 0; } +static int +cnxk_nix_tm_shaper_profile_add(struct rte_eth_dev *eth_dev, uint32_t id, + struct rte_tm_shaper_params *params, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_nix_tm_shaper_profile *profile; + struct roc_nix *nix = &dev->nix; + int rc; + + if (roc_nix_tm_shaper_profile_get(nix, id)) { + error->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + error->message = "shaper profile ID exist"; + return -EINVAL; + } + + profile = rte_zmalloc("cnxk_nix_tm_shaper_profile", + sizeof(struct cnxk_nix_tm_shaper_profile), 0); + if (!profile) + return -ENOMEM; + profile->profile.id = id; + profile->profile.commit_rate = params->committed.rate; + profile->profile.peak_rate = params->peak.rate; + profile->profile.commit_sz = params->committed.size; + profile->profile.peak_sz = params->peak.size; + /* If Byte mode, then convert to bps */ + if (!params->packet_mode) { + profile->profile.commit_rate *= 8; + profile->profile.peak_rate *= 8; + profile->profile.commit_sz *= 8; + profile->profile.peak_sz *= 8; + } + profile->profile.pkt_len_adj = params->pkt_length_adjust; + profile->profile.pkt_mode = params->packet_mode; + profile->profile.free_fn = rte_free; + rte_memcpy(&profile->params, params, + sizeof(struct rte_tm_shaper_params)); + + rc = roc_nix_tm_shaper_profile_add(nix, &profile->profile); + + /* fill error information based on return value */ + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + } + + return rc; +} + +static int +cnxk_nix_tm_shaper_profile_delete(struct rte_eth_dev *eth_dev, + uint32_t profile_id, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + int rc; + + rc = roc_nix_tm_shaper_profile_delete(nix, profile_id); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + } + + return rc; +} + +static int +cnxk_nix_tm_node_add(struct rte_eth_dev *eth_dev, uint32_t node_id, + uint32_t parent_node_id, uint32_t priority, + uint32_t weight, uint32_t lvl, + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix_tm_shaper_profile *profile; + struct roc_nix_tm_node *parent_node; + struct roc_nix *nix = &dev->nix; + struct cnxk_nix_tm_node *node; + int rc; + + /* we don't support dynamic updates */ + if (roc_nix_tm_is_user_hierarchy_enabled(nix)) { + error->type = RTE_TM_ERROR_TYPE_CAPABILITIES; + error->message = "dynamic update not supported"; + return -EIO; + } + + parent_node = roc_nix_tm_node_get(nix, parent_node_id); + /* find the right level */ + if (lvl == RTE_TM_NODE_LEVEL_ID_ANY) { + if (parent_node_id == RTE_TM_NODE_ID_NULL) { + lvl = ROC_TM_LVL_ROOT; + } else if (parent_node) { + lvl = parent_node->lvl + 1; + } else { + /* Neither proper parent nor proper level id given */ + error->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + error->message = "invalid parent node id"; + return -ERANGE; + } + } + + node = rte_zmalloc("cnxk_nix_tm_node", sizeof(struct cnxk_nix_tm_node), + 0); + if (!node) + return -ENOMEM; + + rte_memcpy(&node->params, params, sizeof(struct rte_tm_node_params)); + + node->nix_node.id = node_id; + node->nix_node.parent_id = parent_node_id; + node->nix_node.priority = priority; + node->nix_node.weight = weight; + node->nix_node.lvl = lvl; + node->nix_node.shaper_profile_id = params->shaper_profile_id; + + profile = roc_nix_tm_shaper_profile_get(nix, params->shaper_profile_id); + /* Packet mode */ + if (!roc_nix_tm_lvl_is_leaf(nix, lvl) && + ((profile && profile->pkt_mode) || + (params->nonleaf.wfq_weight_mode && + params->nonleaf.n_sp_priorities && + !params->nonleaf.wfq_weight_mode[0]))) + node->nix_node.pkt_mode = 1; + + rc = roc_nix_tm_node_add(nix, &node->nix_node); + if (rc < 0) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + return rc; + } + error->type = RTE_TM_ERROR_TYPE_NONE; + roc_nix_tm_shaper_default_red_algo(&node->nix_node, profile); + + return 0; +} + +static int +cnxk_nix_tm_node_delete(struct rte_eth_dev *eth_dev, uint32_t node_id, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + struct cnxk_nix_tm_node *node; + int rc; + + /* we don't support dynamic updates yet */ + if (roc_nix_tm_is_user_hierarchy_enabled(nix)) { + error->type = RTE_TM_ERROR_TYPE_CAPABILITIES; + error->message = "hierarchy exists"; + return -EIO; + } + + if (node_id == RTE_TM_NODE_ID_NULL) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "invalid node id"; + return -EINVAL; + } + + node = (struct cnxk_nix_tm_node *)roc_nix_tm_node_get(nix, node_id); + + rc = roc_nix_tm_node_delete(nix, node_id, 0); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + } else { + rte_free(node); + } + + return rc; +} + +static int +cnxk_nix_tm_node_suspend(struct rte_eth_dev *eth_dev, uint32_t node_id, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + int rc; + + rc = roc_nix_tm_node_suspend_resume(&dev->nix, node_id, true); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + } + + return rc; +} + +static int +cnxk_nix_tm_node_resume(struct rte_eth_dev *eth_dev, uint32_t node_id, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + int rc; + + rc = roc_nix_tm_node_suspend_resume(&dev->nix, node_id, false); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + } + + return rc; +} + +static int +cnxk_nix_tm_hierarchy_commit(struct rte_eth_dev *eth_dev, + int clear_on_fail __rte_unused, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + int rc; + + if (roc_nix_tm_is_user_hierarchy_enabled(nix)) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message = "hierarchy exists"; + return -EIO; + } + + if (roc_nix_tm_leaf_cnt(nix) < dev->nb_txq) { + error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message = "incomplete hierarchy"; + return -EINVAL; + } + + rc = roc_nix_tm_hierarchy_disable(nix); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + return -EIO; + } + + rc = roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_USER, true); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + return -EIO; + } + error->type = RTE_TM_ERROR_TYPE_NONE; + + return 0; +} + +static int +cnxk_nix_tm_node_shaper_update(struct rte_eth_dev *eth_dev, uint32_t node_id, + uint32_t profile_id, struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix_tm_shaper_profile *profile; + struct roc_nix *nix = &dev->nix; + struct roc_nix_tm_node *node; + int rc; + + rc = roc_nix_tm_node_shaper_update(nix, node_id, profile_id, false); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + return -EINVAL; + } + node = roc_nix_tm_node_get(nix, node_id); + if (!node) + return -EINVAL; + + profile = roc_nix_tm_shaper_profile_get(nix, profile_id); + roc_nix_tm_shaper_default_red_algo(node, profile); + + return 0; +} + +static int +cnxk_nix_tm_node_parent_update(struct rte_eth_dev *eth_dev, uint32_t node_id, + uint32_t new_parent_id, uint32_t priority, + uint32_t weight, struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + int rc; + + rc = roc_nix_tm_node_parent_update(nix, node_id, new_parent_id, + priority, weight); + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + return -EINVAL; + } + + return 0; +} + +static int +cnxk_nix_tm_node_stats_read(struct rte_eth_dev *eth_dev, uint32_t node_id, + struct rte_tm_node_stats *stats, + uint64_t *stats_mask, int clear, + struct rte_tm_error *error) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix_tm_node_stats nix_tm_stats; + struct roc_nix *nix = &dev->nix; + struct roc_nix_tm_node *node; + int rc; + + node = roc_nix_tm_node_get(nix, node_id); + if (!node) { + error->type = RTE_TM_ERROR_TYPE_NODE_ID; + error->message = "no such node"; + return -EINVAL; + } + + if (roc_nix_tm_lvl_is_leaf(nix, node->lvl)) { + struct roc_nix_stats_queue qstats; + + rc = roc_nix_stats_queue_get(nix, node->id, 0, &qstats); + if (!rc) { + stats->n_pkts = qstats.tx_pkts; + stats->n_bytes = qstats.tx_octs; + *stats_mask = + RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_BYTES; + } + goto exit; + } + + rc = roc_nix_tm_node_stats_get(nix, node_id, clear, &nix_tm_stats); + if (!rc) { + stats->leaf.n_pkts_dropped[RTE_COLOR_RED] = + nix_tm_stats.stats[ROC_NIX_TM_NODE_PKTS_DROPPED]; + stats->leaf.n_bytes_dropped[RTE_COLOR_RED] = + nix_tm_stats.stats[ROC_NIX_TM_NODE_BYTES_DROPPED]; + *stats_mask = RTE_TM_STATS_N_PKTS_RED_DROPPED | + RTE_TM_STATS_N_BYTES_RED_DROPPED; + } + +exit: + if (rc) { + error->type = roc_nix_tm_err_to_rte_err(rc); + error->message = roc_error_msg_get(rc); + } + return rc; +} + const struct rte_tm_ops cnxk_tm_ops = { .node_type_get = cnxk_nix_tm_node_type_get, .capabilities_get = cnxk_nix_tm_capa_get, .level_capabilities_get = cnxk_nix_tm_level_capa_get, .node_capabilities_get = cnxk_nix_tm_node_capa_get, + + .shaper_profile_add = cnxk_nix_tm_shaper_profile_add, + .shaper_profile_delete = cnxk_nix_tm_shaper_profile_delete, + + .node_add = cnxk_nix_tm_node_add, + .node_delete = cnxk_nix_tm_node_delete, + .node_suspend = cnxk_nix_tm_node_suspend, + .node_resume = cnxk_nix_tm_node_resume, + .hierarchy_commit = cnxk_nix_tm_hierarchy_commit, + + .node_shaper_update = cnxk_nix_tm_node_shaper_update, + .node_parent_update = cnxk_nix_tm_node_parent_update, + .node_stats_read = cnxk_nix_tm_node_stats_read, }; int diff --git a/drivers/net/cnxk/cnxk_tm.h b/drivers/net/cnxk/cnxk_tm.h index f7470c2..419c551 100644 --- a/drivers/net/cnxk/cnxk_tm.h +++ b/drivers/net/cnxk/cnxk_tm.h @@ -15,4 +15,9 @@ struct cnxk_nix_tm_node { struct rte_tm_node_params params; }; +struct cnxk_nix_tm_shaper_profile { + struct roc_nix_tm_shaper_profile profile; + struct rte_tm_shaper_params params; /* Rate in bits/sec */ +}; + #endif /* __CNXK_TM_H__ */