From patchwork Fri Oct 12 11:09:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46696 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 268211B53B; Fri, 12 Oct 2018 13:09:09 +0200 (CEST) Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720071.outbound.protection.outlook.com [40.107.72.71]) by dpdk.org (Postfix) with ESMTP id B27411B463 for ; Fri, 12 Oct 2018 13:09:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UNnvq7E+PfqaAmN0H7xEFfagOGYHL8A6D3r6F9A8koI=; b=gLOdTlspKsZPkR0wgZwb5uCrzxfVpESvt1xhAIuj26WXuteoLnckjd6vTDsOJUTtpQ1wxCPVQ43v0K4LhPZ6XZoamItJ2RYkTZ2o3+0WdkJIK0/TJMU5nwXm3ptvw4dTVdgOpN0krOzQO4Y54jAzz/HIMVM0wiGZ0KAcDdExw+s= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:04 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:04 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 01/22] net/atlantic: add atlantic PMD driver skeleton Thread-Index: AQHUYhv8tWO5jmHvNEKuhVEhT8GFwg== Date: Fri, 12 Oct 2018 11:09:03 +0000 Message-ID: <60035a144b2ecf4190fd1ed4c5aef70e24dafdee.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:MbGRVltWRU9UhFgZz4Jc18zNrkcE9ImsPn9JwBv/EOGF70KIXy5+pUHJqiGGSXSqWiyAb8XYCLbNvM2u6ip8Nb49zZ84c1DQfspjz6GzcBds3PKhVB+9abdWMy+CxDVLIjzBu7YyHVG5REr11Z7HWM1yHZiZVLNdYxuViQc8netI9JzXMxPl/L0QAXmr44kdw5uQszOcc6lbV46Az6VVw5tOA5+xgRjhlQdiOOyvE2f8j/CXE47WNsFc2iNPgOaXpq+MTtCh27/Q6KTzbxcI9L3OxAXCR9Woj0XFCM97EQR11Be6w4fsRg5pb2Pujl82kNx06/odo/lKNDwwS6jIFaDYZihJZRkx5fJptFTYZYgr5Uc89PeiHim3qQCSqhxrQcj3mKFVq5zKpk9L+2KoR/kqAA7wd30jvBnFRgO78iVxqCXP3AMeI+LEVLAcBJTarsErzjFjoaL5FcJO47qs7SA6FZ7NF8pDM4XJqnmEn/A=; 5:o0+ST+rOKPieJirdwE3t1kPZWmfGzRlu9DWZmdpKcRjn+ekTUXD3CplZFvJkG7AX8esFPK5DU/mJxkZrrOZnD3EI1jdTKmvBu0LPI1m/UjAd5xK9aYod2HPBb//xmAO5Y8+ptTX/lU7WvwA12ZdfYESQY4tlDf1pJF/KQmkqycY=; 7:Lo8/Ac/JII/jKjHV9mZd3qzxwXM7irajg5SFVINKb9pZTXOlfmpMQpVGIOgzvBPi9GuESwYZhXn2681OgkteC3tYnh59lW0uKBhGtzZtjBXfughymrCR6RWOoV+SIaE9GwvrJQnz7ENhs+O7K97BmfaIuGKDVNmhC5OoirFJJyLb9Fu6/E6WwE8J7KkUioCvh1TQm0ZoG5oboZ6rac/pTip6+02kJEe9bNNRI4HGQrpKn+nSuH8BLAFAgYaqBtU+ x-ms-office365-filtering-correlation-id: 90bf74fc-f171-46c5-f63b-08d630331e5b x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(4744004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(53946003)(6306002)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(575784001)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: brfrQSMJKz2ebGI72cJBXqLnKzq9rjAdpDmBUmeYeN2VX9aLAG80t+/rZMf26OhF6TDrua1RKW50Dkexv1SNpBzNX69rLvqv1TsEWgBehOCTq6pLGHighu6aGoarjGDPGQ2DSN43g6ZVMejBViGyIlE6H6XTJYyTPWGtUXp6KPRG19LUqn13e1VXjvZUzacEb41J3+CCHv9Ndu4uFBFt27ojcmEEKeRll4lRJw4qGPVNL04ky4/c6oEw6CXWWaW+7ACo4fxj7XhuFJO736VmxuPw9rVkUcCL5oXaTof4PhIS3L6i19fKJ/oc3J8K0x4C+taIBjhz5/pglYgu5nUthsJl/LewopdReANJXRuitJg= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 90bf74fc-f171-46c5-f63b-08d630331e5b X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:03.9349 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 01/22] net/atlantic: add atlantic PMD driver skeleton X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Makefile/meson build infrastructure, atl_ethdev minimal skeleton, header with aquantia aQtion NIC device and vendor IDs. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- MAINTAINERS | 7 + config/common_base | 5 + config/defconfig_ppc_64-power8-linuxapp-gcc | 1 + doc/guides/nics/atlantic.rst | 37 +++++ doc/guides/nics/features/atlantic.ini | 10 ++ doc/guides/nics/index.rst | 1 + drivers/net/Makefile | 1 + drivers/net/atlantic/Makefile | 27 ++++ drivers/net/atlantic/atl_common.h | 96 ++++++++++++ drivers/net/atlantic/atl_ethdev.c | 170 ++++++++++++++++++++++ drivers/net/atlantic/atl_ethdev.h | 15 ++ drivers/net/atlantic/meson.build | 6 + drivers/net/atlantic/rte_pmd_atlantic_version.map | 4 + drivers/net/meson.build | 1 + mk/rte.app.mk | 1 + 15 files changed, 382 insertions(+) create mode 100644 doc/guides/nics/atlantic.rst create mode 100644 doc/guides/nics/features/atlantic.ini create mode 100644 drivers/net/atlantic/Makefile create mode 100644 drivers/net/atlantic/atl_common.h create mode 100644 drivers/net/atlantic/atl_ethdev.c create mode 100644 drivers/net/atlantic/atl_ethdev.h create mode 100644 drivers/net/atlantic/meson.build create mode 100644 drivers/net/atlantic/rte_pmd_atlantic_version.map diff --git a/MAINTAINERS b/MAINTAINERS index 84b9ff786628..80c964a5144f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -485,6 +485,13 @@ F: drivers/net/axgbe/ F: doc/guides/nics/axgbe.rst F: doc/guides/nics/features/axgbe.ini +Aquantia atlantic +M: Igor Russkikh +M: Pavel Belous +F: drivers/net/atlantic/ +F: doc/guides/nics/atlantic.rst +F: doc/guides/nics/features/atlantic.ini + Atomic Rules ARK M: Shepard Siegel M: Ed Czeck diff --git a/config/common_base b/config/common_base index acc5211bcc17..090ed26d13a1 100644 --- a/config/common_base +++ b/config/common_base @@ -641,6 +641,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n # +# Compile Aquantia Atlantic PMD driver +# +CONFIG_RTE_LIBRTE_ATLANTIC_PMD=y + +# # Compile raw device support # EXPERIMENTAL: API may change without prior notice # diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc index a52e22efcc9d..8cbf7ed50c15 100644 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc @@ -48,6 +48,7 @@ CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n # Note: Initially, all of the PMD drivers compilation are turned off on Power # Will turn on them only after the successful testing on Power +CONFIG_RTE_LIBRTE_ATLANTIC_PMD=n CONFIG_RTE_LIBRTE_IXGBE_PMD=n CONFIG_RTE_LIBRTE_VIRTIO_PMD=y CONFIG_RTE_LIBRTE_VMXNET3_PMD=n diff --git a/doc/guides/nics/atlantic.rst b/doc/guides/nics/atlantic.rst new file mode 100644 index 000000000000..21e52bb26625 --- /dev/null +++ b/doc/guides/nics/atlantic.rst @@ -0,0 +1,37 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2018 Aquantia Corporation. + +Aquantia Atlantic DPDK Driver +============================= + +Atlantic DPDK driver provides DPDK support for Aquantia's AQtion family of chipsets: AQC107/AQC108/AQC109 + +More information can be found at `Aquantia Official Website +`_. + +Supported features +^^^^^^^^^^^^^^^^^^ + +Configuration Information +^^^^^^^^^^^^^^^^^^^^^^^^^ + +- ``CONFIG_RTE_LIBRTE_ATLANTIC_PMD`` (default ``y``) + +Application Programming Interface +--------------------------------- + +Limitations or Known issues +--------------------------- + +Statistics +~~~~~~~~~~ + +MTU setting +~~~~~~~~~~~ + +Supported Chipsets and NICs +--------------------------- + +- Aquantia AQtion AQC107 10 Gigabit Ethernet Controller +- Aquantia AQtion AQC108 5 Gigabit Ethernet Controller +- Aquantia AQtion AQC109 2.5 Gigabit Ethernet Controller diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini new file mode 100644 index 000000000000..e6c5676acf7a --- /dev/null +++ b/doc/guides/nics/features/atlantic.ini @@ -0,0 +1,10 @@ +; +; Supported features of the 'atlantic' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Linux UIO = Y +ARMv8 = Y +x86-32 = Y +x86-64 = Y diff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst index 59f6063dce92..7925c2bd86ff 100644 --- a/doc/guides/nics/index.rst +++ b/doc/guides/nics/index.rst @@ -12,6 +12,7 @@ Network Interface Controller Drivers features build_and_test ark + atlantic avp axgbe bnx2x diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 664398de983a..8ac6b9db5916 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -10,6 +10,7 @@ endif DIRS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += af_packet DIRS-$(CONFIG_RTE_LIBRTE_ARK_PMD) += ark +DIRS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atlantic DIRS-$(CONFIG_RTE_LIBRTE_AVF_PMD) += avf DIRS-$(CONFIG_RTE_LIBRTE_AVP_PMD) += avp DIRS-$(CONFIG_RTE_LIBRTE_AXGBE_PMD) += axgbe diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile new file mode 100644 index 000000000000..e42ce5b178ab --- /dev/null +++ b/drivers/net/atlantic/Makefile @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Aquantia Corporation + +include $(RTE_SDK)/mk/rte.vars.mk + +# +# library name +# +LIB = librte_pmd_atlantic.a + +CFLAGS += -O3 +CFLAGS += $(WERROR_FLAGS) + +EXPORT_MAP := rte_pmd_atlantic_version.map + +LIBABIVER := 1 + +LDLIBS += -lrte_eal +LDLIBS += -lrte_ethdev -lrte_net +LDLIBS += -lrte_bus_pci + +# +# all source are stored in SRCS-y +# +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_common.h b/drivers/net/atlantic/atl_common.h new file mode 100644 index 000000000000..b3a0aa5cd212 --- /dev/null +++ b/drivers/net/atlantic/atl_common.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#ifndef AQ_COMMON_H +#define AQ_COMMON_H + +#define ATL_PMD_DRIVER_VERSION "0.4.1" + +#define PCI_VENDOR_ID_AQUANTIA 0x1D6A + +#define AQ_DEVICE_ID_0001 0x0001 +#define AQ_DEVICE_ID_D100 0xD100 +#define AQ_DEVICE_ID_D107 0xD107 +#define AQ_DEVICE_ID_D108 0xD108 +#define AQ_DEVICE_ID_D109 0xD109 + +#define AQ_DEVICE_ID_AQC100 0x00B1 +#define AQ_DEVICE_ID_AQC107 0x07B1 +#define AQ_DEVICE_ID_AQC108 0x08B1 +#define AQ_DEVICE_ID_AQC109 0x09B1 +#define AQ_DEVICE_ID_AQC111 0x11B1 +#define AQ_DEVICE_ID_AQC112 0x12B1 + +#define AQ_DEVICE_ID_AQC100S 0x80B1 +#define AQ_DEVICE_ID_AQC107S 0x87B1 +#define AQ_DEVICE_ID_AQC108S 0x88B1 +#define AQ_DEVICE_ID_AQC109S 0x89B1 +#define AQ_DEVICE_ID_AQC111S 0x91B1 +#define AQ_DEVICE_ID_AQC112S 0x92B1 + +#define AQ_DEVICE_ID_AQC111E 0x51B1 +#define AQ_DEVICE_ID_AQC112E 0x52B1 + +#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter" + +#define AQ_HWREV_ANY 0 +#define AQ_HWREV_1 1 +#define AQ_HWREV_2 2 + +#define AQ_NIC_RATE_10G BIT(0) +#define AQ_NIC_RATE_5G BIT(1) +#define AQ_NIC_RATE_5G5R BIT(2) +#define AQ_NIC_RATE_2G5 BIT(3) +#define AQ_NIC_RATE_1G BIT(4) +#define AQ_NIC_RATE_100M BIT(5) + +#define AQ_NIC_RATE_EEE_10G BIT(6) +#define AQ_NIC_RATE_EEE_5G BIT(7) +#define AQ_NIC_RATE_EEE_2G5 BIT(8) +#define AQ_NIC_RATE_EEE_1G BIT(9) + + +#define ATL_MAX_RING_DESC (8 * 1024 - 8) +#define ATL_MIN_RING_DESC 32 +#define ATL_RXD_ALIGN 8 +#define ATL_TXD_ALIGN 8 +#define ATL_TX_MAX_SEG 16 + +#define ATL_MAX_INTR_QUEUE_NUM 15 + +#define ATL_MISC_VEC_ID 10 +#define ATL_RX_VEC_START 0 + +#define AQ_NIC_WOL_ENABLED BIT(0) + + +#define AQ_NIC_FC_OFF 0U +#define AQ_NIC_FC_TX 1U +#define AQ_NIC_FC_RX 2U +#define AQ_NIC_FC_FULL 3U +#define AQ_NIC_FC_AUTO 4U + + +#define AQ_CFG_TX_FRAME_MAX (16U * 1024U) +#define AQ_CFG_RX_FRAME_MAX (2U * 1024U) + +#define AQ_HW_MULTICAST_ADDRESS_MAX 32 +#define AQ_HW_MAX_SEGS_SIZE 40 + +#define AQ_HW_MAX_RX_QUEUES 8 +#define AQ_HW_MAX_TX_QUEUES 8 +#define AQ_HW_MIN_RX_RING_SIZE 512 +#define AQ_HW_MAX_RX_RING_SIZE 8192 +#define AQ_HW_MIN_TX_RING_SIZE 512 +#define AQ_HW_MAX_TX_RING_SIZE 8192 + +#define ATL_DEFAULT_RX_FREE_THRESH 64 +#define ATL_DEFAULT_TX_FREE_THRESH 64 + +#define ATL_IRQ_CAUSE_LINK 0x8 + +#define AQ_HW_LED_BLINK 0x2U +#define AQ_HW_LED_DEFAULT 0x0U + +#endif /* AQ_COMMON_H */ diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c new file mode 100644 index 000000000000..a9d7a5a49398 --- /dev/null +++ b/drivers/net/atlantic/atl_ethdev.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#include + +#include "atl_ethdev.h" +#include "atl_common.h" + +static int eth_atl_dev_init(struct rte_eth_dev *eth_dev); +static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev); + +static int atl_dev_configure(struct rte_eth_dev *dev); +static int atl_dev_start(struct rte_eth_dev *dev); +static void atl_dev_stop(struct rte_eth_dev *dev); +static void atl_dev_close(struct rte_eth_dev *dev); +static int atl_dev_reset(struct rte_eth_dev *dev); + +static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev); +static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); + +static void atl_dev_info_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *dev_info); + +/* + * The set of PCI devices this driver supports + */ +static const struct rte_pci_id pci_id_atl_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_0001) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D100) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D107) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D108) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D109) }, + + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC100) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC107) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC108) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC109) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112) }, + + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC100S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC107S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC108S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC109S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112S) }, + + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111E) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112E) }, + { .vendor_id = 0, /* sentinel */ }, +}; + +static struct rte_pci_driver rte_atl_pmd = { + .id_table = pci_id_atl_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | + RTE_PCI_DRV_IOVA_AS_VA, + .probe = eth_atl_pci_probe, + .remove = eth_atl_pci_remove, +}; + +static const struct eth_dev_ops atl_eth_dev_ops = { + .dev_configure = atl_dev_configure, + .dev_start = atl_dev_start, + .dev_stop = atl_dev_stop, + .dev_close = atl_dev_close, + .dev_reset = atl_dev_reset, + .dev_infos_get = atl_dev_info_get, +}; + +static int +eth_atl_dev_init(struct rte_eth_dev *eth_dev) +{ + eth_dev->dev_ops = &atl_eth_dev_ops; + + /* Allocate memory for storing MAC addresses */ + eth_dev->data->mac_addrs = rte_zmalloc("atlantic", ETHER_ADDR_LEN, 0); + if (eth_dev->data->mac_addrs == NULL) + return -ENOMEM; + + return 0; +} + +static int +eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) +{ + rte_free(eth_dev->data->mac_addrs); + + return 0; +} + +static int +eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(struct atl_adapter), eth_atl_dev_init); +} + +static int +eth_atl_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, eth_atl_dev_uninit); +} + +static int +atl_dev_configure(struct rte_eth_dev *dev __rte_unused) +{ + return 0; +} + +/* + * Configure device link speed and setup link. + * It returns 0 on success. + */ +static int +atl_dev_start(struct rte_eth_dev *dev __rte_unused) +{ + return 0; +} + +/* + * Stop device: disable rx and tx functions to allow for reconfiguring. + */ +static void +atl_dev_stop(struct rte_eth_dev *dev __rte_unused) +{ +} + +/* + * Reset and stop device. + */ +static void +atl_dev_close(struct rte_eth_dev *dev __rte_unused) +{ +} + +static int +atl_dev_reset(struct rte_eth_dev *dev) +{ + int ret; + + ret = eth_atl_dev_uninit(dev); + if (ret) + return ret; + + ret = eth_atl_dev_init(dev); + + return ret; +} + +static void +atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + + dev_info->max_rx_queues = 0; + dev_info->max_rx_queues = 0; + + dev_info->max_vfs = pci_dev->max_vfs; + + dev_info->max_hash_mac_addrs = 0; + dev_info->max_vmdq_pools = 0; + dev_info->vmdq_queue_num = 0; +} + +RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); +RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h new file mode 100644 index 000000000000..622806837379 --- /dev/null +++ b/drivers/net/atlantic/atl_ethdev.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#ifndef _ATLANTIC_ETHDEV_H_ +#define _ATLANTIC_ETHDEV_H_ +#include +#include "rte_ethdev.h" +/* + * Structure to store private data for each driver instance (for each port). + */ +struct atl_adapter { +}; + +#endif /* _ATLANTIC_ETHDEV_H_ */ diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build new file mode 100644 index 000000000000..c5a2546ef657 --- /dev/null +++ b/drivers/net/atlantic/meson.build @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Aquantia Corporation + +sources = files( + 'atl_ethdev.c', +) diff --git a/drivers/net/atlantic/rte_pmd_atlantic_version.map b/drivers/net/atlantic/rte_pmd_atlantic_version.map new file mode 100644 index 000000000000..521e51f411fb --- /dev/null +++ b/drivers/net/atlantic/rte_pmd_atlantic_version.map @@ -0,0 +1,4 @@ +DPDK_18.11 { + + local: *; +}; diff --git a/drivers/net/meson.build b/drivers/net/meson.build index 5906283c2f5c..32374141a9ea 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -3,6 +3,7 @@ drivers = ['af_packet', 'ark', + 'atlantic', 'avf', 'avp', 'axgbe', 'bonding', diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 32579e4b7587..009280701034 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -123,6 +123,7 @@ endif _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += -lrte_pmd_af_packet _LDLIBS-$(CONFIG_RTE_LIBRTE_ARK_PMD) += -lrte_pmd_ark +_LDLIBS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += -lrte_pmd_atlantic _LDLIBS-$(CONFIG_RTE_LIBRTE_AVF_PMD) += -lrte_pmd_avf _LDLIBS-$(CONFIG_RTE_LIBRTE_AVP_PMD) += -lrte_pmd_avp _LDLIBS-$(CONFIG_RTE_LIBRTE_AXGBE_PMD) += -lrte_pmd_axgbe From patchwork Fri Oct 12 11:09:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46697 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0972B1B55B; Fri, 12 Oct 2018 13:09:11 +0200 (CEST) Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720056.outbound.protection.outlook.com [40.107.72.56]) by dpdk.org (Postfix) with ESMTP id 5A8F71B502 for ; Fri, 12 Oct 2018 13:09:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QWnvlqlfJ4IsoKUorapPPmPi4/lyrxMRcI3tPH4qxoU=; b=n+9qURg8f0nyjE5N4/f3GqHfVlmRfia47969TQJXzT0K6mXWtKh0zHPoTnYgiYTmUOSADRuJGQHOKTkkZWe6ZlyZgOZmjuUnLgDoTjWKF5V7I8+ip45BYPpCazetfxP7hm6IPqWf6Nz9JNVIkU7x9nc7ifl6YZ/RgZsWbL5wUWE= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:06 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:06 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 02/22] net/atlantic: add logging structure Thread-Index: AQHUYhv9FGg2yK0mkke26HAgVbX44Q== Date: Fri, 12 Oct 2018 11:09:06 +0000 Message-ID: <1244aa0d2a52522e382b38c4792b7401f2fa4c87.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:25aGtHIF1ggQnRal1P+CrCdu62LonB+3PYmcN/hdg2pFg3wdS5uuYExXbnULd/z0u96+oIksXIaBV+MbT2oimlMpQWEIrmxBkuC3FcxIVL+MoXNen5xDtRQ4RE/GTUpUnJwbIELZcGIAQOGx3MWdycO979tYHuZWA2mWhAhWELl8CN/31c8RJiexI+8D9JVDixv99ZogEXpfZ10czHWRXtRF+y20BAezrPavYdAq1jeI8Xsnk0AdrvtofxAQxuMytLKpNu74WkTDzls0/5iaPWhTx/mPxUwJsx9GJmW+54GkwUn/x5PPz6ASqXkxk2BATNhUn+hRZnnZwXwO/fnHCQDktKtQZdvDOp3Wxw1LEANwjqqnTICBRtl29x8q4YgH0y31yDQZOMhD6G/9Dj6BtIatusZckcfHRr1k8RqrqXRXtftc4Ni+nMfbnQnlOpr010vdgGfggYEueatTz3HUsvdPYv3DgH4zlm1/TWPN6uA=; 5:BKPkH7XP9SKi5DoUxhIetMAirXGy/Ob8X/8YdxThhFpVcb5HySSXjLEQvG9caiYfqqb3vwi8f9c4tOq/sG3P4InUcWtv0IC2tXOG/GNg9avE9R6H00slTfLyGvNDKMmgIU9ZjKiwXB3Tjof5uOZp350tQ1HXSvPkraEGrJLpUXk=; 7:K+dI/Zp1veUWc/XUzhfOZDSQ4L9FWm/RnMd2vs2aOC4gCoCzMTEzxHeLD/O4HNAnAz8AqviwMC3qZ2w12Brf3nmhdwZsUd/m2YaG/PbA9owjX3t7L1kcpyIQDYElzJO+WKQW6OsLaatjDKsH7H0V0bKT5IZhPeCrBBqghVLZIauqXdzv7VIQsFyLCFtIzDcJgTW/7D0b+bErWKD/e+BLe0NsEyIWeVqlAm47UeXlbrMac7esleFWDmGh44Ry1BTE x-ms-office365-filtering-correlation-id: f50aee4f-dec0-422a-f03e-08d630332011 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: vZIKBnj3jHuVfSrrQGuDouEIBDb2cbNQFXtM++hFBplnq4Xxt3uPGILNBZTMHVyaDEum9O2iDZV0jEDQPq+KsHCBHVLhkeXAhk9soX544igawhmKrl2bwWk0GOULF7IiWKL9I6xz/xoBLCMZfdvajh6Z1u4+zpkY6BL/0U2+Hq1+RgR3GO6BZwayjYAcv1ShuUH3nTnVxvuHJs/QWShzNsaB/+VR/2UjWslkkte2CbW45odNd/KaspQiNcHa1Br6RxfCZB3rAtNbWnVSZ1J4aQdatb7INc6OkNfxCKTwwcbnul8RdKcLwJHExvOnc0oDbakiVHEmLXloOG9bJIGpXNImZuxHEqD21cBZ+KNFMmk= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f50aee4f-dec0-422a-f03e-08d630332011 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:06.4920 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 02/22] net/atlantic: add logging structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Implement logging macroses for debug purposes. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 14 ++++++++++++++ drivers/net/atlantic/atl_logs.h | 31 +++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_types.h | 25 +++++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100644 drivers/net/atlantic/atl_logs.h create mode 100644 drivers/net/atlantic/atl_types.h diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index a9d7a5a49398..5b05ca180bc7 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -23,6 +23,9 @@ static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); static void atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); +int atl_logtype_init; +int atl_logtype_driver; + /* * The set of PCI devices this driver supports */ @@ -168,3 +171,14 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); + +RTE_INIT(atl_init_log) +{ + atl_logtype_init = rte_log_register("pmd.net.atlantic.init"); + if (atl_logtype_init >= 0) + rte_log_set_level(atl_logtype_init, RTE_LOG_NOTICE); + atl_logtype_driver = rte_log_register("pmd.net.atlantic.driver"); + if (atl_logtype_driver >= 0) + rte_log_set_level(atl_logtype_driver, RTE_LOG_NOTICE); +} + diff --git a/drivers/net/atlantic/atl_logs.h b/drivers/net/atlantic/atl_logs.h new file mode 100644 index 000000000000..e3dba334fe92 --- /dev/null +++ b/drivers/net/atlantic/atl_logs.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ +#ifndef ATL_LOGS_H +#define ATL_LOGS_H + +#include + +extern int atl_logtype_init; + +#define PMD_INIT_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, atl_logtype_init, \ + "%s(): " fmt "\n", __func__, ##args) + +#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>") + +#define PMD_RX_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, "%s(): " fmt "\n", __func__, ## args) + +#define PMD_TX_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, "%s(): " fmt "\n", __func__, ## args) + +extern int atl_logtype_driver; +#define PMD_DRV_LOG_RAW(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, atl_logtype_driver, "%s(): " fmt, \ + __func__, ## args) + +#define PMD_DRV_LOG(level, fmt, args...) \ + PMD_DRV_LOG_RAW(level, fmt "\n", ## args) + +#endif diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h new file mode 100644 index 000000000000..d8c2560807d3 --- /dev/null +++ b/drivers/net/atlantic/atl_types.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ +#ifndef ATL_TYPES_H +#define ATL_TYPES_H + +#include +#include +#include +#include +#include + + +typedef uint8_t u8; +typedef int8_t s8; +typedef uint16_t u16; +typedef int16_t s16; +typedef uint32_t u32; +typedef int32_t s32; +typedef uint64_t u64; + +#define min(a, b) RTE_MIN(a, b) +#define max(a, b) RTE_MAX(a, b) + +#endif From patchwork Fri Oct 12 11:09:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46698 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7B4491B552; Fri, 12 Oct 2018 13:09:13 +0200 (CEST) Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720062.outbound.protection.outlook.com [40.107.72.62]) by dpdk.org (Postfix) with ESMTP id B45431B557 for ; Fri, 12 Oct 2018 13:09:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=M67Ae2jQX59iRHihVErnTHBmM6cCjuFcgpBbDMOGnlQ=; b=Lo3vkmKY16PKlinSqpBUOGUZMuyQIOn0glIbKjn7mzitRlyCCmcdVmhTHxDy6e4Fp9swVHWDvMrN4D08/Wzg2+v7B36y/ZTex/Y0Pp+90X3Z09h5Y66Sqa42Tanda0CqusY1ah3zs/BY7J5KQviXf/2O2goiZysOI9ijrF/+u3A= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:08 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:08 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 03/22] net/atlantic: add hardware registers access routines Thread-Index: AQHUYhv/lMFW7oxTK0O/fgVgfrlbTA== Date: Fri, 12 Oct 2018 11:09:08 +0000 Message-ID: <5b263410a8c36c1cbf751142e930a73ab3064621.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:hEdiqME76eHc3fGs6+biy8iKKgcW5+PL7G09wuLbLtF1zd2Y4LLp0mXGMearHYWqmSK7BDWndhDFTUbq8sEUZZzqS4l0y8S5DALpH3xtE/jBIV6ZlnmFrPtD7c9mOxCa1BLCtshZHXNTYUJx21+7UJh3RYb16gs55/Iq2FuR4rwUkry2BCaehIXz0n3Rr8epxnV3EOTxvJKyD6QVPgienDhR+V6jfF9ug56/mkMkOlAiW1Mz6fgvRjerGaIesitgnvdXqFlcutkpqUg1B/OmYQCILM2AQDdt4otQzQL6IgCQtGIvnTEidnNtjPL8jdOAUQowq2QefpHk+nrXhij8ADVm3YNTFqm4ruy+SUBQ3+A15nACvcqClooO1z6IZv3Yb3Fo0sC8SxBxGOcsjQHq6o+wU93EUdDo+u3U8N+jU07P/RiT8rq8K+HvJDHLJBq4UaKwEmT9mTf75/h3xeixiDa/vsAAMYSy88d/3m7laDM=; 5:LtPjDchUh72EIJiAZVw3WeMpSTcGuwM693++wuUxkCMcOp3/fpAKpqzG03z146ZXiaAcBMtcZwP4fC6tS+nQodzn5C2c4Wl0l+BHcoEPP18i7u4mISa7pSKjN4eob1RLaOlB2Stg9O3FTrieGwuytkDEwpeRZWy6UYACVmp9YGY=; 7:g1DgTsgztSWlAMXFoBvlt9bXALteIhCA2d5GvFN6ZG/8dYAzXVPoxy6Ub+vktOyzAEe7DWFtdZoPaP2RRgsuQ5pflBEyMiBZwlZTgzs7kbfobmyagO5Pep5BQW3PhYUhGuuK4CFlfjoHCMq+m4ny9XT21cKGyckCKt9AMwTQk3mbvxviFvd3sNInaXoMYQUeUfvHY7g13fsdYPxy5GYjkhL5PivpX33UVbWn5kHdFrkXMuqbI6DHOQUFpjkJl7sh x-ms-office365-filtering-correlation-id: 58263b69-cdc7-49bf-630f-08d630332169 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(575784001)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 3IWF1FtEsQElrwY0voXujkUHMg3y6EPQXMDaEV0jRmtHm85Sq78vx6nPWFDodhQh+s7zXr5rxkOQ9UHZa7woIjbE2RW/Y7RMcOmoTyP6eJPdFIUgyL8HFijdCLrvO7DlpoaphGrOJRjy6PmkvQRbBbTrh6NFp3f/rVvcEjZWGOfJGbl/cqDVtf6x6PHY8/LJVlTDYtVPoQ3F3U/JB4KAX63NP1iJt4NdADmuxVrhAEeOchSzhukyLKaCkYNeYul+2y96OzyCeR+R0mjYf8tIcbS9wP56iRHcdTHqzx9RoxaMVdaBUVW/nhvQs/Voe7+e+EoA9UKgurTQ5iVf/YnVZfAfGWI7lX0t6poztoB+q1U= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58263b69-cdc7-49bf-630f-08d630332169 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:08.7168 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 03/22] net/atlantic: add hardware registers access routines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add implementation for hardware registers access routines. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 1 + drivers/net/atlantic/atl_hw_regs.c | 52 +++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_hw_regs.h | 53 ++++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_types.h | 4 +++ drivers/net/atlantic/meson.build | 1 + 5 files changed, 111 insertions(+) create mode 100644 drivers/net/atlantic/atl_hw_regs.c create mode 100644 drivers/net/atlantic/atl_hw_regs.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index e42ce5b178ab..8613ced71732 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -23,5 +23,6 @@ LDLIBS += -lrte_bus_pci # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_hw_regs.c b/drivers/net/atlantic/atl_hw_regs.c new file mode 100644 index 000000000000..bd42c8341e2b --- /dev/null +++ b/drivers/net/atlantic/atl_hw_regs.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File aq_hw_utils.c: Definitions of helper functions used across + * hardware layer. + */ + +#include "atl_hw_regs.h" + +#include +#include + +void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, + u32 shift, u32 val) +{ + if (msk ^ ~0) { + u32 reg_old, reg_new; + + reg_old = aq_hw_read_reg(aq_hw, addr); + reg_new = (reg_old & (~msk)) | (val << shift); + + if (reg_old != reg_new) + aq_hw_write_reg(aq_hw, addr, reg_new); + } else { + aq_hw_write_reg(aq_hw, addr, val); + } +} + +u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift) +{ + return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift); +} + +u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg) +{ + return rte_le_to_cpu_32(rte_read32((u8 *)hw->mmio + reg)); +} + +void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value) +{ + rte_write32((rte_cpu_to_le_32(value)), (u8 *)hw->mmio + reg); +} + +int aq_hw_err_from_flags(struct aq_hw_s *hw) +{ + int err = 0; + + if (aq_hw_read_reg(hw, 0x10U) == ~0U) + return -ENXIO; + + return err; +} diff --git a/drivers/net/atlantic/atl_hw_regs.h b/drivers/net/atlantic/atl_hw_regs.h new file mode 100644 index 000000000000..a2d6ca804e5e --- /dev/null +++ b/drivers/net/atlantic/atl_hw_regs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File aq_hw_utils.h: Declaration of helper functions used across hardware + * layer. + */ + +#ifndef AQ_HW_UTILS_H +#define AQ_HW_UTILS_H + +#include +#include +#include +#include +#include +#include "atl_common.h" +#include "atl_types.h" + + +#ifndef HIDWORD +#define LODWORD(_qw) ((u32)(_qw)) +#define HIDWORD(_qw) ((u32)(((_qw) >> 32) & 0xffffffff)) +#endif + +#define AQ_HW_SLEEP(_US_) rte_delay_ms(_US_) + +#define mdelay rte_delay_ms +#define udelay rte_delay_us +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#define BIT(x) (1UL << (x)) + +#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \ +do { \ + unsigned int AQ_HW_WAIT_FOR_i; \ + for (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\ + --AQ_HW_WAIT_FOR_i) {\ + udelay(_US_); \ + } \ + if (!AQ_HW_WAIT_FOR_i) {\ + err = -ETIMEDOUT; \ + } \ +} while (0) + +#define ATL_WRITE_FLUSH(aq_hw) { (void)aq_hw_read_reg(aq_hw, 0x10); } + +void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, + u32 shift, u32 val); +u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift); +u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg); +void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value); +int aq_hw_err_from_flags(struct aq_hw_s *hw); + +#endif /* AQ_HW_UTILS_H */ diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index d8c2560807d3..725b0c4dc670 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -22,4 +22,8 @@ typedef uint64_t u64; #define min(a, b) RTE_MIN(a, b) #define max(a, b) RTE_MAX(a, b) +struct aq_hw_s { + void *mmio; +}; + #endif diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index c5a2546ef657..cd6a0f637a7d 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -3,4 +3,5 @@ sources = files( 'atl_ethdev.c', + 'atl_hw_regs.c', ) From patchwork Fri Oct 12 11:09:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46699 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 60AE41B563; Fri, 12 Oct 2018 13:09:18 +0200 (CEST) Received: from NAM04-BN3-obe.outbound.protection.outlook.com (mail-eopbgr680088.outbound.protection.outlook.com [40.107.68.88]) by dpdk.org (Postfix) with ESMTP id 966AD1B564 for ; Fri, 12 Oct 2018 13:09:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5fcy9thjnjHU1eb7+YLHBT42YaNygMXWX4nvVCecFa8=; b=FmtjLvdRiOdQh/MVJRaQ66lcMqY8jJ6UiT3445BvAS+ZxFymVcEv7ADVxnHyP9Gjq09VA/TR5+q+B5znXCBT74K73ZZpSsHPCK95eoQMTq/pW4Vuvo0NoJ7lmc21AB3R1jH0ZuKWD5YenoCDEb4ndh5kHKYKjF9a5s2ti2TOiX8= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:12 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:12 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 04/22] net/atlantic: add hardware access layer Thread-Index: AQHUYhwA61ovW8dPDkWYeNhNCNqdgQ== Date: Fri, 12 Oct 2018 11:09:11 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:sLIlJc/Jj2ALktzSdtwI2lISxXC56Kw2Qae8BzL3YQU7xN/ZCl0NZmZRq6gx1yZSQEukwLhNlaHOb6x+l+L0Qip5AztexkygRJd9+7n5etPPNqUFAiAK0Rhm0w4nEQs1/urLtvfKDsZMfNNe0iISopQjQNEfovi0PSCANCYr/+W7mETZrSeDLCTo5JkvgULweiDFg6EmoR1+n4bRZ+k+z56ErIzvLUjBZ6cgZHBII7nNLGOUZCzhQTeeKtqEVptNXE8edfEuFFdNq+oUZpTKcNgtRQQyqez+zghxn5TkqCE2gCCwDyLL0JYmeIJ2Erk6+P2uFpc+SOW1DOy1YEytPcabVuK/bnE6wEmUnVY0q2if0jFQc7I8FrQLQDL755o63e3ablpMZho3kebL/ZAyw+u16juMiVIw5sUVCbGn7ndzZRp2ZCAEndWnrrh3rOX0Q76SxfrBbVMPv+u21d/Zqhvo1j4Yyh6Mflk+pFQa05c=; 5:kajHg0YSLNXuXQyqqc+gL56qaM3IKx+36gKT16HcV1XtbpWYAU2qfWurGg1iUyEhibe8+1mw7ktYAq/mmJNHg3UjwrfbvQMoWUnuImCtR40Hucn0TH17M3YmJbEtur5g4yvBQldH5T6cNLKIhNYh7wH87CqNt72/cqOZsvl4zJU=; 7:YNHMgfmOZ88HfkoE+yZRzlbK0jETIk+E+BVCqXU/VHBHZHJ/A652eRJMvJQsurGL4xkKBDNsLvHvMpujnXiudCg+i6xfcf6IQqiIYHmhrmfH8opeSpHLV4u6M9vtPdDK9mYmc1v/qBcbWRkaPeMLxbOZmKrzVEHfN6wfGimgo6JO03prT4ReUipbrUAgMvinEwo0hYs87k1glGs1vn26JAlTs3QSpFSFTU+XBCrAQh0VRVuH6BqTbBR+YUJbfaEk x-ms-office365-filtering-correlation-id: 40a513e0-21cf-4a89-f293-08d6303322bb x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(114624004)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(4744004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(16200700003)(53946003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(575784001)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: Lt4fN+KnMeBkJ5gZfjqfNF0n1OF9AQksymsq66FRKDefq0qA65rsemuK6Ozt1opRajvpuMNMH9sk27yGY5pN6J+wUDLfoSyq3hCMErTjMulxglDb0B7kjOAtvQ6LyF4BDUU1IRICZg0C0Le6iLjObWGkCm9/c4JZDmOhpTRp+eXDORf3NOPhNsIE9owktzPtrJqCyAKO209JhxMXkrp/0DVkic/RRY8IlkGwYvEVU0tG8jJRVvLfAvOibXueU8cc1NAPEtsIM4e7d+l0CIvd+cpmhaUFIuEJGKKirgG07+8j6EXsYeK8E0rkyNg1R3DAiGYQu2i71aIZ52JsXFMbMh6Vmk3Ce3TpZDbCgApt/24= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40a513e0-21cf-4a89-f293-08d6303322bb X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:12.0695 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 04/22] net/atlantic: add hardware access layer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch introduces hw_atl layer which is maintained in sync with linux kernel driver. It will generally be in sync with linux upstream. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 3 + drivers/net/atlantic/hw_atl/hw_atl_llh.c | 1490 +++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_llh.h | 714 ++++++ drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h | 2407 +++++++++++++++++++++ drivers/net/atlantic/meson.build | 1 + 5 files changed, 4615 insertions(+) create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh.c create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh.h create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index 8613ced71732..cae317badc0c 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -19,10 +19,13 @@ LDLIBS += -lrte_eal LDLIBS += -lrte_ethdev -lrte_net LDLIBS += -lrte_bus_pci +VPATH += $(SRCDIR)/hw_atl + # # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/atlantic/hw_atl/hw_atl_llh.c new file mode 100644 index 000000000000..2dc5be2ff167 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_llh.c @@ -0,0 +1,1490 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_llh.c: Definitions of bitfield and register access functions for + * Atlantic registers. + */ + +#include "hw_atl_llh.h" + +#include "../atl_hw_regs.h" +#include "hw_atl_llh_internal.h" + +/* global */ +void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, + u32 semaphore) +{ + aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem); +} + +u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore)); +} + +void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR, + HW_ATL_GLB_REG_RES_DIS_MSK, + HW_ATL_GLB_REG_RES_DIS_SHIFT, + glb_reg_res_dis); +} + +void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, + HW_ATL_GLB_SOFT_RES_MSK, + HW_ATL_GLB_SOFT_RES_SHIFT, soft_res); +} + +u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, + HW_ATL_GLB_SOFT_RES_MSK, + HW_ATL_GLB_SOFT_RES_SHIFT); +} + +u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR); +} + +/* stats */ +u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR); +} + +u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW); +} + +u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW); +} + +u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW); +} + +u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW); +} + +u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW); +} + +u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW); +} + +u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW); +} + +u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW); +} + +/* interrupt */ +void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, + u32 irq_auto_masklsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw); +} + +void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, + u32 rx) +{ +/* register address for bitfield imr_rx{r}_en */ + static const u32 itr_imr_rxren_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_rx{r}_en */ + static const u32 itr_imr_rxren_msk[32] = { + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U + }; + +/* lower bit position of bitfield imr_rx{r}_en */ + static const u32 itr_imr_rxren_shift[32] = { + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx], + itr_imr_rxren_msk[rx], + itr_imr_rxren_shift[rx], + irq_map_en_rx); +} + +void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, + u32 tx) +{ +/* register address for bitfield imr_tx{t}_en */ + static const u32 itr_imr_txten_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_tx{t}_en */ + static const u32 itr_imr_txten_msk[32] = { + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U + }; + +/* lower bit position of bitfield imr_tx{t}_en */ + static const u32 itr_imr_txten_shift[32] = { + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx], + itr_imr_txten_msk[tx], + itr_imr_txten_shift[tx], + irq_map_en_tx); +} + +void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx) +{ +/* register address for bitfield imr_rx{r}[4:0] */ + static const u32 itr_imr_rxr_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_rx{r}[4:0] */ + static const u32 itr_imr_rxr_msk[32] = { + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU + }; + +/* lower bit position of bitfield imr_rx{r}[4:0] */ + static const u32 itr_imr_rxr_shift[32] = { + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx], + itr_imr_rxr_msk[rx], + itr_imr_rxr_shift[rx], + irq_map_rx); +} + +void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx) +{ +/* register address for bitfield imr_tx{t}[4:0] */ + static const u32 itr_imr_txt_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_tx{t}[4:0] */ + static const u32 itr_imr_txt_msk[32] = { + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U + }; + +/* lower bit position of bitfield imr_tx{t}[4:0] */ + static const u32 itr_imr_txt_shift[32] = { + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx], + itr_imr_txt_msk[tx], + itr_imr_txt_shift[tx], + irq_map_tx); +} + +void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_msk_clearlsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw); +} + +void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw); +} + +void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR, + HW_ATL_ITR_REG_RES_DSBL_MSK, + HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis); +} + +void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_status_clearlsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw); +} + +u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR); +} + +u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, + HW_ATL_ITR_RES_SHIFT); +} + +void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, + HW_ATL_ITR_RES_SHIFT, res_irq); +} + +/* rdm */ +void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca), + HW_ATL_RDM_DCADCPUID_MSK, + HW_ATL_RDM_DCADCPUID_SHIFT, cpuid); +} + +void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK, + HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en); +} + +void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR, + HW_ATL_RDM_DCA_MODE_MSK, + HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode); +} + +void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_data_buff_size, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor), + HW_ATL_RDM_DESCDDATA_SIZE_MSK, + HW_ATL_RDM_DESCDDATA_SIZE_SHIFT, + rx_desc_data_buff_size); +} + +void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca), + HW_ATL_RDM_DCADDESC_EN_MSK, + HW_ATL_RDM_DCADDESC_EN_SHIFT, + rx_desc_dca_en); +} + +void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor), + HW_ATL_RDM_DESCDEN_MSK, + HW_ATL_RDM_DESCDEN_SHIFT, + rx_desc_en); +} + +void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_buff_size, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor), + HW_ATL_RDM_DESCDHDR_SIZE_MSK, + HW_ATL_RDM_DESCDHDR_SIZE_SHIFT, + rx_desc_head_buff_size); +} + +void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_splitting, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor), + HW_ATL_RDM_DESCDHDR_SPLIT_MSK, + HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT, + rx_desc_head_splitting); +} + +u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor), + HW_ATL_RDM_DESCDHD_MSK, + HW_ATL_RDM_DESCDHD_SHIFT); +} + +void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor), + HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT, + rx_desc_len); +} + +void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor), + HW_ATL_RDM_DESCDRESET_MSK, + HW_ATL_RDM_DESCDRESET_SHIFT, + rx_desc_res); +} + +void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 rx_desc_wr_wb_irq_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR, + HW_ATL_RDM_INT_DESC_WRB_EN_MSK, + HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT, + rx_desc_wr_wb_irq_en); +} + +void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca), + HW_ATL_RDM_DCADHDR_EN_MSK, + HW_ATL_RDM_DCADHDR_EN_SHIFT, + rx_head_dca_en); +} + +void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca), + HW_ATL_RDM_DCADPAY_EN_MSK, + HW_ATL_RDM_DCADPAY_EN_SHIFT, + rx_pld_dca_en); +} + +void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 rdm_intr_moder_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR, + HW_ATL_RDM_INT_RIM_EN_MSK, + HW_ATL_RDM_INT_RIM_EN_SHIFT, + rdm_intr_moder_en); +} + +/* reg */ +void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, + u32 regidx) +{ + aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map); +} + +u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR); +} + +void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl) +{ + aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl); +} + +void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle) +{ + aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr); +} + +void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrlsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), + rx_dma_desc_base_addrlsw); +} + +void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrmsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), + rx_dma_desc_base_addrmsw); +} + +u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor)); +} + +void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_tail_ptr, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor), + rx_dma_desc_tail_ptr); +} + +void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, + u32 rx_flr_mcst_flr_msk) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR, + rx_flr_mcst_flr_msk); +} + +void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, + u32 filter) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter), + rx_flr_mcst_flr); +} + +void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, + u32 rx_flr_rss_control1) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR, + rx_flr_rss_control1); +} + +void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, + u32 rx_filter_control2) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2); +} + +void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 rx_intr_moderation_ctl, + u32 queue) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue), + rx_intr_moderation_ctl); +} + +void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, + u32 tx_dma_debug_ctl) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl); +} + +void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrlsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), + tx_dma_desc_base_addrlsw); +} + +void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrmsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), + tx_dma_desc_base_addrmsw); +} + +void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_tail_ptr, + u32 descriptor) +{ + rte_wmb(); + + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor), + tx_dma_desc_tail_ptr); +} + +void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue), + tx_intr_moderation_ctl); +} + +/* RPB: rx packet buffer */ +void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR, + HW_ATL_RPB_DMA_SYS_LBK_MSK, + HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk); +} + +void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, + u32 rx_traf_class_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR, + HW_ATL_RPB_RPF_RX_TC_MODE_MSK, + HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT, + rx_traf_class_mode); +} + +u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR, + HW_ATL_RPB_RPF_RX_TC_MODE_MSK, + HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT); +} + +void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR, + HW_ATL_RPB_RX_BUF_EN_MSK, + HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en); +} + +void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_hi_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer), + HW_ATL_RPB_RXBHI_THRESH_MSK, + HW_ATL_RPB_RXBHI_THRESH_SHIFT, + rx_buff_hi_threshold_per_tc); +} + +void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_lo_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer), + HW_ATL_RPB_RXBLO_THRESH_MSK, + HW_ATL_RPB_RXBLO_THRESH_SHIFT, + rx_buff_lo_threshold_per_tc); +} + +void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, + u32 rx_flow_ctl_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR, + HW_ATL_RPB_RX_FC_MODE_MSK, + HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode); +} + +void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_pkt_buff_size_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer), + HW_ATL_RPB_RXBBUF_SIZE_MSK, + HW_ATL_RPB_RXBBUF_SIZE_SHIFT, + rx_pkt_buff_size_per_tc); +} + +void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_xoff_en_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer), + HW_ATL_RPB_RXBXOFF_EN_MSK, + HW_ATL_RPB_RXBXOFF_EN_SHIFT, + rx_xoff_en_per_tc); +} + +/* rpf */ + +void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_count_threshold) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR, + HW_ATL_RPFL2BC_THRESH_MSK, + HW_ATL_RPFL2BC_THRESH_SHIFT, + l2broadcast_count_threshold); +} + +void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK, + HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en); +} + +void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_flr_act) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR, + HW_ATL_RPFL2BC_ACT_MSK, + HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act); +} + +void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, + u32 l2multicast_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter), + HW_ATL_RPFL2MC_ENF_MSK, + HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en); +} + +void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, + u32 l2promiscuous_mode_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR, + HW_ATL_RPFL2PROMIS_MODE_MSK, + HW_ATL_RPFL2PROMIS_MODE_SHIFT, + l2promiscuous_mode_en); +} + +void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2unicast_flr_act, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter), + HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT, + l2unicast_flr_act); +} + +void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter), + HW_ATL_RPFL2UC_ENF_MSK, + HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en); +} + +void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addresslsw, + u32 filter) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter), + l2unicast_dest_addresslsw); +} + +void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addressmsw, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter), + HW_ATL_RPFL2UC_DAFMSW_MSK, + HW_ATL_RPFL2UC_DAFMSW_SHIFT, + l2unicast_dest_addressmsw); +} + +void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, + u32 l2_accept_all_mc_packets) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR, + HW_ATL_RPFL2MC_ACCEPT_ALL_MSK, + HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT, + l2_accept_all_mc_packets); +} + +void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, + u32 user_priority_tc_map, u32 tc) +{ +/* register address for bitfield rx_tc_up{t}[2:0] */ + static const u32 rpf_rpb_rx_tc_upt_adr[8] = { + 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U, + 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U + }; + +/* bitmask for bitfield rx_tc_up{t}[2:0] */ + static const u32 rpf_rpb_rx_tc_upt_msk[8] = { + 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U, + 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U + }; + +/* lower bit position of bitfield rx_tc_up{t}[2:0] */ + static const u32 rpf_rpb_rx_tc_upt_shft[8] = { + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U + }; + + aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc], + rpf_rpb_rx_tc_upt_msk[tc], + rpf_rpb_rx_tc_upt_shft[tc], + user_priority_tc_map); +} + +void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR, + HW_ATL_RPF_RSS_KEY_ADDR_MSK, + HW_ATL_RPF_RSS_KEY_ADDR_SHIFT, + rss_key_addr); +} + +void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR, + rss_key_wr_data); +} + +u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, + HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, + HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT); +} + +void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, + HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, + HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT, + rss_key_wr_en); +} + +void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_addr) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR, + HW_ATL_RPF_RSS_REDIR_ADDR_MSK, + HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT, + rss_redir_tbl_addr); +} + +void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_wr_data) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR, + HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK, + HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT, + rss_redir_tbl_wr_data); +} + +u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, + HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, + HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT); +} + +void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, + HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, + HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en); +} + +void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, + u32 tpo_to_rpf_sys_lbk) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR, + HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK, + HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT, + tpo_to_rpf_sys_lbk); +} + +void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR, + HW_ATL_RPF_VL_INNER_TPID_MSK, + HW_ATL_RPF_VL_INNER_TPID_SHIFT, + vlan_inner_etht); +} + +void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR, + HW_ATL_RPF_VL_OUTER_TPID_MSK, + HW_ATL_RPF_VL_OUTER_TPID_SHIFT, + vlan_outer_etht); +} + +void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, + u32 vlan_prom_mode_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR, + HW_ATL_RPF_VL_PROMIS_MODE_MSK, + HW_ATL_RPF_VL_PROMIS_MODE_SHIFT, + vlan_prom_mode_en); +} + +void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, + u32 vlan_acc_untagged_packets) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR, + HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK, + HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT, + vlan_acc_untagged_packets); +} + +void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, + u32 vlan_untagged_act) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR, + HW_ATL_RPF_VL_UNTAGGED_ACT_MSK, + HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT, + vlan_untagged_act); +} + +void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter), + HW_ATL_RPF_VL_EN_F_MSK, + HW_ATL_RPF_VL_EN_F_SHIFT, + vlan_flr_en); +} + +void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter), + HW_ATL_RPF_VL_ACT_F_MSK, + HW_ATL_RPF_VL_ACT_F_SHIFT, + vlan_flr_act); +} + +void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter), + HW_ATL_RPF_VL_ID_F_MSK, + HW_ATL_RPF_VL_ID_F_SHIFT, + vlan_id_flr); +} + +void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter), + HW_ATL_RPF_ET_ENF_MSK, + HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en); +} + +void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority_en, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter), + HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT, + etht_user_priority_en); +} + +void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, + u32 etht_rx_queue_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter), + HW_ATL_RPF_ET_RXQFEN_MSK, + HW_ATL_RPF_ET_RXQFEN_SHIFT, + etht_rx_queue_en); +} + +void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter), + HW_ATL_RPF_ET_UPF_MSK, + HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority); +} + +void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter), + HW_ATL_RPF_ET_RXQF_MSK, + HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue); +} + +void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter), + HW_ATL_RPF_ET_MNG_RXQF_MSK, + HW_ATL_RPF_ET_MNG_RXQF_SHIFT, + etht_mgt_queue); +} + +void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter), + HW_ATL_RPF_ET_ACTF_MSK, + HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act); +} + +void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter), + HW_ATL_RPF_ET_VALF_MSK, + HW_ATL_RPF_ET_VALF_SHIFT, etht_flr); +} + +/* RPO: rx packet offload */ +void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR, + HW_ATL_RPO_IPV4CHK_EN_MSK, + HW_ATL_RPO_IPV4CHK_EN_SHIFT, + ipv4header_crc_offload_en); +} + +void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, + u32 rx_desc_vlan_stripping, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor), + HW_ATL_RPO_DESCDVL_STRIP_MSK, + HW_ATL_RPO_DESCDVL_STRIP_SHIFT, + rx_desc_vlan_stripping); +} + +void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR, + HW_ATL_RPOL4CHK_EN_MSK, + HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en); +} + +void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en); +} + +void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, + u32 lro_patch_optimization_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR, + HW_ATL_RPO_LRO_PTOPT_EN_MSK, + HW_ATL_RPO_LRO_PTOPT_EN_SHIFT, + lro_patch_optimization_en); +} + +void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, + u32 lro_qsessions_lim) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR, + HW_ATL_RPO_LRO_QSES_LMT_MSK, + HW_ATL_RPO_LRO_QSES_LMT_SHIFT, + lro_qsessions_lim); +} + +void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, + u32 lro_total_desc_lim) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR, + HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK, + HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT, + lro_total_desc_lim); +} + +void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lro_min_pld_of_first_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR, + HW_ATL_RPO_LRO_PKT_MIN_MSK, + HW_ATL_RPO_LRO_PKT_MIN_SHIFT, + lro_min_pld_of_first_pkt); +} + +void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim); +} + +void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, + u32 lro_max_number_of_descriptors, + u32 lro) +{ +/* Register address for bitfield lro{L}_des_max[1:0] */ + static const u32 rpo_lro_ldes_max_adr[32] = { + 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, + 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, + 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, + 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, + 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, + 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, + 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU, + 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU + }; + +/* Bitmask for bitfield lro{L}_des_max[1:0] */ + static const u32 rpo_lro_ldes_max_msk[32] = { + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U + }; + +/* Lower bit position of bitfield lro{L}_des_max[1:0] */ + static const u32 rpo_lro_ldes_max_shift[32] = { + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U + }; + + aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro], + rpo_lro_ldes_max_msk[lro], + rpo_lro_ldes_max_shift[lro], + lro_max_number_of_descriptors); +} + +void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, + u32 lro_time_base_divider) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR, + HW_ATL_RPO_LRO_TB_DIV_MSK, + HW_ATL_RPO_LRO_TB_DIV_SHIFT, + lro_time_base_divider); +} + +void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, + u32 lro_inactive_interval) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR, + HW_ATL_RPO_LRO_INA_IVAL_MSK, + HW_ATL_RPO_LRO_INA_IVAL_SHIFT, + lro_inactive_interval); +} + +void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, + u32 lro_max_coal_interval) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR, + HW_ATL_RPO_LRO_MAX_IVAL_MSK, + HW_ATL_RPO_LRO_MAX_IVAL_SHIFT, + lro_max_coal_interval); +} + +/* rx */ +void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR, + HW_ATL_RX_REG_RES_DSBL_MSK, + HW_ATL_RX_REG_RES_DSBL_SHIFT, + rx_reg_res_dis); +} + +/* tdm */ +void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca), + HW_ATL_TDM_DCADCPUID_MSK, + HW_ATL_TDM_DCADCPUID_SHIFT, cpuid); +} + +void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, + u32 large_send_offload_en) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en); +} + +void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK, + HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en); +} + +void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR, + HW_ATL_TDM_DCA_MODE_MSK, + HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode); +} + +void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca), + HW_ATL_TDM_DCADDESC_EN_MSK, + HW_ATL_TDM_DCADDESC_EN_SHIFT, + tx_desc_dca_en); +} + +void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor), + HW_ATL_TDM_DESCDEN_MSK, + HW_ATL_TDM_DESCDEN_SHIFT, + tx_desc_en); +} + +u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor), + HW_ATL_TDM_DESCDHD_MSK, + HW_ATL_TDM_DESCDHD_SHIFT); +} + +void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor), + HW_ATL_TDM_DESCDLEN_MSK, + HW_ATL_TDM_DESCDLEN_SHIFT, + tx_desc_len); +} + +void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_irq_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR, + HW_ATL_TDM_INT_DESC_WRB_EN_MSK, + HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT, + tx_desc_wr_wb_irq_en); +} + +void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_threshold, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor), + HW_ATL_TDM_DESCDWRB_THRESH_MSK, + HW_ATL_TDM_DESCDWRB_THRESH_SHIFT, + tx_desc_wr_wb_threshold); +} + +void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 tdm_irq_moderation_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR, + HW_ATL_TDM_INT_MOD_EN_MSK, + HW_ATL_TDM_INT_MOD_EN_SHIFT, + tdm_irq_moderation_en); +} + +/* thm */ +void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_first_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR, + HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK, + HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT, + lso_tcp_flag_of_first_pkt); +} + +void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_last_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR, + HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK, + HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT, + lso_tcp_flag_of_last_pkt); +} + +void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_middle_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR, + HW_ATL_THM_LSO_TCP_FLAG_MID_MSK, + HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT, + lso_tcp_flag_of_middle_pkt); +} + +/* TPB: tx packet buffer */ +void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR, + HW_ATL_TPB_TX_BUF_EN_MSK, + HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en); +} + +u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, + HW_ATL_TPB_TX_TC_MODE_MSK, + HW_ATL_TPB_TX_TC_MODE_SHIFT); +} + +void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, + u32 tx_traf_class_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, + HW_ATL_TPB_TX_TC_MODE_MSK, + HW_ATL_TPB_TX_TC_MODE_SHIFT, + tx_traf_class_mode); +} + +void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_hi_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer), + HW_ATL_TPB_TXBHI_THRESH_MSK, + HW_ATL_TPB_TXBHI_THRESH_SHIFT, + tx_buff_hi_threshold_per_tc); +} + +void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_lo_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer), + HW_ATL_TPB_TXBLO_THRESH_MSK, + HW_ATL_TPB_TXBLO_THRESH_SHIFT, + tx_buff_lo_threshold_per_tc); +} + +void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_dma_sys_lbk_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR, + HW_ATL_TPB_DMA_SYS_LBK_MSK, + HW_ATL_TPB_DMA_SYS_LBK_SHIFT, + tx_dma_sys_lbk_en); +} + +void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_buff_size_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer), + HW_ATL_TPB_TXBBUF_SIZE_MSK, + HW_ATL_TPB_TXBBUF_SIZE_SHIFT, + tx_pkt_buff_size_per_tc); +} + +void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, + u32 tx_path_scp_ins_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR, + HW_ATL_TPB_TX_SCP_INS_EN_MSK, + HW_ATL_TPB_TX_SCP_INS_EN_SHIFT, + tx_path_scp_ins_en); +} + +/* TPO: tx packet offload */ +void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR, + HW_ATL_TPO_IPV4CHK_EN_MSK, + HW_ATL_TPO_IPV4CHK_EN_SHIFT, + ipv4header_crc_offload_en); +} + +void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR, + HW_ATL_TPOL4CHK_EN_MSK, + HW_ATL_TPOL4CHK_EN_SHIFT, + tcp_udp_crc_offload_en); +} + +void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_sys_lbk_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR, + HW_ATL_TPO_PKT_SYS_LBK_MSK, + HW_ATL_TPO_PKT_SYS_LBK_SHIFT, + tx_pkt_sys_lbk_en); +} + +/* TPS: tx packet scheduler */ +void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_data_arb_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR, + HW_ATL_TPS_DATA_TC_ARB_MODE_MSK, + HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT, + tx_pkt_shed_data_arb_mode); +} + +void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, + u32 curr_time_res) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR, + HW_ATL_TPS_DESC_RATE_TA_RST_MSK, + HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT, + curr_time_res); +} + +void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_rate_lim) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR, + HW_ATL_TPS_DESC_RATE_LIM_MSK, + HW_ATL_TPS_DESC_RATE_LIM_SHIFT, + tx_pkt_shed_desc_rate_lim); +} + +void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR, + HW_ATL_TPS_DESC_TC_ARB_MODE_MSK, + HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT, + arb_mode); +} + +void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc), + HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK, + HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT, + max_credit); +} + +void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_tc_weight, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc), + HW_ATL_TPS_DESC_TCTWEIGHT_MSK, + HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT, + tx_pkt_shed_desc_tc_weight); +} + +void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR, + HW_ATL_TPS_DESC_VM_ARB_MODE_MSK, + HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT, + arb_mode); +} + +void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc), + HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK, + HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT, + max_credit); +} + +void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_tc_data_weight, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc), + HW_ATL_TPS_DATA_TCTWEIGHT_MSK, + HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT, + tx_pkt_shed_tc_data_weight); +} + +/* tx */ +void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR, + HW_ATL_TX_REG_RES_DSBL_MSK, + HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis); +} + +/* msm */ +u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR, + HW_ATL_MSM_REG_ACCESS_BUSY_MSK, + HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT); +} + +void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, + u32 reg_addr_for_indirect_addr) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR, + HW_ATL_MSM_REG_ADDR_MSK, + HW_ATL_MSM_REG_ADDR_SHIFT, + reg_addr_for_indirect_addr); +} + +void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR, + HW_ATL_MSM_REG_RD_STROBE_MSK, + HW_ATL_MSM_REG_RD_STROBE_SHIFT, + reg_rd_strobe); +} + +u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR); +} + +void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data) +{ + aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data); +} + +void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR, + HW_ATL_MSM_REG_WR_STROBE_MSK, + HW_ATL_MSM_REG_WR_STROBE_SHIFT, + reg_wr_strobe); +} + +/* pci */ +void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR, + HW_ATL_PCI_REG_RES_DSBL_MSK, + HW_ATL_PCI_REG_RES_DSBL_SHIFT, + pci_reg_res_dis); +} + +void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, + u32 glb_cpu_scratch_scp, + u32 scratch_scp) +{ + aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp), + glb_cpu_scratch_scp); +} + +void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR, + HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK, + HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT, up_force_intr); +} diff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/atlantic/hw_atl/hw_atl_llh.h new file mode 100644 index 000000000000..e30083cea501 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_llh.h @@ -0,0 +1,714 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_llh.h: Declarations of bitfield and register access functions for + * Atlantic registers. + */ + +#ifndef HW_ATL_LLH_H +#define HW_ATL_LLH_H + +#include "../atl_types.h" + +struct aq_hw_s; + +/* global */ + +/* set global microprocessor semaphore */ +void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, + u32 semaphore); + +/* get global microprocessor semaphore */ +u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore); + +/* set global register reset disable */ +void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis); + +/* set soft reset */ +void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res); + +/* get soft reset */ +u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw); + +/* stats */ + +u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw); + +/* get rx dma good octet counter lsw */ +u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get rx dma good packet counter lsw */ +u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good octet counter lsw */ +u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good packet counter lsw */ +u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get rx dma good octet counter msw */ +u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); + +/* get rx dma good packet counter msw */ +u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good octet counter msw */ +u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good packet counter msw */ +u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); + +/* get msm rx errors counter register */ +u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx unicast frames counter register */ +u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx multicast frames counter register */ +u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx broadcast frames counter register */ +u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx broadcast octets counter register 1 */ +u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); + +/* get msm rx unicast octets counter register 0 */ +u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); + +/* get rx dma statistics counter 7 */ +u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw); + +/* get msm tx errors counter register */ +u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx unicast frames counter register */ +u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx multicast frames counter register */ +u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx broadcast frames counter register */ +u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx multicast octets counter register 1 */ +u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw); + +/* get msm tx broadcast octets counter register 1 */ +u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); + +/* get msm tx unicast octets counter register 0 */ +u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); + +/* get global mif identification */ +u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw); + +/* interrupt */ + +/* set interrupt auto mask lsw */ +void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, + u32 irq_auto_masklsw); + +/* set interrupt mapping enable rx */ +void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, + u32 rx); + +/* set interrupt mapping enable tx */ +void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, + u32 tx); + +/* set interrupt mapping rx */ +void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx); + +/* set interrupt mapping tx */ +void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx); + +/* set interrupt mask clear lsw */ +void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_msk_clearlsw); + +/* set interrupt mask set lsw */ +void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw); + +/* set interrupt register reset disable */ +void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis); + +/* set interrupt status clear lsw */ +void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_status_clearlsw); + +/* get interrupt status lsw */ +u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw); + +/* get reset interrupt */ +u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw); + +/* set reset interrupt */ +void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq); + +/* rdm */ + +/* set cpu id */ +void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); + +/* set rx dca enable */ +void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en); + +/* set rx dca mode */ +void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode); + +/* set rx descriptor data buffer size */ +void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_data_buff_size, + u32 descriptor); + +/* set rx descriptor dca enable */ +void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, + u32 dca); + +/* set rx descriptor enable */ +void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, + u32 descriptor); + +/* set rx descriptor header splitting */ +void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_splitting, + u32 descriptor); + +/* get rx descriptor head pointer */ +u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); + +/* set rx descriptor length */ +void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, + u32 descriptor); + +/* set rx descriptor write-back interrupt enable */ +void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 rx_desc_wr_wb_irq_en); + +/* set rx header dca enable */ +void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, + u32 dca); + +/* set rx payload dca enable */ +void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, + u32 dca); + +/* set rx descriptor header buffer size */ +void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_buff_size, + u32 descriptor); + +/* set rx descriptor reset */ +void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, + u32 descriptor); + +/* Set RDM Interrupt Moderation Enable */ +void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 rdm_intr_moder_en); + +/* reg */ + +/* set general interrupt mapping register */ +void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, + u32 regidx); + +/* get general interrupt status register */ +u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw); + +/* set interrupt global control register */ +void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl); + +/* set interrupt throttle register */ +void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle); + +/* set rx dma descriptor base address lsw */ +void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrlsw, + u32 descriptor); + +/* set rx dma descriptor base address msw */ +void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrmsw, + u32 descriptor); + +/* get rx dma descriptor status register */ +u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor); + +/* set rx dma descriptor tail pointer register */ +void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_tail_ptr, + u32 descriptor); + +/* set rx filter multicast filter mask register */ +void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, + u32 rx_flr_mcst_flr_msk); + +/* set rx filter multicast filter register */ +void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, + u32 filter); + +/* set rx filter rss control register 1 */ +void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, + u32 rx_flr_rss_control1); + +/* Set RX Filter Control Register 2 */ +void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2); + +/* Set RX Interrupt Moderation Control Register */ +void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 rx_intr_moderation_ctl, + u32 queue); + +/* set tx dma debug control */ +void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, + u32 tx_dma_debug_ctl); + +/* set tx dma descriptor base address lsw */ +void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrlsw, + u32 descriptor); + +/* set tx dma descriptor base address msw */ +void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrmsw, + u32 descriptor); + +/* set tx dma descriptor tail pointer register */ +void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_tail_ptr, + u32 descriptor); + +/* Set TX Interrupt Moderation Control Register */ +void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue); + +/* set global microprocessor scratch pad */ +void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, + u32 glb_cpu_scratch_scp, + u32 scratch_scp); + +/* rpb */ + +/* set dma system loopback */ +void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk); + +/* set rx traffic class mode */ +void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, + u32 rx_traf_class_mode); + +/* get rx traffic class mode */ +u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw); + +/* set rx buffer enable */ +void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en); + +/* set rx buffer high threshold (per tc) */ +void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_hi_threshold_per_tc, + u32 buffer); + +/* set rx buffer low threshold (per tc) */ +void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_lo_threshold_per_tc, + u32 buffer); + +/* set rx flow control mode */ +void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, + u32 rx_flow_ctl_mode); + +/* set rx packet buffer size (per tc) */ +void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_pkt_buff_size_per_tc, + u32 buffer); + +/* set rx xoff enable (per tc) */ +void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_xoff_en_per_tc, + u32 buffer); + +/* rpf */ + +/* set l2 broadcast count threshold */ +void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_count_threshold); + +/* set l2 broadcast enable */ +void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en); + +/* set l2 broadcast filter action */ +void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_flr_act); + +/* set l2 multicast filter enable */ +void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, + u32 l2multicast_flr_en, + u32 filter); + +/* set l2 promiscuous mode enable */ +void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, + u32 l2promiscuous_mode_en); + +/* set l2 unicast filter action */ +void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2unicast_flr_act, + u32 filter); + +/* set l2 unicast filter enable */ +void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, + u32 filter); + +/* set l2 unicast destination address lsw */ +void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addresslsw, + u32 filter); + +/* set l2 unicast destination address msw */ +void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addressmsw, + u32 filter); + +/* Set L2 Accept all Multicast packets */ +void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, + u32 l2_accept_all_mc_packets); + +/* set user-priority tc mapping */ +void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, + u32 user_priority_tc_map, u32 tc); + +/* set rss key address */ +void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr); + +/* set rss key write data */ +void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data); + +/* get rss key write enable */ +u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw); + +/* set rss key write enable */ +void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en); + +/* set rss redirection table address */ +void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_addr); + +/* set rss redirection table write data */ +void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_wr_data); + +/* get rss redirection write enable */ +u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw); + +/* set rss redirection write enable */ +void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en); + +/* set tpo to rpf system loopback */ +void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, + u32 tpo_to_rpf_sys_lbk); + +/* set vlan inner ethertype */ +void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht); + +/* set vlan outer ethertype */ +void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht); + +/* set vlan promiscuous mode enable */ +void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, + u32 vlan_prom_mode_en); + +/* Set VLAN untagged action */ +void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, + u32 vlan_untagged_act); + +/* Set VLAN accept untagged packets */ +void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, + u32 vlan_acc_untagged_packets); + +/* Set VLAN filter enable */ +void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, + u32 filter); + +/* Set VLAN Filter Action */ +void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act, + u32 filter); + +/* Set VLAN ID Filter */ +void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, + u32 filter); + +/* set ethertype filter enable */ +void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, + u32 filter); + +/* set ethertype user-priority enable */ +void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority_en, + u32 filter); + +/* set ethertype rx queue enable */ +void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, + u32 etht_rx_queue_en, + u32 filter); + +/* set ethertype rx queue */ +void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, + u32 filter); + +/* set ethertype user-priority */ +void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority, + u32 filter); + +/* set ethertype management queue */ +void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, + u32 filter); + +/* set ethertype filter action */ +void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, + u32 filter); + +/* set ethertype filter */ +void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter); + +/* rpo */ + +/* set ipv4 header checksum offload enable */ +void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en); + +/* set rx descriptor vlan stripping */ +void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, + u32 rx_desc_vlan_stripping, + u32 descriptor); + +/* set tcp/udp checksum offload enable */ +void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en); + +/* Set LRO Patch Optimization Enable. */ +void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, + u32 lro_patch_optimization_en); + +/* Set Large Receive Offload Enable */ +void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en); + +/* Set LRO Q Sessions Limit */ +void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, + u32 lro_qsessions_lim); + +/* Set LRO Total Descriptor Limit */ +void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, + u32 lro_total_desc_lim); + +/* Set LRO Min Payload of First Packet */ +void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lro_min_pld_of_first_pkt); + +/* Set LRO Packet Limit */ +void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim); + +/* Set LRO Max Number of Descriptors */ +void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, + u32 lro_max_desc_num, u32 lro); + +/* Set LRO Time Base Divider */ +void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, + u32 lro_time_base_divider); + +/*Set LRO Inactive Interval */ +void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, + u32 lro_inactive_interval); + +/*Set LRO Max Coalescing Interval */ +void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, + u32 lro_max_coal_interval); + +/* rx */ + +/* set rx register reset disable */ +void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis); + +/* tdm */ + +/* set cpu id */ +void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); + +/* set large send offload enable */ +void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, + u32 large_send_offload_en); + +/* set tx descriptor enable */ +void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, + u32 descriptor); + +/* set tx dca enable */ +void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en); + +/* set tx dca mode */ +void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode); + +/* set tx descriptor dca enable */ +void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, + u32 dca); + +/* get tx descriptor head pointer */ +u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); + +/* set tx descriptor length */ +void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, + u32 descriptor); + +/* set tx descriptor write-back interrupt enable */ +void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_irq_en); + +/* set tx descriptor write-back threshold */ +void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_threshold, + u32 descriptor); + +/* Set TDM Interrupt Moderation Enable */ +void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 tdm_irq_moderation_en); +/* thm */ + +/* set lso tcp flag of first packet */ +void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_first_pkt); + +/* set lso tcp flag of last packet */ +void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_last_pkt); + +/* set lso tcp flag of middle packet */ +void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_middle_pkt); + +/* tpb */ + +/* set TX Traffic Class Mode */ +void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, + u32 tx_traf_class_mode); + +/* get TX Traffic Class Mode */ +u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw); + +/* set tx buffer enable */ +void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en); + +/* set tx buffer high threshold (per tc) */ +void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_hi_threshold_per_tc, + u32 buffer); + +/* set tx buffer low threshold (per tc) */ +void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_lo_threshold_per_tc, + u32 buffer); + +/* set tx dma system loopback enable */ +void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_dma_sys_lbk_en); + +/* set tx packet buffer size (per tc) */ +void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_buff_size_per_tc, + u32 buffer); + +/* set tx path pad insert enable */ +void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, + u32 tx_path_scp_ins_en); + +/* tpo */ + +/* set ipv4 header checksum offload enable */ +void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en); + +/* set tcp/udp checksum offload enable */ +void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en); + +/* set tx pkt system loopback enable */ +void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_sys_lbk_en); + +/* tps */ + +/* set tx packet scheduler data arbitration mode */ +void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_data_arb_mode); + +/* set tx packet scheduler descriptor rate current time reset */ +void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, + u32 curr_time_res); + +/* set tx packet scheduler descriptor rate limit */ +void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_rate_lim); + +/* set tx packet scheduler descriptor tc arbitration mode */ +void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode); + +/* set tx packet scheduler descriptor tc max credit */ +void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc); + +/* set tx packet scheduler descriptor tc weight */ +void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_tc_weight, + u32 tc); + +/* set tx packet scheduler descriptor vm arbitration mode */ +void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode); + +/* set tx packet scheduler tc data max credit */ +void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc); + +/* set tx packet scheduler tc data weight */ +void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_tc_data_weight, + u32 tc); + +/* tx */ + +/* set tx register reset disable */ +void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis); + +/* msm */ + +/* get register access status */ +u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw); + +/* set register address for indirect address */ +void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, + u32 reg_addr_for_indirect_addr); + +/* set register read strobe */ +void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe); + +/* get register read data */ +u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw); + +/* set register write data */ +void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data); + +/* set register write strobe */ +void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe); + +/* pci */ + +/* set pci register reset disable */ +void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis); + +/* set uP Force Interrupt */ +void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr); + + +#endif /* HW_ATL_LLH_H */ diff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h new file mode 100644 index 000000000000..27b9b9cb3be1 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h @@ -0,0 +1,2407 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_llh_internal.h: Preprocessor definitions + * for Atlantic registers. + */ + +#ifndef HW_ATL_LLH_INTERNAL_H +#define HW_ATL_LLH_INTERNAL_H + +/* global microprocessor semaphore definitions + * base address: 0x000003a0 + * parameter: semaphore {s} | stride size 0x4 | range [0, 15] + */ +#define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) +/* register address for bitfield rx dma good octet counter lsw [1f:0] */ +#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 +/* register address for bitfield rx dma good packet counter lsw [1f:0] */ +#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 +/* register address for bitfield tx dma good octet counter lsw [1f:0] */ +#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 +/* register address for bitfield tx dma good packet counter lsw [1f:0] */ +#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 + +/* register address for bitfield rx dma good octet counter msw [3f:20] */ +#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c +/* register address for bitfield rx dma good packet counter msw [3f:20] */ +#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 +/* register address for bitfield tx dma good octet counter msw [3f:20] */ +#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c +/* register address for bitfield tx dma good packet counter msw [3f:20] */ +#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 + +/* preprocessor definitions for msm rx errors counter register */ +#define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u + +/* preprocessor definitions for msm rx unicast frames counter register */ +#define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u + +/* preprocessor definitions for msm rx multicast frames counter register */ +#define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u + +/* preprocessor definitions for msm rx broadcast frames counter register */ +#define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u + +/* preprocessor definitions for msm rx broadcast octets counter register 1 */ +#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u + +/* preprocessor definitions for msm rx broadcast octets counter register 2 */ +#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u + +/* preprocessor definitions for msm rx unicast octets counter register 0 */ +#define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u + +/* preprocessor definitions for msm tx unicast frames counter register */ +#define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u + +/* preprocessor definitions for msm tx multicast frames counter register */ +#define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u + +/* preprocessor definitions for global mif identification */ +#define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu + +/* register address for bitfield iamr_lsw[1f:0] */ +#define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 +/* register address for bitfield rx dma drop packet counter [1f:0] */ +#define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 + +/* register address for bitfield imcr_lsw[1f:0] */ +#define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 +/* register address for bitfield imsr_lsw[1f:0] */ +#define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 +/* register address for bitfield itr_reg_res_dsbl */ +#define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 +/* bitmask for bitfield itr_reg_res_dsbl */ +#define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 +/* lower bit position of bitfield itr_reg_res_dsbl */ +#define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 +/* register address for bitfield iscr_lsw[1f:0] */ +#define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 +/* register address for bitfield isr_lsw[1f:0] */ +#define HW_ATL_ITR_ISRLSW_ADR 0x00002000 +/* register address for bitfield itr_reset */ +#define HW_ATL_ITR_RES_ADR 0x00002300 +/* bitmask for bitfield itr_reset */ +#define HW_ATL_ITR_RES_MSK 0x80000000 +/* lower bit position of bitfield itr_reset */ +#define HW_ATL_ITR_RES_SHIFT 31 +/* register address for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff +/* lower bit position of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_RDM_DCADCPUID_SHIFT 0 +/* register address for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 + +/* rx dca_en bitfield definitions + * preprocessor definitions for the bitfield "dca_en". + * port="pif_rdm_dca_en_i" + */ + +/* register address for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 +/* bitmask for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_SHIFT 31 +/* width of bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_WIDTH 1 +/* default value of bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 + +/* rx dca_mode[3:0] bitfield definitions + * preprocessor definitions for the bitfield "dca_mode[3:0]". + * port="pif_rdm_dca_mode_i[3:0]" + */ + +/* register address for bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 +/* bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f +/* inverted bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 +/* lower bit position of bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_SHIFT 0 +/* width of bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_WIDTH 4 +/* default value of bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 + +/* rx desc{d}_data_size[4:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc0_data_size_i[4:0]" + */ + +/* register address for bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ + (0x00005b18 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f +/* inverted bitmask for bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 +/* lower bit position of bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 +/* width of bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 +/* default value of bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 + +/* rx dca{d}_desc_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_desc_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_rdm_dca_desc_en_i[0]" + */ + +/* register address for bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 +/* width of bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 +/* default value of bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 + +/* rx desc{d}_en bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_en". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc_en_i[0]" + */ + +/* register address for bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_MSK 0x80000000 +/* inverted bitmask for bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff +/* lower bit position of bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_SHIFT 31 +/* width of bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_WIDTH 1 +/* default value of bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 + +/* rx desc{d}_hdr_size[4:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc0_hdr_size_i[4:0]" + */ + +/* register address for bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ + (0x00005b18 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 +/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff +/* lower bit position of bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 +/* width of bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 +/* default value of bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 + +/* rx desc{d}_hdr_split bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hdr_split". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc_hdr_split_i[0]" + */ + +/* register address for bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ + (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 +/* inverted bitmask for bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff +/* lower bit position of bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 +/* width of bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 +/* default value of bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 + +/* rx desc{d}_hd[c:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="rdm_pif_desc0_hd_o[12:0]" + */ + +/* register address for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_MSK 0x00001fff +/* inverted bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 +/* lower bit position of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_SHIFT 0 +/* width of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_WIDTH 13 + +/* rx desc{d}_len[9:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_len[9:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc0_len_i[9:0]" + */ + +/* register address for bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 +/* inverted bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 +/* lower bit position of bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_SHIFT 3 +/* width of bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_WIDTH 10 +/* default value of bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 + +/* rx desc{d}_reset bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_reset". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_q_pf_res_i[0]" + */ + +/* register address for bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 +/* inverted bitmask for bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff +/* lower bit position of bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_SHIFT 25 +/* width of bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_WIDTH 1 +/* default value of bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 + +/* rx int_desc_wrb_en bitfield definitions + * preprocessor definitions for the bitfield "int_desc_wrb_en". + * port="pif_rdm_int_desc_wrb_en_i" + */ + +/* register address for bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 +/* bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 +/* inverted bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb +/* lower bit position of bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 +/* width of bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 +/* default value of bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 + +/* rx dca{d}_hdr_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_hdr_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_rdm_dca_hdr_en_i[0]" + */ + +/* register address for bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 +/* inverted bitmask for bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff +/* lower bit position of bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 +/* width of bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 +/* default value of bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 + +/* rx dca{d}_pay_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_pay_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_rdm_dca_pay_en_i[0]" + */ + +/* register address for bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 +/* inverted bitmask for bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff +/* lower bit position of bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 +/* width of bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 +/* default value of bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 + +/* RX rdm_int_rim_en Bitfield Definitions + * Preprocessor definitions for the bitfield "rdm_int_rim_en". + * PORT="pif_rdm_int_rim_en_i" + */ + +/* Register address for bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 +/* Bitmask for bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 +/* Inverted bitmask for bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 +/* Lower bit position of bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 +/* Width of bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 +/* Default value of bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 + +/* general interrupt mapping register definitions + * preprocessor definitions for general interrupt mapping register + * base address: 0x00002180 + * parameter: regidx {f} | stride size 0x4 | range [0, 3] + */ +#define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) + +/* general interrupt status register definitions + * preprocessor definitions for general interrupt status register + * address: 0x000021A0 + */ + +#define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U + +/* interrupt global control register definitions + * preprocessor definitions for interrupt global control register + * address: 0x00002300 + */ +#define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u + +/* interrupt throttle register definitions + * preprocessor definitions for interrupt throttle register + * base address: 0x00002800 + * parameter: throttle {t} | stride size 0x4 | range [0, 31] + */ +#define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) + +/* rx dma descriptor base address lsw definitions + * preprocessor definitions for rx dma descriptor base address lsw + * base address: 0x00005b00 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ +(0x00005b00u + (descriptor) * 0x20) + +/* rx dma descriptor base address msw definitions + * preprocessor definitions for rx dma descriptor base address msw + * base address: 0x00005b04 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ +(0x00005b04u + (descriptor) * 0x20) + +/* rx dma descriptor status register definitions + * preprocessor definitions for rx dma descriptor status register + * base address: 0x00005b14 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ + (0x00005b14u + (descriptor) * 0x20) + +/* rx dma descriptor tail pointer register definitions + * preprocessor definitions for rx dma descriptor tail pointer register + * base address: 0x00005b10 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ + (0x00005b10u + (descriptor) * 0x20) + +/* rx interrupt moderation control register definitions + * Preprocessor definitions for RX Interrupt Moderation Control Register + * Base Address: 0x00005A40 + * Parameter: RIM {R} | stride size 0x4 | range [0, 31] + */ +#define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) + +/* rx filter multicast filter mask register definitions + * preprocessor definitions for rx filter multicast filter mask register + * address: 0x00005270 + */ +#define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u + +/* rx filter multicast filter register definitions + * preprocessor definitions for rx filter multicast filter register + * base address: 0x00005250 + * parameter: filter {f} | stride size 0x4 | range [0, 7] + */ +#define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) + +/* RX Filter RSS Control Register 1 Definitions + * Preprocessor definitions for RX Filter RSS Control Register 1 + * Address: 0x000054C0 + */ +#define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u + +/* RX Filter Control Register 2 Definitions + * Preprocessor definitions for RX Filter Control Register 2 + * Address: 0x00005104 + */ +#define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u + +/* tx tx dma debug control [1f:0] bitfield definitions + * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". + * port="pif_tdm_debug_cntl_i[31:0]" + */ + +/* register address for bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 +/* bitmask for bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff +/* inverted bitmask for bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 +/* lower bit position of bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 +/* width of bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 +/* default value of bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 + +/* tx dma descriptor base address lsw definitions + * preprocessor definitions for tx dma descriptor base address lsw + * base address: 0x00007c00 + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + */ +#define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ + (0x00007c00u + (descriptor) * 0x40) + +/* tx dma descriptor tail pointer register definitions + * preprocessor definitions for tx dma descriptor tail pointer register + * base address: 0x00007c10 + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + */ +#define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ + (0x00007c10u + (descriptor) * 0x40) + +/* rx dma_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "dma_sys_loopback". + * port="pif_rpb_dma_sys_lbk_i" + */ + +/* register address for bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 +/* bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 +/* inverted bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf +/* lower bit position of bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 +/* width of bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 +/* default value of bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 + +/* rx rx_tc_mode bitfield definitions + * preprocessor definitions for the bitfield "rx_tc_mode". + * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" + */ + +/* register address for bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 +/* bitmask for bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 +/* inverted bitmask for bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff +/* lower bit position of bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 +/* width of bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 +/* default value of bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 + +/* rx rx_buf_en bitfield definitions + * preprocessor definitions for the bitfield "rx_buf_en". + * port="pif_rpb_rx_buf_en_i" + */ + +/* register address for bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 +/* bitmask for bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 +/* inverted bitmask for bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe +/* lower bit position of bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 +/* width of bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 +/* default value of bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 + +/* rx rx{b}_hi_thresh[d:0] bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx0_hi_thresh_i[13:0]" + */ + +/* register address for bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 +/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff +/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 +/* width of bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 +/* default value of bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 + +/* rx rx{b}_lo_thresh[d:0] bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx0_lo_thresh_i[13:0]" + */ + +/* register address for bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff +/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 +/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 +/* width of bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 +/* default value of bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 + +/* rx rx_fc_mode[1:0] bitfield definitions + * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". + * port="pif_rpb_rx_fc_mode_i[1:0]" + */ + +/* register address for bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 +/* bitmask for bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 +/* inverted bitmask for bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf +/* lower bit position of bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 +/* width of bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 +/* default value of bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 + +/* rx rx{b}_buf_size[8:0] bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx0_buf_size_i[8:0]" + */ + +/* register address for bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff +/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 +/* lower bit position of bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 +/* width of bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 +/* default value of bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 + +/* rx rx{b}_xoff_en bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_xoff_en". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx_xoff_en_i[0]" + */ + +/* register address for bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 +/* inverted bitmask for bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff +/* lower bit position of bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 +/* width of bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 +/* default value of bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 + +/* rx l2_bc_thresh[f:0] bitfield definitions + * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". + * port="pif_rpf_l2_bc_thresh_i[15:0]" + */ + +/* register address for bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 +/* bitmask for bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 +/* inverted bitmask for bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff +/* lower bit position of bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_SHIFT 16 +/* width of bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_WIDTH 16 +/* default value of bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 + +/* rx l2_bc_en bitfield definitions + * preprocessor definitions for the bitfield "l2_bc_en". + * port="pif_rpf_l2_bc_en_i" + */ + +/* register address for bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_ADR 0x00005100 +/* bitmask for bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_MSK 0x00000001 +/* inverted bitmask for bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe +/* lower bit position of bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_SHIFT 0 +/* width of bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_WIDTH 1 +/* default value of bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 + +/* rx l2_bc_act[2:0] bitfield definitions + * preprocessor definitions for the bitfield "l2_bc_act[2:0]". + * port="pif_rpf_l2_bc_act_i[2:0]" + */ + +/* register address for bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 +/* bitmask for bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 +/* inverted bitmask for bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff +/* lower bit position of bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_SHIFT 12 +/* width of bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_WIDTH 3 +/* default value of bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 + +/* rx l2_mc_en{f} bitfield definitions + * preprocessor definitions for the bitfield "l2_mc_en{f}". + * parameter: filter {f} | stride size 0x4 | range [0, 7] + * port="pif_rpf_l2_mc_en_i[0]" + */ + +/* register address for bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) +/* bitmask for bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 +/* inverted bitmask for bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff +/* lower bit position of bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_SHIFT 31 +/* width of bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_WIDTH 1 +/* default value of bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 + +/* rx l2_promis_mode bitfield definitions + * preprocessor definitions for the bitfield "l2_promis_mode". + * port="pif_rpf_l2_promis_mode_i" + */ + +/* register address for bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 +/* bitmask for bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 +/* inverted bitmask for bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 +/* lower bit position of bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 +/* width of bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 +/* default value of bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 + +/* rx l2_uc_act{f}[2:0] bitfield definitions + * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". + * parameter: filter {f} | stride size 0x8 | range [0, 37] + * port="pif_rpf_l2_uc_act0_i[2:0]" + */ + +/* register address for bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) +/* bitmask for bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 +/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff +/* lower bit position of bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_SHIFT 16 +/* width of bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_WIDTH 3 +/* default value of bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 + +/* rx l2_uc_en{f} bitfield definitions + * preprocessor definitions for the bitfield "l2_uc_en{f}". + * parameter: filter {f} | stride size 0x8 | range [0, 37] + * port="pif_rpf_l2_uc_en_i[0]" + */ + +/* register address for bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) +/* bitmask for bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 +/* inverted bitmask for bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff +/* lower bit position of bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_SHIFT 31 +/* width of bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_WIDTH 1 +/* default value of bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 + +/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ +#define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) +/* register address for bitfield l2_uc_da{f}_msw[f:0] */ +#define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) +/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ +#define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff +/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ +#define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 + +/* rx l2_mc_accept_all bitfield definitions + * Preprocessor definitions for the bitfield "l2_mc_accept_all". + * PORT="pif_rpf_l2_mc_all_accept_i" + */ + +/* Register address for bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 +/* Bitmask for bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 +/* Inverted bitmask for bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF +/* Lower bit position of bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 +/* Width of bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 +/* Default value of bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 + +/* width of bitfield rx_tc_up{t}[2:0] */ +#define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 +/* default value of bitfield rx_tc_up{t}[2:0] */ +#define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 + +/* rx rss_key_addr[4:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_key_addr[4:0]". + * port="pif_rpf_rss_key_addr_i[4:0]" + */ + +/* register address for bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 +/* bitmask for bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f +/* inverted bitmask for bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 +/* lower bit position of bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 +/* width of bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 +/* default value of bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 + +/* rx rss_key_wr_data[1f:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". + * port="pif_rpf_rss_key_wr_data_i[31:0]" + */ + +/* register address for bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 +/* bitmask for bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff +/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 +/* lower bit position of bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 +/* width of bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 +/* default value of bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 + +/* rx rss_key_wr_en_i bitfield definitions + * preprocessor definitions for the bitfield "rss_key_wr_en_i". + * port="pif_rpf_rss_key_wr_en_i" + */ + +/* register address for bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 +/* bitmask for bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 +/* inverted bitmask for bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf +/* lower bit position of bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 +/* width of bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 +/* default value of bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 + +/* rx rss_redir_addr[3:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". + * port="pif_rpf_rss_redir_addr_i[3:0]" + */ + +/* register address for bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 +/* bitmask for bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f +/* inverted bitmask for bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 +/* lower bit position of bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 +/* width of bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 +/* default value of bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 + +/* rx rss_redir_wr_data[f:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". + * port="pif_rpf_rss_redir_wr_data_i[15:0]" + */ + +/* register address for bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 +/* bitmask for bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff +/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 +/* lower bit position of bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 +/* width of bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 +/* default value of bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 + +/* rx rss_redir_wr_en_i bitfield definitions + * preprocessor definitions for the bitfield "rss_redir_wr_en_i". + * port="pif_rpf_rss_redir_wr_en_i" + */ + +/* register address for bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 +/* bitmask for bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 +/* inverted bitmask for bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef +/* lower bit position of bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 +/* width of bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 +/* default value of bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 + +/* rx tpo_rpf_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". + * port="pif_rpf_tpo_pkt_sys_lbk_i" + */ + +/* register address for bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 +/* bitmask for bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 +/* inverted bitmask for bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff +/* lower bit position of bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 +/* width of bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 +/* default value of bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 + +/* rx vl_inner_tpid[f:0] bitfield definitions + * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". + * port="pif_rpf_vl_inner_tpid_i[15:0]" + */ + +/* register address for bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 +/* bitmask for bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff +/* inverted bitmask for bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 +/* lower bit position of bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 +/* width of bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 +/* default value of bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 + +/* rx vl_outer_tpid[f:0] bitfield definitions + * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". + * port="pif_rpf_vl_outer_tpid_i[15:0]" + */ + +/* register address for bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 +/* bitmask for bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 +/* inverted bitmask for bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff +/* lower bit position of bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 +/* width of bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 +/* default value of bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 + +/* rx vl_promis_mode bitfield definitions + * preprocessor definitions for the bitfield "vl_promis_mode". + * port="pif_rpf_vl_promis_mode_i" + */ + +/* register address for bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 +/* bitmask for bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 +/* inverted bitmask for bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd +/* lower bit position of bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 +/* width of bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 +/* default value of bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 + +/* RX vl_accept_untagged_mode Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". + * PORT="pif_rpf_vl_accept_untagged_i" + */ + +/* Register address for bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 +/* Bitmask for bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 +/* Inverted bitmask for bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB +/* Lower bit position of bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 +/* Width of bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 +/* Default value of bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 + +/* rX vl_untagged_act[2:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". + * PORT="pif_rpf_vl_untagged_act_i[2:0]" + */ + +/* Register address for bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 +/* Bitmask for bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 +/* Inverted bitmask for bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 +/* Lower bit position of bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 +/* Width of bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 +/* Default value of bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 + +/* RX vl_en{F} Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_en{F}". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_vl_en_i[0]" + */ + +/* Register address for bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) +/* Bitmask for bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 +/* Inverted bitmask for bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_SHIFT 31 +/* Width of bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_WIDTH 1 +/* Default value of bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 + +/* RX vl_act{F}[2:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_vl_act0_i[2:0]" + */ + +/* Register address for bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) +/* Bitmask for bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 +/* Inverted bitmask for bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF +/* Lower bit position of bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_SHIFT 16 +/* Width of bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_WIDTH 3 +/* Default value of bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 + +/* RX vl_id{F}[B:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_vl_id0_i[11:0]" + */ + +/* Register address for bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) +/* Bitmask for bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF +/* Inverted bitmask for bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 +/* Lower bit position of bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_SHIFT 0 +/* Width of bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_WIDTH 12 +/* Default value of bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 + +/* RX et_en{F} Bitfield Definitions + * Preprocessor definitions for the bitfield "et_en{F}". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_et_en_i[0]" + */ + +/* Register address for bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4) +/* Bitmask for bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000 +/* Inverted bitmask for bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_SHIFT 31 +/* Width of bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_WIDTH 1 +/* Default value of bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0 + +/* rx et_en{f} bitfield definitions + * preprocessor definitions for the bitfield "et_en{f}". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_en_i[0]" + */ + +/* register address for bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_MSK 0x80000000 +/* inverted bitmask for bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff +/* lower bit position of bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_SHIFT 31 +/* width of bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_WIDTH 1 +/* default value of bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 + +/* rx et_up{f}_en bitfield definitions + * preprocessor definitions for the bitfield "et_up{f}_en". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_up_en_i[0]" + */ + +/* register address for bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 +/* inverted bitmask for bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff +/* lower bit position of bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_SHIFT 30 +/* width of bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_WIDTH 1 +/* default value of bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 + +/* rx et_rxq{f}_en bitfield definitions + * preprocessor definitions for the bitfield "et_rxq{f}_en". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_rxq_en_i[0]" + */ + +/* register address for bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 +/* inverted bitmask for bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff +/* lower bit position of bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 +/* width of bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 +/* default value of bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 + +/* rx et_up{f}[2:0] bitfield definitions + * preprocessor definitions for the bitfield "et_up{f}[2:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_up0_i[2:0]" + */ + +/* register address for bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 +/* inverted bitmask for bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff +/* lower bit position of bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_SHIFT 26 +/* width of bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_WIDTH 3 +/* default value of bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 + +/* rx et_rxq{f}[4:0] bitfield definitions + * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_rxq0_i[4:0]" + */ + +/* register address for bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 +/* inverted bitmask for bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff +/* lower bit position of bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_SHIFT 20 +/* width of bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_WIDTH 5 +/* default value of bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 + +/* rx et_mng_rxq{f} bitfield definitions + * preprocessor definitions for the bitfield "et_mng_rxq{f}". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_mng_rxq_i[0]" + */ + +/* register address for bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 +/* inverted bitmask for bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff +/* lower bit position of bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 +/* width of bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 +/* default value of bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 + +/* rx et_act{f}[2:0] bitfield definitions + * preprocessor definitions for the bitfield "et_act{f}[2:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_act0_i[2:0]" + */ + +/* register address for bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 +/* inverted bitmask for bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff +/* lower bit position of bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_SHIFT 16 +/* width of bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_WIDTH 3 +/* default value of bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 + +/* rx et_val{f}[f:0] bitfield definitions + * preprocessor definitions for the bitfield "et_val{f}[f:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_val0_i[15:0]" + */ + +/* register address for bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff +/* inverted bitmask for bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 +/* lower bit position of bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_SHIFT 0 +/* width of bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_WIDTH 16 +/* default value of bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 + +/* rx ipv4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "ipv4_chk_en". + * port="pif_rpo_ipv4_chk_en_i" + */ + +/* register address for bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 +/* bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 +/* inverted bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd +/* lower bit position of bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 +/* width of bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 +/* default value of bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 + +/* rx desc{d}_vl_strip bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_vl_strip". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rpo_desc_vl_strip_i[0]" + */ + +/* register address for bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ + (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 +/* inverted bitmask for bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff +/* lower bit position of bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 +/* width of bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 +/* default value of bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 + +/* rx l4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "l4_chk_en". + * port="pif_rpo_l4_chk_en_i" + */ + +/* register address for bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 +/* bitmask for bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 +/* inverted bitmask for bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe +/* lower bit position of bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_SHIFT 0 +/* width of bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_WIDTH 1 +/* default value of bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 + +/* rx reg_res_dsbl bitfield definitions + * preprocessor definitions for the bitfield "reg_res_dsbl". + * port="pif_rx_reg_res_dsbl_i" + */ + +/* register address for bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 +/* bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 +/* inverted bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff +/* lower bit position of bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 +/* width of bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 +/* default value of bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 + +/* tx dca{d}_cpuid[7:0] bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_tdm_dca0_cpuid_i[7:0]" + */ + +/* register address for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff +/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 +/* lower bit position of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_SHIFT 0 +/* width of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_WIDTH 8 +/* default value of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 + +/* tx lso_en[1f:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_en[1f:0]". + * port="pif_tdm_lso_en_i[31:0]" + */ + +/* register address for bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_ADR 0x00007810 +/* bitmask for bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_MSK 0xffffffff +/* inverted bitmask for bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 +/* lower bit position of bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_SHIFT 0 +/* width of bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_WIDTH 32 +/* default value of bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 + +/* tx dca_en bitfield definitions + * preprocessor definitions for the bitfield "dca_en". + * port="pif_tdm_dca_en_i" + */ + +/* register address for bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_ADR 0x00008480 +/* bitmask for bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_SHIFT 31 +/* width of bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_WIDTH 1 +/* default value of bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 + +/* tx dca_mode[3:0] bitfield definitions + * preprocessor definitions for the bitfield "dca_mode[3:0]". + * port="pif_tdm_dca_mode_i[3:0]" + */ + +/* register address for bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 +/* bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f +/* inverted bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 +/* lower bit position of bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_SHIFT 0 +/* width of bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_WIDTH 4 +/* default value of bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 + +/* tx dca{d}_desc_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_desc_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_tdm_dca_desc_en_i[0]" + */ + +/* register address for bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 +/* width of bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 +/* default value of bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 + +/* tx desc{d}_en bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_en". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="pif_tdm_desc_en_i[0]" + */ + +/* register address for bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_MSK 0x80000000 +/* inverted bitmask for bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff +/* lower bit position of bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_SHIFT 31 +/* width of bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_WIDTH 1 +/* default value of bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 + +/* tx desc{d}_hd[c:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="tdm_pif_desc0_hd_o[12:0]" + */ + +/* register address for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_MSK 0x00001fff +/* inverted bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 +/* lower bit position of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_SHIFT 0 +/* width of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_WIDTH 13 + +/* tx desc{d}_len[9:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_len[9:0]". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="pif_tdm_desc0_len_i[9:0]" + */ + +/* register address for bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 +/* inverted bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 +/* lower bit position of bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_SHIFT 3 +/* width of bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_WIDTH 10 +/* default value of bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 + +/* tx int_desc_wrb_en bitfield definitions + * preprocessor definitions for the bitfield "int_desc_wrb_en". + * port="pif_tdm_int_desc_wrb_en_i" + */ + +/* register address for bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 +/* bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 +/* inverted bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd +/* lower bit position of bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 +/* width of bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 +/* default value of bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 + +/* tx desc{d}_wrb_thresh[6:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="pif_tdm_desc0_wrb_thresh_i[6:0]" + */ + +/* register address for bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ + (0x00007c18 + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 +/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff +/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 +/* width of bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 +/* default value of bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 + +/* tx lso_tcp_flag_first[b:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". + * port="pif_thm_lso_tcp_flag_first_i[11:0]" + */ + +/* register address for bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 +/* bitmask for bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff +/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 +/* lower bit position of bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 +/* width of bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 +/* default value of bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 + +/* tx lso_tcp_flag_last[b:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". + * port="pif_thm_lso_tcp_flag_last_i[11:0]" + */ + +/* register address for bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 +/* bitmask for bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff +/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 +/* lower bit position of bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 +/* width of bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 +/* default value of bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 + +/* tx lso_tcp_flag_mid[b:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". + * port="pif_thm_lso_tcp_flag_mid_i[11:0]" + */ + +/* Register address for bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 +/* Bitmask for bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF +/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 +/* Lower bit position of bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 +/* Width of bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 +/* Default value of bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 + +/* RX lro_en[1F:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_en[1F:0]". + * PORT="pif_rpo_lro_en_i[31:0]" + */ + +/* Register address for bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_ADR 0x00005590 +/* Bitmask for bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF +/* Inverted bitmask for bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 +/* Lower bit position of bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_SHIFT 0 +/* Width of bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_WIDTH 32 +/* Default value of bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 + +/* RX lro_ptopt_en Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_ptopt_en". + * PORT="pif_rpo_lro_ptopt_en_i" + */ + +/* Register address for bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 +/* Bitmask for bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 +/* Inverted bitmask for bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF +/* Lower bit position of bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 +/* Width of bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 +/* Default value of bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 + +/* RX lro_q_ses_lmt Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_q_ses_lmt". + * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" + */ + +/* Register address for bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 +/* Bitmask for bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 +/* Inverted bitmask for bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF +/* Lower bit position of bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 +/* Width of bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 +/* Default value of bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 + +/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". + * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" + */ + +/* Register address for bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 +/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 +/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F +/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 +/* Width of bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 +/* Default value of bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 + +/* RX lro_pkt_min[4:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". + * PORT="pif_rpo_lro_pkt_min_i[4:0]" + */ + +/* Register address for bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 +/* Bitmask for bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F +/* Inverted bitmask for bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 +/* Lower bit position of bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 +/* Width of bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 +/* Default value of bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 + +/* Width of bitfield lro{L}_des_max[1:0] */ +#define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 +/* Default value of bitfield lro{L}_des_max[1:0] */ +#define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 + +/* RX lro_tb_div[11:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". + * PORT="pif_rpo_lro_tb_div_i[11:0]" + */ + +/* Register address for bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 +/* Bitmask for bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 +/* Inverted bitmask for bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF +/* Lower bit position of bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 +/* Width of bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 +/* Default value of bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 + +/* RX lro_ina_ival[9:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". + * PORT="pif_rpo_lro_ina_ival_i[9:0]" + */ + +/* Register address for bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 +/* Bitmask for bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 +/* Inverted bitmask for bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF +/* Lower bit position of bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 +/* Width of bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 +/* Default value of bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA + +/* RX lro_max_ival[9:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". + * PORT="pif_rpo_lro_max_ival_i[9:0]" + */ + +/* Register address for bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 +/* Bitmask for bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF +/* Inverted bitmask for bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 +/* Lower bit position of bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 +/* Width of bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 +/* Default value of bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 + +/* TX dca{D}_cpuid[7:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". + * Parameter: DCA {D} | stride size 0x4 | range [0, 31] + * PORT="pif_tdm_dca0_cpuid_i[7:0]" + */ + +/* Register address for bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) +/* Bitmask for bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF +/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 +/* Lower bit position of bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 +/* Width of bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 +/* Default value of bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 + +/* TX dca{D}_desc_en Bitfield Definitions + * Preprocessor definitions for the bitfield "dca{D}_desc_en". + * Parameter: DCA {D} | stride size 0x4 | range [0, 31] + * PORT="pif_tdm_dca_desc_en_i[0]" + */ + +/* Register address for bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) +/* Bitmask for bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 +/* Inverted bitmask for bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 +/* Width of bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 +/* Default value of bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 + +/* TX desc{D}_en Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_en". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="pif_tdm_desc_en_i[0]" + */ + +/* Register address for bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 +/* Inverted bitmask for bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_SHIFT 31 +/* Width of bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_WIDTH 1 +/* Default value of bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 + +/* TX desc{D}_hd[C:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="tdm_pif_desc0_hd_o[12:0]" + */ + +/* Register address for bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF +/* Inverted bitmask for bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 +/* Lower bit position of bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_SHIFT 0 +/* Width of bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_WIDTH 13 + +/* TX desc{D}_len[9:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="pif_tdm_desc0_len_i[9:0]" + */ + +/* Register address for bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 +/* Inverted bitmask for bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 +/* Lower bit position of bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_SHIFT 3 +/* Width of bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_WIDTH 10 +/* Default value of bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 + +/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" + */ + +/* Register address for bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ + (0x00007C18 + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 +/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF +/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 +/* Width of bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 +/* Default value of bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 + +/* TX tdm_int_mod_en Bitfield Definitions + * Preprocessor definitions for the bitfield "tdm_int_mod_en". + * PORT="pif_tdm_int_mod_en_i" + */ + +/* Register address for bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 +/* Bitmask for bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 +/* Inverted bitmask for bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF +/* Lower bit position of bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 +/* Width of bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 +/* Default value of bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 + +/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". + * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" + */ +/* register address for bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 +/* bitmask for bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 +/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff +/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 +/* width of bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 +/* default value of bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 + +/* tx tx_buf_en bitfield definitions + * preprocessor definitions for the bitfield "tx_buf_en". + * port="pif_tpb_tx_buf_en_i" + */ + +/* register address for bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 +/* bitmask for bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 +/* inverted bitmask for bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe +/* lower bit position of bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 +/* width of bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 +/* default value of bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 + +/* register address for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 +/* bitmask for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 +/* inverted bitmask for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF +/* lower bit position of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 +/* width of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 +/* default value of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 + +/* tx tx{b}_hi_thresh[c:0] bitfield definitions + * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_tpb_tx0_hi_thresh_i[12:0]" + */ + +/* register address for bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) +/* bitmask for bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 +/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff +/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 +/* width of bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 +/* default value of bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 + +/* tx tx{b}_lo_thresh[c:0] bitfield definitions + * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_tpb_tx0_lo_thresh_i[12:0]" + */ + +/* register address for bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) +/* bitmask for bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff +/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 +/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 +/* width of bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 +/* default value of bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 + +/* tx dma_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "dma_sys_loopback". + * port="pif_tpb_dma_sys_lbk_i" + */ + +/* register address for bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 +/* bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 +/* inverted bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf +/* lower bit position of bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 +/* width of bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 +/* default value of bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 + +/* tx tx{b}_buf_size[7:0] bitfield definitions + * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_tpb_tx0_buf_size_i[7:0]" + */ + +/* register address for bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) +/* bitmask for bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff +/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 +/* lower bit position of bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 +/* width of bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 +/* default value of bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 + +/* tx tx_scp_ins_en bitfield definitions + * preprocessor definitions for the bitfield "tx_scp_ins_en". + * port="pif_tpb_scp_ins_en_i" + */ + +/* register address for bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 +/* bitmask for bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 +/* inverted bitmask for bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb +/* lower bit position of bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 +/* width of bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 +/* default value of bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 + +/* tx ipv4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "ipv4_chk_en". + * port="pif_tpo_ipv4_chk_en_i" + */ + +/* register address for bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 +/* bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 +/* inverted bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd +/* lower bit position of bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 +/* width of bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 +/* default value of bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 + +/* tx l4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "l4_chk_en". + * port="pif_tpo_l4_chk_en_i" + */ + +/* register address for bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 +/* bitmask for bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 +/* inverted bitmask for bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe +/* lower bit position of bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_SHIFT 0 +/* width of bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_WIDTH 1 +/* default value of bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 + +/* tx pkt_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "pkt_sys_loopback". + * port="pif_tpo_pkt_sys_lbk_i" + */ + +/* register address for bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 +/* bitmask for bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 +/* inverted bitmask for bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f +/* lower bit position of bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 +/* width of bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 +/* default value of bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 + +/* tx data_tc_arb_mode bitfield definitions + * preprocessor definitions for the bitfield "data_tc_arb_mode". + * port="pif_tps_data_tc_arb_mode_i" + */ + +/* register address for bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 +/* bitmask for bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 +/* inverted bitmask for bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe +/* lower bit position of bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 +/* width of bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 +/* default value of bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 + +/* tx desc_rate_ta_rst bitfield definitions + * preprocessor definitions for the bitfield "desc_rate_ta_rst". + * port="pif_tps_desc_rate_ta_rst_i" + */ + +/* register address for bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 +/* bitmask for bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 +/* inverted bitmask for bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff +/* lower bit position of bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 +/* width of bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 +/* default value of bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 + +/* tx desc_rate_limit[a:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". + * port="pif_tps_desc_rate_lim_i[10:0]" + */ + +/* register address for bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 +/* bitmask for bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff +/* inverted bitmask for bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 +/* lower bit position of bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 +/* width of bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 +/* default value of bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 + +/* tx desc_tc_arb_mode[1:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". + * port="pif_tps_desc_tc_arb_mode_i[1:0]" + */ + +/* register address for bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 +/* bitmask for bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 +/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc +/* lower bit position of bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 +/* width of bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 +/* default value of bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 + +/* tx desc_tc{t}_credit_max[b:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_desc_tc0_credit_max_i[11:0]" + */ + +/* register address for bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) +/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 +/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff +/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 +/* width of bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 +/* default value of bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 + +/* tx desc_tc{t}_weight[8:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_desc_tc0_weight_i[8:0]" + */ + +/* register address for bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) +/* bitmask for bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff +/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 +/* lower bit position of bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 +/* width of bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 +/* default value of bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 + +/* tx desc_vm_arb_mode bitfield definitions + * preprocessor definitions for the bitfield "desc_vm_arb_mode". + * port="pif_tps_desc_vm_arb_mode_i" + */ + +/* register address for bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 +/* bitmask for bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 +/* inverted bitmask for bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe +/* lower bit position of bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 +/* width of bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 +/* default value of bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 + +/* tx data_tc{t}_credit_max[b:0] bitfield definitions + * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_data_tc0_credit_max_i[11:0]" + */ + +/* register address for bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) +/* bitmask for bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 +/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff +/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 +/* width of bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 +/* default value of bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 + +/* tx data_tc{t}_weight[8:0] bitfield definitions + * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_data_tc0_weight_i[8:0]" + */ + +/* register address for bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) +/* bitmask for bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff +/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 +/* lower bit position of bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 +/* width of bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 +/* default value of bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 + +/* tx reg_res_dsbl bitfield definitions + * preprocessor definitions for the bitfield "reg_res_dsbl". + * port="pif_tx_reg_res_dsbl_i" + */ + +/* register address for bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 +/* bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 +/* inverted bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff +/* lower bit position of bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 +/* width of bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 +/* default value of bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 + +/* mac_phy register access busy bitfield definitions + * preprocessor definitions for the bitfield "register access busy". + * port="msm_pif_reg_busy_o" + */ + +/* register address for bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 +/* bitmask for bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 +/* inverted bitmask for bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff +/* lower bit position of bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 +/* width of bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 + +/* mac_phy msm register address[7:0] bitfield definitions + * preprocessor definitions for the bitfield "msm register address[7:0]". + * port="pif_msm_reg_addr_i[7:0]" + */ + +/* register address for bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 +/* bitmask for bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff +/* inverted bitmask for bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 +/* lower bit position of bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_SHIFT 0 +/* width of bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_WIDTH 8 +/* default value of bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 + +/* mac_phy register read strobe bitfield definitions + * preprocessor definitions for the bitfield "register read strobe". + * port="pif_msm_reg_rden_i" + */ + +/* register address for bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 +/* bitmask for bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 +/* inverted bitmask for bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff +/* lower bit position of bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 +/* width of bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 +/* default value of bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 + +/* mac_phy msm register read data[31:0] bitfield definitions + * preprocessor definitions for the bitfield "msm register read data[31:0]". + * port="msm_pif_reg_rd_data_o[31:0]" + */ + +/* register address for bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 +/* bitmask for bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff +/* inverted bitmask for bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 +/* lower bit position of bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 +/* width of bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 + +/* mac_phy msm register write data[31:0] bitfield definitions + * preprocessor definitions for the bitfield "msm register write data[31:0]". + * port="pif_msm_reg_wr_data_i[31:0]" + */ + +/* register address for bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 +/* bitmask for bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff +/* inverted bitmask for bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 +/* lower bit position of bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 +/* width of bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 +/* default value of bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 + +/* mac_phy register write strobe bitfield definitions + * preprocessor definitions for the bitfield "register write strobe". + * port="pif_msm_reg_wren_i" + */ + +/* register address for bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 +/* bitmask for bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 +/* inverted bitmask for bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff +/* lower bit position of bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 +/* width of bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 +/* default value of bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 + +/* mif soft reset bitfield definitions + * preprocessor definitions for the bitfield "soft reset". + * port="pif_glb_res_i" + */ + +/* register address for bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 +/* bitmask for bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 +/* inverted bitmask for bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff +/* lower bit position of bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_SHIFT 15 +/* width of bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_WIDTH 1 +/* default value of bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 + +/* mif register reset disable bitfield definitions + * preprocessor definitions for the bitfield "register reset disable". + * port="pif_glb_reg_res_dsbl_i" + */ + +/* register address for bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 +/* bitmask for bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 +/* inverted bitmask for bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff +/* lower bit position of bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 +/* width of bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 +/* default value of bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 + +/* tx dma debug control definitions */ +#define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u + +/* tx dma descriptor base address msw definitions */ +#define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ + (0x00007c04u + (descriptor) * 0x40) + +/* tx dma total request limit */ +#define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u + +/* tx interrupt moderation control register definitions + * Preprocessor definitions for TX Interrupt Moderation Control Register + * Base Address: 0x00008980 + * Parameter: queue {Q} | stride size 0x4 | range [0, 31] + */ + +#define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) + +/* pcie reg_res_dsbl bitfield definitions + * preprocessor definitions for the bitfield "reg_res_dsbl". + * port="pif_pci_reg_res_dsbl_i" + */ + +/* register address for bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 +/* bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 +/* inverted bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff +/* lower bit position of bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 +/* width of bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 +/* default value of bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 + +/* PCI core control register */ +#define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u + +/* global microprocessor scratch pad definitions */ +#define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ + (0x00000300u + (scratch_scp) * 0x4) + +/* register address for bitfield uP Force Interrupt */ +#define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR 0x00000404 +/* bitmask for bitfield uP Force Interrupt */ +#define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK 0x00000002 +/* inverted bitmask for bitfield uP Force Interrupt */ +#define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN 0xFFFFFFFD +/* lower bit position of bitfield uP Force Interrupt */ +#define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT 1 +/* width of bitfield uP Force Interrupt */ +#define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH 1 +/* default value of bitfield uP Force Interrupt */ +#define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0 + +#endif /* HW_ATL_LLH_INTERNAL_H */ diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index cd6a0f637a7d..055342ec9db7 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -4,4 +4,5 @@ sources = files( 'atl_ethdev.c', 'atl_hw_regs.c', + 'hw_atl/hw_atl_llh.c', ) From patchwork Fri Oct 12 11:09:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46700 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 28D0D1B576; Fri, 12 Oct 2018 13:09:21 +0200 (CEST) Received: from NAM04-BN3-obe.outbound.protection.outlook.com (mail-eopbgr680088.outbound.protection.outlook.com [40.107.68.88]) by dpdk.org (Postfix) with ESMTP id 8E0181B563 for ; Fri, 12 Oct 2018 13:09:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=szMguBGLtuimMWmwFwdn6C/Eq6iWcRweXxIkT8Zbacs=; b=vQ9kHa6Xs6g4n2RJJdhsg4cHBYkt29n6YR1xnKQK6V7qGcKLyl8XXuPlZwtQ8gW8vXJJkmL5T5eVBkfdo5VG0qcQVZVn1o+JPeRCNpIxYPrpGxTmGDIOgo9d32IW8lGZ6QHwFo5zKpqEhQqYt17U9tappj/lFZnpPFWIHXhPjMs= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:15 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:15 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 05/22] net/atlantic: implement firmware operations Thread-Index: AQHUYhwCHs8I+ZIxfUyBtyKDCt3WdA== Date: Fri, 12 Oct 2018 11:09:14 +0000 Message-ID: <8e0e8eb1e71d73521b8dc8f272f6fa3cc222df9a.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:FERN9mFlVvt1KhK0S86RLmPXTOOK/0vOUHheuo1wNKR0wmff3DpRDC5zWgGRzQl8x9cOO68GpLiEVrSWcRvoucPyTA36Ni1Pp8jqFzTp4Nqel+OwTnFPMIN+CxPWQabKz9Zaqot5n/Rx/lA/Yt6URp0NYKm5gbvIyi0XHPr9IKZs/7PRJI4+6mOLwAAF5MYaVIveoyea/MNPAeNGX6QpnHg+HEVZwYBMIYxU+OT/uWFXODJsWC67wWIvx8gd2TmVSSgXMWAolsxitVgWWbfH4YyfOjmZwjZgjAHd0mfnOE0Axv87Ia3guYG9idQXPJwYU//EX80iuzCiXEHMcCPECv2neyoHFL7DB82ilOubFQwLU4XIb+LJgDEX85/lW3QyFcFbbLRYssfO/y6rSnMyrX9MtP1ZqjDJUlUDKYlsi76cZWtPcHjcNWIyzI35W1/nmrTfXR0kVEtIE348rChIPWszI8emGSuR8RV52uFXoF8=; 5:+wmO8zzK0TkK/gjslLyTr24ymok9siOlpCwtfMffXQNh+dqijgOMZCp4gm8mmTWCe8nU2Z4rJdPzxwaY0UP03w5IkaVmG+NVnWYkBrNFR64EvDpSGrpYbem5aR0n3kAZg+NyiDMITgnZF885S91TIvSRjp7kUZQRXxu6r0J6r8Y=; 7:TnONX9JwGcQ3YAwWcC2fsbUo6ARl0poZrqMiEwJQzddoIbNBYuNEpuwu1N5kLPbdMhoiVUsEe3oytqJQD0Ap0K2QgmssAuV7v81bMeIpa711c3EGRODQ9BAfp/y19Gc1eWDCbymQ4mnoqhEXHRruhMSBXBwWjHmLAsh0Nr5Gx4jULISovnY33bCrGcix5/aTLgYjoMCEV/XrRVv6MdRjZvbSkYCdUxE049samDEj27kJjoSOxUfEChsFN1vyY9QH x-ms-office365-filtering-correlation-id: dc95be52-80b9-4ff3-d643-08d6303324bb x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(4744004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(16200700003)(53946003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(575784001)(551934003)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: GASQDfeyaINxcF3+bUMZPmEniTRfT6dyjx84YFIaZNprQhQ+BXTipywMS1D5Y+eft35aGdn+8uqxOHEO/da88kYWneYRtSHeXnu11PSKNS1bPoqI1qhmPVSEaaiMSiGGgGG5YmzeyCfc/MsJNkUVNxxYOoTfjq8v01YqPAKrO8S2lQxXnvu8Yu2rBQLQ5OI4s1YHxd+U+MCoUQOhI4CX1HM8k0ITLtVDbTooE4CFmtOzNy1FIuLr3/Wl6vW40ge5t3g1E23v+MGv1DfjCIU/rttGsxwAw8QCV9Z7HsUCtS0s8gap73a8gYwClzUiV3BfufR+ONINOJOKd5QltwwUAtdbtT7N3FZ34MgwFNkqG1Q= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: dc95be52-80b9-4ff3-d643-08d6303324bb X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:14.8448 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 05/22] net/atlantic: implement firmware operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" AQC NICs comes in fields with two major FW generations: 1x and 3x. This is part of linux atlantic driver shared code, responsible for internal NIC firmware interactions, including link management ops, FW initialization, various lifecycle features. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 2 + drivers/net/atlantic/atl_types.h | 95 +++ drivers/net/atlantic/hw_atl/hw_atl_utils.c | 942 ++++++++++++++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_utils.h | 510 +++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c | 618 ++++++++++++++++ drivers/net/atlantic/meson.build | 2 + 6 files changed, 2169 insertions(+) create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_utils.c create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_utils.h create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index cae317badc0c..a291053b5ab7 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -26,6 +26,8 @@ VPATH += $(SRCDIR)/hw_atl # SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils_fw2x.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 725b0c4dc670..af24da3a5a54 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -22,8 +22,103 @@ typedef uint64_t u64; #define min(a, b) RTE_MIN(a, b) #define max(a, b) RTE_MAX(a, b) +#include "hw_atl/hw_atl_utils.h" + +struct aq_hw_link_status_s { + unsigned int mbps; +}; + +struct aq_stats_s { + u64 uprc; + u64 mprc; + u64 bprc; + u64 erpt; + u64 uptc; + u64 mptc; + u64 bptc; + u64 erpr; + u64 mbtc; + u64 bbtc; + u64 mbrc; + u64 bbrc; + u64 ubrc; + u64 ubtc; + u64 dpc; + u64 dma_pkt_rc; + u64 dma_pkt_tc; + u64 dma_oct_rc; + u64 dma_oct_tc; +}; + +struct aq_hw_cfg_s { + bool is_lro; + int wol; + + int link_speed_msk; + int irq_type; + int irq_mask; + unsigned int vecs; + + uint32_t flow_control; +}; + struct aq_hw_s { + u8 rbl_enabled:1; + struct aq_hw_cfg_s *aq_nic_cfg; + const struct aq_fw_ops *aq_fw_ops; void *mmio; + + struct aq_hw_link_status_s aq_link_status; + + struct hw_aq_atl_utils_mbox mbox; + struct hw_atl_stats_s last_stats; + struct aq_stats_s curr_stats; + + unsigned int chip_features; + u32 fw_ver_actual; + u32 mbox_addr; + u32 rpc_addr; + u32 rpc_tid; + struct hw_aq_atl_utils_fw_rpc rpc; +}; + +struct aq_fw_ops { + int (*init)(struct aq_hw_s *self); + + int (*deinit)(struct aq_hw_s *self); + + int (*reset)(struct aq_hw_s *self); + + int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); + + int (*set_link_speed)(struct aq_hw_s *self, u32 speed); + + int (*set_state)(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state); + + int (*update_link_status)(struct aq_hw_s *self); + + int (*update_stats)(struct aq_hw_s *self); + + int (*set_power)(struct aq_hw_s *self, unsigned int power_state, + u8 *mac); + + int (*get_temp)(struct aq_hw_s *self, int *temp); + + int (*get_cable_len)(struct aq_hw_s *self, int *cable_len); + + int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); + + int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, + u32 *supported_rates); + + int (*set_flow_control)(struct aq_hw_s *self); + + int (*led_control)(struct aq_hw_s *self, u32 mode); + + int (*get_eeprom)(struct aq_hw_s *self, u32 *data, u32 len); + + int (*set_eeprom)(struct aq_hw_s *self, u32 *data, u32 len); }; #endif diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/atlantic/hw_atl/hw_atl_utils.c new file mode 100644 index 000000000000..f11093a50404 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils.c @@ -0,0 +1,942 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_utils.c: Definition of common functions for Atlantic hardware + * abstraction layer. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../atl_hw_regs.h" + +#include "hw_atl_llh.h" +#include "hw_atl_llh_internal.h" +#include "../atl_logs.h" + +#define HW_ATL_UCP_0X370_REG 0x0370U + +#define HW_ATL_MIF_CMD 0x0200U +#define HW_ATL_MIF_ADDR 0x0208U +#define HW_ATL_MIF_VAL 0x020CU + +#define HW_ATL_FW_SM_RAM 0x2U +#define HW_ATL_MPI_FW_VERSION 0x18 +#define HW_ATL_MPI_CONTROL_ADR 0x0368U +#define HW_ATL_MPI_STATE_ADR 0x036CU + +#define HW_ATL_MPI_STATE_MSK 0x00FFU +#define HW_ATL_MPI_STATE_SHIFT 0U +#define HW_ATL_MPI_SPEED_MSK 0x00FF0000U +#define HW_ATL_MPI_SPEED_SHIFT 16U +#define HW_ATL_MPI_DIRTY_WAKE_MSK 0x02000000U + +#define HW_ATL_MPI_DAISY_CHAIN_STATUS 0x704 +#define HW_ATL_MPI_BOOT_EXIT_CODE 0x388 + +#define HW_ATL_MAC_PHY_CONTROL 0x4000 +#define HW_ATL_MAC_PHY_MPI_RESET_BIT 0x1D + +#define HW_ATL_FW_VER_1X 0x01050006U +#define HW_ATL_FW_VER_2X 0x02000000U +#define HW_ATL_FW_VER_3X 0x03000000U + +#define FORCE_FLASHLESS 0 + +static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual); +static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state); + + +int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops) +{ + int err = 0; + + err = hw_atl_utils_soft_reset(self); + if (err) + return err; + + hw_atl_utils_hw_chip_features_init(self, + &self->chip_features); + + hw_atl_utils_get_fw_version(self, &self->fw_ver_actual); + + if (hw_atl_utils_ver_match(HW_ATL_FW_VER_1X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_fw_1x_ops; + } else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_2X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_fw_2x_ops; + } else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_3X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_fw_2x_ops; + } else { + PMD_DRV_LOG(ERR, "Bad FW version detected: %x\n", + self->fw_ver_actual); + return -EOPNOTSUPP; + } + self->aq_fw_ops = *fw_ops; + err = self->aq_fw_ops->init(self); + return err; +} + +static int hw_atl_utils_soft_reset_flb(struct aq_hw_s *self) +{ + u32 gsr, val; + int k = 0; + + aq_hw_write_reg(self, 0x404, 0x40e1); + AQ_HW_SLEEP(50); + + /* Cleanup SPI */ + val = aq_hw_read_reg(self, 0x53C); + aq_hw_write_reg(self, 0x53C, val | 0x10); + + gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR); + aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000); + + /* Kickstart MAC */ + aq_hw_write_reg(self, 0x404, 0x80e0); + aq_hw_write_reg(self, 0x32a8, 0x0); + aq_hw_write_reg(self, 0x520, 0x1); + + /* Reset SPI again because of possible interrupted SPI burst */ + val = aq_hw_read_reg(self, 0x53C); + aq_hw_write_reg(self, 0x53C, val | 0x10); + AQ_HW_SLEEP(10); + /* Clear SPI reset state */ + aq_hw_write_reg(self, 0x53C, val & ~0x10); + + aq_hw_write_reg(self, 0x404, 0x180e0); + + for (k = 0; k < 1000; k++) { + u32 flb_status = aq_hw_read_reg(self, + HW_ATL_MPI_DAISY_CHAIN_STATUS); + + flb_status = flb_status & 0x10; + if (flb_status) + break; + AQ_HW_SLEEP(10); + } + if (k == 1000) { + PMD_DRV_LOG(ERR, "MAC kickstart failed\n"); + return -EIO; + } + + /* FW reset */ + aq_hw_write_reg(self, 0x404, 0x80e0); + AQ_HW_SLEEP(50); + aq_hw_write_reg(self, 0x3a0, 0x1); + + /* Kickstart PHY - skipped */ + + /* Global software reset*/ + hw_atl_rx_rx_reg_res_dis_set(self, 0U); + hw_atl_tx_tx_reg_res_dis_set(self, 0U); + aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL, + BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT), + HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0); + gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR); + aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000); + + for (k = 0; k < 1000; k++) { + u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION); + + if (fw_state) + break; + AQ_HW_SLEEP(10); + } + if (k == 1000) { + PMD_DRV_LOG(ERR, "FW kickstart failed\n"); + return -EIO; + } + /* Old FW requires fixed delay after init */ + AQ_HW_SLEEP(15); + + return 0; +} + +static int hw_atl_utils_soft_reset_rbl(struct aq_hw_s *self) +{ + u32 gsr, val, rbl_status; + int k; + + aq_hw_write_reg(self, 0x404, 0x40e1); + aq_hw_write_reg(self, 0x3a0, 0x1); + aq_hw_write_reg(self, 0x32a8, 0x0); + + /* Alter RBL status */ + aq_hw_write_reg(self, 0x388, 0xDEAD); + + /* Cleanup SPI */ + val = aq_hw_read_reg(self, 0x53C); + aq_hw_write_reg(self, 0x53C, val | 0x10); + + /* Global software reset*/ + hw_atl_rx_rx_reg_res_dis_set(self, 0U); + hw_atl_tx_tx_reg_res_dis_set(self, 0U); + aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL, + BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT), + HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0); + gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR); + aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, + (gsr & 0xFFFFBFFF) | 0x8000); + + if (FORCE_FLASHLESS) + aq_hw_write_reg(self, 0x534, 0x0); + + aq_hw_write_reg(self, 0x404, 0x40e0); + + /* Wait for RBL boot */ + for (k = 0; k < 1000; k++) { + rbl_status = aq_hw_read_reg(self, 0x388) & 0xFFFF; + if (rbl_status && rbl_status != 0xDEAD) + break; + AQ_HW_SLEEP(10); + } + if (!rbl_status || rbl_status == 0xDEAD) { + PMD_DRV_LOG(ERR, "RBL Restart failed"); + return -EIO; + } + + /* Restore NVR */ + if (FORCE_FLASHLESS) + aq_hw_write_reg(self, 0x534, 0xA0); + + if (rbl_status == 0xF1A7) { + PMD_DRV_LOG(ERR, "No FW detected. Dynamic FW load not implemented\n"); + return -EOPNOTSUPP; + } + + for (k = 0; k < 1000; k++) { + u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION); + + if (fw_state) + break; + AQ_HW_SLEEP(10); + } + if (k == 1000) { + PMD_DRV_LOG(ERR, "FW kickstart failed\n"); + return -EIO; + } + /* Old FW requires fixed delay after init */ + AQ_HW_SLEEP(15); + + return 0; +} + +int hw_atl_utils_soft_reset(struct aq_hw_s *self) +{ + int err = 0; + int k; + u32 boot_exit_code = 0; + + for (k = 0; k < 1000; ++k) { + u32 flb_status = aq_hw_read_reg(self, + HW_ATL_MPI_DAISY_CHAIN_STATUS); + boot_exit_code = aq_hw_read_reg(self, + HW_ATL_MPI_BOOT_EXIT_CODE); + if (flb_status != 0x06000000 || boot_exit_code != 0) + break; + } + + if (k == 1000) { + PMD_DRV_LOG(ERR, "Neither RBL nor FLB firmware started\n"); + return -EOPNOTSUPP; + } + + self->rbl_enabled = (boot_exit_code != 0); + + /* FW 1.x may bootup in an invalid POWER state (WOL feature). + * We should work around this by forcing its state back to DEINIT + */ + if (!hw_atl_utils_ver_match(HW_ATL_FW_VER_1X, + aq_hw_read_reg(self, + HW_ATL_MPI_FW_VERSION))) { + hw_atl_utils_mpi_set_state(self, MPI_DEINIT); + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR) & + HW_ATL_MPI_STATE_MSK) == MPI_DEINIT, + 10, 1000U); + } + + if (self->rbl_enabled) + err = hw_atl_utils_soft_reset_rbl(self); + else + err = hw_atl_utils_soft_reset_flb(self); + + return err; +} + +int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, + u32 *p, u32 cnt) +{ + int err = 0; + + AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self, + HW_ATL_FW_SM_RAM) == 1U, + 1U, 10000U); + + if (err < 0) { + bool is_locked; + + hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); + is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); + if (!is_locked) { + err = -ETIMEDOUT; + goto err_exit; + } + } + + aq_hw_write_reg(self, HW_ATL_MIF_ADDR, a); + + for (++cnt; --cnt && !err;) { + aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U); + + if (IS_CHIP_FEATURE(REVISION_B1)) + AQ_HW_WAIT_FOR(a != aq_hw_read_reg(self, + HW_ATL_MIF_ADDR), + 1, 1000U); + else + AQ_HW_WAIT_FOR(!(0x100 & aq_hw_read_reg(self, + HW_ATL_MIF_CMD)), + 1, 1000U); + + *(p++) = aq_hw_read_reg(self, HW_ATL_MIF_VAL); + a += 4; + } + + hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); + +err_exit: + return err; +} + +int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, + u32 cnt) +{ + int err = 0; + bool is_locked; + + is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); + if (!is_locked) { + err = -ETIMEDOUT; + goto err_exit; + } + if (IS_CHIP_FEATURE(REVISION_B1)) { + u32 offset = 0; + + for (; offset < cnt; ++offset) { + aq_hw_write_reg(self, 0x328, p[offset]); + aq_hw_write_reg(self, 0x32C, + (0x80000000 | (0xFFFF & (offset * 4)))); + hw_atl_mcp_up_force_intr_set(self, 1); + /* 1000 times by 10us = 10ms */ + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, + 0x32C) & 0xF0000000) != 0x80000000, + 10, 1000); + } + } else { + u32 offset = 0; + + aq_hw_write_reg(self, 0x208, a); + + for (; offset < cnt; ++offset) { + aq_hw_write_reg(self, 0x20C, p[offset]); + aq_hw_write_reg(self, 0x200, 0xC000); + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x200U) + & 0x100) == 0, 10, 1000); + } + } + + hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); + +err_exit: + return err; +} + +static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual) +{ + int err = 0; + const u32 dw_major_mask = 0xff000000U; + const u32 dw_minor_mask = 0x00ffffffU; + + err = (dw_major_mask & (ver_expected ^ ver_actual)) ? -EOPNOTSUPP : 0; + if (err < 0) + goto err_exit; + err = ((dw_minor_mask & ver_expected) > (dw_minor_mask & ver_actual)) ? + -EOPNOTSUPP : 0; +err_exit: + return err; +} + +static int hw_atl_utils_init_ucp(struct aq_hw_s *self) +{ + int err = 0; + + if (!aq_hw_read_reg(self, 0x370U)) { + unsigned int rnd = (uint32_t)rte_rand(); + unsigned int ucp_0x370 = 0U; + + ucp_0x370 = 0x02020202U | (0xFEFEFEFEU & rnd); + aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370); + } + + hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U); + + /* check 10 times by 1ms */ + AQ_HW_WAIT_FOR(0U != (self->mbox_addr = + aq_hw_read_reg(self, 0x360U)), 1000U, 10U); + AQ_HW_WAIT_FOR(0U != (self->rpc_addr = + aq_hw_read_reg(self, 0x334U)), 1000U, 100U); + + return err; +} + +#define HW_ATL_RPC_CONTROL_ADR 0x0338U +#define HW_ATL_RPC_STATE_ADR 0x033CU + +struct aq_hw_atl_utils_fw_rpc_tid_s { + union { + u32 val; + struct { + u16 tid; + u16 len; + }; + }; +}; + +#define hw_atl_utils_fw_rpc_init(_H_) hw_atl_utils_fw_rpc_wait(_H_, NULL) + +int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size) +{ + int err = 0; + struct aq_hw_atl_utils_fw_rpc_tid_s sw; + + if (!IS_CHIP_FEATURE(MIPS)) { + err = -1; + goto err_exit; + } + err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr, + (u32 *)(void *)&self->rpc, + (rpc_size + sizeof(u32) - + sizeof(u8)) / sizeof(u32)); + if (err < 0) + goto err_exit; + + sw.tid = 0xFFFFU & (++self->rpc_tid); + sw.len = (u16)rpc_size; + aq_hw_write_reg(self, HW_ATL_RPC_CONTROL_ADR, sw.val); + +err_exit: + return err; +} + +int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, + struct hw_aq_atl_utils_fw_rpc **rpc) +{ + int err = 0; + struct aq_hw_atl_utils_fw_rpc_tid_s sw; + struct aq_hw_atl_utils_fw_rpc_tid_s fw; + + do { + sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR); + + self->rpc_tid = sw.tid; + + AQ_HW_WAIT_FOR(sw.tid == + (fw.val = + aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR), + fw.tid), 1000U, 100U); + if (err < 0) + goto err_exit; + + if (fw.len == 0xFFFFU) { + err = hw_atl_utils_fw_rpc_call(self, sw.len); + if (err < 0) + goto err_exit; + } + } while (sw.tid != fw.tid || 0xFFFFU == fw.len); + if (err < 0) + goto err_exit; + + if (rpc) { + if (fw.len) { + err = + hw_atl_utils_fw_downld_dwords(self, + self->rpc_addr, + (u32 *)(void *) + &self->rpc, + (fw.len + sizeof(u32) - + sizeof(u8)) / + sizeof(u32)); + if (err < 0) + goto err_exit; + } + + *rpc = &self->rpc; + } + +err_exit: + return err; +} + +static int hw_atl_utils_mpi_create(struct aq_hw_s *self) +{ + int err = 0; + + err = hw_atl_utils_init_ucp(self); + if (err < 0) + goto err_exit; + + err = hw_atl_utils_fw_rpc_init(self); + if (err < 0) + goto err_exit; + +err_exit: + return err; +} + +int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox_header *pmbox) +{ + return hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr, + (u32 *)(void *)pmbox, + sizeof(*pmbox) / sizeof(u32)); +} + +void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox *pmbox) +{ + int err = 0; + + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr, + (u32 *)(void *)pmbox, + sizeof(*pmbox) / sizeof(u32)); + if (err < 0) + goto err_exit; + + if (IS_CHIP_FEATURE(REVISION_A0)) { + unsigned int mtu = 1514; + pmbox->stats.ubrc = pmbox->stats.uprc * mtu; + pmbox->stats.ubtc = pmbox->stats.uptc * mtu; + } else { + pmbox->stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self); + } + +err_exit:; +} + +static +int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed) +{ + u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR); + + val = val & ~HW_ATL_MPI_SPEED_MSK; + val |= speed << HW_ATL_MPI_SPEED_SHIFT; + aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val); + + return 0; +} + +int hw_atl_utils_mpi_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state) +{ + int err = 0; + u32 transaction_id = 0; + struct hw_aq_atl_utils_mbox_header mbox; + u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR); + + if (state == MPI_RESET) { + hw_atl_utils_mpi_read_mbox(self, &mbox); + + transaction_id = mbox.transaction_id; + + AQ_HW_WAIT_FOR(transaction_id != + (hw_atl_utils_mpi_read_mbox(self, &mbox), + mbox.transaction_id), + 1000U, 100U); + if (err < 0) + goto err_exit; + } + /* On interface DEINIT we disable DW (raise bit) + * Otherwise enable DW (clear bit) + */ + if (state == MPI_DEINIT || state == MPI_POWER) + val |= HW_ATL_MPI_DIRTY_WAKE_MSK; + else + val &= ~HW_ATL_MPI_DIRTY_WAKE_MSK; + + /* Set new state bits */ + val = val & ~HW_ATL_MPI_STATE_MSK; + val |= state & HW_ATL_MPI_STATE_MSK; + + aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val); +err_exit: + return err; +} + +int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self) +{ + u32 cp0x036C = aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR); + u32 link_speed_mask = cp0x036C >> HW_ATL_MPI_SPEED_SHIFT; + struct aq_hw_link_status_s *link_status = &self->aq_link_status; + + if (!link_speed_mask) { + link_status->mbps = 0U; + } else { + switch (link_speed_mask) { + case HAL_ATLANTIC_RATE_10G: + link_status->mbps = 10000U; + break; + + case HAL_ATLANTIC_RATE_5G: + case HAL_ATLANTIC_RATE_5GSR: + link_status->mbps = 5000U; + break; + + case HAL_ATLANTIC_RATE_2GS: + link_status->mbps = 2500U; + break; + + case HAL_ATLANTIC_RATE_1G: + link_status->mbps = 1000U; + break; + + case HAL_ATLANTIC_RATE_100M: + link_status->mbps = 100U; + break; + + default: + return -EBUSY; + } + } + + return 0; +} + +static int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self, + u8 *mac) +{ + int err = 0; + u32 h = 0U; + u32 l = 0U; + u32 mac_addr[2]; + + if (!aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) { + unsigned int rnd = (uint32_t)rte_rand(); + unsigned int ucp_0x370 = 0; + + //get_random_bytes(&rnd, sizeof(unsigned int)); + + ucp_0x370 = 0x02020202 | (0xFEFEFEFE & rnd); + aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370); + } + + err = hw_atl_utils_fw_downld_dwords(self, + aq_hw_read_reg(self, 0x00000374U) + + (40U * 4U), + mac_addr, + ARRAY_SIZE(mac_addr)); + if (err < 0) { + mac_addr[0] = 0U; + mac_addr[1] = 0U; + err = 0; + } else { + mac_addr[0] = rte_constant_bswap32(mac_addr[0]); + mac_addr[1] = rte_constant_bswap32(mac_addr[1]); + } + + ether_addr_copy((struct ether_addr *)mac_addr, + (struct ether_addr *)mac); + + if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) { + /* chip revision */ + l = 0xE3000000U + | (0xFFFFU & aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) + | (0x00 << 16); + h = 0x8001300EU; + + mac[5] = (u8)(0xFFU & l); + l >>= 8; + mac[4] = (u8)(0xFFU & l); + l >>= 8; + mac[3] = (u8)(0xFFU & l); + l >>= 8; + mac[2] = (u8)(0xFFU & l); + mac[1] = (u8)(0xFFU & h); + h >>= 8; + mac[0] = (u8)(0xFFU & h); + } + + return err; +} + +unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps) +{ + unsigned int ret = 0U; + + switch (mbps) { + case 100U: + ret = 5U; + break; + + case 1000U: + ret = 4U; + break; + + case 2500U: + ret = 3U; + break; + + case 5000U: + ret = 1U; + break; + + case 10000U: + ret = 0U; + break; + + default: + break; + } + return ret; +} + +void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p) +{ + u32 chip_features = 0U; + u32 val = hw_atl_reg_glb_mif_id_get(self); + u32 mif_rev = val & 0xFFU; + + if ((0xFU & mif_rev) == 1U) { + chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 | + HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | + HAL_ATLANTIC_UTILS_CHIP_MIPS; + } else if ((0xFU & mif_rev) == 2U) { + chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 | + HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | + HAL_ATLANTIC_UTILS_CHIP_MIPS | + HAL_ATLANTIC_UTILS_CHIP_TPO2 | + HAL_ATLANTIC_UTILS_CHIP_RPF2; + } else if ((0xFU & mif_rev) == 0xAU) { + chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 | + HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | + HAL_ATLANTIC_UTILS_CHIP_MIPS | + HAL_ATLANTIC_UTILS_CHIP_TPO2 | + HAL_ATLANTIC_UTILS_CHIP_RPF2; + } + + *p = chip_features; +} + +static int hw_atl_fw1x_deinit(struct aq_hw_s *self) +{ + hw_atl_utils_mpi_set_speed(self, 0); + hw_atl_utils_mpi_set_state(self, MPI_DEINIT); + return 0; +} + +int hw_atl_utils_update_stats(struct aq_hw_s *self) +{ + struct hw_aq_atl_utils_mbox mbox; + + hw_atl_utils_mpi_read_stats(self, &mbox); + +#define AQ_SDELTA(_N_) (self->curr_stats._N_ += \ + mbox.stats._N_ - self->last_stats._N_) + + if (1) {//self->aq_link_status.mbps) { + AQ_SDELTA(uprc); + AQ_SDELTA(mprc); + AQ_SDELTA(bprc); + AQ_SDELTA(erpt); + + AQ_SDELTA(uptc); + AQ_SDELTA(mptc); + AQ_SDELTA(bptc); + AQ_SDELTA(erpr); + AQ_SDELTA(ubrc); + AQ_SDELTA(ubtc); + AQ_SDELTA(mbrc); + AQ_SDELTA(mbtc); + AQ_SDELTA(bbrc); + AQ_SDELTA(bbtc); + AQ_SDELTA(dpc); + } +#undef AQ_SDELTA + self->curr_stats.dma_pkt_rc = + hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self) + + ((u64)hw_atl_stats_rx_dma_good_pkt_countermsw_get(self) << 32); + self->curr_stats.dma_pkt_tc = + hw_atl_stats_tx_dma_good_pkt_counterlsw_get(self) + + ((u64)hw_atl_stats_tx_dma_good_pkt_countermsw_get(self) << 32); + self->curr_stats.dma_oct_rc = + hw_atl_stats_rx_dma_good_octet_counterlsw_get(self) + + ((u64)hw_atl_stats_rx_dma_good_octet_countermsw_get(self) << 32); + self->curr_stats.dma_oct_tc = + hw_atl_stats_tx_dma_good_octet_counterlsw_get(self) + + ((u64)hw_atl_stats_tx_dma_good_octet_countermsw_get(self) << 32); + + self->curr_stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self); + + memcpy(&self->last_stats, &mbox.stats, sizeof(mbox.stats)); + + return 0; +} + +struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self) +{ + return &self->curr_stats; +} + +static const u32 hw_atl_utils_hw_mac_regs[] = { + 0x00005580U, 0x00005590U, 0x000055B0U, 0x000055B4U, + 0x000055C0U, 0x00005B00U, 0x00005B04U, 0x00005B08U, + 0x00005B0CU, 0x00005B10U, 0x00005B14U, 0x00005B18U, + 0x00005B1CU, 0x00005B20U, 0x00005B24U, 0x00005B28U, + 0x00005B2CU, 0x00005B30U, 0x00005B34U, 0x00005B38U, + 0x00005B3CU, 0x00005B40U, 0x00005B44U, 0x00005B48U, + 0x00005B4CU, 0x00005B50U, 0x00005B54U, 0x00005B58U, + 0x00005B5CU, 0x00005B60U, 0x00005B64U, 0x00005B68U, + 0x00005B6CU, 0x00005B70U, 0x00005B74U, 0x00005B78U, + 0x00005B7CU, 0x00007C00U, 0x00007C04U, 0x00007C08U, + 0x00007C0CU, 0x00007C10U, 0x00007C14U, 0x00007C18U, + 0x00007C1CU, 0x00007C20U, 0x00007C40U, 0x00007C44U, + 0x00007C48U, 0x00007C4CU, 0x00007C50U, 0x00007C54U, + 0x00007C58U, 0x00007C5CU, 0x00007C60U, 0x00007C80U, + 0x00007C84U, 0x00007C88U, 0x00007C8CU, 0x00007C90U, + 0x00007C94U, 0x00007C98U, 0x00007C9CU, 0x00007CA0U, + 0x00007CC0U, 0x00007CC4U, 0x00007CC8U, 0x00007CCCU, + 0x00007CD0U, 0x00007CD4U, 0x00007CD8U, 0x00007CDCU, + 0x00007CE0U, 0x00000300U, 0x00000304U, 0x00000308U, + 0x0000030cU, 0x00000310U, 0x00000314U, 0x00000318U, + 0x0000031cU, 0x00000360U, 0x00000364U, 0x00000368U, + 0x0000036cU, 0x00000370U, 0x00000374U, 0x00006900U, +}; + +unsigned int hw_atl_utils_hw_get_reg_length(void) +{ + return ARRAY_SIZE(hw_atl_utils_hw_mac_regs); +} + +int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, + u32 *regs_buff) +{ + unsigned int i = 0U; + unsigned int mac_regs_count = hw_atl_utils_hw_get_reg_length(); + + for (i = 0; i < mac_regs_count; i++) + regs_buff[i] = aq_hw_read_reg(self, + hw_atl_utils_hw_mac_regs[i]); + return 0; +} + +int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version) +{ + *fw_version = aq_hw_read_reg(self, 0x18U); + return 0; +} + +static int aq_fw1x_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac) +{ + struct hw_aq_atl_utils_fw_rpc *prpc = NULL; + unsigned int rpc_size = 0U; + int err = 0; + + err = hw_atl_utils_fw_rpc_wait(self, &prpc); + if (err < 0) + goto err_exit; + + memset(prpc, 0, sizeof(*prpc)); + + if (wol_enabled) { + rpc_size = sizeof(prpc->msg_id) + sizeof(prpc->msg_wol); + + prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD; + prpc->msg_wol.priority = 0x10000000; /* normal priority */ + prpc->msg_wol.pattern_id = 1U; + prpc->msg_wol.wol_packet_type = 2U; /* Magic Packet */ + + ether_addr_copy((struct ether_addr *)mac, + (struct ether_addr *)&prpc->msg_wol.wol_pattern); + } else { + rpc_size = sizeof(prpc->msg_id) + sizeof(prpc->msg_del_id); + + prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL; + prpc->msg_wol.pattern_id = 1U; + } + + err = hw_atl_utils_fw_rpc_call(self, rpc_size); + if (err < 0) + goto err_exit; +err_exit: + return err; +} + +static +int aq_fw1x_set_power(struct aq_hw_s *self, + unsigned int power_state __rte_unused, + u8 *mac) +{ + struct hw_aq_atl_utils_fw_rpc *prpc = NULL; + unsigned int rpc_size = 0U; + int err = 0; + if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) { + err = aq_fw1x_set_wol(self, 1, mac); + + if (err < 0) + goto err_exit; + + rpc_size = sizeof(prpc->msg_id) + + sizeof(prpc->msg_enable_wakeup); + + err = hw_atl_utils_fw_rpc_wait(self, &prpc); + + if (err < 0) + goto err_exit; + + memset(prpc, 0, rpc_size); + + prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP; + prpc->msg_enable_wakeup.pattern_mask = 0x00000002; + + err = hw_atl_utils_fw_rpc_call(self, rpc_size); + if (err < 0) + goto err_exit; + } + + hw_atl_utils_mpi_set_speed(self, 0); + hw_atl_utils_mpi_set_state(self, MPI_POWER); +err_exit: + return err; +} + + + +const struct aq_fw_ops aq_fw_1x_ops = { + .init = hw_atl_utils_mpi_create, + .deinit = hw_atl_fw1x_deinit, + .reset = NULL, + .get_mac_permanent = hw_atl_utils_get_mac_permanent, + .set_link_speed = hw_atl_utils_mpi_set_speed, + .set_state = hw_atl_utils_mpi_set_state, + .update_link_status = hw_atl_utils_mpi_get_link_status, + .update_stats = hw_atl_utils_update_stats, + .set_power = aq_fw1x_set_power, + .get_temp = NULL, + .get_cable_len = NULL, + .set_eee_rate = NULL, + .get_eee_rate = NULL, + .set_flow_control = NULL, + .led_control = NULL, + .get_eeprom = NULL, + .set_eeprom = NULL, +}; diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/atlantic/hw_atl/hw_atl_utils.h new file mode 100644 index 000000000000..5f3f70847310 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils.h @@ -0,0 +1,510 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware + * abstraction layer. + */ + +#ifndef HW_ATL_UTILS_H +#define HW_ATL_UTILS_H + +#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); } + +/* Hardware tx descriptor */ +struct hw_atl_txd_s { + u64 buf_addr; + + union { + struct { + u32 type:3; + u32:1; + u32 len:16; + u32 dd:1; + u32 eop:1; + u32 cmd:8; + u32:14; + u32 ct_idx:1; + u32 ct_en:1; + u32 pay_len:18; + } __attribute__((__packed__)); + u64 flags; + }; +} __attribute__((__packed__)); + +/* Hardware tx context descriptor */ +union hw_atl_txc_s { + struct { + u64 flags1; + u64 flags2; + }; + + struct { + u64:40; + u32 tun_len:8; + u32 out_len:16; + u32 type:3; + u32 idx:1; + u32 vlan_tag:16; + u32 cmd:4; + u32 l2_len:7; + u32 l3_len:9; + u32 l4_len:8; + u32 mss_len:16; + } __attribute__((__packed__)); +} __attribute__((__packed__)); + +enum aq_tx_desc_type { + tx_desc_type_desc = 1, + tx_desc_type_ctx = 2, +}; + +enum aq_tx_desc_cmd { + tx_desc_cmd_vlan = 1, + tx_desc_cmd_fcs = 2, + tx_desc_cmd_ipv4 = 4, + tx_desc_cmd_l4cs = 8, + tx_desc_cmd_lso = 0x10, + tx_desc_cmd_wb = 0x20, +}; + + +/* Hardware rx descriptor */ +struct hw_atl_rxd_s { + u64 buf_addr; + u64 hdr_addr; +} __attribute__((__packed__)); + +/* Hardware rx descriptor writeback */ +struct hw_atl_rxd_wb_s { + u32 rss_type:4; + u32 pkt_type:8; + u32 type:20; + u32 rss_hash; + u16 dd:1; + u16 eop:1; + u16 rx_stat:4; + u16 rx_estat:6; + u16 rsc_cnt:4; + u16 pkt_len; + u16 next_desc_ptr; + u16 vlan; +} __attribute__((__packed__)); + +struct hw_atl_stats_s { + u32 uprc; + u32 mprc; + u32 bprc; + u32 erpt; + u32 uptc; + u32 mptc; + u32 bptc; + u32 erpr; + u32 mbtc; + u32 bbtc; + u32 mbrc; + u32 bbrc; + u32 ubrc; + u32 ubtc; + u32 dpc; +} __attribute__((__packed__)); + +union ip_addr { + struct { + u8 addr[16]; + } v6; + struct { + u8 padding[12]; + u8 addr[4]; + } v4; +} __attribute__((__packed__)); + +struct hw_aq_atl_utils_fw_rpc { + u32 msg_id; + + union { + struct { + u32 pong; + } msg_ping; + + struct { + u8 mac_addr[6]; + u32 ip_addr_cnt; + + struct { + union ip_addr addr; + union ip_addr mask; + } ip[1]; + } msg_arp; + + struct { + u32 len; + u8 packet[1514U]; + } msg_inject; + + struct { + u32 priority; + u32 wol_packet_type; + u32 pattern_id; + u32 next_wol_pattern_offset; + union { + struct { + u32 flags; + u8 ipv4_source_address[4]; + u8 ipv4_dest_address[4]; + u16 tcp_source_port_number; + u16 tcp_dest_port_number; + } ipv4_tcp_syn_parameters; + + struct { + u32 flags; + u8 ipv6_source_address[16]; + u8 ipv6_dest_address[16]; + u16 tcp_source_port_number; + u16 tcp_dest_port_number; + } ipv6_tcp_syn_parameters; + + struct { + u32 flags; + } eapol_request_id_message_parameters; + + struct { + u32 flags; + u32 mask_offset; + u32 mask_size; + u32 pattern_offset; + u32 pattern_size; + } wol_bit_map_pattern; + struct { + u8 mac_addr[6]; + } wol_magic_packet_pattern; + + } wol_pattern; + } msg_wol; + + struct { + u16 tc_quanta[8]; + u16 tc_threshold[8]; + } msg_msm_pfc_quantas; + + struct { + union { + u32 pattern_mask; + struct { + u32 aq_pm_wol_reason_arp_v4_pkt : 1; + u32 aq_pm_wol_reason_ipv4_ping_pkt : 1; + u32 aq_pm_wol_reason_ipv6_ns_pkt : 1; + u32 aq_pm_wol_reason_ipv6_ping_pkt : 1; + u32 aq_pm_wol_reason_link_up : 1; + u32 aq_pm_wol_reason_link_down : 1; + u32 aq_pm_wol_reason_maximum : 1; + }; + }; + union { + u32 offload_mask; + }; + } msg_enable_wakeup; + + struct { + u32 priority; + u32 protocol_offload_type; + u32 protocol_offload_id; + u32 next_protocol_offload_offset; + + union { + struct { + u32 flags; + u8 remote_ipv4_addr[4]; + u8 host_ipv4_addr[4]; + u8 mac_addr[6]; + } ipv4_arp_params; + }; + } msg_offload; + + struct { + u32 id; + } msg_del_id; + + }; +} __attribute__((__packed__)); + +struct hw_aq_atl_utils_mbox_header { + u32 version; + u32 transaction_id; + u32 error; +} __attribute__((__packed__)); + +struct hw_aq_info { + u8 reserved[6]; + u16 phy_fault_code; + u16 phy_temperature; + u8 cable_len; + u8 reserved1; + u32 cable_diag_data[4]; + u8 reserved2[32]; + u32 caps_lo; + u32 caps_hi; +} __attribute__((__packed__)); + +struct hw_aq_atl_utils_mbox { + struct hw_aq_atl_utils_mbox_header header; + struct hw_atl_stats_s stats; + struct hw_aq_info info; +} __attribute__((__packed__)); + +/* fw2x */ +typedef u16 in_port_t; +typedef u32 ip4_addr_t; +typedef int int32_t; +typedef short int16_t; +typedef u32 fw_offset_t; + +struct ip6_addr { + u32 addr[4]; +} __attribute__((__packed__)); + +struct offload_ka_v4 { + u32 timeout; + in_port_t local_port; + in_port_t remote_port; + u8 remote_mac_addr[6]; + u16 win_size; + u32 seq_num; + u32 ack_num; + ip4_addr_t local_ip; + ip4_addr_t remote_ip; +} __attribute__((__packed__)); + +struct offload_ka_v6 { + u32 timeout; + in_port_t local_port; + in_port_t remote_port; + u8 remote_mac_addr[6]; + u16 win_size; + u32 seq_num; + u32 ack_num; + struct ip6_addr local_ip; + struct ip6_addr remote_ip; +} __attribute__((__packed__)); + +struct offload_ip_info { + u8 v4_local_addr_count; + u8 v4_addr_count; + u8 v6_local_addr_count; + u8 v6_addr_count; + fw_offset_t v4_addr; + fw_offset_t v4_prefix; + fw_offset_t v6_addr; + fw_offset_t v6_prefix; +} __attribute__((__packed__)); + +struct offload_port_info { + u16 udp_port_count; + u16 tcp_port_count; + fw_offset_t udp_port; + fw_offset_t tcp_port; +} __attribute__((__packed__)); + +struct offload_ka_info { + u16 v4_ka_count; + u16 v6_ka_count; + u32 retry_count; + u32 retry_interval; + fw_offset_t v4_ka; + fw_offset_t v6_ka; +} __attribute__((__packed__)); + +struct offload_rr_info { + u32 rr_count; + u32 rr_buf_len; + fw_offset_t rr_id_x; + fw_offset_t rr_buf; +} __attribute__((__packed__)); + +struct offload_info { + u32 version; // current version is 0x00000000 + u32 len; // The whole structure length + // including the variable-size buf + u8 mac_addr[6]; // 8 bytes to keep alignment. Only + // first 6 meaningful. + + u8 reserved[2]; + + struct offload_ip_info ips; + struct offload_port_info ports; + struct offload_ka_info kas; + struct offload_rr_info rrs; + u8 buf[0]; +} __attribute__((__packed__)); + +struct smbus_read_request { + u32 offset; /* not used */ + u32 device_id; + u32 address; + u32 length; +} __attribute__((__packed__)); + +struct smbus_write_request { + u32 offset; /* not used */ + u32 device_id; + u32 address; + u32 length; +} __attribute__((__packed__)); + +#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U +#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U +#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U +#define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U +#define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U +#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U +#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U + + +#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \ + self->chip_features) + +enum hal_atl_utils_fw_state_e { + MPI_DEINIT = 0, + MPI_RESET = 1, + MPI_INIT = 2, + MPI_POWER = 4, +}; + +#define HAL_ATLANTIC_RATE_10G BIT(0) +#define HAL_ATLANTIC_RATE_5G BIT(1) +#define HAL_ATLANTIC_RATE_5GSR BIT(2) +#define HAL_ATLANTIC_RATE_2GS BIT(3) +#define HAL_ATLANTIC_RATE_1G BIT(4) +#define HAL_ATLANTIC_RATE_100M BIT(5) +#define HAL_ATLANTIC_RATE_INVALID BIT(6) + +#define HAL_ATLANTIC_UTILS_FW_MSG_PING 1U +#define HAL_ATLANTIC_UTILS_FW_MSG_ARP 2U +#define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 3U +#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 4U +#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 5U +#define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 6U +#define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 7U +#define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 8U +#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 9U +#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 10U +#define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 13U // 0xd + +#define SMBUS_READ_REQUEST BIT(13) +#define SMBUS_WRITE_REQUEST BIT(14) +#define SMBUS_DEVICE_ID 0x50 + +enum hw_atl_fw2x_rate { + FW2X_RATE_100M = 0x20, + FW2X_RATE_1G = 0x100, + FW2X_RATE_2G5 = 0x200, + FW2X_RATE_5G = 0x400, + FW2X_RATE_10G = 0x800, +}; + +enum hw_atl_fw2x_caps_lo { + CAPS_LO_10BASET_HD = 0x00, + CAPS_LO_10BASET_FD, + CAPS_LO_100BASETX_HD, + CAPS_LO_100BASET4_HD, + CAPS_LO_100BASET2_HD, + CAPS_LO_100BASETX_FD, + CAPS_LO_100BASET2_FD, + CAPS_LO_1000BASET_HD, + CAPS_LO_1000BASET_FD, + CAPS_LO_2P5GBASET_FD, + CAPS_LO_5GBASET_FD, + CAPS_LO_10GBASET_FD, +}; + +enum hw_atl_fw2x_caps_hi { + CAPS_HI_RESERVED1 = 0x00, + CAPS_HI_10BASET_EEE, + CAPS_HI_RESERVED2, + CAPS_HI_PAUSE, + CAPS_HI_ASYMMETRIC_PAUSE, + CAPS_HI_100BASETX_EEE, + CAPS_HI_RESERVED3, + CAPS_HI_RESERVED4, + CAPS_HI_1000BASET_FD_EEE, + CAPS_HI_2P5GBASET_FD_EEE, + CAPS_HI_5GBASET_FD_EEE, + CAPS_HI_10GBASET_FD_EEE, + CAPS_HI_RESERVED5, + CAPS_HI_RESERVED6, + CAPS_HI_RESERVED7, + CAPS_HI_RESERVED8, + CAPS_HI_RESERVED9, + CAPS_HI_CABLE_DIAG, + CAPS_HI_TEMPERATURE, + CAPS_HI_DOWNSHIFT, + CAPS_HI_PTP_AVB_EN, + CAPS_HI_MEDIA_DETECT, + CAPS_HI_LINK_DROP, + CAPS_HI_SLEEP_PROXY, + CAPS_HI_WOL, + CAPS_HI_MAC_STOP, + CAPS_HI_EXT_LOOPBACK, + CAPS_HI_INT_LOOPBACK, + CAPS_HI_EFUSE_AGENT, + CAPS_HI_WOL_TIMER, + CAPS_HI_STATISTICS, + CAPS_HI_TRANSACTION_ID, +}; + +struct aq_hw_s; +struct aq_fw_ops; +struct aq_hw_link_status_s; + +int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops); + +int hw_atl_utils_soft_reset(struct aq_hw_s *self); + +void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p); + +int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox_header *pmbox); + +void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox *pmbox); + +void hw_atl_utils_mpi_set(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state, + u32 speed); + +int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self); + +unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps); + +unsigned int hw_atl_utils_hw_get_reg_length(void); + +int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, + u32 *regs_buff); + +int hw_atl_utils_hw_set_power(struct aq_hw_s *self, + unsigned int power_state); + +int hw_atl_utils_hw_deinit(struct aq_hw_s *self); + +int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version); + +int hw_atl_utils_update_stats(struct aq_hw_s *self); + +struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self); + +int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, + u32 *p, u32 cnt); + +int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, + u32 cnt); + +int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac); + +int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size); + +int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, + struct hw_aq_atl_utils_fw_rpc **rpc); + +extern const struct aq_fw_ops aq_fw_1x_ops; +extern const struct aq_fw_ops aq_fw_2x_ops; + +#endif /* HW_ATL_UTILS_H */ diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c b/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c new file mode 100644 index 000000000000..6841d9bce39c --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for + * Atlantic hardware abstraction layer. + */ + +#include +#include "../atl_hw_regs.h" + +#include "../atl_types.h" +#include "hw_atl_utils.h" +#include "hw_atl_llh.h" + +#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364 +#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360 +#define HW_ATL_FW2X_MPI_RPC_ADDR 0x334 + +#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368 +#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C +#define HW_ATL_FW2X_MPI_LED_ADDR 0x31c + +#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370 +#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374 + +#define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY) +#define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL) + +#define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE) +#define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE) +#define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE) +#define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE) + +#define HAL_ATLANTIC_WOL_FILTERS_COUNT 8 +#define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E + +#define HW_ATL_FW_FEATURE_EEPROM 0x03010025 +#define HW_ATL_FW_FEATURE_LED 0x03010026 + +struct fw2x_msg_wol_pattern { + u8 mask[16]; + u32 crc; +} __attribute__((__packed__)); + +struct fw2x_msg_wol { + u32 msg_id; + u8 hw_addr[6]; + u8 magic_packet_enabled; + u8 filter_count; + struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT]; + u8 link_up_enabled; + u8 link_down_enabled; + u16 reserved; + u32 link_up_timeout; + u32 link_down_timeout; +} __attribute__((__packed__)); + +static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed); +static int aq_fw2x_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state); + +static int aq_fw2x_init(struct aq_hw_s *self) +{ + int err = 0; + + /* check 10 times by 1ms */ + AQ_HW_WAIT_FOR(0U != (self->mbox_addr = + aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)), + 1000U, 10U); + AQ_HW_WAIT_FOR(0U != (self->rpc_addr = + aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)), + 1000U, 100U); + return err; +} + +static int aq_fw2x_deinit(struct aq_hw_s *self) +{ + int err = aq_fw2x_set_link_speed(self, 0); + + if (!err) + err = aq_fw2x_set_state(self, MPI_DEINIT); + + return err; +} + +static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed) +{ + enum hw_atl_fw2x_rate rate = 0; + + if (speed & AQ_NIC_RATE_10G) + rate |= FW2X_RATE_10G; + + if (speed & AQ_NIC_RATE_5G) + rate |= FW2X_RATE_5G; + + if (speed & AQ_NIC_RATE_5G5R) + rate |= FW2X_RATE_5G; + + if (speed & AQ_NIC_RATE_2G5) + rate |= FW2X_RATE_2G5; + + if (speed & AQ_NIC_RATE_1G) + rate |= FW2X_RATE_1G; + + if (speed & AQ_NIC_RATE_100M) + rate |= FW2X_RATE_100M; + + return rate; +} + +static u32 fw2x_to_eee_mask(u32 speed) +{ + u32 rate = 0; + + if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK) + rate |= AQ_NIC_RATE_EEE_10G; + + if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK) + rate |= AQ_NIC_RATE_EEE_5G; + + if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK) + rate |= AQ_NIC_RATE_EEE_2G5; + + if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK) + rate |= AQ_NIC_RATE_EEE_1G; + + return rate; +} + +static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed) +{ + u32 val = link_speed_mask_2fw2x_ratemask(speed); + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val); + + return 0; +} + +static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state) +{ + if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX) + *mpi_state |= BIT(CAPS_HI_PAUSE); + else + *mpi_state &= ~BIT(CAPS_HI_PAUSE); + + if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX) + *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE); + else + *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE); +} + +static int aq_fw2x_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state) +{ + u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + + switch (state) { + case MPI_INIT: + mpi_state &= ~BIT(CAPS_HI_LINK_DROP); + aq_fw2x_set_mpi_flow_control(self, &mpi_state); + break; + case MPI_DEINIT: + mpi_state |= BIT(CAPS_HI_LINK_DROP); + break; + case MPI_RESET: + case MPI_POWER: + /* No actions */ + break; + } + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state); + return 0; +} + +static int aq_fw2x_update_link_status(struct aq_hw_s *self) +{ + u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR); + u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G | + FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G); + struct aq_hw_link_status_s *link_status = &self->aq_link_status; + + if (speed) { + if (speed & FW2X_RATE_10G) + link_status->mbps = 10000; + else if (speed & FW2X_RATE_5G) + link_status->mbps = 5000; + else if (speed & FW2X_RATE_2G5) + link_status->mbps = 2500; + else if (speed & FW2X_RATE_1G) + link_status->mbps = 1000; + else if (speed & FW2X_RATE_100M) + link_status->mbps = 100; + else + link_status->mbps = 10000; + } else { + link_status->mbps = 0; + } + + return 0; +} + +static +int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac) +{ + int err = 0; + u32 h = 0U; + u32 l = 0U; + u32 mac_addr[2] = { 0 }; + u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR); + + if (efuse_addr != 0) { + err = hw_atl_utils_fw_downld_dwords(self, + efuse_addr + (40U * 4U), + mac_addr, + ARRAY_SIZE(mac_addr)); + if (err) + return err; + mac_addr[0] = rte_constant_bswap32(mac_addr[0]); + mac_addr[1] = rte_constant_bswap32(mac_addr[1]); + } + + ether_addr_copy((struct ether_addr *)mac_addr, + (struct ether_addr *)mac); + + if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) { + unsigned int rnd = (uint32_t)rte_rand(); + + //get_random_bytes(&rnd, sizeof(unsigned int)); + + l = 0xE3000000U + | (0xFFFFU & rnd) + | (0x00 << 16); + h = 0x8001300EU; + + mac[5] = (u8)(0xFFU & l); + l >>= 8; + mac[4] = (u8)(0xFFU & l); + l >>= 8; + mac[3] = (u8)(0xFFU & l); + l >>= 8; + mac[2] = (u8)(0xFFU & l); + mac[1] = (u8)(0xFFU & h); + h >>= 8; + mac[0] = (u8)(0xFFU & h); + } + return err; +} + +static int aq_fw2x_update_stats(struct aq_hw_s *self) +{ + int err = 0; + u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS); + + /* Toggle statistics bit for FW to update */ + mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS); + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + /* Wait FW to report back */ + AQ_HW_WAIT_FOR(orig_stats_val != + (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + BIT(CAPS_HI_STATISTICS)), + 1U, 10000U); + if (err) + return err; + + return hw_atl_utils_update_stats(self); +} + +static int aq_fw2x_get_temp(struct aq_hw_s *self, int *temp) +{ + int err = 0; + u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + u32 temp_val = mpi_opts & BIT(CAPS_HI_TEMPERATURE); + u32 temp_res; + + /* Toggle statistics bit for FW to 0x36C.18 (CAPS_HI_TEMPERATURE) */ + mpi_opts = mpi_opts ^ BIT(CAPS_HI_TEMPERATURE); + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + /* Wait FW to report back */ + AQ_HW_WAIT_FOR(temp_val != + (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + BIT(CAPS_HI_TEMPERATURE)), 1U, 10000U); + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr + + offsetof(struct hw_aq_atl_utils_mbox, info) + + offsetof(struct hw_aq_info, phy_temperature), + &temp_res, + sizeof(temp_res) / sizeof(u32)); + + if (err) + return err; + + *temp = temp_res * 100 / 256; + return 0; +} + +static int aq_fw2x_get_cable_len(struct aq_hw_s *self, int *cable_len) +{ + int err = 0; + u32 cable_len_res; + + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr + + offsetof(struct hw_aq_atl_utils_mbox, info) + + offsetof(struct hw_aq_info, phy_temperature), + &cable_len_res, + sizeof(cable_len_res) / sizeof(u32)); + + if (err) + return err; + + *cable_len = (cable_len_res >> 16) & 0xFF; + return 0; +} + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac) +{ + int err = 0; + struct hw_aq_atl_utils_fw_rpc *rpc = NULL; + struct offload_info *cfg = NULL; + unsigned int rpc_size = 0U; + u32 mpi_opts; + + rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg); + + err = hw_atl_utils_fw_rpc_wait(self, &rpc); + if (err < 0) + goto err_exit; + + memset(rpc, 0, rpc_size); + cfg = (struct offload_info *)(&rpc->msg_id + 1); + + memcpy(cfg->mac_addr, mac, ETH_ALEN); + cfg->len = sizeof(*cfg); + + /* Clear bit 0x36C.23 */ + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + mpi_opts &= ~HW_ATL_FW2X_CAP_SLEEP_PROXY; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + err = hw_atl_utils_fw_rpc_call(self, rpc_size); + if (err < 0) + goto err_exit; + + /* Set bit 0x36C.23 */ + mpi_opts |= HW_ATL_FW2X_CAP_SLEEP_PROXY; + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + HW_ATL_FW2X_CAP_SLEEP_PROXY), 1U, 10000U); +err_exit: + return err; +} + +static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac) +{ + int err = 0; + struct fw2x_msg_wol *msg = NULL; + u32 mpi_opts; + + struct hw_aq_atl_utils_fw_rpc *rpc = NULL; + + err = hw_atl_utils_fw_rpc_wait(self, &rpc); + if (err < 0) + goto err_exit; + + msg = (struct fw2x_msg_wol *)rpc; + + msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL; + msg->magic_packet_enabled = true; + memcpy(msg->hw_addr, mac, ETH_ALEN); + + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + mpi_opts &= ~(HW_ATL_FW2X_CAP_SLEEP_PROXY | HW_ATL_FW2X_CAP_WOL); + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg)); + if (err < 0) + goto err_exit; + + /* Set bit 0x36C.24 */ + mpi_opts |= HW_ATL_FW2X_CAP_WOL; + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + HW_ATL_FW2X_CAP_WOL), 1U, 10000U); +err_exit: + return err; +} + +static int aq_fw2x_set_power(struct aq_hw_s *self, + unsigned int power_state __rte_unused, + u8 *mac) +{ + int err = 0; + + if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) { + err = aq_fw2x_set_sleep_proxy(self, mac); + if (err < 0) + goto err_exit; + err = aq_fw2x_set_wol_params(self, mac); + if (err < 0) + goto err_exit; + } +err_exit: + return err; +} + +static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed) +{ + u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK | + HW_ATL_FW2X_CAP_EEE_2G5_MASK | HW_ATL_FW2X_CAP_EEE_5G_MASK | + HW_ATL_FW2X_CAP_EEE_10G_MASK); + + if (speed & AQ_NIC_RATE_EEE_10G) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_10G_MASK; + + if (speed & AQ_NIC_RATE_EEE_5G) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_5G_MASK; + + if (speed & AQ_NIC_RATE_EEE_2G5) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_2G5_MASK; + + if (speed & AQ_NIC_RATE_EEE_1G) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_1G_MASK; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + return 0; +} + +static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate, + u32 *supported_rates) +{ + int err = 0; + u32 caps_hi; + u32 mpi_state; + + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr + + offsetof(struct hw_aq_atl_utils_mbox, info) + + offsetof(struct hw_aq_info, caps_hi), + &caps_hi, + sizeof(caps_hi) / sizeof(u32)); + + if (err) + return err; + + *supported_rates = fw2x_to_eee_mask(caps_hi); + + mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR); + *rate = fw2x_to_eee_mask(mpi_state); + + return err; +} + + + +static int aq_fw2x_set_flow_control(struct aq_hw_s *self) +{ + u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + + aq_fw2x_set_mpi_flow_control(self, &mpi_state); + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state); + + return 0; +} + +static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode) +{ + if (self->fw_ver_actual < HW_ATL_FW_FEATURE_LED) + return -EOPNOTSUPP; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode); + return 0; +} + +static int aq_fw2x_get_eeprom(struct aq_hw_s *self, u32 *data, u32 len) +{ + int err = 0; + struct smbus_read_request request; + u32 mpi_opts; + u32 result = 0; + + if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM) + return -EOPNOTSUPP; + + request.device_id = SMBUS_DEVICE_ID; + request.address = 0; + request.length = len; + + /* Write SMBUS request to cfg memory */ + err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr, + (u32 *)(void *)&request, + RTE_ALIGN(sizeof(request), sizeof(u32))); + + if (err < 0) + return err; + + /* Toggle 0x368.SMBUS_READ_REQUEST bit */ + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR); + mpi_opts ^= SMBUS_READ_REQUEST; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts); + + /* Wait until REQUEST_BIT matched in 0x370 */ + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) & + SMBUS_READ_REQUEST) == (mpi_opts & SMBUS_READ_REQUEST), + 10U, 10000U); + + if (err < 0) + return err; + + err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32), + &result, + RTE_ALIGN(sizeof(result), sizeof(u32))); + + if (err < 0) + return err; + + if (result == 0) { + err = hw_atl_utils_fw_downld_dwords(self, + self->rpc_addr + sizeof(u32) * 2, + data, + RTE_ALIGN(len, sizeof(u32))); + + if (err < 0) + return err; + } + + return 0; +} + + +static int aq_fw2x_set_eeprom(struct aq_hw_s *self, u32 *data, u32 len) +{ + struct smbus_write_request request; + u32 mpi_opts, result = 0; + int err = 0; + + if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM) + return -EOPNOTSUPP; + + request.device_id = SMBUS_DEVICE_ID; + request.address = 0; + request.length = len; + + /* Write SMBUS request to cfg memory */ + err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr, + (u32 *)(void *)&request, + RTE_ALIGN(sizeof(request), sizeof(u32))); + + if (err < 0) + return err; + + /* Write SMBUS data to cfg memory */ + err = hw_atl_utils_fw_upload_dwords(self, + self->rpc_addr + sizeof(request), + (u32 *)(void *)data, + RTE_ALIGN(len, sizeof(u32))); + + if (err < 0) + return err; + + /* Toggle 0x368.SMBUS_WRITE_REQUEST bit */ + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR); + mpi_opts ^= SMBUS_WRITE_REQUEST; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts); + + /* Wait until REQUEST_BIT matched in 0x370 */ + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) & + SMBUS_WRITE_REQUEST) == (mpi_opts & SMBUS_WRITE_REQUEST), + 10U, 10000U); + + if (err < 0) + return err; + + /* Read status of write operation */ + err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32), + &result, + RTE_ALIGN(sizeof(result), sizeof(u32))); + + if (err < 0) + return err; + + return 0; +} + +const struct aq_fw_ops aq_fw_2x_ops = { + .init = aq_fw2x_init, + .deinit = aq_fw2x_deinit, + .reset = NULL, + .get_mac_permanent = aq_fw2x_get_mac_permanent, + .set_link_speed = aq_fw2x_set_link_speed, + .set_state = aq_fw2x_set_state, + .update_link_status = aq_fw2x_update_link_status, + .update_stats = aq_fw2x_update_stats, + .set_power = aq_fw2x_set_power, + .get_temp = aq_fw2x_get_temp, + .get_cable_len = aq_fw2x_get_cable_len, + .set_eee_rate = aq_fw2x_set_eee_rate, + .get_eee_rate = aq_fw2x_get_eee_rate, + .set_flow_control = aq_fw2x_set_flow_control, + .led_control = aq_fw2x_led_control, + .get_eeprom = aq_fw2x_get_eeprom, + .set_eeprom = aq_fw2x_set_eeprom, +}; diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index 055342ec9db7..b05c97773541 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -5,4 +5,6 @@ sources = files( 'atl_ethdev.c', 'atl_hw_regs.c', 'hw_atl/hw_atl_llh.c', + 'hw_atl/hw_atl_utils_fw2x.c', + 'hw_atl/hw_atl_utils.c', ) From patchwork Fri Oct 12 11:09:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46701 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A93681B581; Fri, 12 Oct 2018 13:09:23 +0200 (CEST) Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720080.outbound.protection.outlook.com [40.107.72.80]) by dpdk.org (Postfix) with ESMTP id 3A80D1B56A for ; Fri, 12 Oct 2018 13:09:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qfAPQtlBuzY+I1mYxN2l9mqzLXEQOdko1SL9VDN7XXE=; b=ETzXV2vqvNNywHeieOlbdqAgeQtbkTiKKLM5UNrsmx3/mU8CwPIKA91X4x1UcxIiDdcmctfVC7VdwFjoBqE0KQ/68ZyHNpDPu5vQs4YO3qJ/Cg0GPjOfaVkequAC0bKizkzflyyYBawEntK3LHWV30cKJ8Z8mjEs+7CDDDVhW3U= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:18 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:17 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" , Pavel Belous Thread-Topic: [PATCH v6 06/22] net/atlantic: add b0 hardware layer Thread-Index: AQHUYhwEqksI5+qvrk2lr+zGPRD2JQ== Date: Fri, 12 Oct 2018 11:09:17 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:rvSaNT4Tu4gdfPqvK3Rk9U9PsqwzR3snq7ZJOf7/3A1pfutnbCjDqhRgOl6ydzNB3e+P77RVCaiYFoYt1Oh1YyjKebNOouhiIgjjp3NWO4p6qqMoUkDxl9ZN0zPh3w51fjWZLSbd2KfL1AgR716TDjzkLSJIKpjRvpQ/4Eik8Ah4umcuz3gKKMFP4V01Mo1sRpEGLJB8xDj50vGQJx3o2avug0gEMr8PREyYnJa2LY0M4r8TG9ThPowES0uOsCvuyubkSNxmhRiPyxtjjIioKXfaSrmgHDK/SJ3vrhWMkIGlg9lgw2JQDfNL7QEtZYS7XlCHnSQ4Xrc1qGzTxzq74SXiydm261A5/VdkQnR7ZM6K+3Z6pAnyu/COI1KuaUKxYIJbA+Lj59BO1dbtJrk3FiyMq0dBmcKtqd9y3M5tU+MZsnE6OaLkCdAoK1SpIVMfI9KXBt2lswTdSJuwLK/qcpFWyKV6Lzmm2Bf6msXJp+M=; 5:nZ8WM8GUODdOgABbzv8pTqdZIzOLKD0ySOJgsRe/VPlzK9uRCqWwOfhrIXrHK3E82wi8pPv7sfIn7UtWgC1ATIBN8bD0eurbEBaz+SuIbGehMP+ZnpQbvqJUoFRQNfnu5qtzPtVCXTbw/QMLGKds3kVhvvJvzUKzACLLW525JpE=; 7:xfWMiPqKqddS5ZNOR4PoCFUHVna59QBshFAseHiZvNciZ8iWvfGe9pUYOwCDXh8yva7sHyEDN23Erw3DHLJ9nBq4y8FkJAyIQrdyuoE2brApDdCf99fn40AX+MBeQ+INw005eszEeoahunGjsjq2Bm7bb0htVbD6jSVfoDxlYAxsfl/Q8ebDwXO6M9CbjxhEDW+slbaK0SG5qY/ozwNgK9jqjhG+J4xtTXIiBr/GFtbRT32JTgZ+4V2yEdvYKLQw x-ms-office365-filtering-correlation-id: 9b80262a-1ec1-45fc-38e6-08d630332683 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(4744004)(446003)(486006)(256004)(118296001)(186003)(105586002)(107886003)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(53946003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(575784001)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: QtSICTDiABfeiCe66BWZ1pIz5xk8rLXMym7oytx8xAGa+pxBmC2IDbheVKw+lh87NxkcuGGDD+GFeLTDyIHlGclPgd7VE86s+CMlehaHjN1Nv4mOKS24T53dGpAq9Yrv8qVnZrY4y3rajhki4f4n4n0NnW4JpdJwWJjilWqxuibHCe8prZ+y3ibbNrURoSyo4ecqZqwZ5VXrhuBpmU085BsZNqGKyoQPWeUat+T0PQZIW3JO2Hbx/lpkknVxIa99Sv3SyDnzDN9nHNCcoDH1I832rUxXc+MMXTUWuZ5PZqbuslBJKw4+lWVVwTy4cVKqV+1Uui09oPV0gCBdDpU8ulh6TQ5NW+OF9mmcjYcCB3U= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9b80262a-1ec1-45fc-38e6-08d630332683 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:17.6861 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 06/22] net/atlantic: add b0 hardware layer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is hw_atl logic layer derived from linux atlantic driver. It contains RX/TX hardware initialization sequences, various hw configuration. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 1 + drivers/net/atlantic/atl_types.h | 15 +- drivers/net/atlantic/hw_atl/hw_atl_b0.c | 510 +++++++++++++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_b0.h | 40 ++ drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h | 145 +++++++ drivers/net/atlantic/meson.build | 1 + 6 files changed, 711 insertions(+), 1 deletion(-) create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.c create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.h create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index a291053b5ab7..91306d71ba97 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -29,5 +29,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils_fw2x.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_b0.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index af24da3a5a54..c9ebbf4e91d8 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -9,7 +9,7 @@ #include #include #include - +#include typedef uint8_t u8; typedef int8_t s8; @@ -22,6 +22,7 @@ typedef uint64_t u64; #define min(a, b) RTE_MIN(a, b) #define max(a, b) RTE_MAX(a, b) +#include "hw_atl/hw_atl_b0_internal.h" #include "hw_atl/hw_atl_utils.h" struct aq_hw_link_status_s { @@ -50,8 +51,18 @@ struct aq_stats_s { u64 dma_oct_tc; }; +struct aq_rss_parameters { + u16 base_cpu_number; + u16 indirection_table_size; + u16 hash_secret_key_size; + u32 hash_secret_key[HW_ATL_B0_RSS_HASHKEY_BITS / 8]; + u8 indirection_table[HW_ATL_B0_RSS_REDIRECTION_MAX]; +}; + struct aq_hw_cfg_s { bool is_lro; + bool is_rss; + unsigned int num_rss_queues; int wol; int link_speed_msk; @@ -60,6 +71,8 @@ struct aq_hw_cfg_s { unsigned int vecs; uint32_t flow_control; + + struct aq_rss_parameters aq_rss; }; struct aq_hw_s { diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/atlantic/hw_atl/hw_atl_b0.c new file mode 100644 index 000000000000..9400e0edb999 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.c @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */ + +#include "../atl_types.h" +#include "hw_atl_b0.h" + +#include "../atl_hw_regs.h" +#include "hw_atl_utils.h" +#include "hw_atl_llh.h" +#include "hw_atl_b0_internal.h" +#include "hw_atl_llh_internal.h" +#include "../atl_logs.h" + +int hw_atl_b0_hw_reset(struct aq_hw_s *self) +{ + int err = 0; + + err = hw_atl_utils_soft_reset(self); + if (err) + return err; + + self->aq_fw_ops->set_state(self, MPI_RESET); + + return err; +} + +static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self) +{ + u32 tc = 0U; + u32 buff_size = 0U; + unsigned int i_priority = 0U; + bool is_rx_flow_control = false; + + /* TPS Descriptor rate init */ + hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); + hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); + + /* TPS VM init */ + hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); + + /* TPS TC credits init */ + hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); + hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U); + + hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U); + hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U); + hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U); + hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U); + + /* Tx buf size */ + buff_size = HW_ATL_B0_TXBUF_MAX; + + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc); + hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, + (buff_size * + (1024 / 32U) * 66U) / + 100U, tc); + hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, + (buff_size * + (1024 / 32U) * 50U) / + 100U, tc); + + /* QoS Rx buf size per TC */ + tc = 0; + is_rx_flow_control = 0; + buff_size = HW_ATL_B0_RXBUF_MAX; + + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc); + hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, + (buff_size * + (1024U / 32U) * 66U) / + 100U, tc); + hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, + (buff_size * + (1024U / 32U) * 50U) / + 100U, tc); + hw_atl_rpb_rx_xoff_en_per_tc_set(self, + is_rx_flow_control ? 1U : 0U, + tc); + + /* QoS 802.1p priority -> TC mapping */ + for (i_priority = 8U; i_priority--;) + hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U); + + return aq_hw_err_from_flags(self); +} + +/* calc hash only in IPv4 header, regardless of presence of TCP */ +#define pif_rpf_rss_ipv4_hdr_only_i (1 << 4) +/* calc hash only if TCP header and IPv4 */ +#define pif_rpf_rss_ipv4_tcp_hdr_only_i (1 << 3) +/* calc hash only in IPv6 header, regardless of presence of TCP */ +#define pif_rpf_rss_ipv6_hdr_only_i (1 << 2) +/* calc hash only if TCP header and IPv4 */ +#define pif_rpf_rss_ipv6_tcp_hdr_only_i (1 << 1) +/* bug 5124 - rss hashing types - FIXME */ +#define pif_rpf_rss_dont_use_udp_i (1 << 0) + +static int hw_atl_b0_hw_rss_hash_type_set(struct aq_hw_s *self) +{ + /* misc */ + unsigned int control_reg_val = + IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U; + + /* RSS hash type set for IP/TCP */ + control_reg_val |= pif_rpf_rss_ipv4_hdr_only_i;//0x1EU; + + aq_hw_write_reg(self, 0x5040U, control_reg_val); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params) +{ + struct aq_hw_cfg_s *cfg = self->aq_nic_cfg; + int err = 0; + unsigned int i = 0U; + unsigned int addr = 0U; + + for (i = 10, addr = 0U; i--; ++addr) { + u32 key_data = cfg->is_rss ? + htonl(rss_params->hash_secret_key[i]) : 0U; + hw_atl_rpf_rss_key_wr_data_set(self, key_data); + hw_atl_rpf_rss_key_addr_set(self, addr); + hw_atl_rpf_rss_key_wr_en_set(self, 1U); + AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0, + 1000U, 10U); + if (err < 0) + goto err_exit; + } + + /* RSS Ring selection */ + hw_atl_reg_rx_flr_rss_control1set(self, + cfg->is_rss ? 0xB3333333U : 0x00000000U); + hw_atl_b0_hw_rss_hash_type_set(self); + + err = aq_hw_err_from_flags(self); + +err_exit: + return err; +} + + +int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params) +{ + u8 *indirection_table = rss_params->indirection_table; + u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues); + u32 i = 0; + u32 addr = 0; + u32 val = 0; + u32 shift = 0; + int err = 0; + + for (i = 0; i < HW_ATL_B0_RSS_REDIRECTION_MAX; i++) { + val |= (u32)(indirection_table[i] % num_rss_queues) << shift; + shift += 3; + + if (shift < 16) + continue; + + hw_atl_rpf_rss_redir_tbl_wr_data_set(self, val & 0xffff); + hw_atl_rpf_rss_redir_tbl_addr_set(self, addr); + + hw_atl_rpf_rss_redir_wr_en_set(self, 1U); + AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0, + 1000U, 10U); + + if (err < 0) + goto err_exit; + + shift -= 16; + val >>= 16; + addr++; + } + +err_exit: + return err; +} + +static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self) + /*struct aq_nic_cfg_s *aq_nic_cfg)*/ +{ + unsigned int i; + + /* TX checksums offloads*/ + hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1); + hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1); + + /* RX checksums offloads*/ + hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1); + hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1); + + /* LSO offloads*/ + hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); + +/* LRO offloads */ + { + unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U : + ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U : + ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0)); + + for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++) + hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i); + + hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU); + hw_atl_rpo_lro_inactive_interval_set(self, 0); + hw_atl_rpo_lro_max_coalescing_interval_set(self, 2); + + hw_atl_rpo_lro_qsessions_lim_set(self, 1U); + + hw_atl_rpo_lro_total_desc_lim_set(self, 2U); + + hw_atl_rpo_lro_patch_optimization_en_set(self, 0U); + + hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U); + + hw_atl_rpo_lro_pkt_lim_set(self, 1U); + + hw_atl_rpo_lro_en_set(self, + self->aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U); + } + return aq_hw_err_from_flags(self); +} + +static +int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) +{ + /* Tx TC/RSS number config */ + hw_atl_rpb_tps_tx_tc_mode_set(self, 1U); + + hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); + + /* Tx interrupts */ + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U); + + /* misc */ + aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ? + 0x00010000U : 0x00000000U); + hw_atl_tdm_tx_dca_en_set(self, 0U); + hw_atl_tdm_tx_dca_mode_set(self, 0U); + + hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U); + + return aq_hw_err_from_flags(self); +} + +static +int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) +{ + struct aq_hw_cfg_s *cfg = self->aq_nic_cfg; + int i; + + /* Rx TC/RSS number config */ + hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U); /* 1: 4TC/8Queues */ + + /* Rx flow control */ + hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U); + + /* RSS Ring selection */ + hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ? + 0xB3333333U : 0x00000000U); + + /* Multicast filters */ + for (i = HW_ATL_B0_MAC_MAX; i--;) { + hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); + hw_atl_rpfl2unicast_flr_act_set(self, 1U, i); + } + + hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); + hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U); + + /* Vlan filters */ + hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U); + hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U); + + /* VLAN proimisc bu defauld */ + hw_atl_rpf_vlan_prom_mode_en_set(self, 1); + + /* Rx Interrupts */ + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U); + + hw_atl_b0_hw_rss_hash_type_set(self); + + hw_atl_rpfl2broadcast_flr_act_set(self, 1U); + hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); + + hw_atl_rdm_rx_dca_en_set(self, 0U); + hw_atl_rdm_rx_dca_mode_set(self, 0U); + + return aq_hw_err_from_flags(self); +} + +static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) +{ + int err = 0; + unsigned int h = 0U; + unsigned int l = 0U; + + if (!mac_addr) { + err = -EINVAL; + goto err_exit; + } + h = (mac_addr[0] << 8) | (mac_addr[1]); + l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + + hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC); + hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC); + hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC); + hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC); + + err = aq_hw_err_from_flags(self); + +err_exit: + return err; +} + +int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr) +{ + static u32 aq_hw_atl_igcr_table_[4][2] = { + { 0x20000080U, 0x20000080U }, /* AQ_IRQ_INVALID */ + { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */ + { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */ + { 0x200000A2U, 0x200000A6U } /* AQ_IRQ_MSIX */ + }; + + int err = 0; + u32 val; + + struct aq_hw_cfg_s *aq_nic_cfg = self->aq_nic_cfg; + + hw_atl_b0_hw_init_tx_path(self); + hw_atl_b0_hw_init_rx_path(self); + + hw_atl_b0_hw_mac_addr_set(self, mac_addr); + + self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); + self->aq_fw_ops->set_state(self, MPI_INIT); + + hw_atl_b0_hw_qos_set(self); + hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss); + hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); + + /* Force limit MRRS on RDM/TDM to 2K */ + val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR); + aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR, + (val & ~0x707) | 0x404); + + /* TX DMA total request limit. B0 hardware is not capable to + * handle more than (8K-MRRS) incoming DMA data. + * Value 24 in 256byte units + */ + aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24); + + /* Reset link status and read out initial hardware counters */ + self->aq_link_status.mbps = 0; + self->aq_fw_ops->update_stats(self); + + err = aq_hw_err_from_flags(self); + if (err < 0) + goto err_exit; + + /* Interrupts */ + hw_atl_reg_irq_glb_ctl_set(self, + aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type] + [(aq_nic_cfg->vecs > 1U) ? + 1 : 0]); + + hw_atl_itr_irq_auto_masklsw_set(self, 0xffffffff); + + /* Interrupts */ + hw_atl_reg_gen_irq_map_set(self, 0, 0); + hw_atl_reg_gen_irq_map_set(self, 0x80 | ATL_IRQ_CAUSE_LINK, 3); + + hw_atl_b0_hw_offload_set(self); + +err_exit: + return err; +} + +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index) +{ + hw_atl_tdm_tx_desc_en_set(self, 1, index); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index) +{ + hw_atl_rdm_rx_desc_en_set(self, 1, index); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_start(struct aq_hw_s *self) +{ + hw_atl_tpb_tx_buff_en_set(self, 1); + hw_atl_rpb_rx_buff_en_set(self, 1); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index) +{ + hw_atl_reg_tx_dma_desc_tail_ptr_set(self, tail, index); + return 0; +} + +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int buff_size, int cpu, int vec) +{ + u32 dma_desc_addr_lsw = (u32)base_addr; + u32 dma_desc_addr_msw = (u32)(base_addr >> 32); + + hw_atl_rdm_rx_desc_en_set(self, false, index); + + hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index); + + hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, + index); + + hw_atl_reg_rx_dma_desc_base_addressmswset(self, dma_desc_addr_msw, + index); + + hw_atl_rdm_rx_desc_len_set(self, size / 8U, index); + + hw_atl_rdm_rx_desc_data_buff_size_set(self, buff_size / 1024U, index); + + hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, index); + hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index); + hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, index); + + /* Rx ring set mode */ + + /* Mapping interrupt vector */ + hw_atl_itr_irq_map_rx_set(self, vec, index); + hw_atl_itr_irq_map_en_rx_set(self, true, index); + + hw_atl_rdm_cpu_id_set(self, cpu, index); + hw_atl_rdm_rx_desc_dca_en_set(self, 0U, index); + hw_atl_rdm_rx_head_dca_en_set(self, 0U, index); + hw_atl_rdm_rx_pld_dca_en_set(self, 0U, index); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int cpu, int vec) +{ + u32 dma_desc_lsw_addr = (u32)base_addr; + u32 dma_desc_msw_addr = (u32)(base_addr >> 32); + + hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, + index); + + hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, + index); + + hw_atl_tdm_tx_desc_len_set(self, size / 8U, index); + + hw_atl_b0_hw_tx_ring_tail_update(self, 0, index); + + /* Set Tx threshold */ + hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, index); + + /* Mapping interrupt vector */ + hw_atl_itr_irq_map_tx_set(self, vec, index); + hw_atl_itr_irq_map_en_tx_set(self, true, index); + + hw_atl_tdm_cpu_id_set(self, cpu, index); + hw_atl_tdm_tx_desc_dca_en_set(self, 0U, index); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) +{ + hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask)); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) +{ + hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask)); + hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask)); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) +{ + *mask = hw_atl_itr_irq_statuslsw_get(self); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index) +{ + hw_atl_tdm_tx_desc_en_set(self, 0U, index); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index) +{ + hw_atl_rdm_rx_desc_en_set(self, 0U, index); + return aq_hw_err_from_flags(self); +} + diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/atlantic/hw_atl/hw_atl_b0.h new file mode 100644 index 000000000000..06feb56c1620 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_b0.h: Declaration of abstract interface for Atlantic hardware + * specific functions. + */ + +#ifndef HW_ATL_B0_H +#define HW_ATL_B0_H + +int hw_atl_b0_hw_reset(struct aq_hw_s *self); +int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr); + +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int cpu, int vec); +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int buff_size, int cpu, int vec); + +int hw_atl_b0_hw_start(struct aq_hw_s *self); + +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index); +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index); + + +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index); +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index); + + +int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index); + +int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params); +int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params); + +int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask); +int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask); +int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask); + +#endif /* HW_ATL_B0_H */ diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h new file mode 100644 index 000000000000..48152eada731 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific + * constants. + */ + +#ifndef HW_ATL_B0_INTERNAL_H +#define HW_ATL_B0_INTERNAL_H + + +#define HW_ATL_B0_MTU_JUMBO 16352U +#define HW_ATL_B0_MTU 1514U + +#define HW_ATL_B0_TX_RINGS 4U +#define HW_ATL_B0_RX_RINGS 4U + +#define HW_ATL_B0_RINGS_MAX 32U +#define HW_ATL_B0_TXD_SIZE (16U) +#define HW_ATL_B0_RXD_SIZE (16U) + +#define HW_ATL_B0_MAC 0U +#define HW_ATL_B0_MAC_MIN 1U +#define HW_ATL_B0_MAC_MAX 33U + +/* Maximum supported VLAN filters */ +#define HW_ATL_B0_MAX_VLAN_IDS 16 + +/* UCAST/MCAST filters */ +#define HW_ATL_B0_UCAST_FILTERS_MAX 38 +#define HW_ATL_B0_MCAST_FILTERS_MAX 8 + +/* interrupts */ +#define HW_ATL_B0_ERR_INT 8U +#define HW_ATL_B0_INT_MASK (0xFFFFFFFFU) + +#define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000) +#define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000) +#define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000) + +#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001) +#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002) +#define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0) +#define HW_ATL_B0_TXD_CTL_DD (0x00100000) +#define HW_ATL_B0_TXD_CTL_EOP (0x00200000) + +#define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000) + +#define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22) +#define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23) +#define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24) +#define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25) +#define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26) +#define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27) +#define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28) + +#define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21) +#define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22) + +#define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U +#define HW_ATL_B0_MPI_STATE_ADR 0x036CU + +#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU +#define HW_ATL_B0_MPI_SPEED_SHIFT 16U + +#define HW_ATL_B0_TXBUF_MAX 160U +#define HW_ATL_B0_RXBUF_MAX 320U + +#define HW_ATL_B0_RXD_BUF_SIZE_MAX (16 * 1024) + +#define HW_ATL_B0_RSS_REDIRECTION_MAX 64U +#define HW_ATL_B0_RSS_REDIRECTION_BITS 3U +#define HW_ATL_B0_RSS_HASHKEY_BITS 320U + +#define HW_ATL_B0_TCRSS_4_8 1 +#define HW_ATL_B0_TC_MAX 1U +#define HW_ATL_B0_RSS_MAX 8U + +#define HW_ATL_B0_LRO_RXD_MAX 2U +#define HW_ATL_B0_RS_SLIP_ENABLED 0U + +/* (256k -1(max pay_len) - 54(header)) */ +#define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U + +/* (256k -1(max pay_len) - 74(header)) */ +#define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U + +#define HW_ATL_B0_CHIP_REVISION_B0 0xA0U +#define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU + +#define HW_ATL_B0_FW_SEMA_RAM 0x2U + +#define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00) +#define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000) + +#define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007) +#define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008) +#define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0) +#define HW_ATL_B0_TXC_CTL_CMD (0x00F00000) +#define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000) + +#define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */ +#define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */ +#define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00) +#define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000) + +#define HW_ATL_B0_RXD_DD (0x1) +#define HW_ATL_B0_RXD_NCEA0 (0x1) + +#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F) +#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0) +#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000) +#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000) +#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000) + +#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001) +#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002) +#define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C) +#define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004) +#define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008) +#define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010) +#define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0) +#define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000) + +#define L2_FILTER_ACTION_DISCARD (0x0) +#define L2_FILTER_ACTION_HOST (0x1) + +#define HW_ATL_B0_UCP_0X370_REG (0x370) + +#define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10) + +#define HW_ATL_INTR_MODER_MAX 0x1FF +#define HW_ATL_INTR_MODER_MIN 0xFF + +#define HW_ATL_B0_MIN_RXD \ + (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) +#define HW_ATL_B0_MIN_TXD \ + (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) + +#define HW_ATL_B0_MAX_RXD 8184U +#define HW_ATL_B0_MAX_TXD 8184U + +/* HW layer capabilities */ + +#endif /* HW_ATL_B0_INTERNAL_H */ diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index b05c97773541..a0ad8f088571 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -4,6 +4,7 @@ sources = files( 'atl_ethdev.c', 'atl_hw_regs.c', + 'hw_atl/hw_atl_b0.c', 'hw_atl/hw_atl_llh.c', 'hw_atl/hw_atl_utils_fw2x.c', 'hw_atl/hw_atl_utils.c', From patchwork Fri Oct 12 11:09:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46702 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 22B0A1B59F; Fri, 12 Oct 2018 13:09:26 +0200 (CEST) Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720067.outbound.protection.outlook.com [40.107.72.67]) by dpdk.org (Postfix) with ESMTP id 3E8521B56D for ; Fri, 12 Oct 2018 13:09:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7W4emC9LlU05VozK5DadBm9BmNL8i6g9FQ0BvrH7eJQ=; b=SC1J3qlgmVrhl1vgOs0xKxMPOCheyUhB8gPPvw0liyIDQC8Do6hZo8cKBkODBZgNaNH18oq9tJt8C+yXaehrXUWoPEDADlnp5PmOOXLOV7DA9+OOVXi6NZ4JCE2CisR4Sb/uiW60Kb5hPgLiq1t8b5KifpTKUNZxUvAQBx9NU6E= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:20 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:20 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 07/22] net/atlantic: configure rte device start/stop Thread-Index: AQHUYhwGbOn0mEMLCEW5j1OTsn6dRA== Date: Fri, 12 Oct 2018 11:09:20 +0000 Message-ID: <9a99afae180726da58f68bab92f25a472720fd8a.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:BsxcEHJiDdpZzqC1WAx4kMlzbw9n9OaSAyr/H7ellhjd10KGtpv0GQTpZG8SL6xWyw6b7PCb/aH3A0hcIvGfd2/j+4Ku/XPByX2lY0kdA6jgMJ2bKz10BjE6HrNSqBiMHrKuL/Oid/XmLHX5l1O0r8S3WLxjGRbVkLrdy3+i7SgGrsrSVcJ+b0l+XE3RYhzS1/vWFvGvsf6CnnW0OmuVVY9nLWMTp141dhxqMRaskHHeAWnuvIHhFtwoZ/DEkjFQz17WSdpnsx05Z0YdrbKcL5bFb6KL+T8rs7Jq0P0uolQFJtJTqLpp1kyQqQ3zhwfOvHmeUY2lLPTErlgGqVYhsOaqa0erMxpzWMjuFqyZkmGc1YJE96gV6Ffnw38IuXxDvlQuXrQqe6gLkhD1BPf8XtMnCujNltNPAdLrx8KoyT5utLwoBeR9RDtuGw5NBg+CEDvBAWe3BkeX82+BpOQSHM98u4AkRX//3YX7sHaBbj0=; 5:IQDQuc+p27owW2Kk1fedU4z5puo8EFvxA1q5Xy6Vat68M4SX6ajKOxoSmdPOmlqSb0f2b/L6j5zJ2Obl212RsNzrubiNxR3U+X+MCgxXO+qkcg/Zy/mvBMlcjs8IMOxk4CsbYVeUK4+MMPvAh6GZA4/x6FCZpUTBfL+lqpv3Aas=; 7:daqBoSh1odIkByfOudGryH/3wB0wGOxmGiWVOqVFfHLi2f+XrY9er4BCuXyA4F3DTbcgfw+7xW6EyI/sqHAEVbmvW28rcFFgqqs3KySkElSfxvNdg8tBigQZFDU2uS9z4B1CkOMxR4aYxdvpP5DI54ZmhIaYW9xo3iBh9nNMGVtRXgK8ly8YfmVEg/7QN1R3k075xUYtF6TA+qhwXby7hAs2fH30UK0Z9NitdiX6BMpzz1bCF1VPlq09tPeiZwLU x-ms-office365-filtering-correlation-id: 76f1ffa4-0558-4e50-28a4-08d630332815 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(1496009)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(575784001)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 0PdKjWf8NimBZUYJLSz5ougJk4x0eKxsXaOFHVC6Z4b2OLqv6Y1wy7uzbs3FNfCAH3/CSYwAsAtOuuqwKIScmdMcRnvQgEm5b6i2kv//kzgZ70FUWGfxSblvpzJJcGucat+i5ZYlzcPJR64HuBTR36P87KuvowWoC2zg+/pmCaJlj3Piz6bbK8aXbB8wHWVsx5XO7FrwvHiZbXtUGZuTB6pxygL9kHO8ailYeA6ZJIVD7kEcjep8Kv2NnE4eU9/pLN21FbFRHiSTfu3mnBVlZhNFZLy76S4/cC+JOLxDqgXLMREWFk6shIPe4OE6HVlj5Dc0Vc1XLXscuoWahHbWxAwDRQWoSPNDgHmbmwNTAE8= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 76f1ffa4-0558-4e50-28a4-08d630332815 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:20.1961 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 07/22] net/atlantic: configure rte device start/stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Start, stop and reset are all done via hw_atl layer. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 1 + drivers/net/atlantic/atl_ethdev.c | 140 ++++++++++++++++++++++++++++++++-- drivers/net/atlantic/atl_ethdev.h | 9 +++ drivers/net/atlantic/atl_types.h | 4 + 4 files changed, 147 insertions(+), 7 deletions(-) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index e6c5676acf7a..1b9cbf95077f 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -4,6 +4,7 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +FW version = Y Linux UIO = Y ARMv8 = Y x86-32 = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 5b05ca180bc7..d756ad4c8b99 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -6,6 +6,11 @@ #include "atl_ethdev.h" #include "atl_common.h" +#include "atl_hw_regs.h" +#include "atl_logs.h" +#include "hw_atl/hw_atl_llh.h" +#include "hw_atl/hw_atl_b0.h" +#include "hw_atl/hw_atl_b0_internal.h" static int eth_atl_dev_init(struct rte_eth_dev *eth_dev); static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev); @@ -16,6 +21,13 @@ static void atl_dev_stop(struct rte_eth_dev *dev); static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); +static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, + size_t fw_size); + +static void atl_dev_info_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *dev_info); + + static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); @@ -69,26 +81,83 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_stop = atl_dev_stop, .dev_close = atl_dev_close, .dev_reset = atl_dev_reset, - .dev_infos_get = atl_dev_info_get, + + .fw_version_get = atl_fw_version_get, + .dev_infos_get = atl_dev_info_get, }; +static inline int32_t +atl_reset_hw(struct aq_hw_s *hw) +{ + return hw_atl_b0_hw_reset(hw); +} + static int eth_atl_dev_init(struct rte_eth_dev *eth_dev) { + struct atl_adapter *adapter = + (struct atl_adapter *)eth_dev->data->dev_private; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + int err = 0; + + PMD_INIT_FUNC_TRACE(); + eth_dev->dev_ops = &atl_eth_dev_ops; + /* For secondary processes, the primary process has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + /* Vendor and Device ID need to be set before init of shared code */ + hw->device_id = pci_dev->id.device_id; + hw->vendor_id = pci_dev->id.vendor_id; + hw->mmio = (void *)pci_dev->mem_resource[0].addr; + + /* Hardware configuration - hardcode */ + adapter->hw_cfg.is_lro = false; + adapter->hw_cfg.wol = false; + + hw->aq_nic_cfg = &adapter->hw_cfg; + /* Allocate memory for storing MAC addresses */ eth_dev->data->mac_addrs = rte_zmalloc("atlantic", ETHER_ADDR_LEN, 0); - if (eth_dev->data->mac_addrs == NULL) + if (eth_dev->data->mac_addrs == NULL) { + PMD_INIT_LOG(ERR, "MAC Malloc failed"); return -ENOMEM; + } - return 0; + err = hw_atl_utils_initfw(hw, &hw->aq_fw_ops); + if (err) + return err; + + /* Copy the permanent MAC address */ + if (hw->aq_fw_ops->get_mac_permanent(hw, + eth_dev->data->mac_addrs->addr_bytes) != 0) + return -EINVAL; + + return err; } static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) { + struct aq_hw_s *hw; + + PMD_INIT_FUNC_TRACE(); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return -EPERM; + + hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + + if (hw->adapter_stopped == 0) + atl_dev_close(eth_dev); + + eth_dev->dev_ops = NULL; + rte_free(eth_dev->data->mac_addrs); + eth_dev->data->mac_addrs = NULL; return 0; } @@ -118,25 +187,60 @@ atl_dev_configure(struct rte_eth_dev *dev __rte_unused) * It returns 0 on success. */ static int -atl_dev_start(struct rte_eth_dev *dev __rte_unused) +atl_dev_start(struct rte_eth_dev *dev) { - return 0; + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int status; + int err; + + PMD_INIT_FUNC_TRACE(); + + /* set adapter started */ + hw->adapter_stopped = 0; + + /* reinitialize adapter + * this calls reset and start + */ + status = atl_reset_hw(hw); + if (status != 0) + return -EIO; + + err = hw_atl_b0_hw_init(hw, dev->data->mac_addrs->addr_bytes); + + hw_atl_b0_hw_start(hw); + + PMD_INIT_LOG(DEBUG, "FW version: %u.%u.%u", + hw->fw_ver_actual >> 24, + (hw->fw_ver_actual >> 16) & 0xFF, + hw->fw_ver_actual & 0xFFFF); + PMD_INIT_LOG(DEBUG, "Driver version: %s", ATL_PMD_DRIVER_VERSION); + + return err; } /* * Stop device: disable rx and tx functions to allow for reconfiguring. */ static void -atl_dev_stop(struct rte_eth_dev *dev __rte_unused) +atl_dev_stop(struct rte_eth_dev *dev) { + struct aq_hw_s *hw = + ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + /* reset the NIC */ + atl_reset_hw(hw); + hw->adapter_stopped = 1; } /* * Reset and stop device. */ static void -atl_dev_close(struct rte_eth_dev *dev __rte_unused) +atl_dev_close(struct rte_eth_dev *dev) { + PMD_INIT_FUNC_TRACE(); + + atl_dev_stop(dev); } static int @@ -153,6 +257,28 @@ atl_dev_reset(struct rte_eth_dev *dev) return ret; } +static int +atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t fw_ver = 0; + unsigned int ret = 0; + + ret = hw_atl_utils_get_fw_version(hw, &fw_ver); + if (ret) + return -EIO; + + ret = snprintf(fw_version, fw_size, "%u.%u.%u", fw_ver >> 24, + (fw_ver >> 16) & 0xFFU, fw_ver & 0xFFFFU); + + ret += 1; /* add string null-terminator */ + + if (fw_size < ret) + return ret; + + return 0; +} + static void atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 622806837379..c0cc5475a091 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -6,10 +6,19 @@ #define _ATLANTIC_ETHDEV_H_ #include #include "rte_ethdev.h" + +#include "atl_types.h" +#include "hw_atl/hw_atl_utils.h" + +#define ATL_DEV_PRIVATE_TO_HW(adapter) \ + (&((struct atl_adapter *)adapter)->hw) + /* * Structure to store private data for each driver instance (for each port). */ struct atl_adapter { + struct aq_hw_s hw; + struct aq_hw_cfg_s hw_cfg; }; #endif /* _ATLANTIC_ETHDEV_H_ */ diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index c9ebbf4e91d8..37ad43a110f0 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -76,6 +76,10 @@ struct aq_hw_cfg_s { }; struct aq_hw_s { + u16 device_id; + u16 vendor_id; + bool adapter_stopped; + u8 rbl_enabled:1; struct aq_hw_cfg_s *aq_nic_cfg; const struct aq_fw_ops *aq_fw_ops; From patchwork Fri Oct 12 11:09:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46703 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E790F1B5A5; Fri, 12 Oct 2018 13:09:27 +0200 (CEST) Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720051.outbound.protection.outlook.com [40.107.72.51]) by dpdk.org (Postfix) with ESMTP id EE3D01B589 for ; Fri, 12 Oct 2018 13:09:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RYT6LmAdvUU/RpsMBSWzEtSAwvAl9ucjpkcsw9PwurQ=; b=OT6WwO9ESSHWzXtbGEnHyt/G0OyQhATAICjKXHhPfEOJlg0sRuJAyWB6cbOzv4Uj5AtK52TgckPFmE7FpxuhNEfMqANmnvVL3diZ5Z/Fo1j42iXW+FVO43uNTLbP/MucHIt8NZSoSlThQvFqg4BXIBKgIAeeuk0jyYmmhJb06rI= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:22 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:22 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 08/22] net/atlantic: implement core logic for Tx/Rx Thread-Index: AQHUYhwH8y1Xq9SRGkiVcyraeXDHLA== Date: Fri, 12 Oct 2018 11:09:22 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:0L9CF9X5AEtqixaHY6RS3ZCVGWfTuYPCF4tRzBiOU8m01UlixyAdlOaneVxaifKB4itJ/yoGJGFe5kkKeP0M6HwUyl6h/GK+mIP7v+IOvizpyM6zKSCUYxyA+DmbwmGjRZLqkR2DDg22Nz6cV5QCiXLW8tz5lMLxQUlmL9qTb6EozFW0z9TfmXt1JhDoTnlbfZnHbcD/Fty61NDZq1hKzkk4ABmbJIiXbyYYyTKpWAGcDIBeDkq0S8sxzNJuzHvNvtXzjcTUoVY7CjPJ7PkaY7mbLbZd6ao4NQJMfEROTfGrUmsk/jT/ITSf8b87YcmQKauVlxnLTz+K/Wzdr4/I1W8+WSW4yrkFA6j+ZjogSIL6w8fgCEWBNyWbmt4znH4plkBmr4E+osL7GfsrCtS+WTQNDEX3Tmuqcf95p02GS5tmtjHeO7maN3TzR+1otUiBWvQCsyCoplXkAMeUasyHmmYfRZXOHzH3fUzgXJ100yI=; 5:ALFouJoXOAUOjYDdgIR4iCYMGIrNeAJ8s9c8g8J27A1LyhP4uBDcvwLPV6a/Z45QV+tBa70UrvL1+OIxsL7GbT6KvUIiRj8aS6aaMBxVpNVygRtMfvaQ0jGjjrId4zZkcsCMOb5oJa61pJUkXPi+JY6GWNXfsWko6idrHUzecCM=; 7:fTDQdVrdlWnBrGAVWauAGs8I1wqWM/a7U32DMhhHDtWt+XBjmNgbKTnhVIDFB0JlN3718gQfoLWt2ZoCqpOfmtQ+IeHhVCCAKZmUDeN3Wrq8VzFmwN7rxS3Ec+QLnwXUARPsamx3+evnvEgEdtks5qaK5ZyAIs+TmyIGP07EcwKs8E4KewVsxN63+iq4oAU6V0cG6/kzPvihIsO6mBAtg7MLUPRxACjOf6yiPILMjNYle40gfI/jlmBrgLgF7070 x-ms-office365-filtering-correlation-id: 8da77de3-5554-426f-22bb-08d6303329cb x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(1496009)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(575784001)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: A1TyFdn0OHlxweM58h033Oz3eooWUgS1urAJKvwWsUGzSjKiTH5mm3wahziTeUHXZMK6TDMMVvSmLe8MzVMV7j/vCRhTaYnFVXdpOn6L8zlRsRyUZtiUYzcsfQbIF22rl/DFqwGh7ydJI5k56fKH/aatUayYmTugOuhPg820wPWPveyPhQbnwYWih/nlCxb9WfeX2PUeMFOKEqQcYjyqYlBF0tWVFzjh96vODoQLDrEztO11AGVNjyzlDcYhRA+im2+oYAWukIAH/F+kEtarYYQiGmfpMeqQjW5wkDIUhiXrKaIEP05Wk9pkHKDeylOw/0aO6FQPCcMnJ1NbIMaDvfU1bzuMS84NUvJ0zLrt/Co= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8da77de3-5554-426f-22bb-08d6303329cb X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:22.7472 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 08/22] net/atlantic: implement core logic for Tx/Rx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add RX/TX function prototypes for further datapath development. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 1 + drivers/net/atlantic/Makefile | 1 + drivers/net/atlantic/atl_ethdev.c | 14 ++++++++++++ drivers/net/atlantic/atl_ethdev.h | 15 +++++++++++++ drivers/net/atlantic/atl_rxtx.c | 42 +++++++++++++++++++++++++++++++++++ drivers/net/atlantic/meson.build | 1 + 6 files changed, 74 insertions(+) create mode 100644 drivers/net/atlantic/atl_rxtx.c diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index 1b9cbf95077f..c603b7bfcd42 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -4,6 +4,7 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Queue start/stop = Y FW version = Y Linux UIO = Y ARMv8 = Y diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index 91306d71ba97..b88da362146d 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -24,6 +24,7 @@ VPATH += $(SRCDIR)/hw_atl # # all source are stored in SRCS-y # +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_rxtx.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index d756ad4c8b99..870eafba3e13 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -104,6 +104,9 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(); eth_dev->dev_ops = &atl_eth_dev_ops; + eth_dev->rx_pkt_burst = &atl_recv_pkts; + eth_dev->tx_pkt_burst = &atl_xmit_pkts; + eth_dev->tx_pkt_prepare = &atl_prep_pkts; /* For secondary processes, the primary process has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) @@ -155,6 +158,8 @@ eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) atl_dev_close(eth_dev); eth_dev->dev_ops = NULL; + eth_dev->rx_pkt_burst = NULL; + eth_dev->tx_pkt_burst = NULL; rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; @@ -208,6 +213,15 @@ atl_dev_start(struct rte_eth_dev *dev) err = hw_atl_b0_hw_init(hw, dev->data->mac_addrs->addr_bytes); hw_atl_b0_hw_start(hw); + /* initialize transmission unit */ + atl_tx_init(dev); + + /* This can fail when allocating mbufs for descriptor rings */ + err = atl_rx_init(dev); + if (err) { + PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); + return -EIO; + } PMD_INIT_LOG(DEBUG, "FW version: %u.%u.%u", hw->fw_ver_actual >> 24, diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index c0cc5475a091..990e8e4e9978 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -21,4 +21,19 @@ struct atl_adapter { struct aq_hw_cfg_s hw_cfg; }; +/* + * RX/TX function prototypes + */ +int atl_rx_init(struct rte_eth_dev *dev); +int atl_tx_init(struct rte_eth_dev *dev); + +uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); + +uint16_t atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); + +uint16_t atl_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); + #endif /* _ATLANTIC_ETHDEV_H_ */ diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c new file mode 100644 index 000000000000..0fbd93038075 --- /dev/null +++ b/drivers/net/atlantic/atl_rxtx.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#include "atl_ethdev.h" + +int +atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) +{ + return 0; +} + +int +atl_rx_init(struct rte_eth_dev *eth_dev __rte_unused) +{ + return 0; +} + +uint16_t +atl_prep_pkts(void *tx_queue __rte_unused, + struct rte_mbuf **tx_pkts __rte_unused, + uint16_t nb_pkts __rte_unused) +{ + return 0; +} + +uint16_t +atl_recv_pkts(void *rx_queue __rte_unused, + struct rte_mbuf **rx_pkts __rte_unused, + uint16_t nb_pkts __rte_unused) +{ + return 0; +} + +uint16_t +atl_xmit_pkts(void *tx_queue __rte_unused, + struct rte_mbuf **tx_pkts __rte_unused, + uint16_t nb_pkts __rte_unused) +{ + return 0; +} + diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index a0ad8f088571..28fb97cace6e 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -2,6 +2,7 @@ # Copyright(c) 2018 Aquantia Corporation sources = files( + 'atl_rxtx.c', 'atl_ethdev.c', 'atl_hw_regs.c', 'hw_atl/hw_atl_b0.c', From patchwork Fri Oct 12 11:09:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46704 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AD0171B5B1; Fri, 12 Oct 2018 13:09:30 +0200 (CEST) Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720042.outbound.protection.outlook.com [40.107.72.42]) by dpdk.org (Postfix) with ESMTP id 915F51B5A2 for ; Fri, 12 Oct 2018 13:09:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8fkWLzvEWCl2L/FQmmGBLOE3qj4jx+lnbtGyA5NolLY=; b=jaELDJebDfzv/6XZuGkvItSVc7dxR0oTLjReNDA5mKFmfS48sKJaUvJQZ8mhyUmPyw6bugO3xhiCi3372dabzQCKwnDx0FgvaEmN5BHJ7bZewEpKULQcO/P7JawwMCmrLe81vAy75xUg81HaTlGdsRav8/N9QVqm8DkdiEoMOL4= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1879.namprd07.prod.outlook.com (10.162.143.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1207.26; Fri, 12 Oct 2018 11:09:25 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:25 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 09/22] net/atlantic: implement Rx path Thread-Index: AQHUYhwIH/WQy00dhkiO4U249x0UGw== Date: Fri, 12 Oct 2018 11:09:25 +0000 Message-ID: <81d854b0821545151f493db80650250887ba1ed4.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1879; 6:3CdOFq9BoWrrNAGZe9jKb8xhvraKDrCnylUIkHiDnvkpnhw0610kh62jqMteP6tkpzt8DpV3LFhIHIG6WVn/DYx3umg6oDo4JL16hHtN9FbU02cj3YGBzlkUqcKdz3753s/fgjBrFc58jJRqYb0N7IPrilEZqdHtTCl/3DEcYyyZTCeFYIg0GlvWebW8fFuqs7bGNxaFDF5veBfJFHczXxGxu6NEizEo91PlBAHHt4DiBLR9WNI0slsmcIJWP/vogpcbeg1+QZGD760Ybz5cHSqKOSOGPE5IsDgwpG8VrvoAatetxZnA+uMI3VlyY1yZooc/0/zTjCnY2RIlt2dbatX9D4xBaBcZQaDFrSyNKI9jJHP3R2E/WoDUplqlhJ+IQngV75AvvLG1yU4YRK3FcZM0IM7Ox2M6j71x9GPx3borKzOwbVS618fMpew8LBbmJaCCbAFpA9EF3PVj64fOHxpHI3rpFMpPX1i8WrDWzQM=; 5:NLnZUZCuODrqcq3kzvwJuFTLKLBCOqglfTmIvGf8omOIS0xTh1QBe4+p52LzL8yWz6M+JqKyjHtaPL+ddBnRRbUx0eNlhzSWt3w8NHPtg0WW55BvP9tS1Y9CXY2RRVz6DO4AHrERIKfmAhY8OmPxu2F9ByMwz9+e+DAtvl/zBbA=; 7:XzqR2IryLJ6HfAVpajbFlRhjRyzCZtnfZcsxxwk3tBRJXy05crMx59x/jSJz64UBC+OD2Ln7zOyT/o3MOCGdFNi2LMFKAq8PbQjL1rTCTrsET/FjUUU4YjMzXIvaV7okvBYXNlbUGzQb/Ki6P0G1VfwJ1nGqOFtZx/c/H6U4KvF+ADIgHOHLSrg603Wi/bEikOimnflB9Sz+V3zw1cFRhu/VAl6J2x7elW8ExaKZps/UOkx2XAjCW/WjJrJNn6nW x-ms-office365-filtering-correlation-id: 35cf0ffd-46d3-4fe7-59fa-08d630332b18 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1879; x-ms-traffictypediagnostic: BY1PR0701MB1879: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123558120)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123560045)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1879; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1879; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(1496009)(346002)(376002)(366004)(136003)(39850400004)(396003)(189003)(199004)(6436002)(5640700003)(3846002)(68736007)(2900100001)(478600001)(6486002)(14454004)(2906002)(72206003)(71190400001)(71200400001)(26005)(2616005)(44832011)(102836004)(4744004)(446003)(486006)(256004)(118296001)(186003)(105586002)(2351001)(6116002)(106356001)(6512007)(97736004)(6916009)(5660300001)(54906003)(6506007)(386003)(53946003)(11346002)(476003)(14444005)(53936002)(5250100002)(2501003)(25786009)(8936002)(8676002)(4326008)(86362001)(305945005)(7736002)(99286004)(81166006)(1730700003)(81156014)(66066001)(52116002)(36756003)(316002)(76176011)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1879; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: a7uOMeZvsV6hGexJw7v6xP4iolWCGEXF+23CO9HnRDS5VVINcPxJSEs4nkhX1aJ7+qfVL89zv4agEQ8LIrX1h8yfMO46A9M6p3bDkqY4vfLO0KTb7nXe7MxdKP6xAjw7d8VZSSFSkfe9Le5ctUxw2ijh2J3X6+CxE7K3sFYLAqsju/GeOgNEYiUUBOxiRZGVDkIYqzpZbkvbIhK/CS+7xpryjr6zqnIk6W4sQ9DUHDuyz0QWMTKzMHz8vum9ByP6g/qIGn+f9Fn8aEwNP2z948FHMKYBuSkfxFrcmtGeKiksx7BpeB05uCpH0dtmhjxhyiIwEHmC4tMTKkZIGJsunYk7lhbFZEhVVS6KYjxuXHw= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 35cf0ffd-46d3-4fe7-59fa-08d630332b18 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:25.0600 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1879 Subject: [dpdk-dev] [PATCH v6 09/22] net/atlantic: implement Rx path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add implementation for RX datapath. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/atlantic.rst | 6 + doc/guides/nics/features/atlantic.ini | 5 + drivers/net/atlantic/Makefile | 2 +- drivers/net/atlantic/atl_ethdev.c | 79 ++++- drivers/net/atlantic/atl_ethdev.h | 19 + drivers/net/atlantic/atl_rxtx.c | 632 +++++++++++++++++++++++++++++++++- 6 files changed, 733 insertions(+), 10 deletions(-) diff --git a/doc/guides/nics/atlantic.rst b/doc/guides/nics/atlantic.rst index 21e52bb26625..a003ef5110c9 100644 --- a/doc/guides/nics/atlantic.rst +++ b/doc/guides/nics/atlantic.rst @@ -12,6 +12,10 @@ More information can be found at `Aquantia Official Website Supported features ^^^^^^^^^^^^^^^^^^ +- Base L2 features +- Checksum offload +- Jumbo Frame upto 16K + Configuration Information ^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -29,6 +33,8 @@ Statistics MTU setting ~~~~~~~~~~~ +Atlantic NIC supports up to 16K jumbo frame size + Supported Chipsets and NICs --------------------------- diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index c603b7bfcd42..374cf9fb1061 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -5,6 +5,11 @@ ; [Features] Queue start/stop = Y +Jumbo frame = Y +CRC offload = Y +L3 checksum offload = Y +L4 checksum offload = Y +Packet type parsing = Y FW version = Y Linux UIO = Y ARMv8 = Y diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index b88da362146d..62dcdbffa69c 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -15,7 +15,7 @@ EXPORT_MAP := rte_pmd_atlantic_version.map LIBABIVER := 1 -LDLIBS += -lrte_eal +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring LDLIBS += -lrte_ethdev -lrte_net LDLIBS += -lrte_bus_pci diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 870eafba3e13..521376d1398c 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -27,6 +27,7 @@ static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, static void atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); +static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); @@ -75,6 +76,18 @@ static struct rte_pci_driver rte_atl_pmd = { .remove = eth_atl_pci_remove, }; +#define ATL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP \ + | DEV_RX_OFFLOAD_IPV4_CKSUM \ + | DEV_RX_OFFLOAD_UDP_CKSUM \ + | DEV_RX_OFFLOAD_TCP_CKSUM \ + | DEV_RX_OFFLOAD_JUMBO_FRAME) + +static const struct rte_eth_desc_lim rx_desc_lim = { + .nb_max = ATL_MAX_RING_DESC, + .nb_min = ATL_MIN_RING_DESC, + .nb_align = ATL_RXD_ALIGN, +}; + static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, @@ -84,6 +97,13 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .fw_version_get = atl_fw_version_get, .dev_infos_get = atl_dev_info_get, + .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, + + /* Queue Control */ + .rx_queue_start = atl_rx_queue_start, + .rx_queue_stop = atl_rx_queue_stop, + .rx_queue_setup = atl_rx_queue_setup, + .rx_queue_release = atl_rx_queue_release, }; static inline int32_t @@ -220,7 +240,7 @@ atl_dev_start(struct rte_eth_dev *dev) err = atl_rx_init(dev); if (err) { PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); - return -EIO; + goto error; } PMD_INIT_LOG(DEBUG, "FW version: %u.%u.%u", @@ -229,7 +249,17 @@ atl_dev_start(struct rte_eth_dev *dev) hw->fw_ver_actual & 0xFFFF); PMD_INIT_LOG(DEBUG, "Driver version: %s", ATL_PMD_DRIVER_VERSION); - return err; + err = atl_start_queues(dev); + if (err < 0) { + PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); + goto error; + } + + return 0; + +error: + atl_stop_queues(dev); + return -EIO; } /* @@ -244,6 +274,12 @@ atl_dev_stop(struct rte_eth_dev *dev) /* reset the NIC */ atl_reset_hw(hw); hw->adapter_stopped = 1; + + atl_stop_queues(dev); + + /* Clear stored conf */ + dev->data->scattered_rx = 0; + dev->data->lro = 0; } /* @@ -255,6 +291,8 @@ atl_dev_close(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); atl_dev_stop(dev); + + atl_free_queues(dev); } static int @@ -298,14 +336,47 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - dev_info->max_rx_queues = 0; - dev_info->max_rx_queues = 0; + dev_info->max_rx_queues = AQ_HW_MAX_RX_QUEUES; + dev_info->max_tx_queues = AQ_HW_MAX_TX_QUEUES; + dev_info->min_rx_bufsize = 1024; + dev_info->max_rx_pktlen = HW_ATL_B0_MTU_JUMBO; + dev_info->max_mac_addrs = HW_ATL_B0_MAC_MAX; dev_info->max_vfs = pci_dev->max_vfs; dev_info->max_hash_mac_addrs = 0; dev_info->max_vmdq_pools = 0; dev_info->vmdq_queue_num = 0; + + dev_info->rx_offload_capa = ATL_RX_OFFLOADS; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = ATL_DEFAULT_RX_FREE_THRESH, + }; + + dev_info->rx_desc_lim = rx_desc_lim; +} + +static const uint32_t * +atl_dev_supported_ptypes_get(struct rte_eth_dev *dev) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L2_ETHER_ARP, + RTE_PTYPE_L2_ETHER_VLAN, + RTE_PTYPE_L3_IPV4, + RTE_PTYPE_L3_IPV6, + RTE_PTYPE_L4_TCP, + RTE_PTYPE_L4_UDP, + RTE_PTYPE_L4_SCTP, + RTE_PTYPE_L4_ICMP, + RTE_PTYPE_UNKNOWN + }; + + if (dev->rx_pkt_burst == atl_recv_pkts) + return ptypes; + + return NULL; } RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 990e8e4e9978..a9a9fc8fe7ff 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -13,6 +13,10 @@ #define ATL_DEV_PRIVATE_TO_HW(adapter) \ (&((struct atl_adapter *)adapter)->hw) +#define ATL_DEV_TO_ADAPTER(dev) \ + ((struct atl_adapter *)(dev)->data->dev_private) + + /* * Structure to store private data for each driver instance (for each port). */ @@ -24,9 +28,24 @@ struct atl_adapter { /* * RX/TX function prototypes */ +void atl_rx_queue_release(void *rxq); + +int atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool); + int atl_rx_init(struct rte_eth_dev *dev); int atl_tx_init(struct rte_eth_dev *dev); +int atl_start_queues(struct rte_eth_dev *dev); +int atl_stop_queues(struct rte_eth_dev *dev); +void atl_free_queues(struct rte_eth_dev *dev); + +int atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); + + uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 0fbd93038075..61dbb83b4572 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -2,7 +2,150 @@ * Copyright(c) 2018 Aquantia Corporation */ +#include +#include + #include "atl_ethdev.h" +#include "atl_hw_regs.h" + +#include "atl_logs.h" +#include "hw_atl/hw_atl_llh.h" +#include "hw_atl/hw_atl_b0.h" +#include "hw_atl/hw_atl_b0_internal.h" + +/** + * Structure associated with each descriptor of the RX ring of a RX queue. + */ +struct atl_rx_entry { + struct rte_mbuf *mbuf; +}; + +/** + * Structure associated with each RX queue. + */ +struct atl_rx_queue { + struct rte_mempool *mb_pool; + struct hw_atl_rxd_s *hw_ring; + uint64_t hw_ring_phys_addr; + struct atl_rx_entry *sw_ring; + uint16_t nb_rx_desc; + uint16_t rx_tail; + uint16_t nb_rx_hold; + uint16_t rx_free_thresh; + uint16_t queue_id; + uint16_t port_id; + uint16_t buff_size; + bool l3_csum_enabled; + bool l4_csum_enabled; +}; + +static inline void +atl_reset_rx_queue(struct atl_rx_queue *rxq) +{ + struct hw_atl_rxd_s *rxd = NULL; + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < rxq->nb_rx_desc; i++) { + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[i]; + rxd->buf_addr = 0; + rxd->hdr_addr = 0; + } + + rxq->rx_tail = 0; +} + +int +atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool) +{ + struct atl_rx_queue *rxq; + const struct rte_memzone *mz; + + PMD_INIT_FUNC_TRACE(); + + /* make sure a valid number of descriptors have been requested */ + if (nb_rx_desc < AQ_HW_MIN_RX_RING_SIZE || + nb_rx_desc > AQ_HW_MAX_RX_RING_SIZE) { + PMD_INIT_LOG(ERR, "Number of Rx descriptors must be " + "less than or equal to %d, " + "greater than or equal to %d", AQ_HW_MAX_RX_RING_SIZE, + AQ_HW_MIN_RX_RING_SIZE); + return -EINVAL; + } + + /* + * if this queue existed already, free the associated memory. The + * queue cannot be reused in case we need to allocate memory on + * different socket than was previously used. + */ + if (dev->data->rx_queues[rx_queue_id] != NULL) { + atl_rx_queue_release(dev->data->rx_queues[rx_queue_id]); + dev->data->rx_queues[rx_queue_id] = NULL; + } + + /* allocate memory for the queue structure */ + rxq = rte_zmalloc_socket("atlantic Rx queue", sizeof(*rxq), + RTE_CACHE_LINE_SIZE, socket_id); + if (rxq == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate queue structure"); + return -ENOMEM; + } + + /* setup queue */ + rxq->mb_pool = mb_pool; + rxq->nb_rx_desc = nb_rx_desc; + rxq->port_id = dev->data->port_id; + rxq->queue_id = rx_queue_id; + rxq->rx_free_thresh = rx_conf->rx_free_thresh; + + rxq->l3_csum_enabled = dev->data->dev_conf.rxmode.offloads & + DEV_RX_OFFLOAD_IPV4_CKSUM; + rxq->l4_csum_enabled = dev->data->dev_conf.rxmode.offloads & + (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM); + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) + PMD_DRV_LOG(ERR, "PMD does not support KEEP_CRC offload"); + + /* allocate memory for the software ring */ + rxq->sw_ring = rte_zmalloc_socket("atlantic sw rx ring", + nb_rx_desc * sizeof(struct atl_rx_entry), + RTE_CACHE_LINE_SIZE, socket_id); + if (rxq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate software ring for queue %d", + rxq->port_id, rxq->queue_id); + rte_free(rxq); + return -ENOMEM; + } + + /* + * allocate memory for the hardware descriptor ring. A memzone large + * enough to hold the maximum ring size is requested to allow for + * resizing in later calls to the queue setup function. + */ + mz = rte_eth_dma_zone_reserve(dev, "rx hw_ring", rx_queue_id, + HW_ATL_B0_MAX_RXD * + sizeof(struct hw_atl_rxd_s), + 128, socket_id); + if (mz == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate hardware ring for queue %d", + rxq->port_id, rxq->queue_id); + rte_free(rxq->sw_ring); + rte_free(rxq); + return -ENOMEM; + } + rxq->hw_ring = mz->addr; + rxq->hw_ring_phys_addr = mz->iova; + + atl_reset_rx_queue(rxq); + + dev->data->rx_queues[rx_queue_id] = rxq; + return 0; +} int atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) @@ -11,11 +154,177 @@ atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) } int -atl_rx_init(struct rte_eth_dev *eth_dev __rte_unused) +atl_rx_init(struct rte_eth_dev *eth_dev) { + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + struct atl_rx_queue *rxq; + uint64_t base_addr = 0; + int i = 0; + int err = 0; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { + rxq = eth_dev->data->rx_queues[i]; + base_addr = rxq->hw_ring_phys_addr; + + /* Take requested pool mbuf size and adapt + * descriptor buffer to best fit + */ + int buff_size = rte_pktmbuf_data_room_size(rxq->mb_pool) - + RTE_PKTMBUF_HEADROOM; + + buff_size = RTE_ALIGN_FLOOR(buff_size, 1024); + if (buff_size > HW_ATL_B0_RXD_BUF_SIZE_MAX) { + PMD_INIT_LOG(WARNING, + "Port %d queue %d: mem pool buff size is too big\n", + rxq->port_id, rxq->queue_id); + buff_size = HW_ATL_B0_RXD_BUF_SIZE_MAX; + } + if (buff_size < 1024) { + PMD_INIT_LOG(ERR, + "Port %d queue %d: mem pool buff size is too small\n", + rxq->port_id, rxq->queue_id); + return -EINVAL; + } + rxq->buff_size = buff_size; + + err = hw_atl_b0_hw_ring_rx_init(hw, base_addr, rxq->queue_id, + rxq->nb_rx_desc, buff_size, 0, + rxq->port_id); + + if (err) { + PMD_INIT_LOG(ERR, "Port %d: Cannot init RX queue %d", + rxq->port_id, rxq->queue_id); + break; + } + } + + return err; +} + +static int +atl_alloc_rx_queue_mbufs(struct atl_rx_queue *rxq) +{ + struct atl_rx_entry *rx_entry = rxq->sw_ring; + struct hw_atl_rxd_s *rxd; + uint64_t dma_addr = 0; + uint32_t i = 0; + + PMD_INIT_FUNC_TRACE(); + + /* fill Rx ring */ + for (i = 0; i < rxq->nb_rx_desc; i++) { + struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); + + if (mbuf == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: mbuf alloc failed for rx queue %d", + rxq->port_id, rxq->queue_id); + return -ENOMEM; + } + + mbuf->data_off = RTE_PKTMBUF_HEADROOM; + mbuf->port = rxq->port_id; + + dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[i]; + rxd->buf_addr = dma_addr; + rxd->hdr_addr = 0; + rx_entry[i].mbuf = mbuf; + } + return 0; } +static void +atl_rx_queue_release_mbufs(struct atl_rx_queue *rxq) +{ + int i; + + PMD_INIT_FUNC_TRACE(); + + if (rxq->sw_ring != NULL) { + for (i = 0; i < rxq->nb_rx_desc; i++) { + if (rxq->sw_ring[i].mbuf != NULL) { + rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf); + rxq->sw_ring[i].mbuf = NULL; + } + } + } +} + +int +atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_rx_queue *rxq = NULL; + + PMD_INIT_FUNC_TRACE(); + + if (rx_queue_id < dev->data->nb_rx_queues) { + rxq = dev->data->rx_queues[rx_queue_id]; + + if (atl_alloc_rx_queue_mbufs(rxq) != 0) { + PMD_INIT_LOG(ERR, + "Port %d: Allocate mbufs for queue %d failed", + rxq->port_id, rxq->queue_id); + return -1; + } + + hw_atl_b0_hw_ring_rx_start(hw, rx_queue_id); + + rte_wmb(); + hw_atl_reg_rx_dma_desc_tail_ptr_set(hw, rxq->nb_rx_desc - 1, + rx_queue_id); + dev->data->rx_queue_state[rx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + return -1; + } + + return 0; +} + +int +atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_rx_queue *rxq = NULL; + + PMD_INIT_FUNC_TRACE(); + + if (rx_queue_id < dev->data->nb_rx_queues) { + rxq = dev->data->rx_queues[rx_queue_id]; + + hw_atl_b0_hw_ring_rx_stop(hw, rx_queue_id); + + atl_rx_queue_release_mbufs(rxq); + atl_reset_rx_queue(rxq); + + dev->data->rx_queue_state[rx_queue_id] = + RTE_ETH_QUEUE_STATE_STOPPED; + } else { + return -1; + } + + return 0; +} + +void +atl_rx_queue_release(void *rx_queue) +{ + PMD_INIT_FUNC_TRACE(); + + if (rx_queue != NULL) { + struct atl_rx_queue *rxq = (struct atl_rx_queue *)rx_queue; + + atl_rx_queue_release_mbufs(rxq); + rte_free(rxq->sw_ring); + rte_free(rxq); + } +} + uint16_t atl_prep_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts __rte_unused, @@ -24,14 +333,327 @@ atl_prep_pkts(void *tx_queue __rte_unused, return 0; } -uint16_t -atl_recv_pkts(void *rx_queue __rte_unused, - struct rte_mbuf **rx_pkts __rte_unused, - uint16_t nb_pkts __rte_unused) +void +atl_free_queues(struct rte_eth_dev *dev) +{ + unsigned int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + atl_rx_queue_release(dev->data->rx_queues[i]); + dev->data->rx_queues[i] = 0; + } + dev->data->nb_rx_queues = 0; +} + +int +atl_start_queues(struct rte_eth_dev *dev) { + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + if (atl_rx_queue_start(dev, i) != 0) { + PMD_DRV_LOG(ERR, + "Port %d: Start Rx queue %d failed", + dev->data->port_id, i); + return -1; + } + } + return 0; } +int +atl_stop_queues(struct rte_eth_dev *dev) +{ + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + if (atl_rx_queue_stop(dev, i) != 0) { + PMD_DRV_LOG(ERR, + "Port %d: Stop Rx queue %d failed", + dev->data->port_id, i); + return -1; + } + } + + return 0; +} + +static uint64_t +atl_desc_to_offload_flags(struct atl_rx_queue *rxq, + struct hw_atl_rxd_wb_s *rxd_wb) +{ + uint64_t mbuf_flags = 0; + + PMD_INIT_FUNC_TRACE(); + + /* IPv4 ? */ + if (rxq->l3_csum_enabled && ((rxd_wb->pkt_type & 0x3) == 0)) { + /* IPv4 csum error ? */ + if (rxd_wb->rx_stat & BIT(1)) + mbuf_flags |= PKT_RX_IP_CKSUM_BAD; + else + mbuf_flags |= PKT_RX_IP_CKSUM_GOOD; + } else { + mbuf_flags |= PKT_RX_IP_CKSUM_UNKNOWN; + } + + /* CSUM calculated ? */ + if (rxq->l4_csum_enabled && (rxd_wb->rx_stat & BIT(3))) { + if (rxd_wb->rx_stat & BIT(2)) + mbuf_flags |= PKT_RX_L4_CKSUM_BAD; + else + mbuf_flags |= PKT_RX_L4_CKSUM_GOOD; + } else { + mbuf_flags |= PKT_RX_L4_CKSUM_UNKNOWN; + } + + return mbuf_flags; +} + +static uint32_t +atl_desc_to_pkt_type(struct hw_atl_rxd_wb_s *rxd_wb) +{ + uint32_t type = RTE_PTYPE_UNKNOWN; + uint16_t l2_l3_type = rxd_wb->pkt_type & 0x3; + uint16_t l4_type = (rxd_wb->pkt_type & 0x1C) >> 2; + + switch (l2_l3_type) { + case 0: + type = RTE_PTYPE_L3_IPV4; + break; + case 1: + type = RTE_PTYPE_L3_IPV6; + break; + case 2: + type = RTE_PTYPE_L2_ETHER; + break; + case 3: + type = RTE_PTYPE_L2_ETHER_ARP; + break; + } + + switch (l4_type) { + case 0: + type |= RTE_PTYPE_L4_TCP; + break; + case 1: + type |= RTE_PTYPE_L4_UDP; + break; + case 2: + type |= RTE_PTYPE_L4_SCTP; + break; + case 3: + type |= RTE_PTYPE_L4_ICMP; + break; + } + + if (rxd_wb->pkt_type & BIT(5)) + type |= RTE_PTYPE_L2_ETHER_VLAN; + + return type; +} + +uint16_t +atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) +{ + struct atl_rx_queue *rxq = (struct atl_rx_queue *)rx_queue; + struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id]; + struct atl_adapter *adapter = + ATL_DEV_TO_ADAPTER(&rte_eth_devices[rxq->port_id]); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(adapter); + struct atl_rx_entry *sw_ring = rxq->sw_ring; + + struct rte_mbuf *new_mbuf; + struct rte_mbuf *rx_mbuf, *rx_mbuf_prev, *rx_mbuf_first; + struct atl_rx_entry *rx_entry; + uint16_t nb_rx = 0; + uint16_t nb_hold = 0; + struct hw_atl_rxd_wb_s rxd_wb; + struct hw_atl_rxd_s *rxd = NULL; + uint16_t tail = rxq->rx_tail; + uint64_t dma_addr; + uint16_t pkt_len = 0; + + while (nb_rx < nb_pkts) { + uint16_t eop_tail = tail; + + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[tail]; + rxd_wb = *(struct hw_atl_rxd_wb_s *)rxd; + + if (!rxd_wb.dd) { /* RxD is not done */ + break; + } + + PMD_RX_LOG(ERR, "port_id=%u queue_id=%u tail=%u " + "eop=0x%x pkt_len=%u hash=0x%x hash_type=0x%x", + (unsigned int)rxq->port_id, + (unsigned int)rxq->queue_id, + (unsigned int)tail, (unsigned int)rxd_wb.eop, + (unsigned int)rte_le_to_cpu_16(rxd_wb.pkt_len), + rxd_wb.rss_hash, rxd_wb.rss_type); + + /* RxD is not done */ + if (!rxd_wb.eop) { + while (true) { + struct hw_atl_rxd_wb_s *eop_rxwbd; + + eop_tail = (eop_tail + 1) % rxq->nb_rx_desc; + eop_rxwbd = (struct hw_atl_rxd_wb_s *) + &rxq->hw_ring[eop_tail]; + if (!eop_rxwbd->dd) { + /* no EOP received yet */ + eop_tail = tail; + break; + } + if (eop_rxwbd->dd && eop_rxwbd->eop) + break; + } + /* No EOP in ring */ + if (eop_tail == tail) + break; + } + rx_mbuf_prev = NULL; + rx_mbuf_first = NULL; + + /* Run through packet segments */ + while (true) { + new_mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); + if (new_mbuf == NULL) { + PMD_RX_LOG(ERR, + "RX mbuf alloc failed port_id=%u " + "queue_id=%u", (unsigned int)rxq->port_id, + (unsigned int)rxq->queue_id); + dev->data->rx_mbuf_alloc_failed++; + goto err_stop; + } + + nb_hold++; + rx_entry = &sw_ring[tail]; + + rx_mbuf = rx_entry->mbuf; + rx_entry->mbuf = new_mbuf; + dma_addr = rte_cpu_to_le_64( + rte_mbuf_data_iova_default(new_mbuf)); + + /* setup RX descriptor */ + rxd->hdr_addr = 0; + rxd->buf_addr = dma_addr; + + /* + * Initialize the returned mbuf. + * 1) setup generic mbuf fields: + * - number of segments, + * - next segment, + * - packet length, + * - RX port identifier. + * 2) integrate hardware offload data, if any: + * < - RSS flag & hash, + * - IP checksum flag, + * - VLAN TCI, if any, + * - error flags. + */ + pkt_len = (uint16_t)rte_le_to_cpu_16(rxd_wb.pkt_len); + rx_mbuf->data_off = RTE_PKTMBUF_HEADROOM; + rte_prefetch1((char *)rx_mbuf->buf_addr + + rx_mbuf->data_off); + rx_mbuf->nb_segs = 0; + rx_mbuf->next = NULL; + rx_mbuf->pkt_len = pkt_len; + rx_mbuf->data_len = pkt_len; + if (rxd_wb.eop) { + u16 remainder_len = pkt_len % rxq->buff_size; + if (!remainder_len) + remainder_len = rxq->buff_size; + rx_mbuf->data_len = remainder_len; + } else { + rx_mbuf->data_len = pkt_len > rxq->buff_size ? + rxq->buff_size : pkt_len; + } + rx_mbuf->port = rxq->port_id; + + rx_mbuf->hash.rss = rxd_wb.rss_hash; + + rx_mbuf->vlan_tci = rxd_wb.vlan; + + rx_mbuf->ol_flags = + atl_desc_to_offload_flags(rxq, &rxd_wb); + rx_mbuf->packet_type = atl_desc_to_pkt_type(&rxd_wb); + + if (!rx_mbuf_first) + rx_mbuf_first = rx_mbuf; + rx_mbuf_first->nb_segs++; + + if (rx_mbuf_prev) + rx_mbuf_prev->next = rx_mbuf; + rx_mbuf_prev = rx_mbuf; + + tail = (tail + 1) % rxq->nb_rx_desc; + /* Prefetch next mbufs */ + rte_prefetch0(sw_ring[tail].mbuf); + if ((tail & 0x3) == 0) { + rte_prefetch0(&sw_ring[tail]); + rte_prefetch0(&sw_ring[tail]); + } + + /* filled mbuf_first */ + if (rxd_wb.eop) + break; + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[tail]; + rxd_wb = *(struct hw_atl_rxd_wb_s *)rxd; + }; + + /* + * Store the mbuf address into the next entry of the array + * of returned packets. + */ + rx_pkts[nb_rx++] = rx_mbuf_first; + + PMD_RX_LOG(ERR, "add mbuf segs=%d pkt_len=%d", + rx_mbuf_first->nb_segs, + rx_mbuf_first->pkt_len); + } + +err_stop: + + rxq->rx_tail = tail; + + /* + * If the number of free RX descriptors is greater than the RX free + * threshold of the queue, advance the Receive Descriptor Tail (RDT) + * register. + * Update the RDT with the value of the last processed RX descriptor + * minus 1, to guarantee that the RDT register is never equal to the + * RDH register, which creates a "full" ring situtation from the + * hardware point of view... + */ + nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold); + if (nb_hold > rxq->rx_free_thresh) { + PMD_RX_LOG(ERR, "port_id=%u queue_id=%u rx_tail=%u " + "nb_hold=%u nb_rx=%u", + (unsigned int)rxq->port_id, (unsigned int)rxq->queue_id, + (unsigned int)tail, (unsigned int)nb_hold, + (unsigned int)nb_rx); + tail = (uint16_t)((tail == 0) ? + (rxq->nb_rx_desc - 1) : (tail - 1)); + + hw_atl_reg_rx_dma_desc_tail_ptr_set(hw, tail, rxq->queue_id); + + nb_hold = 0; + } + + rxq->nb_rx_hold = nb_hold; + + return nb_rx; +} + + uint16_t atl_xmit_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts __rte_unused, From patchwork Fri Oct 12 11:09:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46705 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3F3DE1B5BB; Fri, 12 Oct 2018 13:09:33 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0083.outbound.protection.outlook.com [104.47.38.83]) by dpdk.org (Postfix) with ESMTP id 2AE7C1B5AD for ; Fri, 12 Oct 2018 13:09:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eeMUay/QIVhlnmzBOCzccgCmYnwyaOGunUigTthUmhs=; b=OhlxQCK3pcYqEbTLsmNEkiI/CvFWYMa7UydUuNzoDSP1i6H5rV6vBTXGrmEmPqTETTpUQuyy/cvOIe2Fey+ujanfh0qgqiLL6Z1sDk/2ec0a+8fgo3uZuwUuepbNOH+Pvr0KqFxqZcvQ0tidgoYctwWHFlPerH8BBm/vK24VYNo= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:27 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:27 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 10/22] net/atlantic: implement Tx path Thread-Index: AQHUYhwKGhPlLvxpsk2EUCBTBWKZQQ== Date: Fri, 12 Oct 2018 11:09:27 +0000 Message-ID: <4a77b5e45cc3c2a741804c0efd62436df9885ed5.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:nFvj6Cy3Kgv6xVIWww/PsnEj3SI4K/LzWi0fDBgREePZCtY/L+TfqKdR+dKPtLrkRsxlAK3pZsWTdP+KjvqI6iuWYDCvj9tLOpNistJtauPd4xLtVcRusZ9uowXXFosSVL32iHn8GgxkGlw3n3v5fuMaT6qflCyvhPG5eX9pEvMHDNIVlwUZiNjALrkhQXYmeMUr3rMsI9v7yTnlxMNaotFmZL2PgxPXSsKfH5ZGZtBVvjEnJ4NyrA3TQF7V6Tgt+shOtiJN5b6GrpS3XwJ40+ZqZG962rsY3mIT3ghCB3Jh0pfeRmlGmOw+XtAV6LrgpTHngzvQ7uX2bxpk+HosbS8CWovIZLTTG2O8njviYy2X3Tu5pxE+fW8OGg5aE6m3x1VdSMY2YCRI5KxvweqeBpzJpE7FAWiJaDHBzIi32t2CcBFouCE3Y+0SNfO42erRMNyughowVMruqU5cEKuwSw==; 5:8duct0IE9SyQgk4SL3iE0txgAMegFSo+ZivW4T+HggwCSmEMo5Nwj0QHOxU4QST/Xf+rWuEMmkywBkZMkUJbtYzWyXEzcn3xW58ZrMeSsWTDiIHm6WOzUiZgZp5C6V8KAx297mDMfxfkBt9WNKpR7Lp9w2gmGHV+0UPAqcJb25c=; 7:ZwOnFN+C2DjwDXT5A84hmmDo0diQ3yOXaJ0+JfH1hCm7sM/RfpfG4C2FUbXXdtRgxMK+0STesa1h+nBvTZMYqtNejIelx1FPJn2XPPw6w9C2+6zB1WWZaG+oScCO69dZBQI0fxduOAN1wFIavdzYn0X7MKyL/2w4Us52I9h+QkWDhyPx0ES+c5wVjNf8XP1VaYKrDRXwG1JI8+l/f8QPN94a3eQIaXbvih2NnWch1f6NsyIIjLFN5A23y3853+VZ x-ms-office365-filtering-correlation-id: eeb37344-0231-4b11-75c1-08d630332c7e x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(53946003)(5250100002)(11346002)(86362001)(25786009)(4744004)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011)(309714004); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: k48DKjN0ykEXtrLfJSOIViOskTuqrEtrjhayBh0AZ4A7DmAN5n+mxILI6DKehirBSsRhJ28WBgL7FhPgG/CyDMG+DGKJCniaEtcDhCpQdqE3T91376ZqZ2swnPUkBF29ItXMUnghkSJW/FaCT2+aLvm6XwcCnliIWMI0LfB0An1GwUbT+UWh8LyUV8+TsSL6hJfbnecVZmCxYeGYQWv5QopLavmo4nQKYy7yDbE8k8D6UMLRg2oTrjQCh8PrYU4nOpY2rDr8a2hztdLdCISRUG1NcNdk2wDflZxnt8LPtHisX5MZtfl2IZK45gZrNv8lENSKrJ8YUDViaAPKaSBSJAwwv84EFF9ExwwP9+6qgp0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: eeb37344-0231-4b11-75c1-08d630332c7e X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:27.2068 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 10/22] net/atlantic: implement Tx path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add implementation for TX datapath. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 28 ++ drivers/net/atlantic/atl_ethdev.h | 7 + drivers/net/atlantic/atl_rxtx.c | 546 +++++++++++++++++++++++++++++++++++++- 3 files changed, 572 insertions(+), 9 deletions(-) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 521376d1398c..156f1be99cdf 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -82,12 +82,27 @@ static struct rte_pci_driver rte_atl_pmd = { | DEV_RX_OFFLOAD_TCP_CKSUM \ | DEV_RX_OFFLOAD_JUMBO_FRAME) +#define ATL_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT \ + | DEV_TX_OFFLOAD_IPV4_CKSUM \ + | DEV_TX_OFFLOAD_UDP_CKSUM \ + | DEV_TX_OFFLOAD_TCP_CKSUM \ + | DEV_TX_OFFLOAD_TCP_TSO \ + | DEV_TX_OFFLOAD_MULTI_SEGS) + static const struct rte_eth_desc_lim rx_desc_lim = { .nb_max = ATL_MAX_RING_DESC, .nb_min = ATL_MIN_RING_DESC, .nb_align = ATL_RXD_ALIGN, }; +static const struct rte_eth_desc_lim tx_desc_lim = { + .nb_max = ATL_MAX_RING_DESC, + .nb_min = ATL_MIN_RING_DESC, + .nb_align = ATL_TXD_ALIGN, + .nb_seg_max = ATL_TX_MAX_SEG, + .nb_mtu_seg_max = ATL_TX_MAX_SEG, +}; + static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, @@ -104,6 +119,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_queue_stop = atl_rx_queue_stop, .rx_queue_setup = atl_rx_queue_setup, .rx_queue_release = atl_rx_queue_release, + + .tx_queue_start = atl_tx_queue_start, + .tx_queue_stop = atl_tx_queue_stop, + .tx_queue_setup = atl_tx_queue_setup, + .tx_queue_release = atl_tx_queue_release, }; static inline int32_t @@ -350,11 +370,19 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_offload_capa = ATL_RX_OFFLOADS; + dev_info->tx_offload_capa = ATL_TX_OFFLOADS; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { .rx_free_thresh = ATL_DEFAULT_RX_FREE_THRESH, }; + dev_info->default_txconf = (struct rte_eth_txconf) { + .tx_free_thresh = ATL_DEFAULT_TX_FREE_THRESH, + }; + dev_info->rx_desc_lim = rx_desc_lim; + dev_info->tx_desc_lim = tx_desc_lim; } static const uint32_t * diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index a9a9fc8fe7ff..92bb302ffe55 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -29,12 +29,17 @@ struct atl_adapter { * RX/TX function prototypes */ void atl_rx_queue_release(void *rxq); +void atl_tx_queue_release(void *txq); int atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, uint16_t nb_rx_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool); +int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf); + int atl_rx_init(struct rte_eth_dev *dev); int atl_tx_init(struct rte_eth_dev *dev); @@ -45,6 +50,8 @@ void atl_free_queues(struct rte_eth_dev *dev); int atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); +int atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 61dbb83b4572..1d4c8099325d 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -4,6 +4,7 @@ #include #include +#include #include "atl_ethdev.h" #include "atl_hw_regs.h" @@ -13,6 +14,20 @@ #include "hw_atl/hw_atl_b0.h" #include "hw_atl/hw_atl_b0_internal.h" +#define ATL_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_IP_CKSUM | \ + PKT_TX_L4_MASK | \ + PKT_TX_TCP_SEG) + +#define ATL_TX_OFFLOAD_MASK ( \ + PKT_TX_VLAN | \ + PKT_TX_IP_CKSUM | \ + PKT_TX_L4_MASK | \ + PKT_TX_TCP_SEG) + +#define ATL_TX_OFFLOAD_NOTSUP_MASK \ + (PKT_TX_OFFLOAD_MASK ^ ATL_TX_OFFLOAD_MASK) + /** * Structure associated with each descriptor of the RX ring of a RX queue. */ @@ -21,6 +36,15 @@ struct atl_rx_entry { }; /** + * Structure associated with each descriptor of the TX ring of a TX queue. + */ +struct atl_tx_entry { + struct rte_mbuf *mbuf; + uint16_t next_id; + uint16_t last_id; +}; + +/** * Structure associated with each RX queue. */ struct atl_rx_queue { @@ -39,6 +63,22 @@ struct atl_rx_queue { bool l4_csum_enabled; }; +/** + * Structure associated with each TX queue. + */ +struct atl_tx_queue { + struct hw_atl_txd_s *hw_ring; + uint64_t hw_ring_phys_addr; + struct atl_tx_entry *sw_ring; + uint16_t nb_tx_desc; + uint16_t tx_tail; + uint16_t tx_head; + uint16_t queue_id; + uint16_t port_id; + uint16_t tx_free_thresh; + uint16_t tx_free; +}; + static inline void atl_reset_rx_queue(struct atl_rx_queue *rxq) { @@ -147,13 +187,152 @@ atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, return 0; } +static inline void +atl_reset_tx_queue(struct atl_tx_queue *txq) +{ + struct atl_tx_entry *tx_entry; + union hw_atl_txc_s *txc; + uint16_t i; + + PMD_INIT_FUNC_TRACE(); + + if (!txq) { + PMD_DRV_LOG(ERR, "Pointer to txq is NULL"); + return; + } + + tx_entry = txq->sw_ring; + + for (i = 0; i < txq->nb_tx_desc; i++) { + txc = (union hw_atl_txc_s *)&txq->hw_ring[i]; + txc->flags1 = 0; + txc->flags2 = 2; + } + + for (i = 0; i < txq->nb_tx_desc; i++) { + txq->hw_ring[i].dd = 1; + tx_entry[i].mbuf = NULL; + } + + txq->tx_tail = 0; + txq->tx_head = 0; + txq->tx_free = txq->nb_tx_desc - 1; +} + int -atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) +atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf) { + struct atl_tx_queue *txq; + const struct rte_memzone *mz; + + PMD_INIT_FUNC_TRACE(); + + /* make sure a valid number of descriptors have been requested */ + if (nb_tx_desc < AQ_HW_MIN_TX_RING_SIZE || + nb_tx_desc > AQ_HW_MAX_TX_RING_SIZE) { + PMD_INIT_LOG(ERR, "Number of Tx descriptors must be " + "less than or equal to %d, " + "greater than or equal to %d", AQ_HW_MAX_TX_RING_SIZE, + AQ_HW_MIN_TX_RING_SIZE); + return -EINVAL; + } + + /* + * if this queue existed already, free the associated memory. The + * queue cannot be reused in case we need to allocate memory on + * different socket than was previously used. + */ + if (dev->data->tx_queues[tx_queue_id] != NULL) { + atl_tx_queue_release(dev->data->tx_queues[tx_queue_id]); + dev->data->tx_queues[tx_queue_id] = NULL; + } + + /* allocate memory for the queue structure */ + txq = rte_zmalloc_socket("atlantic Tx queue", sizeof(*txq), + RTE_CACHE_LINE_SIZE, socket_id); + if (txq == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate queue structure"); + return -ENOMEM; + } + + /* setup queue */ + txq->nb_tx_desc = nb_tx_desc; + txq->port_id = dev->data->port_id; + txq->queue_id = tx_queue_id; + txq->tx_free_thresh = tx_conf->tx_free_thresh; + + + /* allocate memory for the software ring */ + txq->sw_ring = rte_zmalloc_socket("atlantic sw tx ring", + nb_tx_desc * sizeof(struct atl_tx_entry), + RTE_CACHE_LINE_SIZE, socket_id); + if (txq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate software ring for queue %d", + txq->port_id, txq->queue_id); + rte_free(txq); + return -ENOMEM; + } + + /* + * allocate memory for the hardware descriptor ring. A memzone large + * enough to hold the maximum ring size is requested to allow for + * resizing in later calls to the queue setup function. + */ + mz = rte_eth_dma_zone_reserve(dev, "tx hw_ring", tx_queue_id, + HW_ATL_B0_MAX_TXD * sizeof(struct hw_atl_txd_s), + 128, socket_id); + if (mz == NULL) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot allocate hardware ring for queue %d", + txq->port_id, txq->queue_id); + rte_free(txq->sw_ring); + rte_free(txq); + return -ENOMEM; + } + txq->hw_ring = mz->addr; + txq->hw_ring_phys_addr = mz->iova; + + atl_reset_tx_queue(txq); + + dev->data->tx_queues[tx_queue_id] = txq; return 0; } int +atl_tx_init(struct rte_eth_dev *eth_dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + struct atl_tx_queue *txq; + uint64_t base_addr = 0; + int i = 0; + int err = 0; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { + txq = eth_dev->data->tx_queues[i]; + base_addr = txq->hw_ring_phys_addr; + + err = hw_atl_b0_hw_ring_tx_init(hw, base_addr, + txq->queue_id, + txq->nb_tx_desc, 0, + txq->port_id); + + if (err) { + PMD_INIT_LOG(ERR, + "Port %d: Cannot init TX queue %d", + txq->port_id, txq->queue_id); + break; + } + } + + return err; +} + +int atl_rx_init(struct rte_eth_dev *eth_dev) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); @@ -325,15 +504,78 @@ atl_rx_queue_release(void *rx_queue) } } -uint16_t -atl_prep_pkts(void *tx_queue __rte_unused, - struct rte_mbuf **tx_pkts __rte_unused, - uint16_t nb_pkts __rte_unused) +static void +atl_tx_queue_release_mbufs(struct atl_tx_queue *txq) +{ + int i; + + PMD_INIT_FUNC_TRACE(); + + if (txq->sw_ring != NULL) { + for (i = 0; i < txq->nb_tx_desc; i++) { + if (txq->sw_ring[i].mbuf != NULL) { + rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf); + txq->sw_ring[i].mbuf = NULL; + } + } + } +} + +int +atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + if (tx_queue_id < dev->data->nb_tx_queues) { + hw_atl_b0_hw_ring_tx_start(hw, tx_queue_id); + + rte_wmb(); + hw_atl_b0_hw_tx_ring_tail_update(hw, 0, tx_queue_id); + dev->data->tx_queue_state[tx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + return -1; + } + + return 0; +} + +int +atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) { + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_tx_queue *txq; + + PMD_INIT_FUNC_TRACE(); + + txq = dev->data->tx_queues[tx_queue_id]; + + hw_atl_b0_hw_ring_tx_stop(hw, tx_queue_id); + + atl_tx_queue_release_mbufs(txq); + atl_reset_tx_queue(txq); + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + return 0; } void +atl_tx_queue_release(void *tx_queue) +{ + PMD_INIT_FUNC_TRACE(); + + if (tx_queue != NULL) { + struct atl_tx_queue *txq = (struct atl_tx_queue *)tx_queue; + + atl_tx_queue_release_mbufs(txq); + rte_free(txq->sw_ring); + rte_free(txq); + } +} + +void atl_free_queues(struct rte_eth_dev *dev) { unsigned int i; @@ -345,6 +587,12 @@ atl_free_queues(struct rte_eth_dev *dev) dev->data->rx_queues[i] = 0; } dev->data->nb_rx_queues = 0; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + atl_tx_queue_release(dev->data->tx_queues[i]); + dev->data->tx_queues[i] = 0; + } + dev->data->nb_tx_queues = 0; } int @@ -354,6 +602,15 @@ atl_start_queues(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + for (i = 0; i < dev->data->nb_tx_queues; i++) { + if (atl_tx_queue_start(dev, i) != 0) { + PMD_DRV_LOG(ERR, + "Port %d: Start Tx queue %d failed", + dev->data->port_id, i); + return -1; + } + } + for (i = 0; i < dev->data->nb_rx_queues; i++) { if (atl_rx_queue_start(dev, i) != 0) { PMD_DRV_LOG(ERR, @@ -373,6 +630,15 @@ atl_stop_queues(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + for (i = 0; i < dev->data->nb_tx_queues; i++) { + if (atl_tx_queue_stop(dev, i) != 0) { + PMD_DRV_LOG(ERR, + "Port %d: Stop Tx queue %d failed", + dev->data->port_id, i); + return -1; + } + } + for (i = 0; i < dev->data->nb_rx_queues; i++) { if (atl_rx_queue_stop(dev, i) != 0) { PMD_DRV_LOG(ERR, @@ -385,6 +651,47 @@ atl_stop_queues(struct rte_eth_dev *dev) return 0; } +uint16_t +atl_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + int i, ret; + uint64_t ol_flags; + struct rte_mbuf *m; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < nb_pkts; i++) { + m = tx_pkts[i]; + ol_flags = m->ol_flags; + + if (m->nb_segs > AQ_HW_MAX_SEGS_SIZE) { + rte_errno = -EINVAL; + return i; + } + + if (ol_flags & ATL_TX_OFFLOAD_NOTSUP_MASK) { + rte_errno = -ENOTSUP; + return i; + } + +#ifdef RTE_LIBRTE_ETHDEV_DEBUG + ret = rte_validate_tx_offload(m); + if (ret != 0) { + rte_errno = ret; + return i; + } +#endif + ret = rte_net_intel_cksum_prepare(m); + if (ret != 0) { + rte_errno = ret; + return i; + } + } + + return i; +} + static uint64_t atl_desc_to_offload_flags(struct atl_rx_queue *rxq, struct hw_atl_rxd_wb_s *rxd_wb) @@ -653,12 +960,233 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) return nb_rx; } +static void +atl_xmit_cleanup(struct atl_tx_queue *txq) +{ + struct atl_tx_entry *sw_ring; + struct hw_atl_txd_s *txd; + int to_clean = 0; + + PMD_INIT_FUNC_TRACE(); + + if (txq != NULL) { + sw_ring = txq->sw_ring; + int head = txq->tx_head; + int cnt; + int i; + + for (i = 0, cnt = head; ; i++) { + txd = &txq->hw_ring[cnt]; + + if (txd->dd) + to_clean++; + + cnt = (cnt + 1) % txq->nb_tx_desc; + if (cnt == txq->tx_tail) + break; + } + + if (to_clean == 0) + return; + + while (to_clean) { + txd = &txq->hw_ring[head]; + + struct atl_tx_entry *rx_entry = &sw_ring[head]; + + if (rx_entry->mbuf) { + rte_pktmbuf_free_seg(rx_entry->mbuf); + rx_entry->mbuf = NULL; + } + + if (txd->dd) + to_clean--; + + txd->buf_addr = 0; + txd->flags = 0; + + head = (head + 1) % txq->nb_tx_desc; + txq->tx_free++; + } + + txq->tx_head = head; + } +} + +static int +atl_tso_setup(struct rte_mbuf *tx_pkt, union hw_atl_txc_s *txc) +{ + uint32_t tx_cmd = 0; + uint64_t ol_flags = tx_pkt->ol_flags; + + PMD_INIT_FUNC_TRACE(); + + if (ol_flags & PKT_TX_TCP_SEG) { + PMD_DRV_LOG(DEBUG, "xmit TSO pkt"); + + tx_cmd |= tx_desc_cmd_lso | tx_desc_cmd_l4cs; + + txc->cmd = 0x4; + + if (ol_flags & PKT_TX_IPV6) + txc->cmd |= 0x2; + + txc->l2_len = tx_pkt->l2_len; + txc->l3_len = tx_pkt->l3_len; + txc->l4_len = tx_pkt->l4_len; + + txc->mss_len = tx_pkt->tso_segsz; + } + + if (ol_flags & PKT_TX_VLAN) { + tx_cmd |= tx_desc_cmd_vlan; + txc->vlan_tag = tx_pkt->vlan_tci; + } + + if (tx_cmd) { + txc->type = tx_desc_type_ctx; + txc->idx = 0; + } + + return tx_cmd; +} + +static inline void +atl_setup_csum_offload(struct rte_mbuf *mbuf, struct hw_atl_txd_s *txd, + uint32_t tx_cmd) +{ + txd->cmd |= tx_desc_cmd_fcs; + txd->cmd |= (mbuf->ol_flags & PKT_TX_IP_CKSUM) ? tx_desc_cmd_ipv4 : 0; + /* L4 csum requested */ + txd->cmd |= (mbuf->ol_flags & PKT_TX_L4_MASK) ? tx_desc_cmd_l4cs : 0; + txd->cmd |= tx_cmd; +} + +static inline void +atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq, + struct rte_mbuf *tx_pkt) +{ + uint32_t pay_len = 0; + int tail = 0; + struct atl_tx_entry *tx_entry; + uint64_t buf_dma_addr; + struct rte_mbuf *m_seg; + union hw_atl_txc_s *txc = NULL; + struct hw_atl_txd_s *txd = NULL; + u32 tx_cmd = 0U; + int desc_count = 0; + + PMD_INIT_FUNC_TRACE(); + + tail = txq->tx_tail; + + txc = (union hw_atl_txc_s *)&txq->hw_ring[tail]; + + txc->flags1 = 0U; + txc->flags2 = 0U; + + tx_cmd = atl_tso_setup(tx_pkt, txc); + + if (tx_cmd) { + /* We've consumed the first desc, adjust counters */ + tail = (tail + 1) % txq->nb_tx_desc; + txq->tx_tail = tail; + txq->tx_free -= 1; + + txd = &txq->hw_ring[tail]; + txd->flags = 0U; + } else { + txd = (struct hw_atl_txd_s *)txc; + } + + txd->ct_en = !!tx_cmd; + + txd->type = tx_desc_type_desc; + + atl_setup_csum_offload(tx_pkt, txd, tx_cmd); + + if (tx_cmd) + txd->ct_idx = 0; + + pay_len = tx_pkt->pkt_len; + + txd->pay_len = pay_len; + + for (m_seg = tx_pkt; m_seg; m_seg = m_seg->next) { + if (desc_count > 0) { + txd = &txq->hw_ring[tail]; + txd->flags = 0U; + } + + buf_dma_addr = rte_mbuf_data_iova(m_seg); + txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr); + + txd->type = tx_desc_type_desc; + txd->len = m_seg->data_len; + txd->pay_len = pay_len; + + /* Store mbuf for freeing later */ + tx_entry = &txq->sw_ring[tail]; + + if (tx_entry->mbuf) + rte_pktmbuf_free_seg(tx_entry->mbuf); + tx_entry->mbuf = m_seg; + + tail = (tail + 1) % txq->nb_tx_desc; + + desc_count++; + } + + // Last descriptor requires EOP and WB + txd->eop = 1U; + txd->cmd |= tx_desc_cmd_wb; + + hw_atl_b0_hw_tx_ring_tail_update(hw, tail, txq->queue_id); + + txq->tx_tail = tail; + + txq->tx_free -= desc_count; +} uint16_t -atl_xmit_pkts(void *tx_queue __rte_unused, - struct rte_mbuf **tx_pkts __rte_unused, - uint16_t nb_pkts __rte_unused) +atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { - return 0; + struct rte_eth_dev *dev = NULL; + struct aq_hw_s *hw = NULL; + struct atl_tx_queue *txq = tx_queue; + struct rte_mbuf *tx_pkt; + uint16_t nb_tx; + + dev = &rte_eth_devices[txq->port_id]; + hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + PMD_TX_LOG(DEBUG, + "port %d txq %d pkts: %d tx_free=%d tx_tail=%d tx_head=%d", + txq->port_id, txq->queue_id, nb_pkts, txq->tx_free, + txq->tx_tail, txq->tx_head); + + for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) { + tx_pkt = *tx_pkts++; + + /* Clean Tx queue if needed */ + if (txq->tx_free < txq->tx_free_thresh) + atl_xmit_cleanup(txq); + + /* Check if we have enough free descriptors */ + if (txq->tx_free < tx_pkt->nb_segs) + break; + + /* check mbuf is valid */ + if ((tx_pkt->nb_segs == 0) || + ((tx_pkt->nb_segs > 1) && (tx_pkt->next == NULL))) + break; + + /* Send the packet */ + atl_xmit_pkt(hw, txq, tx_pkt); + } + + PMD_TX_LOG(DEBUG, "atl_xmit_pkts %d transmitted", nb_tx); + + return nb_tx; } From patchwork Fri Oct 12 11:09:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46706 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 344361B5C0; Fri, 12 Oct 2018 13:09:35 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0071.outbound.protection.outlook.com [104.47.38.71]) by dpdk.org (Postfix) with ESMTP id 7EFD61B5B5 for ; Fri, 12 Oct 2018 13:09:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sXeHeyy0ayM6WBTGJ/pl+CAibh/ES1nx2/rPm0MSFy8=; b=ANhM2EYzuz7bEcUb3KVQPKgjunL/sIAzU6LX6ZFfD5YHk4IbbSK+qNP8bb6c46g7DnqRLsW878MYMWumlRyrV/Of21B3AHX6mpd4HfHxs/f9KgebPZ9SQt1UKTV+Teuk9Vz62bvs0EUE+kK9+PxjaWPhTVZGOOE68ATcVjUJ0EA= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:29 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:29 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 11/22] net/atlantic: add link status and interrupt management Thread-Index: AQHUYhwL9rJK6GGYpUGzyMw+lRdSWA== Date: Fri, 12 Oct 2018 11:09:29 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:WQ3YMRPLerYYLB2W/xz1of/tLV3NlyWYNHQZSWoh9gR7pRMa3TVmtiOCIHZ5PQ6t7nHM1F0SC8VpvflROeAXQCPzsVMRw44cpB47GlpFmARCyXWj48nt6fu9C/+bVjL35PPl1oDlql8/NwrAG9jmAq+D8dxLDl4Jd4k0eWNX/H4jp45dutZw0lP+vZirKbsXNbAXdAx8DWvs8jF7115YMaa9Ng2I6p6BdhU2e/TfpApHyflFS/P79QsYyv38HmLCa69PZgisUba/+gsL+jkKvQrmWEswr6+1sy3zJejkLGQ6/UEBB0T+g8x81zx5yT5CkFiWF1aYGGyRPKKAqbOIcw8ws11BDJECB1LS5UuCCnDtEY2bbTPa/BqwGY3kL1QRHGRbzVFe8qxtnPXZ7h7NsMvF+twlYZe5GySSrsZedobVF26yYli78jsblAcFlyAY5Rlyndty3/M6QNOSiMD+U8aC06gjckqVjX0YURA0yFE=; 5:EYfrf+k3cgN8o7Cuz8h4hT9/QB7d9+tATWBs+oEH0IabkbGxh+Nebvbq5ywqs7zxpbhGlKu6HkW6CDzrmh4CVd9uoFHultOVbRI/cjKbhz6Yfokw14Y/vDi6q3SmfVey6ETSiM+OgeKGO1/B/o+Pakkz9J6Us7wgkVvhxOE5oSE=; 7:fnlj1fUZdDwt0k1+KLueKCythh5r52dAbro+y5x8PUyxSRdZTUIse5KFvm4mzoqx3zoK9juAh2CAo2+OzcKl2szPctFU4k3wTwfohijKxKgKdj/X8WOzaldeGFAUwwii4wY54OtHKyZ8/a53TDzdFN/It81BbTBIYxiU+1v6rs0q5WgFoHowaq04tVGpbCnAzhIx8GPz2aWOT4NcxUMl3hcyc/FUUWSlhxoD4n7DdJo/AxkCx12htIPx0CIeKIfh x-ms-office365-filtering-correlation-id: 32c227a4-1ac4-4ea8-0e54-08d630332dc2 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(269456686620040); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(53946003)(5250100002)(11346002)(86362001)(575784001)(25786009)(4744004)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 2QBahycHmwinDul4rkK9tHOQ7nQesDhFgsAadcxLvOopOeFPUpuzUft85dTeYxiH9DcjcUSJqgs5MVQSJPEpFhio+ECpgmlGdWyOXJt8j5FDsV6j/c+ZZfkYg02kabjMk49x7+Gj6hayHOfazB0bFE9EUF/UByCzuXDkOW5luZlt32QyGlmuOGaHHxWIumYjlf7EOe0P+90n1mHaFUYLoiqEPooFlgy9E2nRqtGQKeQjPzpUflMdZU29wOnRMvVL13HSiLTf27hIchzfg4agUysN3n1G2R0T0HjwgBr0RJeypQvgJL5PJXcXU0LlnNLcJ9NhlyRqKLG0we7EGSG9Sv7T9whN1jgTEvkpnZ5dDf0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 32c227a4-1ac4-4ea8-0e54-08d630332dc2 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:29.5927 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 11/22] net/atlantic: add link status and interrupt management X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Implement link interrupt, link info, link polling. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 3 + drivers/net/atlantic/atl_ethdev.c | 411 +++++++++++++++++++++++++++++++++- drivers/net/atlantic/atl_ethdev.h | 16 ++ drivers/net/atlantic/atl_rxtx.c | 36 +++ drivers/net/atlantic/atl_types.h | 2 + 5 files changed, 466 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index 374cf9fb1061..f5650ae8f5f7 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -4,6 +4,9 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y +Link status = Y +Link status event = Y Queue start/stop = Y Jumbo frame = Y CRC offload = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 156f1be99cdf..b4f2326b4b9a 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -18,8 +18,11 @@ static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev); static int atl_dev_configure(struct rte_eth_dev *dev); static int atl_dev_start(struct rte_eth_dev *dev); static void atl_dev_stop(struct rte_eth_dev *dev); +static int atl_dev_set_link_up(struct rte_eth_dev *dev); +static int atl_dev_set_link_down(struct rte_eth_dev *dev); static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); +static int atl_dev_link_update(struct rte_eth_dev *dev, int wait); static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size); @@ -29,6 +32,16 @@ static void atl_dev_info_get(struct rte_eth_dev *dev, static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); +static void atl_dev_link_status_print(struct rte_eth_dev *dev); + +/* Interrupts */ +static int atl_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); +static int atl_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); +static int atl_dev_interrupt_get_status(struct rte_eth_dev *dev); +static int atl_dev_interrupt_action(struct rte_eth_dev *dev, + struct rte_intr_handle *handle); +static void atl_dev_interrupt_handler(void *param); + static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); @@ -70,7 +83,7 @@ static const struct rte_pci_id pci_id_atl_map[] = { static struct rte_pci_driver rte_atl_pmd = { .id_table = pci_id_atl_map, - .drv_flags = RTE_PCI_DRV_NEED_MAPPING | + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA, .probe = eth_atl_pci_probe, .remove = eth_atl_pci_remove, @@ -107,9 +120,14 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, .dev_stop = atl_dev_stop, + .dev_set_link_up = atl_dev_set_link_up, + .dev_set_link_down = atl_dev_set_link_down, .dev_close = atl_dev_close, .dev_reset = atl_dev_reset, + /* Link */ + .link_update = atl_dev_link_update, + .fw_version_get = atl_fw_version_get, .dev_infos_get = atl_dev_info_get, .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, @@ -124,6 +142,9 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .tx_queue_stop = atl_tx_queue_stop, .tx_queue_setup = atl_tx_queue_setup, .tx_queue_release = atl_tx_queue_release, + + .rx_queue_intr_enable = atl_dev_rx_queue_intr_enable, + .rx_queue_intr_disable = atl_dev_rx_queue_intr_disable, }; static inline int32_t @@ -132,12 +153,28 @@ atl_reset_hw(struct aq_hw_s *hw) return hw_atl_b0_hw_reset(hw); } +static inline void +atl_enable_intr(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_itr_irq_msk_setlsw_set(hw, 0xffffffff); +} + +static void +atl_disable_intr(struct aq_hw_s *hw) +{ + PMD_INIT_FUNC_TRACE(); + hw_atl_itr_irq_msk_clearlsw_set(hw, 0xffffffff); +} + static int eth_atl_dev_init(struct rte_eth_dev *eth_dev) { struct atl_adapter *adapter = (struct atl_adapter *)eth_dev->data->dev_private; struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); int err = 0; @@ -160,9 +197,17 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) /* Hardware configuration - hardcode */ adapter->hw_cfg.is_lro = false; adapter->hw_cfg.wol = false; + adapter->hw_cfg.link_speed_msk = AQ_NIC_RATE_10G | + AQ_NIC_RATE_5G | + AQ_NIC_RATE_2G5 | + AQ_NIC_RATE_1G | + AQ_NIC_RATE_100M; hw->aq_nic_cfg = &adapter->hw_cfg; + /* disable interrupt */ + atl_disable_intr(hw); + /* Allocate memory for storing MAC addresses */ eth_dev->data->mac_addrs = rte_zmalloc("atlantic", ETHER_ADDR_LEN, 0); if (eth_dev->data->mac_addrs == NULL) { @@ -179,12 +224,23 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) eth_dev->data->mac_addrs->addr_bytes) != 0) return -EINVAL; + rte_intr_callback_register(intr_handle, + atl_dev_interrupt_handler, eth_dev); + + /* enable uio/vfio intr/eventfd mapping */ + rte_intr_enable(intr_handle); + + /* enable support intr */ + atl_enable_intr(eth_dev); + return err; } static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) { + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; struct aq_hw_s *hw; PMD_INIT_FUNC_TRACE(); @@ -201,6 +257,11 @@ eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; + /* disable uio intr before callback unregister */ + rte_intr_disable(intr_handle); + rte_intr_callback_unregister(intr_handle, + atl_dev_interrupt_handler, eth_dev); + rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; @@ -222,8 +283,16 @@ eth_atl_pci_remove(struct rte_pci_device *pci_dev) } static int -atl_dev_configure(struct rte_eth_dev *dev __rte_unused) +atl_dev_configure(struct rte_eth_dev *dev) { + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + /* set flag to update link status after init */ + intr->flags |= ATL_FLAG_NEED_LINK_UPDATE; + return 0; } @@ -235,6 +304,11 @@ static int atl_dev_start(struct rte_eth_dev *dev) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + uint32_t intr_vector = 0; + uint32_t *link_speeds; + uint32_t speed = 0; int status; int err; @@ -243,6 +317,16 @@ atl_dev_start(struct rte_eth_dev *dev) /* set adapter started */ hw->adapter_stopped = 0; + if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { + PMD_INIT_LOG(ERR, + "Invalid link_speeds for port %u, fix speed not supported", + dev->data->port_id); + return -EINVAL; + } + + /* disable uio/vfio intr/eventfd mapping */ + rte_intr_disable(intr_handle); + /* reinitialize adapter * this calls reset and start */ @@ -253,6 +337,32 @@ atl_dev_start(struct rte_eth_dev *dev) err = hw_atl_b0_hw_init(hw, dev->data->mac_addrs->addr_bytes); hw_atl_b0_hw_start(hw); + /* check and configure queue intr-vector mapping */ + if ((rte_intr_cap_multiple(intr_handle) || + !RTE_ETH_DEV_SRIOV(dev).active) && + dev->data->dev_conf.intr_conf.rxq != 0) { + intr_vector = dev->data->nb_rx_queues; + if (intr_vector > ATL_MAX_INTR_QUEUE_NUM) { + PMD_INIT_LOG(ERR, "At most %d intr queues supported", + ATL_MAX_INTR_QUEUE_NUM); + return -ENOTSUP; + } + if (rte_intr_efd_enable(intr_handle, intr_vector)) { + PMD_INIT_LOG(ERR, "rte_intr_efd_enable failed"); + return -1; + } + } + + if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { + intr_handle->intr_vec = rte_zmalloc("intr_vec", + dev->data->nb_rx_queues * sizeof(int), 0); + if (intr_handle->intr_vec == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" + " intr_vec", dev->data->nb_rx_queues); + return -ENOMEM; + } + } + /* initialize transmission unit */ atl_tx_init(dev); @@ -275,6 +385,61 @@ atl_dev_start(struct rte_eth_dev *dev) goto error; } + err = hw->aq_fw_ops->update_link_status(hw); + + if (err) + goto error; + + dev->data->dev_link.link_status = hw->aq_link_status.mbps != 0; + + link_speeds = &dev->data->dev_conf.link_speeds; + + speed = 0x0; + + if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { + speed = hw->aq_nic_cfg->link_speed_msk; + } else { + if (*link_speeds & ETH_LINK_SPEED_10G) + speed |= AQ_NIC_RATE_10G; + if (*link_speeds & ETH_LINK_SPEED_5G) + speed |= AQ_NIC_RATE_5G; + if (*link_speeds & ETH_LINK_SPEED_1G) + speed |= AQ_NIC_RATE_1G; + if (*link_speeds & ETH_LINK_SPEED_2_5G) + speed |= AQ_NIC_RATE_2G5; + if (*link_speeds & ETH_LINK_SPEED_100M) + speed |= AQ_NIC_RATE_100M; + } + + err = hw->aq_fw_ops->set_link_speed(hw, speed); + if (err) + goto error; + + if (rte_intr_allow_others(intr_handle)) { + /* check if lsc interrupt is enabled */ + if (dev->data->dev_conf.intr_conf.lsc != 0) + atl_dev_lsc_interrupt_setup(dev, true); + else + atl_dev_lsc_interrupt_setup(dev, false); + } else { + rte_intr_callback_unregister(intr_handle, + atl_dev_interrupt_handler, dev); + if (dev->data->dev_conf.intr_conf.lsc != 0) + PMD_INIT_LOG(INFO, "lsc won't enable because of" + " no intr multiplex"); + } + + /* check if rxq interrupt is enabled */ + if (dev->data->dev_conf.intr_conf.rxq != 0 && + rte_intr_dp_is_en(intr_handle)) + atl_dev_rxq_interrupt_setup(dev); + + /* enable uio/vfio intr/eventfd mapping */ + rte_intr_enable(intr_handle); + + /* resume enabled intr since hw reset */ + atl_enable_intr(dev); + return 0; error: @@ -288,8 +453,16 @@ atl_dev_start(struct rte_eth_dev *dev) static void atl_dev_stop(struct rte_eth_dev *dev) { + struct rte_eth_link link; struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + + PMD_INIT_FUNC_TRACE(); + + /* disable interrupts */ + atl_disable_intr(hw); /* reset the NIC */ atl_reset_hw(hw); @@ -300,6 +473,46 @@ atl_dev_stop(struct rte_eth_dev *dev) /* Clear stored conf */ dev->data->scattered_rx = 0; dev->data->lro = 0; + + /* Clear recorded link status */ + memset(&link, 0, sizeof(link)); + rte_eth_linkstatus_set(dev, &link); + + if (!rte_intr_allow_others(intr_handle)) + /* resume to the default handler */ + rte_intr_callback_register(intr_handle, + atl_dev_interrupt_handler, + (void *)dev); + + /* Clean datapath event and queue/vec mapping */ + rte_intr_efd_disable(intr_handle); + if (intr_handle->intr_vec != NULL) { + rte_free(intr_handle->intr_vec); + intr_handle->intr_vec = NULL; + } +} + +/* + * Set device link up: enable tx. + */ +static int +atl_dev_set_link_up(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + return hw->aq_fw_ops->set_link_speed(hw, + hw->aq_nic_cfg->link_speed_msk); +} + +/* + * Set device link down: disable tx. + */ +static int +atl_dev_set_link_down(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + return hw->aq_fw_ops->set_link_speed(hw, 0); } /* @@ -383,6 +596,11 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_desc_lim = rx_desc_lim; dev_info->tx_desc_lim = tx_desc_lim; + + dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; + dev_info->speed_capa |= ETH_LINK_SPEED_100M; + dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; + dev_info->speed_capa |= ETH_LINK_SPEED_5G; } static const uint32_t * @@ -407,6 +625,195 @@ atl_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +/* return 0 means link status changed, -1 means not changed */ +static int +atl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct rte_eth_link link, old; + int err = 0; + + link.link_status = ETH_LINK_DOWN; + link.link_speed = 0; + link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_autoneg = hw->is_autoneg ? ETH_LINK_AUTONEG : ETH_LINK_FIXED; + memset(&old, 0, sizeof(old)); + + /* load old link status */ + rte_eth_linkstatus_get(dev, &old); + + /* read current link status */ + err = hw->aq_fw_ops->update_link_status(hw); + + if (err) + return 0; + + if (hw->aq_link_status.mbps == 0) { + /* write default (down) link status */ + rte_eth_linkstatus_set(dev, &link); + if (link.link_status == old.link_status) + return -1; + return 0; + } + + intr->flags &= ~ATL_FLAG_NEED_LINK_CONFIG; + + link.link_status = ETH_LINK_UP; + link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_speed = hw->aq_link_status.mbps; + + rte_eth_linkstatus_set(dev, &link); + + if (link.link_status == old.link_status) + return -1; + + return 0; +} + + +/** + * It clears the interrupt causes and enables the interrupt. + * It will be called once only during nic initialized. + * + * @param dev + * Pointer to struct rte_eth_dev. + * @param on + * Enable or Disable. + * + * @return + * - On success, zero. + * - On failure, a negative value. + */ + +static int +atl_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on __rte_unused) +{ + atl_dev_link_status_print(dev); + return 0; +} + +static int +atl_dev_rxq_interrupt_setup(struct rte_eth_dev *dev __rte_unused) +{ + return 0; +} + + +static int +atl_dev_interrupt_get_status(struct rte_eth_dev *dev) +{ + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + u64 cause = 0; + + hw_atl_b0_hw_irq_read(hw, &cause); + + atl_disable_intr(hw); + intr->flags = cause & BIT(ATL_IRQ_CAUSE_LINK) ? + ATL_FLAG_NEED_LINK_UPDATE : 0; + + return 0; +} + +/** + * It gets and then prints the link status. + * + * @param dev + * Pointer to struct rte_eth_dev. + * + * @return + * - On success, zero. + * - On failure, a negative value. + */ +static void +atl_dev_link_status_print(struct rte_eth_dev *dev) +{ + struct rte_eth_link link; + + memset(&link, 0, sizeof(link)); + rte_eth_linkstatus_get(dev, &link); + if (link.link_status) { + PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", + (int)(dev->data->port_id), + (unsigned int)link.link_speed, + link.link_duplex == ETH_LINK_FULL_DUPLEX ? + "full-duplex" : "half-duplex"); + } else { + PMD_DRV_LOG(INFO, " Port %d: Link Down", + (int)(dev->data->port_id)); + } + + +#ifdef DEBUG +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + + PMD_DRV_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, + pci_dev->addr.domain, + pci_dev->addr.bus, + pci_dev->addr.devid, + pci_dev->addr.function); +} +#endif + + PMD_DRV_LOG(INFO, "Link speed:%d", link.link_speed); +} + +/* + * It executes link_update after knowing an interrupt occurred. + * + * @param dev + * Pointer to struct rte_eth_dev. + * + * @return + * - On success, zero. + * - On failure, a negative value. + */ +static int +atl_dev_interrupt_action(struct rte_eth_dev *dev, + struct rte_intr_handle *intr_handle) +{ + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + + if (intr->flags & ATL_FLAG_NEED_LINK_UPDATE) { + atl_dev_link_update(dev, 0); + intr->flags &= ~ATL_FLAG_NEED_LINK_UPDATE; + atl_dev_link_status_print(dev); + _rte_eth_dev_callback_process(dev, + RTE_ETH_EVENT_INTR_LSC, NULL); + } + + atl_enable_intr(dev); + rte_intr_enable(intr_handle); + + return 0; +} + +/** + * Interrupt handler triggered by NIC for handling + * specific interrupt. + * + * @param handle + * Pointer to interrupt handle. + * @param param + * The address of parameter (struct rte_eth_dev *) regsitered before. + * + * @return + * void + */ +static void +atl_dev_interrupt_handler(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + + atl_dev_interrupt_get_status(dev); + atl_dev_interrupt_action(dev, dev->intr_handle); +} + RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 92bb302ffe55..55a7e0d6188c 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -16,6 +16,16 @@ #define ATL_DEV_TO_ADAPTER(dev) \ ((struct atl_adapter *)(dev)->data->dev_private) +#define ATL_DEV_PRIVATE_TO_INTR(adapter) \ + (&((struct atl_adapter *)adapter)->intr) + +#define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) +#define ATL_FLAG_NEED_LINK_CONFIG (uint32_t)(4 << 0) + +struct atl_interrupt { + uint32_t flags; + uint32_t mask; +}; /* * Structure to store private data for each driver instance (for each port). @@ -23,6 +33,7 @@ struct atl_adapter { struct aq_hw_s hw; struct aq_hw_cfg_s hw_cfg; + struct atl_interrupt intr; }; /* @@ -40,6 +51,11 @@ int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, uint16_t nb_tx_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); +int atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, + uint16_t queue_id); +int atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, + uint16_t queue_id); + int atl_rx_init(struct rte_eth_dev *dev); int atl_tx_init(struct rte_eth_dev *dev); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 1d4c8099325d..36141564f5c1 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -651,6 +651,42 @@ atl_stop_queues(struct rte_eth_dev *dev) return 0; } +static int +atl_rx_enable_intr(struct rte_eth_dev *dev, uint16_t queue_id, bool enable) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_rx_queue *rxq; + + PMD_INIT_FUNC_TRACE(); + + if (queue_id >= dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Invalid RX queue id=%d", queue_id); + return -EINVAL; + } + + rxq = dev->data->rx_queues[queue_id]; + + if (rxq == NULL) + return 0; + + /* Mapping interrupt vector */ + hw_atl_itr_irq_map_en_rx_set(hw, enable, queue_id); + + return 0; +} + +int +atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t queue_id) +{ + return atl_rx_enable_intr(eth_dev, queue_id, true); +} + +int +atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, uint16_t queue_id) +{ + return atl_rx_enable_intr(eth_dev, queue_id, false); +} + uint16_t atl_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 37ad43a110f0..e636464955e3 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -86,11 +86,13 @@ struct aq_hw_s { void *mmio; struct aq_hw_link_status_s aq_link_status; + bool is_autoneg; struct hw_aq_atl_utils_mbox mbox; struct hw_atl_stats_s last_stats; struct aq_stats_s curr_stats; + u64 speed; unsigned int chip_features; u32 fw_ver_actual; u32 mbox_addr; From patchwork Fri Oct 12 11:09:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46707 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C537C1B56A; Fri, 12 Oct 2018 13:09:39 +0200 (CEST) Received: from NAM05-BY2-obe.outbound.protection.outlook.com (mail-eopbgr710053.outbound.protection.outlook.com [40.107.71.53]) by dpdk.org (Postfix) with ESMTP id 9626D1B5BC for ; Fri, 12 Oct 2018 13:09:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CY4p1rRoEkqIFbyy9+UT56QTPeHNaHtEprHnLGNNzpI=; b=EZDc5bONDkxtUHh84hkLWMz+3nfZpb+o1BUKhTLP6z/UqIORuElsMtMZ/9nJjKN7tIyvGpdaiiAFXI3eg6iQndgGAp0XcQDx94DXbXWpX/0GAbumg4spFQikanHJY8lOj1HbQzIe31xiqTDburRO1dBuixtQc6iQNgV7ZnwSPaI= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:32 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:32 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 12/22] net/atlantic: implement device statistics Thread-Index: AQHUYhwMzbIIwzvxD0G9gMGzLLaG9g== Date: Fri, 12 Oct 2018 11:09:31 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:A0Ek+FkXY91TpdrSnJVndRG79n1Gj1zdvBH6O42mpXgyWfZZgI/9vjTj4WszgSWPs2tJOH3PVLbv+nXxJ1ImOyb42cqDTukik/VNGhUM2G2L2MmCTRiQRRMWGfqDO6niMfNXwHE8A7s+opsXkOP5zmr3dtYrCsSKWcWfos/2kYQYYvk1pewVlfHpZTdF95aUJhh/dFTEQ/Ox6Lt+7B5+KM58JLmH2qh5UggEBq71hyuKXPITaXo3azE+47tXlXxw4YZIcEek1KmyOWy+CCDdcgry11q30w6feJ0Y+Bjcol/Tbqo4KRqm5RAM8KLFawKiHXwKt9apyZrCwVIru050zReg/cL2HR+oJniaxUCZQIo+QZaWIT6HM1uYS5YSllaHYJtpXmq+mLmYmBPXpZ9f9u292lCw9L7nniv2MepTZ+5EXhE5q5BC5ibYzkZp9ZHHA1Rtd4ECQVOLXMbfRc5iT6wQ/X3dU2UDsLGkHGHyHx4=; 5:OarsC8ccmcR4ezvV0ikXOM+3zq0Zmjw0ftqPqQqqXOX7eYQNyYQghhF/XRf0uA7DGiD6OJRovGRLQihgenBAQW8O+2v/DuxhqNLsqphzKTf+Mh8KC0ux61ghcIsunHS/du9RqJRz1fW8a5LdSkwNMpHoyIXirGTdIPh5/Z3PGnA=; 7:cpes9ad7qM7eEZE5lTWpznSPDvdikCl8uwf0CdS+EefRrpL3p2KMK8+ZyXYnVAKsAS3cvW/ZsxFLaD+0s0paumteuamA03i75oQwzfnNKMzEYsBTadyt5j5KIpr3RXqWaZWwIkHtRDe9xaDzyOG5UHREURQNkIvjxHnD/vgjeD+iTHukRCeIGh5FGWrArycAURzCxz/pNNtKsPEczUdxl9enpAdAluSH0WlHU9UviTZZS8DWqGn23LlqrqB91pj5 x-ms-office365-filtering-correlation-id: 8581b173-afb7-41c4-d0a6-08d630332f2d x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(979002)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(575784001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: xULOXtH1ou0li9S20hPG+axkcRn0KFkbmJmwSBl9YLl0i4FQ6wnX5lQPMVNQhz145avTRPPohyUvsEbS96S+CFO9FvdwKSPDacxOkQi9IdF1k9ZQV+Nhd426TgSf9fOOypck8i/nV64/8VtE+mfW7Anl+MsD5bAu1Zkm79dtakO1+uNfRh93iwgaMJtLN1gXuJ9J/l3V1XRyXrz+ddn2HU1jlgVLNc9y1CJ00fPU/iKbAsArSm7bGe1PHFEVJqZx01p4dBBJX7fj9o4Sj7ct18LJ2MAl9QIB5d5vGN/W4ZTwQd4NAQBaq/9p8uuYMrThy9XfPRvK4vrFcS09LBe/S+5LQr/UiF69qo0JU67PqY4= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8581b173-afb7-41c4-d0a6-08d630332f2d X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:31.8425 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 12/22] net/atlantic: implement device statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add support for device stats, xstats and queue stats Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/atlantic.rst | 1 + doc/guides/nics/features/atlantic.ini | 3 + drivers/net/atlantic/atl_ethdev.c | 133 ++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_ethdev.h | 1 + drivers/net/atlantic/atl_rxtx.c | 11 ++- drivers/net/atlantic/atl_types.h | 41 +++++++++++ 6 files changed, 189 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/atlantic.rst b/doc/guides/nics/atlantic.rst index a003ef5110c9..1108d458f836 100644 --- a/doc/guides/nics/atlantic.rst +++ b/doc/guides/nics/atlantic.rst @@ -13,6 +13,7 @@ Supported features ^^^^^^^^^^^^^^^^^^ - Base L2 features +- Port statistics - Checksum offload - Jumbo Frame upto 16K diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index f5650ae8f5f7..4056d4daacc8 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -13,6 +13,9 @@ CRC offload = Y L3 checksum offload = Y L4 checksum offload = Y Packet type parsing = Y +Basic stats = Y +Extended stats = Y +Stats per queue = Y FW version = Y Linux UIO = Y ARMv8 = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index b4f2326b4b9a..b1e7e3030d57 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -24,6 +24,18 @@ static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); static int atl_dev_link_update(struct rte_eth_dev *dev, int wait); +static int atl_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_xstat_name *xstats_names, + unsigned int size); + +static int atl_dev_stats_get(struct rte_eth_dev *dev, + struct rte_eth_stats *stats); + +static int atl_dev_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *stats, unsigned int n); + +static void atl_dev_stats_reset(struct rte_eth_dev *dev); + static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size); @@ -116,6 +128,33 @@ static const struct rte_eth_desc_lim tx_desc_lim = { .nb_mtu_seg_max = ATL_TX_MAX_SEG, }; +#define ATL_XSTATS_FIELD(name) { \ + #name, \ + offsetof(struct aq_stats_s, name) \ +} + +struct atl_xstats_tbl_s { + const char *name; + unsigned int offset; +}; + +static struct atl_xstats_tbl_s atl_xstats_tbl[] = { + ATL_XSTATS_FIELD(uprc), + ATL_XSTATS_FIELD(mprc), + ATL_XSTATS_FIELD(bprc), + ATL_XSTATS_FIELD(erpt), + ATL_XSTATS_FIELD(uptc), + ATL_XSTATS_FIELD(mptc), + ATL_XSTATS_FIELD(bptc), + ATL_XSTATS_FIELD(erpr), + ATL_XSTATS_FIELD(ubrc), + ATL_XSTATS_FIELD(ubtc), + ATL_XSTATS_FIELD(mbrc), + ATL_XSTATS_FIELD(mbtc), + ATL_XSTATS_FIELD(bbrc), + ATL_XSTATS_FIELD(bbtc), +}; + static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, @@ -128,6 +167,13 @@ static const struct eth_dev_ops atl_eth_dev_ops = { /* Link */ .link_update = atl_dev_link_update, + /* Stats */ + .stats_get = atl_dev_stats_get, + .xstats_get = atl_dev_xstats_get, + .xstats_get_names = atl_dev_xstats_get_names, + .stats_reset = atl_dev_stats_reset, + .xstats_reset = atl_dev_stats_reset, + .fw_version_get = atl_fw_version_get, .dev_infos_get = atl_dev_info_get, .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, @@ -224,6 +270,9 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) eth_dev->data->mac_addrs->addr_bytes) != 0) return -EINVAL; + /* Reset the hw statistics */ + atl_dev_stats_reset(eth_dev); + rte_intr_callback_register(intr_handle, atl_dev_interrupt_handler, eth_dev); @@ -542,6 +591,90 @@ atl_dev_reset(struct rte_eth_dev *dev) return ret; } + +static int +atl_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +{ + struct atl_adapter *adapter = ATL_DEV_TO_ADAPTER(dev); + struct aq_hw_s *hw = &adapter->hw; + struct atl_sw_stats *swstats = &adapter->sw_stats; + unsigned int i; + + hw->aq_fw_ops->update_stats(hw); + + /* Fill out the rte_eth_stats statistics structure */ + stats->ipackets = hw->curr_stats.dma_pkt_rc; + stats->ibytes = hw->curr_stats.dma_oct_rc; + stats->imissed = hw->curr_stats.dpc; + stats->ierrors = hw->curr_stats.erpt; + + stats->opackets = hw->curr_stats.dma_pkt_tc; + stats->obytes = hw->curr_stats.dma_oct_tc; + stats->oerrors = 0; + + stats->rx_nombuf = swstats->rx_nombuf; + + for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { + stats->q_ipackets[i] = swstats->q_ipackets[i]; + stats->q_opackets[i] = swstats->q_opackets[i]; + stats->q_ibytes[i] = swstats->q_ibytes[i]; + stats->q_obytes[i] = swstats->q_obytes[i]; + stats->q_errors[i] = swstats->q_errors[i]; + } + return 0; +} + +static void +atl_dev_stats_reset(struct rte_eth_dev *dev) +{ + struct atl_adapter *adapter = ATL_DEV_TO_ADAPTER(dev); + struct aq_hw_s *hw = &adapter->hw; + + hw->aq_fw_ops->update_stats(hw); + + /* Reset software totals */ + memset(&hw->curr_stats, 0, sizeof(hw->curr_stats)); + + memset(&adapter->sw_stats, 0, sizeof(adapter->sw_stats)); +} + +static int +atl_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_xstat_name *xstats_names, + unsigned int size) +{ + unsigned int i; + + if (!xstats_names) + return RTE_DIM(atl_xstats_tbl); + + for (i = 0; i < size && i < RTE_DIM(atl_xstats_tbl); i++) + snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s", + atl_xstats_tbl[i].name); + + return size; +} + +static int +atl_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, + unsigned int n) +{ + struct atl_adapter *adapter = ATL_DEV_TO_ADAPTER(dev); + struct aq_hw_s *hw = &adapter->hw; + unsigned int i; + + if (!stats) + return 0; + + for (i = 0; i < n && i < RTE_DIM(atl_xstats_tbl); i++) { + stats[i].id = i; + stats[i].value = *(u64 *)((uint8_t *)&hw->curr_stats + + atl_xstats_tbl[i].offset); + } + + return n; +} + static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) { diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 55a7e0d6188c..dc48c134b7b8 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -33,6 +33,7 @@ struct atl_interrupt { struct atl_adapter { struct aq_hw_s hw; struct aq_hw_cfg_s hw_cfg; + struct atl_sw_stats sw_stats; struct atl_interrupt intr; }; diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 36141564f5c1..c51d24d74ed2 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -874,7 +874,8 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) "queue_id=%u", (unsigned int)rxq->port_id, (unsigned int)rxq->queue_id); dev->data->rx_mbuf_alloc_failed++; - goto err_stop; + adapter->sw_stats.rx_nombuf++; + goto err_stop; } nb_hold++; @@ -957,6 +958,9 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) * of returned packets. */ rx_pkts[nb_rx++] = rx_mbuf_first; + adapter->sw_stats.q_ipackets[rxq->queue_id]++; + adapter->sw_stats.q_ibytes[rxq->queue_id] += + rx_mbuf_first->pkt_len; PMD_RX_LOG(ERR, "add mbuf segs=%d pkt_len=%d", rx_mbuf_first->nb_segs, @@ -1102,6 +1106,8 @@ static inline void atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq, struct rte_mbuf *tx_pkt) { + struct atl_adapter *adapter = + ATL_DEV_TO_ADAPTER(&rte_eth_devices[txq->port_id]); uint32_t pay_len = 0; int tail = 0; struct atl_tx_entry *tx_entry; @@ -1182,6 +1188,9 @@ atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq, txq->tx_tail = tail; txq->tx_free -= desc_count; + + adapter->sw_stats.q_opackets[txq->queue_id]++; + adapter->sw_stats.q_obytes[txq->queue_id] += pay_len; } uint16_t diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index e636464955e3..56887b14d6f8 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -140,4 +140,45 @@ struct aq_fw_ops { int (*set_eeprom)(struct aq_hw_s *self, u32 *data, u32 len); }; +struct atl_sw_stats { + u64 crcerrs; + u64 errbc; + u64 mspdc; + u64 mpctotal; + u64 mpc[8]; + u64 mlfc; + u64 mrfc; + u64 rlec; + u64 lxontxc; + u64 lxonrxc; + u64 lxofftxc; + u64 lxoffrxc; + u64 pxontxc[8]; + u64 pxonrxc[8]; + u64 pxofftxc[8]; + u64 pxoffrxc[8]; + u64 gprc; + u64 bprc; + u64 mprc; + u64 gptc; + u64 gorc; + u64 gotc; + u64 tor; + u64 tpr; + u64 tpt; + u64 mptc; + u64 bptc; + u64 xec; + u64 fccrc; + u64 ldpcec; + u64 pcrc8ec; + + u64 rx_nombuf; + u64 q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS]; +}; + #endif From patchwork Fri Oct 12 11:09:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46708 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F2F6D1B5DD; Fri, 12 Oct 2018 13:09:41 +0200 (CEST) Received: from NAM05-BY2-obe.outbound.protection.outlook.com (mail-eopbgr710074.outbound.protection.outlook.com [40.107.71.74]) by dpdk.org (Postfix) with ESMTP id C69BC1B56A for ; Fri, 12 Oct 2018 13:09:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=unLqF8f6HT5e2yEwDE7Sa8kBuv9VZ+S+9p7Kln5bYs4=; b=uULxDDiRw+dUACw2TWOJ2T69bxRx7qhWHwXHvwNNjJi4vW2Sa5H6XDWZtPvV2cF8lsYVxYlydSNl447QKfp3AMM7WsLoAx4fDKhR8cpGGwgoje6DomIuzFuY2v0p7DZ4Ggrc/raMqoQNC35Gkp3D/XYBz0rZQ5uNoKGjxDFB1XY= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:34 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:34 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 13/22] net/atlantic: add Rx/Tx descriptors information Thread-Index: AQHUYhwO7AVU68Oue0KRqzxC9JHeOw== Date: Fri, 12 Oct 2018 11:09:34 +0000 Message-ID: <7ed423b17c3744aff458e0d518eb6a698ca8dfd2.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:pocj0YPjCrcT94eiF1vfPoaZeWyvBTyEdDdvCsxiGAyxMKFemIsiW9BYFA2y6mEjPvK9mHL3RdfOuFjprp6fXk9rpQWI+Lr+EwhyDhUt5/2vl10qN+dpLbC0flPEQD+cSVt5N1H8iwmlLN+t2mJrzTEaP7o2R87ggmQQnujLHvGTDUWnntnA+opK8vjLJla+crVSMbb1b7VGXTJzMsFDHJUkjhLJA/qObiF/+xNvgH7lwTCZ4ySw7NjsXYzgzUL3UQi4Kds7J7iVZQ8RkoldNCM/9u4cuQoyDD05p8GLxPLH9cHovQVFpUWxd+oT/BTxBQ0GkR43zLiBa/SAxdLKvl0+Af/58/i+fDd5Zra10THiwnjKBcRCg2hfVraEZqr9AYwiYw0A6f/J5GLHJ91KbYtvLQcZz1Y/P1nM75I5bM3SyD6y+JQP627jPGcaGX7+Tmdl/H5epJ+qlMDgq25K4Q==; 5:V/DBQXAe/a7slQIZlLODFDCyYpDmjndCYEIWPKV0Tsup42Xwhflm4uhUeOrigz0q8TqndwRMGik3mslJTj0V+8/yvN4lEy8CI06SHFvsbqom4BKW7eGqAnZpzPVAwuaf2eJBUNN2liDsUq2VoSVlSOMPLEcdhImfsfNdhbaL188=; 7:+eL00eWSJt1niheyegjkY2t3aeRx/CWQz+7c5xR1afl4RLE1o7kzANofv0Cpe34zVJb2Lh0sgdDFs9RDCDowPtoZXbc+UmoxSuVAUC+Jqd1U5fL8dCh5q+CbHUBtvXDaQH0s7FqlpxzJfIb5n9AgAaNFTLp8c2yNqW7onbX8d5aak7cOQc0KcUFSUiT1tgd18MlhOpt/ul43NX1dkDQnawRhJTi1DrEwVx2dK7Bqqkc8kyX/qHjcfuBlVEs3bsMh x-ms-office365-filtering-correlation-id: 9043b760-831c-49fc-a6c4-08d630333084 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: l7+Uf0fRbF+QFO9FMI3gq0bVlA1mpukzxc+U1Zx29YtPgJ6HfcyklWfYt4XpNvY8GBx32CuULsRArOj4W6SgRLm1f6UAJUrNJ9T/uNojx9kFdZXJ7QaB40zGxo9Km22YWZr/GXX0LsizVHTDzRwnzlmkNcdlfFc9FDRNXrVH3qW5PgZ0RojXpof2PeUy/nq+eZ5A4uKhlWaJS72bGWFoG/Rcov1nkzhs2A5wnjCOYl6nvPgUSSyp29qFvWJiuVQ9AO6oLvYA7VUWTvdpfkPA7/8i4Tf6RTpF+mF9aveRySoIN7YzLntDqINHsPCUiBydYZ56CsUd468UtScWJY4n1vplvGz7BTF5kgLwbWPNSno= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9043b760-831c-49fc-a6c4-08d630333084 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:34.0393 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 13/22] net/atlantic: add Rx/Tx descriptors information X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add support for Rx/Tx descriptors status information. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 2 + drivers/net/atlantic/atl_ethdev.c | 7 +++ drivers/net/atlantic/atl_ethdev.h | 11 ++++ drivers/net/atlantic/atl_rxtx.c | 103 ++++++++++++++++++++++++++++++++++ 4 files changed, 123 insertions(+) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index 4056d4daacc8..cea9787ba1a9 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -13,6 +13,8 @@ CRC offload = Y L3 checksum offload = Y L4 checksum offload = Y Packet type parsing = Y +Rx descriptor status = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index b1e7e3030d57..d76d071dc3e7 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -191,6 +191,13 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_queue_intr_enable = atl_dev_rx_queue_intr_enable, .rx_queue_intr_disable = atl_dev_rx_queue_intr_disable, + + .rx_queue_count = atl_rx_queue_count, + .rx_descriptor_status = atl_dev_rx_descriptor_status, + .tx_descriptor_status = atl_dev_tx_descriptor_status, + + .rxq_info_get = atl_rxq_info_get, + .txq_info_get = atl_txq_info_get, }; static inline int32_t diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index dc48c134b7b8..c315e0436dca 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -52,6 +52,11 @@ int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, uint16_t nb_tx_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); +uint32_t atl_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); + +int atl_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); +int atl_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); + int atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t queue_id); int atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, @@ -70,6 +75,12 @@ int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); int atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); int atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); +void atl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_rxq_info *qinfo); + +void atl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo); + uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index c51d24d74ed2..fbd50a766098 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -651,6 +651,109 @@ atl_stop_queues(struct rte_eth_dev *dev) return 0; } +void +atl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_rxq_info *qinfo) +{ + struct atl_rx_queue *rxq; + + PMD_INIT_FUNC_TRACE(); + + rxq = dev->data->rx_queues[queue_id]; + + qinfo->mp = rxq->mb_pool; + qinfo->scattered_rx = dev->data->scattered_rx; + qinfo->nb_desc = rxq->nb_rx_desc; +} + +void +atl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo) +{ + struct atl_tx_queue *txq; + + PMD_INIT_FUNC_TRACE(); + + txq = dev->data->tx_queues[queue_id]; + + qinfo->nb_desc = txq->nb_tx_desc; +} + +/* Return Rx queue avail count */ + +uint32_t +atl_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct atl_rx_queue *rxq; + + PMD_INIT_FUNC_TRACE(); + + if (rx_queue_id >= dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id); + return 0; + } + + rxq = dev->data->rx_queues[rx_queue_id]; + + if (rxq == NULL) + return 0; + + return rxq->nb_rx_desc - rxq->nb_rx_hold; +} + +int +atl_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + struct atl_rx_queue *rxq = rx_queue; + struct hw_atl_rxd_wb_s *rxd; + uint32_t idx; + + PMD_INIT_FUNC_TRACE(); + + if (unlikely(offset >= rxq->nb_rx_desc)) + return -EINVAL; + + if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + + idx = rxq->rx_tail + offset; + + if (idx >= rxq->nb_rx_desc) + idx -= rxq->nb_rx_desc; + + rxd = (struct hw_atl_rxd_wb_s *)&rxq->hw_ring[idx]; + + if (rxd->dd) + return RTE_ETH_RX_DESC_DONE; + + return RTE_ETH_RX_DESC_AVAIL; +} + +int +atl_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + struct atl_tx_queue *txq = tx_queue; + struct hw_atl_txd_s *txd; + uint32_t idx; + + PMD_INIT_FUNC_TRACE(); + + if (unlikely(offset >= txq->nb_tx_desc)) + return -EINVAL; + + idx = txq->tx_tail + offset; + + if (idx >= txq->nb_tx_desc) + idx -= txq->nb_tx_desc; + + txd = &txq->hw_ring[idx]; + + if (txd->dd) + return RTE_ETH_TX_DESC_DONE; + + return RTE_ETH_TX_DESC_FULL; +} + static int atl_rx_enable_intr(struct rte_eth_dev *dev, uint16_t queue_id, bool enable) { From patchwork Fri Oct 12 11:09:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46709 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AA5CF1B5E7; Fri, 12 Oct 2018 13:09:43 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0055.outbound.protection.outlook.com [104.47.38.55]) by dpdk.org (Postfix) with ESMTP id 000BF1B568 for ; Fri, 12 Oct 2018 13:09:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cjwFIEugipm1Q3BjFlTBrbesqziZ66TlOM8bWSBEops=; b=Wh2jWkRvoxQ9hq4MqQ8MOeWv98uvdXisSsOxAbx4jvdp0JEnT3/fk8Oa5QMr9SUeAJfsI74pAX+cMc44nwrkg77FIHG1Hi0D6UAzw+Vitr3/eu0uLXz1T4uX3pv//mb98IemGjBJQog+54yWElXGRxgxSr9w2EWfRA+i0r+f0fE= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:36 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:36 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 14/22] net/atlantic: implement promisc and allmulti modes Thread-Index: AQHUYhwPe4jihf+4yki85c0yRSCIjw== Date: Fri, 12 Oct 2018 11:09:36 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:rTNQfPodsoPxfS6AFU9oqQb6UOOcNq5FoZOhM+5wXxZJg4hFYWoiJYh5rBQ0l/4hd23ox1l6Vk2AGnJIdHPgR74mrN2g4QFraL/88U2nwb9cFf4Quw6z9ZyyomPypugU0zsX6Grc83t7XV4JU6RC3956kT4zxczQEkoBLLVyuQEHELfYFS88Lw/WWZj7a8n2sq39k3kc+KtTO7PAKAFLkvSZGajQhrAfIKN21/es6Lr6QjDriRV/o6MxlQzxwwyA3rIpjXCMEkyCYxHf0hbqLk1Ab4JTngn6GinZXx5L6k4tLkUqEabfQ/vPhxNEEg6u7ojruUgteuwNs27SkZDoAB4FEEMcKK2+/M+O5IujmceR9jbVon3aJn8aKSD+SrBhoDjHwEEQ2LV4piOp6Xdq4LCqoNA/gxavTGogkUNEDk/JplLs92Djz+n+rvY9dz2CpNsg23XH1dXyVuwTbb9vevaeozD7lrynFFlTY795QUE=; 5:vX7s9d+zL7BoaAVx/8spEu1D/vEn4peF6WcHavq3yivGAzA0gLhnuvuIuAtpOFuSJKGJL4F7XqOePTt73KSzVOuUftStND+QFJpUdAjiOptYpmpYh28RHjAaomSzNV7E2Cew62hsG3TI+BJh3X/vP3rvx2K4c6bl03uu7Icfeh0=; 7:ts4TCNPIpT3Tn9x9idDFMBpbL9LEg7z4OlUwnvGuN9OEu+xwgZ3xOx4hT3oLuB+k/LTuLj83BU2pUkKZZKcqlOk9K0qTJ8m4ClefaVBsvQ6PSWnDsrV1/BSSt6Dx4C2s5gq9J89dmEzEmKAYhAG10wNfnnQc6LCH0pP1F3wD+o/4UojN8N50rKTx8FHcBPus8U2uKxErPMia2S6nXUBcg/fYKItXhIkaZxy7RPeyd31veD/I1W1Q6vrxFKjP4Cxc x-ms-office365-filtering-correlation-id: e25ef704-b00d-4c6b-ec21-08d6303331d4 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 75MgCZX+x6w1nI7RkChrkshMvyGVqUgvz/EDweYy6je6y4TL+L0QR9NU4jaE61WXayx+YxpdtinEWZz/Vx4mxc8EPvORm+8b5wY6IbiI91kusoEAVzU3N29Ls0as58IE7JpT8ccAIxid32E+jsUQkftnaJJmN9Iexg+ATpY0D/fKXyl41M27+D77sLhT90Pk32zjoDUFIx2t2t1rnqbVxhLfFSaz6E+jBlzmsH/2njdrz9jWL/H+ZTtyzqbvb28+2bo7o/mgNDRpkYzFZYDKvjDuBAqUvvJ6lAY5qeVy6EvDPmjdUllpXvUPWtTSRy9o8PJ/tiOlBkuYX4t48Fa2F0cU05rlDoIxO0TP9kIjcyI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e25ef704-b00d-4c6b-ec21-08d6303331d4 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:36.2101 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 14/22] net/atlantic: implement promisc and allmulti modes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add support for promiscuous/allmulticast modes configuration. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/atlantic.rst | 2 ++ doc/guides/nics/features/atlantic.ini | 2 ++ drivers/net/atlantic/atl_ethdev.c | 44 +++++++++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/doc/guides/nics/atlantic.rst b/doc/guides/nics/atlantic.rst index 1108d458f836..b09c79babdf4 100644 --- a/doc/guides/nics/atlantic.rst +++ b/doc/guides/nics/atlantic.rst @@ -13,6 +13,8 @@ Supported features ^^^^^^^^^^^^^^^^^^ - Base L2 features +- Promiscuous mode +- Multicast mode - Port statistics - Checksum offload - Jumbo Frame upto 16K diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index cea9787ba1a9..347ac80a1ceb 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -9,6 +9,8 @@ Link status = Y Link status event = Y Queue start/stop = Y Jumbo frame = Y +Promiscuous mode = Y +Allmulticast mode = Y CRC offload = Y L3 checksum offload = Y L4 checksum offload = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index d76d071dc3e7..5223b57ebd83 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -22,6 +22,10 @@ static int atl_dev_set_link_up(struct rte_eth_dev *dev); static int atl_dev_set_link_down(struct rte_eth_dev *dev); static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); +static void atl_dev_promiscuous_enable(struct rte_eth_dev *dev); +static void atl_dev_promiscuous_disable(struct rte_eth_dev *dev); +static void atl_dev_allmulticast_enable(struct rte_eth_dev *dev); +static void atl_dev_allmulticast_disable(struct rte_eth_dev *dev); static int atl_dev_link_update(struct rte_eth_dev *dev, int wait); static int atl_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, @@ -164,6 +168,12 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_close = atl_dev_close, .dev_reset = atl_dev_reset, + /* PROMISC */ + .promiscuous_enable = atl_dev_promiscuous_enable, + .promiscuous_disable = atl_dev_promiscuous_disable, + .allmulticast_enable = atl_dev_allmulticast_enable, + .allmulticast_disable = atl_dev_allmulticast_disable, + /* Link */ .link_update = atl_dev_link_update, @@ -812,6 +822,40 @@ atl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused) return 0; } +static void +atl_dev_promiscuous_enable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_rpfl2promiscuous_mode_en_set(hw, true); +} + +static void +atl_dev_promiscuous_disable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_rpfl2promiscuous_mode_en_set(hw, false); +} + +static void +atl_dev_allmulticast_enable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_rpfl2_accept_all_mc_packets_set(hw, true); +} + +static void +atl_dev_allmulticast_disable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (dev->data->promiscuous == 1) + return; /* must remain in all_multicast mode */ + + hw_atl_rpfl2_accept_all_mc_packets_set(hw, false); +} /** * It clears the interrupt causes and enables the interrupt. From patchwork Fri Oct 12 11:09:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46710 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DE0911B5FB; Fri, 12 Oct 2018 13:09:45 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0066.outbound.protection.outlook.com [104.47.38.66]) by dpdk.org (Postfix) with ESMTP id 54C8F1B5B5 for ; Fri, 12 Oct 2018 13:09:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XRuDutG4apzBt6hInGOwMb4DYuucerGYEwhhLngUcDQ=; b=CmNJoSi2STD1ZJFe3htrQh6CD9YryFPDr+wjWkcr+HdY53GY2rh9DvTaLqiIWWi+DySlnYQIdmnE3PVJRzIDjQya61t5VxNm/XfpVMTZfyCeJ4wVScBQ9QANEU7LnZ0ipHF7GAYKAPWOK+7gcwxZXVU/9bWelpdpSMqa46Pw5NI= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:38 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:38 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 15/22] net/atlantic: implement RSS and RETA manipulation API Thread-Index: AQHUYhwR90kEsOYWZ0S7PCAGU/CPGA== Date: Fri, 12 Oct 2018 11:09:38 +0000 Message-ID: <2f0052e401a50913d2706875895d078010c4bece.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:P6JIu8ysIR+pe3h7ZYCvXeO6ZNBsMwt0DA2r7csQIisGQe9okrXfXuTEbAc8qA28AuqnOzyt7HBlCOUY2YJKqOaPSaDW6MJ3RErNNf4UIh0xWxgxvVuai6JDz9mu2S+D51qGilAKxTT/cBKd93b3HWIFMG/UqdKo56Md7jTQz5Ex5FYkxT0rpQHD+zhN6aQsjEfe7o6SbZKu6fkdLcv5NAi5MZRMT1/4q0bJonvmLLeNW14Lag6JhJGBA15rJru8UyEFc3gEMRxV7n+/v7s8uNToBQRicnkVGJRQ5jpbECokMrk3LtvVAvnSIE5ZeqLk8HGOeqYn7/NfT1JpyNxY7vVfuubSHIUX6zOwNI3vT52m0gk2UNclpcjLe/pGHY9k5wy03/lvTuQPz+rFFZ8lShbc4KhCHrHM4t9eFNsoRq4GojUIqpu9bUGl7dNzkOwgegcS66s65PdIjiU94M7/A3/QYN3qZdi3JBwvu/kWiMY=; 5:YFdWMuw4KgDXyjHScG4bDkV6uFtewJOeOyA1TyULduPdOMEnFRIWhnv8uZ7CzDEY7s910JPAQ1GxFbeTjV5k7s0P0qN6t7EtMDTXzaYpPYylAQMINHUE1Ose4wBuv5Mqtl9KSWzM/FikL5d814cFMiJad+PrIEJOhInZbI2TorA=; 7:icgn4tJhfB9z76Ecg9DITWG1DxnA/qJ4zwEdLL7rNJBrTR9BWkPyCuDJIfM9rudiIwJLLdzVSN7iVYOeom8Uv2uRVYaqnF+wUsf+U6PHixNiNK23qYphgkyxd4jgTkckNeDHDLy6TA/3nnab1VZ1UrjtWkYxV2IjRkLjBMfGMbycF+wqHiYjCfWp+FQj+oWjb3qk76P+a1AD19rzTxVuxPjes+phZ4IBgFfzyalWW/ydYshEOzzFZUp+CYiur1VQ x-ms-office365-filtering-correlation-id: ebbf6024-f890-46c5-825b-08d63033334d x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(575784001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011)(309714004); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 1DqFiBzVjQNyymdBHvs+FJuxTwJBU1s8yHML6yfqvI6wuIHCD21vrBmjREctMyKap6NPd2oIett4ke1aeK1mbG2yVDJ3L/HvLo10VehkjGgw1PKrMEddHPXS3+vEIXSAtPEoxSLIb0cshj8rxKSuNe+IxPoS/E+Rd0hzP9sliRyZIlHm/JrJnQLkjiCVH81U/316KssvGW78PP7UYdaerIQHQR6xJ9SSY/w9IF0P/YKYt5UptZ09DYf9svLWW9tUWKPR4eZ1XGeNbmEDpe5sJi3OHzQnaA/eAdt5R6qeu7bttom9NpCd1/C+0pDmJjTSQRzj8UD3T1igLNn2HDcc85kcUE3t9E2V+fBVGSh8nlg= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ebbf6024-f890-46c5-825b-08d63033334d X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:38.7431 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 15/22] net/atlantic: implement RSS and RETA manipulation API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for Receive Side Scaling feature. RSS hash and reta table configuration. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/atlantic.rst | 1 + doc/guides/nics/features/atlantic.ini | 3 + drivers/net/atlantic/atl_ethdev.c | 107 ++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_ethdev.h | 14 +++++ drivers/net/atlantic/atl_rxtx.c | 5 ++ 5 files changed, 130 insertions(+) diff --git a/doc/guides/nics/atlantic.rst b/doc/guides/nics/atlantic.rst index b09c79babdf4..80591b13c185 100644 --- a/doc/guides/nics/atlantic.rst +++ b/doc/guides/nics/atlantic.rst @@ -16,6 +16,7 @@ Supported features - Promiscuous mode - Multicast mode - Port statistics +- RSS (Receive Side Scaling) - Checksum offload - Jumbo Frame upto 16K diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index 347ac80a1ceb..592af817931e 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -11,6 +11,9 @@ Queue start/stop = Y Jumbo frame = Y Promiscuous mode = Y Allmulticast mode = Y +RSS hash = Y +RSS key update = Y +RSS reta update = Y CRC offload = Y L3 checksum offload = Y L4 checksum offload = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 5223b57ebd83..2f365844752c 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -58,6 +58,19 @@ static int atl_dev_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *handle); static void atl_dev_interrupt_handler(void *param); +/* RSS */ +static int atl_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +static int atl_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +static int atl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf); +static int atl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf); + + static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); @@ -208,6 +221,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rxq_info_get = atl_rxq_info_get, .txq_info_get = atl_txq_info_get, + + .reta_update = atl_reta_update, + .reta_query = atl_reta_query, + .rss_hash_update = atl_rss_hash_update, + .rss_hash_conf_get = atl_rss_hash_conf_get, }; static inline int32_t @@ -260,12 +278,18 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) /* Hardware configuration - hardcode */ adapter->hw_cfg.is_lro = false; adapter->hw_cfg.wol = false; + adapter->hw_cfg.is_rss = false; + adapter->hw_cfg.num_rss_queues = HW_ATL_B0_RSS_MAX; + adapter->hw_cfg.link_speed_msk = AQ_NIC_RATE_10G | AQ_NIC_RATE_5G | AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M; + adapter->hw_cfg.aq_rss.indirection_table_size = + HW_ATL_B0_RSS_REDIRECTION_MAX; + hw->aq_nic_cfg = &adapter->hw_cfg; /* disable interrupt */ @@ -747,6 +771,10 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_desc_lim = rx_desc_lim; dev_info->tx_desc_lim = tx_desc_lim; + dev_info->hash_key_size = HW_ATL_B0_RSS_HASHKEY_BITS / 8; + dev_info->reta_size = HW_ATL_B0_RSS_REDIRECTION_MAX; + dev_info->flow_type_rss_offloads = ATL_RSS_OFFLOAD_ALL; + dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; dev_info->speed_capa |= ETH_LINK_SPEED_100M; dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; @@ -998,6 +1026,85 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } +static int +atl_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + int i; + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cf = ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + + for (i = 0; i < reta_size && i < cf->aq_rss.indirection_table_size; i++) + cf->aq_rss.indirection_table[i] = min(reta_conf->reta[i], + dev->data->nb_rx_queues - 1); + + hw_atl_b0_hw_rss_set(hw, &cf->aq_rss); + return 0; +} + +static int +atl_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + int i; + struct aq_hw_cfg_s *cf = ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + + for (i = 0; i < reta_size && i < cf->aq_rss.indirection_table_size; i++) + reta_conf->reta[i] = cf->aq_rss.indirection_table[i]; + reta_conf->mask = ~0U; + return 0; +} + +static int +atl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + static u8 def_rss_key[40] = { + 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d, + 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18, + 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8, + 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70, + 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c + }; + + cfg->is_rss = !!rss_conf->rss_hf; + if (rss_conf->rss_key) { + memcpy(cfg->aq_rss.hash_secret_key, rss_conf->rss_key, + rss_conf->rss_key_len); + cfg->aq_rss.hash_secret_key_size = rss_conf->rss_key_len; + } else { + memcpy(cfg->aq_rss.hash_secret_key, def_rss_key, + sizeof(def_rss_key)); + cfg->aq_rss.hash_secret_key_size = sizeof(def_rss_key); + } + + hw_atl_b0_hw_rss_set(hw, &cfg->aq_rss); + hw_atl_b0_hw_rss_hash_set(hw, &cfg->aq_rss); + return 0; +} + +static int +atl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + + rss_conf->rss_hf = cfg->is_rss ? ATL_RSS_OFFLOAD_ALL : 0; + if (rss_conf->rss_key) { + rss_conf->rss_key_len = cfg->aq_rss.hash_secret_key_size; + memcpy(rss_conf->rss_key, cfg->aq_rss.hash_secret_key, + rss_conf->rss_key_len); + } + + return 0; +} + RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index c315e0436dca..1e29999b539c 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -10,6 +10,17 @@ #include "atl_types.h" #include "hw_atl/hw_atl_utils.h" +#define ATL_RSS_OFFLOAD_ALL ( \ + ETH_RSS_IPV4 | \ + ETH_RSS_NONFRAG_IPV4_TCP | \ + ETH_RSS_NONFRAG_IPV4_UDP | \ + ETH_RSS_IPV6 | \ + ETH_RSS_NONFRAG_IPV6_TCP | \ + ETH_RSS_NONFRAG_IPV6_UDP | \ + ETH_RSS_IPV6_EX | \ + ETH_RSS_IPV6_TCP_EX | \ + ETH_RSS_IPV6_UDP_EX) + #define ATL_DEV_PRIVATE_TO_HW(adapter) \ (&((struct atl_adapter *)adapter)->hw) @@ -19,6 +30,9 @@ #define ATL_DEV_PRIVATE_TO_INTR(adapter) \ (&((struct atl_adapter *)adapter)->intr) +#define ATL_DEV_PRIVATE_TO_CFG(adapter) \ + (&((struct atl_adapter *)adapter)->hw_cfg) + #define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) #define ATL_FLAG_NEED_LINK_CONFIG (uint32_t)(4 << 0) diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index fbd50a766098..01267214088b 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -336,6 +336,7 @@ int atl_rx_init(struct rte_eth_dev *eth_dev) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + struct aq_rss_parameters *rss_params = &hw->aq_nic_cfg->aq_rss; struct atl_rx_queue *rxq; uint64_t base_addr = 0; int i = 0; @@ -379,6 +380,10 @@ atl_rx_init(struct rte_eth_dev *eth_dev) } } + for (i = rss_params->indirection_table_size; i--;) + rss_params->indirection_table[i] = i & + (eth_dev->data->nb_rx_queues - 1); + hw_atl_b0_hw_rss_set(hw, rss_params); return err; } From patchwork Fri Oct 12 11:09:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46711 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 630371B602; Fri, 12 Oct 2018 13:09:47 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0063.outbound.protection.outlook.com [104.47.38.63]) by dpdk.org (Postfix) with ESMTP id BB4F71B5B5 for ; Fri, 12 Oct 2018 13:09:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cj+/LPKMH9jzQa8To/zj8dXxKT4ynBfYbBewPsOhtTo=; b=O6VeKFta9VSiYDN9zjr5UgAmVt0lhGZRzSYwsDm916K/GgvhMCzkQsPRtOjM+FhMBGrAOnp6gu8jUMwVu5x7x1xuCEunBms70PikJ6Xuuk4X2pE6wx8HLSUZefXQb4Srf3oAVUcutMcZZ0+hFxzmqQ8HwsVz/BvBEfg2K0OxvTg= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:41 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:41 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" , Pavel Belous Thread-Topic: [PATCH v6 16/22] net/atlantic: add flow control configuration Thread-Index: AQHUYhwSCVpxCk3r1kC4pWP8uLV68g== Date: Fri, 12 Oct 2018 11:09:41 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:7fhaFlMyQ76nRs6IXYUrJuRtVyOKkvk0BgTQ0i8TfgIAa0BbyTm0wJrW5lYaOPf+oGVnz7vmGgydL8BVi6n1Boxyk5JbjUv8UlkVxYdYD7Mm/pp+53eNWfXsopY0YSa+7KdzarHCL5eB2Yq+UolklU3z/QUByaHQ46A53g0UxMSgt00Ik0/bltKGWkp0TnTdQ/GB0ShUK1OlW0Xbx9ly3xNyl+NjAoFMeWM7HHika3I8s8Iqi6JwgRopMGnsabdIJoGNsYnRUdpKcXgYmeQYqmtaIfWgmmDy3Jbbbz8RFhJkMoeD74yEQMDMVfr4k8pjqYw0nf974ZlJmTnPlHce6SG7iSVmZtApGC3VoTFq8TZa+dv7dZ3TpKkE01O5DYVgI4kBHmYK8g/m0ODAVhWyAdwDnQ3qLfDon2iVa1DQTUGRNha3fqX8xwFXmTGhieeHJewq5n/5KO9+Ot6rDReNyQX+FV9F6AYHCPcw0s7XO9A=; 5:ehIWat8xWtkAE+mNnM2E3ksYQErbwGPpSK13eDG2r8vRN5m0W9whL5pEzV3pr/DHMWblwDH5d2etFsHExLFVYx23nxMKirwt9Dl41vlFK5D3OfyMUgVwXkc4M+KGAs7BQEGuuV6lGxg+FufVs8kuHIFFofqPNugwEhWEPSxkmqw=; 7:+hKUtIt7p0ZsfgkxVallBocbHlcoIDCUU9FKeU3E9LQ8nOBUaA1AI583xcgwy9ZVXKsg1zwLa4mv6c/IsjZiPASvlEDqgXoStXyzP1kVFRImowdnos6Pu/RWzaRH8BQG8Xs9mRzIz53Ka6yMy/PIMxVPjmyX2H/C3Hmtv0fXHnX/P8SzBGf/ZZRD3dpQKlF3A79XMckGs8gUADmkhprtUikYowipQOL2hdL2Foqj/8+uIhVKgceelT0VyoAhcTkL x-ms-office365-filtering-correlation-id: 0f0cd2a4-606a-4afc-1fe3-08d6303334c2 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(107886003)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(575784001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 5Eq1i1BKn+EsImJFl3owou9eTXpOGFy8AFUHfCqBgeOkcTIFRVEhg0dGzsYczn+c+03e9GIAQHddbTW9NB1BydFJ+lqgdQmF2VjlrivmimaCQm9+c6Mmk08mnANM4WwyTXz8SVZxLueVZxScnPs90/C8sSszibHVy5cdJS9AOSZDqgx5zEqzgfioOmlZ6ah0wR7XWa2yWkBncxwaiAAcuSRlBunpF6BMQFb4wOXIgchwAyPEE9WfMapETYljpKVM+jpdTYBRNM+v3HybubPJ/M/UjICFTtr5RDEdUpHNztCRSsIWlUsZjoJm/xoR95ZkkGi+LzqCaJKuzpt+xj7hGS/ujfJkUvy5p1cGUCPAZ0A= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f0cd2a4-606a-4afc-1fe3-08d6303334c2 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:41.1430 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 16/22] net/atlantic: add flow control configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add support for flow control feature. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 1 + drivers/net/atlantic/atl_ethdev.c | 54 +++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index 592af817931e..e86707ea5c0a 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -14,6 +14,7 @@ Allmulticast mode = Y RSS hash = Y RSS key update = Y RSS reta update = Y +Flow control = Y CRC offload = Y L3 checksum offload = Y L4 checksum offload = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 2f365844752c..6ce4454fe2f3 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -48,6 +48,12 @@ static void atl_dev_info_get(struct rte_eth_dev *dev, static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); +/* Flow control */ +static int atl_flow_ctrl_get(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); +static int atl_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); + static void atl_dev_link_status_print(struct rte_eth_dev *dev); /* Interrupts */ @@ -219,6 +225,10 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_descriptor_status = atl_dev_rx_descriptor_status, .tx_descriptor_status = atl_dev_tx_descriptor_status, + /* Flow Control */ + .flow_ctrl_get = atl_flow_ctrl_get, + .flow_ctrl_set = atl_flow_ctrl_set, + .rxq_info_get = atl_rxq_info_get, .txq_info_get = atl_txq_info_get, @@ -287,6 +297,7 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) AQ_NIC_RATE_1G | AQ_NIC_RATE_100M; + adapter->hw_cfg.flow_control = (AQ_NIC_FC_RX | AQ_NIC_FC_TX); adapter->hw_cfg.aq_rss.indirection_table_size = HW_ATL_B0_RSS_REDIRECTION_MAX; @@ -1026,6 +1037,49 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } + +static int +atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_nic_cfg->flow_control == AQ_NIC_FC_OFF) + fc_conf->mode = RTE_FC_NONE; + else if (hw->aq_nic_cfg->flow_control & (AQ_NIC_FC_RX | AQ_NIC_FC_TX)) + fc_conf->mode = RTE_FC_FULL; + else if (hw->aq_nic_cfg->flow_control & AQ_NIC_FC_RX) + fc_conf->mode = RTE_FC_RX_PAUSE; + else if (hw->aq_nic_cfg->flow_control & AQ_NIC_FC_RX) + fc_conf->mode = RTE_FC_TX_PAUSE; + + return 0; +} + +static int +atl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t old_flow_control = hw->aq_nic_cfg->flow_control; + + + if (hw->aq_fw_ops->set_flow_control == NULL) + return -ENOTSUP; + + if (fc_conf->mode == RTE_FC_NONE) + hw->aq_nic_cfg->flow_control = AQ_NIC_FC_OFF; + else if (fc_conf->mode == RTE_FC_RX_PAUSE) + hw->aq_nic_cfg->flow_control = AQ_NIC_FC_RX; + else if (fc_conf->mode == RTE_FC_TX_PAUSE) + hw->aq_nic_cfg->flow_control = AQ_NIC_FC_TX; + else if (fc_conf->mode == RTE_FC_FULL) + hw->aq_nic_cfg->flow_control = (AQ_NIC_FC_RX | AQ_NIC_FC_TX); + + if (old_flow_control != hw->aq_nic_cfg->flow_control) + return hw->aq_fw_ops->set_flow_control(hw); + + return 0; +} + static int atl_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, From patchwork Fri Oct 12 11:09:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46712 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 16C981B60C; Fri, 12 Oct 2018 13:09:49 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0048.outbound.protection.outlook.com [104.47.38.48]) by dpdk.org (Postfix) with ESMTP id 0F76F1B5EF for ; Fri, 12 Oct 2018 13:09:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=j0XfASLu+lxxP0ckRsIxiIk1Pfd+70dgrQ6itrwKDGQ=; b=nSP6d7wU+hs3Kvf5ZXabcGjbeMVETySlAGW4715tHTRZeSgpfkESshw4UcV6atOOxPXyzd1JFYo3j+joMd+C9nJr/mczp13HP4kbF+6ABgq7+2QK0CJibMukq1jTnSB5Wf0xQMIPwZ/fSb4mKRYBTYtUQq702DgLlFM4X51WyGo= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:43 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:43 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" , Pavel Belous Thread-Topic: [PATCH v6 17/22] net/atlantic: implement MAC address manipulations Thread-Index: AQHUYhwTfWvFyvoSMEu+BPk+XcwjyA== Date: Fri, 12 Oct 2018 11:09:43 +0000 Message-ID: <665da1a6647d9f4e4c4f657605e20b21237fce38.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:tyeTWji/Fzsl6YPNu0waVjL0Xx9abJeXplOL/viSNkldR2G7uQ3FQXH82IFD5eoTuyD/tpPfXnr6XnscwFrd+pz1ZgQcvOX2fyQYzrn3wauvjd2S4RJ/rCUMX3G/ITugmGUykSU295sksFW6pZxz4PYCz+HHuc2gr2LUyWLDb8+h8FcNyOS8qsnorYtB9Mzx0Uigh3ELpHfWusPTVeIu/H5c0Mxo0amiYvOopABBEvRe1yRaP123Ge99jYL0eKY05fnllMs7+xQCN38Ba0oDzaP+fV/iF3KbMsbhuEGCwBjfqtETEch7KNOD72V+oXzszoAvMomOJd6m3RFKBE3lwNQ/gkLxtm5ig5tt37/s+uTbvtZ5qdN2vYB53AHeGxREN7b/uJYAHE7Dl/F//Jhnm0FiN1AtvwskLz/+Hz3rnOOYrJ23kmHZaJzlB7xEwX3PQsEFMSawPo2UwIRxitcAPncokRw6t0o5KIcKqxmbI7A=; 5:UXpGF6Jlrz5o4FbmNK0ANGWXOnJZD3GMY7ALZg/LsZlanq56ZheSPMOa1pleS75qw428rCyJgLm8MIMGNZmdwfOcJ9o0WuC/Ja4Noh3SZ3sqwIBxpw083EpI0bG9XoB/7YkyZ21fm6DiacdrljkEiVJYPy4kBIjmA3xz5bCBNKI=; 7:RsAhWZR48flf84wJ0IA84//GCr/xknU7ScoB24T6ynGszqVcmre9v1s7cdZUzRwvYgXS0iLqVkvc2agVuyzQE9iWgX0wPjNLsVSKxeQIZwReO+O119gYAIjFbNc56E4SdCgqvM0tPCfd4xHuvZFyaqerI7BePvS4SWzNAIgrP8iGjbMcUPso0d21AFyWSjJzXXE2dgHDI02Fcku0Y+hWfrIljC9BXA1jK33y/uIC1tVRgZXTa9jQp4xR3fSev26p x-ms-office365-filtering-correlation-id: 1369e234-5613-46da-f018-08d630333630 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(107886003)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(575784001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011)(309714004); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 3wETMldwEI0Wnqv6SIXdJQaR1BOKMqMdNDG15JKfZ1wtAiqwwfMlC0oKdMAzLLbIY7u6j5R8ZbO9YlunATaWvEDmK7XbyWQbeCuuMg7jy1FBlFmL7EyoRms7zNOo4zQNcuh7HSuLTTm/ixBrjUosAfuGUyVe0ctZfDOAvUfS+3TGoMg3Kn+/mSxp5lvpcl2x81C9moIaKioPzovI8h2klUwLHcd+b+cNS1ce9htT7L79/3On2lXr7GTyp1Orpg6e14zWh8/uMxvJD/tD3iguJIqVfT8YFg5UkoSEncKRdyZRiI8uY0oFzUBZvUNsquXQVr2ak8rZf8iJa05fTAOjoF3hNky6CmsgRjspvdBmuHA= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1369e234-5613-46da-f018-08d630333630 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:43.5430 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 17/22] net/atlantic: implement MAC address manipulations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add support for adding/removing MAC addresses. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 1 + drivers/net/atlantic/atl_ethdev.c | 105 ++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index e86707ea5c0a..1dd3ff87e512 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -11,6 +11,7 @@ Queue start/stop = Y Jumbo frame = Y Promiscuous mode = Y Allmulticast mode = Y +Unicast MAC filter = Y RSS hash = Y RSS key update = Y RSS reta update = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 6ce4454fe2f3..6cee14b2dcba 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -64,6 +64,18 @@ static int atl_dev_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *handle); static void atl_dev_interrupt_handler(void *param); + +static int atl_add_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *mac_addr, + uint32_t index, uint32_t pool); +static void atl_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); +static int atl_set_default_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *mac_addr); + +static int atl_dev_set_mc_addr_list(struct rte_eth_dev *dev, + struct ether_addr *mc_addr_set, + uint32_t nb_mc_addr); + /* RSS */ static int atl_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, @@ -229,6 +241,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .flow_ctrl_get = atl_flow_ctrl_get, .flow_ctrl_set = atl_flow_ctrl_set, + /* MAC */ + .mac_addr_add = atl_add_mac_addr, + .mac_addr_remove = atl_remove_mac_addr, + .mac_addr_set = atl_set_default_mac_addr, + .set_mc_addr_list = atl_dev_set_mc_addr_list, .rxq_info_get = atl_rxq_info_get, .txq_info_get = atl_txq_info_get, @@ -1081,6 +1098,94 @@ atl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) } static int +atl_update_mac_addr(struct rte_eth_dev *dev, uint32_t index, + u8 *mac_addr, bool enable) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + unsigned int h = 0U; + unsigned int l = 0U; + int err; + + if (mac_addr) { + h = (mac_addr[0] << 8) | (mac_addr[1]); + l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + } + + hw_atl_rpfl2_uc_flr_en_set(hw, 0U, index); + hw_atl_rpfl2unicast_dest_addresslsw_set(hw, l, index); + hw_atl_rpfl2unicast_dest_addressmsw_set(hw, h, index); + + if (enable) + hw_atl_rpfl2_uc_flr_en_set(hw, 1U, index); + + err = aq_hw_err_from_flags(hw); + + return err; +} + +static int +atl_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr, + uint32_t index __rte_unused, uint32_t pool __rte_unused) +{ + if (is_zero_ether_addr(mac_addr)) { + PMD_DRV_LOG(ERR, "Invalid Ethernet Address"); + return -EINVAL; + } + + return atl_update_mac_addr(dev, index, (u8 *)mac_addr, true); +} + +static void +atl_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) +{ + atl_update_mac_addr(dev, index, NULL, false); +} + +static int +atl_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) +{ + atl_remove_mac_addr(dev, 0); + atl_add_mac_addr(dev, addr, 0, 0); + return 0; +} + +static int +atl_dev_set_mc_addr_list(struct rte_eth_dev *dev, + struct ether_addr *mc_addr_set, + uint32_t nb_mc_addr) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + u32 i; + + if (nb_mc_addr > AQ_HW_MULTICAST_ADDRESS_MAX - HW_ATL_B0_MAC_MIN) + return -EINVAL; + + /* Update whole uc filters table */ + for (i = 0; i < AQ_HW_MULTICAST_ADDRESS_MAX - HW_ATL_B0_MAC_MIN; i++) { + u8 *mac_addr = NULL; + u32 l = 0, h = 0; + + if (i < nb_mc_addr) { + mac_addr = mc_addr_set[i].addr_bytes; + l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + h = (mac_addr[0] << 8) | mac_addr[1]; + } + + hw_atl_rpfl2_uc_flr_en_set(hw, 0U, HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2unicast_dest_addresslsw_set(hw, l, + HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2unicast_dest_addressmsw_set(hw, h, + HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2_uc_flr_en_set(hw, !!mac_addr, + HW_ATL_B0_MAC_MIN + i); + } + + return 0; +} + +static int atl_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size) From patchwork Fri Oct 12 11:09:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46713 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 801BA1B61F; Fri, 12 Oct 2018 13:09:51 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0087.outbound.protection.outlook.com [104.47.38.87]) by dpdk.org (Postfix) with ESMTP id 589C01B5FF for ; Fri, 12 Oct 2018 13:09:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TFCrlS+9HPDWzqSc3O8tNbRm/039tlQ9b63w92Gz8yw=; b=XLwm0dwJdx2FcUQ7sr/n52YrlS6Q8HflKP0rFa2tPXpx76nnKoSRoqTtBZ0fKk92fLNiOhRWfxHWk0atcoTrdK6BXBeBV0J7dI5YdbLiQcxH9IdfiBYgNbVq7/3PH/B8pDE0gXSTV0/f7Xzc8i4bTgH0Vn3WJf9RbsQLr7PnflY= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:46 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:46 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" , Pavel Belous Thread-Topic: [PATCH v6 18/22] net/atlantic: implement MTU configuration Thread-Index: AQHUYhwVkox6T2UvLkKosuX++omDXQ== Date: Fri, 12 Oct 2018 11:09:45 +0000 Message-ID: <3b960a834e8a1d9d61eeaec52c0bb36e2cbbec05.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:iXLd7af0w/sfQPGewaST5xhTzNCo/b0jnrcFr/I1j7enPmBqijPdJbRjmVo/yzBu55ItQEFFuTadRUkiDhl6qwywjNs4TN54Btb06pL54ro72LcAuyQ+jqSNn2ieDM9Zf7zVh3ApBjT428DyoY67EELoIPGIFBg5/FMSg1uvSvwOVdKRgBUncUFdxztnOZHZWc3dY0jmgAM5CjS3f0EOwcQfrWwQxu2zpyG90prDi2i9VSjbpXwMQ6M9p5A5gXKJnkZAIivnIqrAgsvF95GBZWyoAZvINafGywCoH7N/Is1XbgyuNcljeEDB9HuIm1eg6uv57ilpv7EU93EbDM0h5Qg5ZVjhq0RgBEVB6/OtKbkfgIX7A0aom0vhOnpbWWdJ0SvHm8fHImXyz8SeywyuuvWbG3t3dGwIbwCPGRLCoAWAaTn0v+S8kFKe58s+qXuzBNeV4qSQ9XTC78Sl+FdAvOISy7fhPnrYA2x1oBsiLoo=; 5:MJEjf6jMpE1tSRQBZbKKgyGzCdlitSNaOcIKB7S+1Lwuj4GFn2aLlNLXj+bPIzvAAut7v/jSRGRywRRSvIfe6yjw7vdsqyqOxh5hWQ51e5KlUJWWV9Z+rNGSe0B9HFY1zVdJAHes4kZquPPTvMRQgT5cCnsXtseR/DAEyKJpS3U=; 7:gqbZfiYIkmIFlrzcKQbMeiz+nW+R6D7awiIps3hZ5+DzBPISVG40l3YD8x3VBWWNsGyW/fNXhwAbCcK3xrlkb4ak0t89EnNSKnqI/AuGQme08oTbGoczMS76gmg8NZMMHaMVCXGMJwL7T9juM6TITaNAWHbpdjtEXrjdCAOQslTkTKTplu1kbdMd7cOOCx3Hz7N5JiteB3AteK85ViAYjs3igC85AN2zt/KkoKMtJVrK5WvyA4fdX9TTOv12z/Bd x-ms-office365-filtering-correlation-id: 77730f91-1c24-4de7-4b05-08d63033379f x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(107886003)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 2i1taoE3jiEb1/f+v6lLZKPMnDkuetifHZ/Z9zI42ofmNDt8+Swnv50V3Kq7bUskD5PEY39BmvKxkExo0QOCu8m5Ok8Al/KAW0v6yn7RmyejxjhsJf1yKfuxG3q7OFXQJCnWezrAslSInNmndN0oEIGgMlK0A73uqLnPREarsoV4RlgnK3tZA7Ia3modPtQE9AZvd/Ze9U+RSYvp1VKEeyhaVefzxxJyWhiBfWWsaG+MMosz3TXsqYpE7U6pvprqF7L37btMz5s4H4Yo/wMj5WO9Ge0WojSBeQdnKB+0pRh/IMujpBWSy6jW4Rdmqf5p6Xo2RhNde4IxRrGo54omONkhL/maY9BfaZrgGgRPFcw= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 77730f91-1c24-4de7-4b05-08d63033379f X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:45.9369 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 18/22] net/atlantic: implement MTU configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add support for updating MTU value. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 1 + drivers/net/atlantic/atl_ethdev.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index 1dd3ff87e512..dd44ed75aef4 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -8,6 +8,7 @@ Speed capabilities = Y Link status = Y Link status event = Y Queue start/stop = Y +MTU update = Y Jumbo frame = Y Promiscuous mode = Y Allmulticast mode = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 6cee14b2dcba..db2d798f28aa 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -48,6 +48,8 @@ static void atl_dev_info_get(struct rte_eth_dev *dev, static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); +static int atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); + /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); @@ -219,6 +221,8 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_infos_get = atl_dev_info_get, .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, + .mtu_set = atl_dev_mtu_set, + /* Queue Control */ .rx_queue_start = atl_rx_queue_start, .rx_queue_stop = atl_rx_queue_stop, @@ -1151,6 +1155,23 @@ atl_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) } static int +atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct rte_eth_dev_info dev_info; + uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; + + atl_dev_info_get(dev, &dev_info); + + if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) + return -EINVAL; + + /* update max frame size */ + dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; + + return 0; +} + +static int atl_dev_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addr_set, uint32_t nb_mc_addr) From patchwork Fri Oct 12 11:09:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46714 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5D20C1B64B; Fri, 12 Oct 2018 13:09:53 +0200 (CEST) Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0056.outbound.protection.outlook.com [104.47.32.56]) by dpdk.org (Postfix) with ESMTP id 0DA121B610 for ; Fri, 12 Oct 2018 13:09:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nUtfXHJQr7AJEqt7jccY/8xbNsDQmcYl8o+lgOeueKY=; b=fvN02pva3s/TOH3sdnrlVRYW/yld83AwynX3H/2V1cwpkVv/j5T2QunfUk38jXtICjlYBQKI1V1gwWEzDS9aHDSuYuJASIlekQCOyZHRAcxFJB8sCFAbQ1Hq6YM+zEl1cUlr1lArIUxZYCUS86C/Z6oEybm+e6jEe3BI3cbTvWY= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:49 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:49 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" , Pavel Belous Thread-Topic: [PATCH v6 19/22] net/atlantic: implement VLAN filters and offloads Thread-Index: AQHUYhwXWjt8mind30Cn8O3BLuY/YA== Date: Fri, 12 Oct 2018 11:09:49 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:A3gEClRfhmn20efh5UBEhh1qYNEi9jB4+lf73bXVnvz+NzOY3aDgm5jBLGG/MCR2+TKb7Isv42bTcxOJWHzb3Gua37d5ahLi30aPa7qCAJAlAOAB1QbOps6a+kFMWrIQ95zw3FSBBpSAv4+9q+li2QXDLoIcqQ2mSf/WpUHycPuQznzZSOVqHP2VkGX3ag3XAiOds+S90egi8wxDnhl7YquGV/3rtu1YNWivib+fMVvoxXCYbVPtVnRpcxHJSkZo0wlYUWHpxDuKkFEC9wuBricelv9Bc5ey4ySSZR/R1sYqyCulq3J07/r3INDGPb7gJXrIsTp89vZDcFRSlt9tMJuUKuBQzdcQeGYG4lPg9fzHI0Tj3bdX/vrCWqWc8EzkV2ieGJdkQN+F2JSvlL82TOnEYwLFRSqZ+sEyLHWoBAWLvxtNP+XXhjVaWDrZFeFARXDYKDObLj71JEjofCwSNvEK9EIuStxCsYWKbLuNMtk=; 5:v02Ad+2MlYg2ZgGNlu7Qm4yd9/Sl1y7CzY8aa0iAivw69w+tdE8uTz0mBLrUrEh/wo+N+Nu5HXWefj/9Fh/RWGLl5WHZov4hmh6BHQHoUY7doa0gfonpcFaIHiCaj8mNlFeu0/cjMbpG3iEdnuZXAOYckT+3wAjrJsxQyIJ3K+o=; 7:+aXeQyLXzJy4MjizOSf14ga5NIFqvQhftl/eY8dDTV8QOGdyBvkCuD9nn5IjgmTAxpaTmNFXw+woKWk4iJsKB/28uKp7WGiGZtarbVsQFyNLoflsBfctw6lR8vNHoyvyTBIEeKlW6oPRpp+Cy3WbJGJTHsZ/uvh4L/Yl59q2vWWIJxxsLD40ERokWq2XfAt2w8uJv7moS2UBWKcY1mWWay3AJ/xjFpI1UQjV/TmqJDjHmEQU2Hvz3z4NySWL+29i x-ms-office365-filtering-correlation-id: fcb466a9-598f-4d98-1ebe-08d63033390c x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(107886003)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: weBkuNDOuVETcAU7vDr9m6Uti4b4ZMJkbvBEV8hhT+VO4G3N9o6Y5CfmDy6Ci0iatWuJxOZzQMt0CTlzpuDTu0aJNrB/SNK/YWR4TmGiiR1dKjUroF3Vcc6f3kSRiKbtK+uiSOyKWTIATjuu86OJYcPXMYIp3r5ri95+zvKkqVtIwj/GzJQxOS53waj7vxdV18S/oNPX/F2tl1JJIaWQd/nih6ywTkqTmt6EPJ8EADsLCUDPbDaIrnzmQkTgQ0zX/JPf2Yvz9h6GCkPJLf7CwY9riI3vBMoKUOKti4PbBH5R7c7t9hZFNPF3FRiWhlnsc3U248ZYFt21WA/122XS3MnyBYnOdy9SjaDTbsviYk0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: fcb466a9-598f-4d98-1ebe-08d63033390c X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:49.1215 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 19/22] net/atlantic: implement VLAN filters and offloads X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous VLAN filters and VLAN offloads implementation. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 2 + drivers/net/atlantic/atl_ethdev.c | 159 ++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_rxtx.c | 12 +++ drivers/net/atlantic/atl_types.h | 2 + 4 files changed, 175 insertions(+) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index dd44ed75aef4..66949b816284 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -16,8 +16,10 @@ Unicast MAC filter = Y RSS hash = Y RSS key update = Y RSS reta update = Y +VLAN filter = Y Flow control = Y CRC offload = Y +VLAN offload = Y L3 checksum offload = Y L4 checksum offload = Y Packet type parsing = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index db2d798f28aa..6ebc02864cfe 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -50,6 +50,18 @@ static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); static int atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); +/* VLAN stuff */ +static int atl_vlan_filter_set(struct rte_eth_dev *dev, + uint16_t vlan_id, int on); + +static int atl_vlan_offload_set(struct rte_eth_dev *dev, int mask); + +static void atl_vlan_strip_queue_set(struct rte_eth_dev *dev, + uint16_t queue_id, int on); + +static int atl_vlan_tpid_set(struct rte_eth_dev *dev, + enum rte_vlan_type vlan_type, uint16_t tpid); + /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); @@ -223,6 +235,12 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .mtu_set = atl_dev_mtu_set, + /* VLAN */ + .vlan_filter_set = atl_vlan_filter_set, + .vlan_offload_set = atl_vlan_offload_set, + .vlan_tpid_set = atl_vlan_tpid_set, + .vlan_strip_queue_set = atl_vlan_strip_queue_set, + /* Queue Control */ .rx_queue_start = atl_rx_queue_start, .rx_queue_stop = atl_rx_queue_stop, @@ -1172,6 +1190,147 @@ atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) } static int +atl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +{ + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int err = 0; + int i = 0; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i] == vlan_id) { + if (!on) { + /* Disable VLAN filter. */ + hw_atl_rpf_vlan_flr_en_set(hw, 0U, i); + + /* Clear VLAN filter entry */ + cfg->vlan_filter[i] = 0; + } + break; + } + } + + /* VLAN_ID was not found. So, nothing to delete. */ + if (i == HW_ATL_B0_MAX_VLAN_IDS && !on) + goto exit; + + /* VLAN_ID already exist, or already removed above. Nothing to do. */ + if (i != HW_ATL_B0_MAX_VLAN_IDS) + goto exit; + + /* Try to found free VLAN filter to add new VLAN_ID */ + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i] == 0) + break; + } + + if (i == HW_ATL_B0_MAX_VLAN_IDS) { + /* We have no free VLAN filter to add new VLAN_ID*/ + err = -ENOMEM; + goto exit; + } + + cfg->vlan_filter[i] = vlan_id; + hw_atl_rpf_vlan_flr_act_set(hw, 1U, i); + hw_atl_rpf_vlan_id_flr_set(hw, vlan_id, i); + hw_atl_rpf_vlan_flr_en_set(hw, 1U, i); + +exit: + /* Enable VLAN promisc mode if vlan_filter empty */ + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i] != 0) + break; + } + + hw_atl_rpf_vlan_prom_mode_en_set(hw, i == HW_ATL_B0_MAX_VLAN_IDS); + + return err; +} + +static int +atl_enable_vlan_filter(struct rte_eth_dev *dev, int en) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i]) + hw_atl_rpf_vlan_flr_en_set(hw, en, i); + } + return 0; +} + +static int +atl_vlan_offload_set(struct rte_eth_dev *dev, int mask) +{ + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int ret = 0; + int i; + + PMD_INIT_FUNC_TRACE(); + + ret = atl_enable_vlan_filter(dev, mask & ETH_VLAN_FILTER_MASK); + + cfg->vlan_strip = !!(mask & ETH_VLAN_STRIP_MASK); + + for (i = 0; i < dev->data->nb_rx_queues; i++) + hw_atl_rpo_rx_desc_vlan_stripping_set(hw, cfg->vlan_strip, i); + + if (mask & ETH_VLAN_EXTEND_MASK) + ret = -ENOTSUP; + + return ret; +} + +static int +atl_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, + uint16_t tpid) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int err = 0; + + PMD_INIT_FUNC_TRACE(); + + switch (vlan_type) { + case ETH_VLAN_TYPE_INNER: + hw_atl_rpf_vlan_inner_etht_set(hw, tpid); + break; + case ETH_VLAN_TYPE_OUTER: + hw_atl_rpf_vlan_outer_etht_set(hw, tpid); + break; + default: + PMD_DRV_LOG(ERR, "Unsupported VLAN type"); + err = -ENOTSUP; + } + + return err; +} + +static void +atl_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue_id, int on) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + if (queue_id > dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Invalid queue id"); + return; + } + + hw_atl_rpo_rx_desc_vlan_stripping_set(hw, on, queue_id); +} + +static int atl_dev_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addr_set, uint32_t nb_mc_addr) diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 01267214088b..fd909476c45f 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -919,6 +919,8 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) struct atl_adapter *adapter = ATL_DEV_TO_ADAPTER(&rte_eth_devices[rxq->port_id]); struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(adapter); + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); struct atl_rx_entry *sw_ring = rxq->sw_ring; struct rte_mbuf *new_mbuf; @@ -1036,8 +1038,18 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) rx_mbuf->ol_flags = atl_desc_to_offload_flags(rxq, &rxd_wb); + rx_mbuf->packet_type = atl_desc_to_pkt_type(&rxd_wb); + if (rx_mbuf->packet_type & RTE_PTYPE_L2_ETHER_VLAN) { + rx_mbuf->ol_flags |= PKT_RX_VLAN; + rx_mbuf->vlan_tci = rxd_wb.vlan; + + if (cfg->vlan_strip) + rx_mbuf->ol_flags |= + PKT_RX_VLAN_STRIPPED; + } + if (!rx_mbuf_first) rx_mbuf_first = rx_mbuf; rx_mbuf_first->nb_segs++; diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 56887b14d6f8..3d90f6caefc2 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -70,6 +70,8 @@ struct aq_hw_cfg_s { int irq_mask; unsigned int vecs; + bool vlan_strip; + uint32_t vlan_filter[HW_ATL_B0_MAX_VLAN_IDS]; uint32_t flow_control; struct aq_rss_parameters aq_rss; From patchwork Fri Oct 12 11:09:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46715 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DCC831B698; Fri, 12 Oct 2018 13:09:55 +0200 (CEST) Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0074.outbound.protection.outlook.com [104.47.32.74]) by dpdk.org (Postfix) with ESMTP id DEA5A1B5AF for ; Fri, 12 Oct 2018 13:09:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZpHkeJyChMGflLeRik4L6XP1ZXHSRjRbJNSpmag4o94=; b=AB2TPOentQ0zweb86bdDgbyLQrkSmj3C76D8bxfqAAVtzsD0bBDZoCB15vaEaey5XivyDKucVh8hi/XAcFfvJat3krRnTlRkhOy74VR8qKcyRZ4euVYvcG09Bupcy/K6ma1XG86All0ETRdstbmkTDgX4dB5IL3zJuVa/hUNpsE= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:51 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:51 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" , Pavel Belous Thread-Topic: [PATCH v6 20/22] net/atlantic: implement EEPROM get/set Thread-Index: AQHUYhwYz3ioYhb9ZkuMBSO9nyZ1ew== Date: Fri, 12 Oct 2018 11:09:51 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:7gXl51lPpgDYp4FjbnLBZ895JR8m3gB9wR0UzuISQbq5sALO6KkTQ05tQ1EyEl6ysc32K5ArmyTSzv0Xbuwp1NsGz0eW1Lr9vHGXHXdQnG82szAq6t+DHwtnB6I1f2g4/0nUEFh7vyj0IKdlFcUJzlVjm6wdi+P7Zx0rWIykDTr6Kk5a86ReYV+y392VbDPAggzQoVGp28Wr5Ow3twkU+1urn3tmqpRf3bmqojjo2HhFr7j3C2GedPJcNyCj3q3qCCfiow8sjD6d4LrtmgiIDYtistD4q/MmXg4/fIZNt71Rorfpae3D5kmWN+D1oHqfGPSDqzrjTiar/l2E4LGvHbgO/clz5lO6dKyeikZ+RsXOAsv82HzqIhMbceXByPRdHuw5vw+LB7BIc0wQwd2mPxb8XODs8JUwTCozQhSgP8sUQ2DKCClxZLB2Uuc/dQulITSXkPjzOldFD6X5eNlIfSjIFZCqsuUJR81vS3Caeag=; 5:hW+PkWvDXusifPYnAPPEMXF6CNIKun+otRruTspTm1tlgJV6KDbzBwQI1QoUUPYfLCAqCiPAKvmqoYzwHpS6b7FKUxUd+ZYBMViYyCQ5XFo8mKvwwQfrzX+q1s2FQQ++085JG2oYHQWgL4EJXyM1dC6/y0yfkjoJI7pUn6XCwZI=; 7:Yd5lt5vh04iy7c1OTeoQJQ69BfumA7qzbbtFycexgHgi73BN/wC/WhP6O/cpqQvzoZ1bpDfeVPqKz90L+p5+xZay5Ns5QrHGN+pvXNhF033vaHDSokPwjWyRNxaLzdLVfeBOkGeff443PG9GGydUJBDEZbEKWz7wkSI58EBixzKroO3Ucvin0BzTiqqDmCyKvGApQA+5HcbMGmxYdiHkay8tkrldENYi2hEHqv4sLmyljH6FGqWxe+3gmFBs1z9j x-ms-office365-filtering-correlation-id: b7452caa-d920-4cd2-1a40-08d630333af5 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(107886003)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: kUu05wp6ylziWczSxovl7pLB/NWEoZjbTdKVVoSkeq+AtdhpRXpXALhLnSBlCY7K8b7+IT5/Lv/WJ20ANklsmqRpR9CABQh1GxU/mZOsNCH2uw7gXqD/XU3NEDkqL3dJctLwRn692SstDGHUl1pPq8ZP9wmXHcDqO+4971ZcpOTWY6ini3z0/xW+cxIsZwI0NXRIFWnsjbOHwzc6Na/UZhgDmomfPugranTwlnzo9gHYaLLU0TLZEloNOifHUPiiHMJmKxqiZ2Gg5+mjAZ0Zp8AYu+aMl1TGNaa8uWQTIOR/czCETyulXn8UwQlfMUVwM2DFWwyWS8K8WOzLFxThxoeiUULaA4Z015mp/wWXuLs= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b7452caa-d920-4cd2-1a40-08d630333af5 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:51.4384 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 20/22] net/atlantic: implement EEPROM get/set X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Add support for EEPROM reading/writing. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 1 + drivers/net/atlantic/atl_ethdev.c | 47 +++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index 66949b816284..f09a75691a28 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -29,6 +29,7 @@ Basic stats = Y Extended stats = Y Stats per queue = Y FW version = Y +EEPROM dump = Y Linux UIO = Y ARMv8 = Y x86-32 = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 6ebc02864cfe..824e624dd772 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -62,6 +62,13 @@ static void atl_vlan_strip_queue_set(struct rte_eth_dev *dev, static int atl_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, uint16_t tpid); +/* EEPROM */ +static int atl_dev_get_eeprom_length(struct rte_eth_dev *dev); +static int atl_dev_get_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *eeprom); +static int atl_dev_set_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *eeprom); + /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); @@ -259,6 +266,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_descriptor_status = atl_dev_rx_descriptor_status, .tx_descriptor_status = atl_dev_tx_descriptor_status, + /* EEPROM */ + .get_eeprom_length = atl_dev_get_eeprom_length, + .get_eeprom = atl_dev_get_eeprom, + .set_eeprom = atl_dev_set_eeprom, + /* Flow Control */ .flow_ctrl_get = atl_flow_ctrl_get, .flow_ctrl_set = atl_flow_ctrl_set, @@ -1076,6 +1088,41 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } +#define SFP_EEPROM_SIZE 0xff + +static int +atl_dev_get_eeprom_length(struct rte_eth_dev *dev __rte_unused) +{ + return SFP_EEPROM_SIZE; +} + +static int +atl_dev_get_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_fw_ops->get_eeprom == NULL) + return -ENOTSUP; + + if (eeprom->length != SFP_EEPROM_SIZE || eeprom->data == NULL) + return -EINVAL; + + return hw->aq_fw_ops->get_eeprom(hw, eeprom->data, eeprom->length); +} + +static int +atl_dev_set_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_fw_ops->set_eeprom == NULL) + return -ENOTSUP; + + if (eeprom->length != SFP_EEPROM_SIZE || eeprom->data == NULL) + return -EINVAL; + + return hw->aq_fw_ops->set_eeprom(hw, eeprom->data, eeprom->length); +} static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) From patchwork Fri Oct 12 11:09:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46716 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 23BCB1B6C9; Fri, 12 Oct 2018 13:09:57 +0200 (CEST) Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0087.outbound.protection.outlook.com [104.47.32.87]) by dpdk.org (Postfix) with ESMTP id 5A5D61B675 for ; Fri, 12 Oct 2018 13:09:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nFbkojfIySDUywBx1q865OZMD5aDus3ffv/sJ1mjuCM=; b=NeXxu3NG/pQ0/bAwSswLMhgtBjMcrIdligrGeotJOQS3A5rT/YRVmxq4E4dr+KVYdx4Z5lG8pCjEB8v4/B4oj5OeQl62o/LtA+3fS46li+5JSq6QczNEFRqmoqilHpRdM2dGhhX3XZ/vTEHN/Wpja6k5yZJkkcT68Ub8/ZHfRJw= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:53 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:53 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 21/22] net/atlantic: read MAC registers for debug purposes Thread-Index: AQHUYhwZt4mRmK9TXESss4oaOE62Jg== Date: Fri, 12 Oct 2018 11:09:53 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:n3nvwKsMgrDaKiMbLl0eW3GU32mELF8q2oz/GQPDDhyk+3030h76H8oyeZS+rtzKQ+LUodwgRGFJ+tpcOqUkdlWnVIXtkcNptwvhO5MSVUWH+m2bOK6dJYKa0UKLVN13wnTkCasp/A4hKV6483B6ghQ4XLdwRGus4D1jiag6a5wXzCIyy1hac3t+oWimYYsH+Yhx/M4soTRHQgh1YZ9ILgAQBxfELcov3MT3m5FMforYTag5r1LIAukSSDY4aQDlDxGpSxq2js3aWtfBHx8EOey80MSlff+EgF3chrppai/xa5BjttLk75LXb138f0MMAFkrOZnpcW+2sd8fFrsNkA9dHi+4X6qNfV5bCINlq7TgT21iEUPLvEtKlWLd5RrBD7I2jI5DYZL8F/x9OWWPaE0ibaXLoxBpxAEnnOgPMVI9k96HzT/WDMWe8OYjmnTpRYbtSY086dvhA6f3Y/54dmK4Gtg02D74PilS5doRy08=; 5:9WqbIdZwQAiwzYbi+q0n9XU7WpeJpfa0HCxqSHTfXOR7KTf9vlQmF92gDK5rAvTk3/2gOJCM/ZH0+2YRLLe0bCcegnXQJ9+BNs1H4DFjykVKYbgFaDIVoj72/rJQqRJ4zLf+ynZajDhiCr32iNSuhjngguWQzkMJUVjFAf1xw0o=; 7:Rp2v1Y9+cxBRewJdr2gX9jE7FIRq0K8nOjVTvqZi0A/pHIhPrgheyaC1JsApHSjDvU2bKd99ZtOtRofTgqlgqWZzds5hGrbjCMdQfYuQK1oD4S531L4UVVyikbigHrxP4N/5+fpdr04q+fzl7Q2NOEK1FBfb/LxbohAOhVMoBwmk54Dkl2/tRa8zxQX5WTdT4U1lDtTuv7yGRh4TkJsrFlrM3BUNXf/qGMk+aGgqgd9scV3knvfT/WgsPlVdkyAC x-ms-office365-filtering-correlation-id: bb578d9b-3b4e-4de2-e169-08d630333c34 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 4nT8kSx+VAL4HjGsLWKVmHojeo2gQsbfYJxzgq3EOg9f5iIcnXzeQu/tpT8kPWbrDoPUNxQYR3FMRwyt3ZboZQb5GS2GLD9D/7C2Jfig7FQ8EmSk/9xYwyBPLb4l+/lJqp5ny2/2GQZY8VZX4PoqKRf8g7LiMcscNSTiKvWMXsw5ZbcMniu2ifywdLYljPvrypBsc2+Uhs9ks7fc2Uq/zxeOd30qsJs6lq+i8C3hIO38FfrZoy5w3nRKUXLTG5yXU2/BDq03LHNe8yesJddtIWXbeA160PR9VbBZ72Fuf2tN4JRdkIgcbL7IS2ZncY9l4E3ojQnaFetlU9CIVgYB31IzR/GIrzTv2kpf2ZJSEF4= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: bb578d9b-3b4e-4de2-e169-08d630333c34 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:53.6241 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 21/22] net/atlantic: read MAC registers for debug purposes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous This patch add support for dumping MAC registers. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/features/atlantic.ini | 1 + drivers/net/atlantic/atl_ethdev.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini index f09a75691a28..5ed095b14323 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -30,6 +30,7 @@ Extended stats = Y Stats per queue = Y FW version = Y EEPROM dump = Y +Registers dump = Y Linux UIO = Y ARMv8 = Y x86-32 = Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 824e624dd772..5bc04f55cc21 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -69,6 +69,10 @@ static int atl_dev_get_eeprom(struct rte_eth_dev *dev, static int atl_dev_set_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom); +/* Regs */ +static int atl_dev_get_regs(struct rte_eth_dev *dev, + struct rte_dev_reg_info *regs); + /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); @@ -229,6 +233,8 @@ static const struct eth_dev_ops atl_eth_dev_ops = { /* Link */ .link_update = atl_dev_link_update, + .get_reg = atl_dev_get_regs, + /* Stats */ .stats_get = atl_dev_stats_get, .xstats_get = atl_dev_xstats_get, @@ -1125,6 +1131,32 @@ atl_dev_set_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom) } static int +atl_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + u32 mif_id; + int err; + + if (regs->data == NULL) { + regs->length = hw_atl_utils_hw_get_reg_length(); + regs->width = sizeof(u32); + return 0; + } + + /* Only full register dump is supported */ + if (regs->length && regs->length != hw_atl_utils_hw_get_reg_length()) + return -ENOTSUP; + + err = hw_atl_utils_hw_get_regs(hw, regs->data); + + /* Device version */ + mif_id = hw_atl_reg_glb_mif_id_get(hw); + regs->version = mif_id & 0xFFU; + + return err; +} + +static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); From patchwork Fri Oct 12 11:09:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 46717 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5BAFA1B607; Fri, 12 Oct 2018 13:09:59 +0200 (CEST) Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-sn1nam01on0056.outbound.protection.outlook.com [104.47.32.56]) by dpdk.org (Postfix) with ESMTP id 5EA001B6CD for ; Fri, 12 Oct 2018 13:09:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tMb9QzwK1zj2amsmJmZ6x/v8MctN+ZDsPjXTOwiiyAw=; b=dK6V5fD4TsPWwXFOFVsgP/dYQSbD4WizRVj8HAMODOSZhsuPcgqinWonkEQhMlPn/4OetbohJxgZDrKTs1+083iYro2bsGFYlLMPFjAX4e2Z7y8KJQvlTkSWXhEvCVZ7enV/Gs9Ull00pdKvAzh6q3NxCY4Nu8iecFt5g7RP6sI= Received: from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by BY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.22; Fri, 12 Oct 2018 11:09:56 +0000 Received: from BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17]) by BY1PR0701MB1660.namprd07.prod.outlook.com ([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020; Fri, 12 Oct 2018 11:09:55 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 22/22] net/atlantic: add release notes Thread-Index: AQHUYhwbFrKjpTrmO0mfoxFCpgOk6A== Date: Fri, 12 Oct 2018 11:09:55 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:JT43DOEm/dQtiwWd+gKBePpmkpA2sp6xnNZxnSYzPUgZO3AKyE5cy4SxTMxEl8iTyAgh2CujN/uIFH9kNh/cXIeMqWh3Y1U8hnclrTxf5Yai7A9CbXb6uvBW2SQ6EkuF35lZhYIb4g0DDKzQZkmUchv8MyhYnnLYWfdOZ5GxhvRIj5KKQDRyM3qZ8dfFRjxFzoNy4IgzABEQTjzIZr4ghbSB03bC6c4tBlmwyfshQ9tTCfdAAY0AyZFf+Od1Ru2mBlSVkJdcA3yXs0BlkUnytj1a1/C9GYsMfpPoidRk/LjJin93Xas1njHUSWMAj88QZSlWReTYwkY8cflEFeO7AdDzvKy+5oL9nf8tcq0qoZXxHKK4HCq3I08U1HB4rRcCqRoirJRWgz+I/MGXtQ+ZGsM42BqiuSWCELIIdrlB5AjgvCcB/FohV3t+Yjiz6Apb1Gl8ze5G8GXnZYNOdOcGjVlEMAKlXVW6QAXeASB+gnA=; 5:fE/95rRaLW7Y1fiV4Dcoc3QSPX0NmChk3FbpWiTiKGQYwy3M6xEZ2MupxNczPT7+vXi0qgmLiu5IyyHccOK6tnEeX0aOQ12oAK84RedYlvUsJWoHGWWuDkutNa0t2qR5m7NKeNRtaqwqogOnLJGWPjGWfDu+ZwFmUmp2r4aHT1s=; 7:cDop88GS+FPTH0GuEAWoVFO0FaB1v/8V8bBKqj/ex6yMB5jZsXHxKtvmnODsZ1MHaqQ9d4CAf4etkD26tXIJj5zBmP3Rlxr1JEcPwkbZpGLjgFYwb5Qwy4PjikxRdMlkWjCiweDa2K827wGCKFDuV791KEnq2PG2jgPULbSqyxLqoipRdxUtWizfwcKPjDS1x0Ni07WCINqPCntF+ZEBDGB4Fgl8xt95tOfOJagZ8LeV4srfAYE2x8V0YKsW4dJv x-ms-office365-filtering-correlation-id: 3aa71310-b652-45fc-439e-08d630333d80 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BY1PR0701MB1627; x-ms-traffictypediagnostic: BY1PR0701MB1627: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(3231355)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(149066)(150057)(6041310)(20161123560045)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(201708071742011)(7699051)(76991067); SRVR:BY1PR0701MB1627; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1627; x-forefront-prvs: 0823A5777B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(5250100002)(11346002)(86362001)(25786009)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011); DIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627; H:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: r0N6faaw5LemMFd36N0evBGgfvHMDQh2pDrk9rhpkRkclhGBM0LVHVQOvlQsx7pCDFKyMV+dP3d0SwlOAnjiQT+9d7iUfPMU5eif25wnaiLXxq+ueeV8S5mne1KAty11wwh3BHqJTrPUIGRTPK98YpYRuxlD1+bnLYpqqHC0sYXLdocGYDQZ30hxbxlj31wwkiLkP4Wc9icOtPWICw9BwD/QVVW8VcQMPfOWqB3SVixaywX3Y5nQ2yC+cC0OtkqVml6gid+x84sWTJanAtB3GbN1CZrkFD7PNLj5DZsxKT5nHcGcqq2Jgo7xc9WQzdurHk8EL5UfKjmnF6vxlatJvVf8MKDGzMY1isjRALmP8/0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3aa71310-b652-45fc-439e-08d630333d80 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:55.8019 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 22/22] net/atlantic: add release notes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Release notes for Aquantia atlantic driver. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/rel_notes/release_18_11.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst index 2133a5b9bb2e..643ec4d9103d 100644 --- a/doc/guides/rel_notes/release_18_11.rst +++ b/doc/guides/rel_notes/release_18_11.rst @@ -104,6 +104,11 @@ New Features the specified port. The port must be stopped before the command call in order to reconfigure queues. +* **Added Ethernet poll mode driver for Aquantia aQtion family of 10G devices.** + + Added the new ``atlantic`` ethernet poll mode driver for Aquantia XGBE devices. + See the :doc:`../nics/atlantic` nic driver guide for more details on this + driver. API Changes -----------