From patchwork Wed Sep 1 16:32:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 97706 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D40C5A0C47; Wed, 1 Sep 2021 18:32:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A7941410FA; Wed, 1 Sep 2021 18:32:31 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 1A70D410F2 for ; Wed, 1 Sep 2021 18:32:28 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10094"; a="198359835" X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="198359835" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 09:32:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="645812711" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:27 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Wed, 1 Sep 2021 17:32:11 +0100 Message-Id: <20210901163216.120087-2-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901163216.120087-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210901163216.120087-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 1/6] dmadev: add device idle check for testing use X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add in a function to check if a device or vchan has completed all jobs assigned to it, without gathering in the results. This is primarily for use in testing, to allow the hardware to be in a known-state prior to gathering completions. Signed-off-by: Bruce Richardson --- lib/dmadev/rte_dmadev.c | 16 ++++++++++++++++ lib/dmadev/rte_dmadev.h | 21 +++++++++++++++++++++ lib/dmadev/rte_dmadev_core.h | 4 ++++ lib/dmadev/version.map | 1 + 4 files changed, 42 insertions(+) diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index 1c946402db..e249411631 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -555,3 +555,19 @@ rte_dmadev_dump(uint16_t dev_id, FILE *f) return 0; } + +int +rte_dmadev_vchan_idle(uint16_t dev_id, uint16_t vchan) +{ + struct rte_dmadev *dev = &rte_dmadevices[dev_id]; + + RTE_DMADEV_VALID_DEV_ID_OR_ERR_RET(dev_id, -EINVAL); + if (vchan >= dev->data->dev_conf.nb_vchans) { + RTE_DMADEV_LOG(ERR, + "Device %u vchan %u out of range\n", dev_id, vchan); + return -EINVAL; + } + + RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vchan_idle, -ENOTSUP); + return (*dev->dev_ops->vchan_idle)(dev, vchan); +} diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h index e8f58e9213..350e7defc8 100644 --- a/lib/dmadev/rte_dmadev.h +++ b/lib/dmadev/rte_dmadev.h @@ -1028,6 +1028,27 @@ rte_dmadev_completed_status(uint16_t dev_id, uint16_t vchan, return (*dev->completed_status)(dev, vchan, nb_cpls, last_idx, status); } +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Determine if all jobs have completed on a device channel. + * This function is primarily designed for testing use, as it allows a process to check if + * all jobs are completed, without actually gathering completions from those jobs. + * + * @param dev_id + * The identifier of the device. + * @param vchan + * The identifier of virtual DMA channel. + * @return + * 1 - if all jobs have completed and the device vchan is idle + * 0 - if there are still outstanding jobs yet to complete + * < 0 - error code indicating there was a problem calling the API + */ +__rte_experimental +int +rte_dmadev_vchan_idle(uint16_t dev_id, uint16_t vchan); + #ifdef __cplusplus } #endif diff --git a/lib/dmadev/rte_dmadev_core.h b/lib/dmadev/rte_dmadev_core.h index e94aa1c457..7ec5a5b572 100644 --- a/lib/dmadev/rte_dmadev_core.h +++ b/lib/dmadev/rte_dmadev_core.h @@ -53,6 +53,9 @@ typedef int (*rte_dmadev_stats_reset_t)(struct rte_dmadev *dev, uint16_t vchan); typedef int (*rte_dmadev_dump_t)(const struct rte_dmadev *dev, FILE *f); /**< @internal Used to dump internal information. */ +typedef int (*rte_dmadev_vchan_idle_t)(const struct rte_dmadev *dev, uint16_t vchan); +/**< @internal Used to check if a virtual channel has finished all jobs. */ + typedef int (*rte_dmadev_copy_t)(struct rte_dmadev *dev, uint16_t vchan, rte_iova_t src, rte_iova_t dst, uint32_t length, uint64_t flags); @@ -106,6 +109,7 @@ struct rte_dmadev_ops { rte_dmadev_stats_get_t stats_get; rte_dmadev_stats_reset_t stats_reset; rte_dmadev_dump_t dev_dump; + rte_dmadev_vchan_idle_t vchan_idle; }; /** diff --git a/lib/dmadev/version.map b/lib/dmadev/version.map index 80be592713..b7e52fda3d 100644 --- a/lib/dmadev/version.map +++ b/lib/dmadev/version.map @@ -18,6 +18,7 @@ EXPERIMENTAL { rte_dmadev_stats_reset; rte_dmadev_stop; rte_dmadev_submit; + rte_dmadev_vchan_idle; rte_dmadev_vchan_setup; local: *; From patchwork Wed Sep 1 16:32:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 97707 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0282A0C47; Wed, 1 Sep 2021 18:32:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC3FE41149; Wed, 1 Sep 2021 18:32:33 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id AABBD4113B for ; Wed, 1 Sep 2021 18:32:32 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10094"; a="198359873" X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="198359873" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 09:32:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="645812761" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:30 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Wed, 1 Sep 2021 17:32:12 +0100 Message-Id: <20210901163216.120087-3-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901163216.120087-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210901163216.120087-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 2/6] app/test: add basic dmadev instance tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Run basic sanity tests for configuring, starting and stopping a dmadev instance to help validate drivers. This also provides the framework for future tests for data-path operation. Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 81 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index bb01e86483..12f7c69629 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -2,6 +2,7 @@ * Copyright(c) 2021 HiSilicon Limited. * Copyright(c) 2021 Intel Corporation. */ +#include #include #include @@ -13,6 +14,77 @@ /* from test_dmadev_api.c */ extern int test_dmadev_api(uint16_t dev_id); +#define PRINT_ERR(...) print_err(__func__, __LINE__, __VA_ARGS__) + +static inline int +__rte_format_printf(3, 4) +print_err(const char *func, int lineno, const char *format, ...) +{ + va_list ap; + int ret; + + ret = fprintf(stderr, "In %s:%d - ", func, lineno); + va_start(ap, format); + ret += vfprintf(stderr, format, ap); + va_end(ap); + + return ret; +} + +static int +test_dmadev_instance(uint16_t dev_id) +{ +#define TEST_RINGSIZE 512 + struct rte_dmadev_stats stats; + struct rte_dmadev_info info; + const struct rte_dmadev_conf conf = { .nb_vchans = 1}; + const struct rte_dmadev_vchan_conf qconf = { + .direction = RTE_DMA_DIR_MEM_TO_MEM, + .nb_desc = TEST_RINGSIZE, + }; + const int vchan = 0; + + printf("\n### Test dmadev instance %u\n", dev_id); + + rte_dmadev_info_get(dev_id, &info); + if (info.max_vchans < 1) { + PRINT_ERR("Error, no channels available on device id %u\n", dev_id); + return -1; + } + if (rte_dmadev_configure(dev_id, &conf) != 0) { + PRINT_ERR("Error with rte_dmadev_configure()\n"); + return -1; + } + if (rte_dmadev_vchan_setup(dev_id, vchan, &qconf) < 0) { + PRINT_ERR("Error with queue configuration\n"); + return -1; + } + + rte_dmadev_info_get(dev_id, &info); + if (info.nb_vchans != 1) { + PRINT_ERR("Error, no configured queues reported on device id %u\n", dev_id); + return -1; + } + + if (rte_dmadev_start(dev_id) != 0) { + PRINT_ERR("Error with rte_dmadev_start()\n"); + return -1; + } + if (rte_dmadev_stats_get(dev_id, vchan, &stats) != 0) { + PRINT_ERR("Error with rte_dmadev_stats_get()\n"); + return -1; + } + if (stats.completed != 0 || stats.submitted != 0 || stats.errors != 0) { + PRINT_ERR("Error device stats are not all zero: completed = %"PRIu64", submitted = %"PRIu64", errors = %"PRIu64"\n", + stats.completed, stats.submitted, stats.errors); + return -1; + } + + rte_dmadev_stop(dev_id); + rte_dmadev_stats_reset(dev_id, vchan); + return 0; +} + static int test_apis(void) { @@ -35,10 +107,19 @@ test_apis(void) static int test_dmadev(void) { + int i; + /* basic sanity on dmadev infrastructure */ if (test_apis() < 0) return -1; + if (rte_dmadev_count() == 0) + return TEST_SKIPPED; + + for (i = 0; i < RTE_DMADEV_MAX_DEVS; i++) + if (rte_dmadevices[i].state == RTE_DMADEV_ATTACHED && test_dmadev_instance(i) < 0) + return -1; + return 0; } From patchwork Wed Sep 1 16:32:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 97708 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53268A0C47; Wed, 1 Sep 2021 18:32:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 078D34116A; Wed, 1 Sep 2021 18:32:39 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id D748540F35 for ; Wed, 1 Sep 2021 18:32:36 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10094"; a="198359892" X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="198359892" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 09:32:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="645812814" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:34 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Wed, 1 Sep 2021 17:32:13 +0100 Message-Id: <20210901163216.120087-4-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901163216.120087-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210901163216.120087-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 3/6] app/test: add basic dmadev copy tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For each dmadev instance, perform some basic copy tests to validate that functionality. Signed-off-by: Bruce Richardson Reviewed-by: Kevin Laatz Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 174 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 12f7c69629..261f45db71 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -2,12 +2,15 @@ * Copyright(c) 2021 HiSilicon Limited. * Copyright(c) 2021 Intel Corporation. */ +#include #include #include #include #include #include +#include +#include #include "test.h" @@ -16,6 +19,11 @@ extern int test_dmadev_api(uint16_t dev_id); #define PRINT_ERR(...) print_err(__func__, __LINE__, __VA_ARGS__) +#define COPY_LEN 1024 + +static struct rte_mempool *pool; +static uint16_t id_count; + static inline int __rte_format_printf(3, 4) print_err(const char *func, int lineno, const char *format, ...) @@ -31,6 +39,134 @@ print_err(const char *func, int lineno, const char *format, ...) return ret; } +static inline void +await_hw(int dev_id, uint16_t vchan) +{ + int idle = rte_dmadev_vchan_idle(dev_id, vchan); + if (idle < 0) { + /* for drivers that don't support this op, just sleep for 25 microseconds */ + usleep(25); + return; + } + + /* for those that do, *max* end time is one second from now, but all should be faster */ + const uint64_t end_cycles = rte_get_timer_cycles() + rte_get_timer_hz(); + while (!idle && rte_get_timer_cycles() < end_cycles) { + rte_pause(); + idle = rte_dmadev_vchan_idle(dev_id, vchan); + } +} + +static int +test_enqueue_copies(int dev_id, uint16_t vchan) +{ + unsigned int i; + uint16_t id; + + /* test doing a single copy */ + do { + struct rte_mbuf *src, *dst; + char *src_data, *dst_data; + + src = rte_pktmbuf_alloc(pool); + dst = rte_pktmbuf_alloc(pool); + src_data = rte_pktmbuf_mtod(src, char *); + dst_data = rte_pktmbuf_mtod(dst, char *); + + for (i = 0; i < COPY_LEN; i++) + src_data[i] = rte_rand() & 0xFF; + + id = rte_dmadev_copy(dev_id, vchan, src->buf_iova + src->data_off, + dst->buf_iova + dst->data_off, COPY_LEN, RTE_DMA_OP_FLAG_SUBMIT); + if (id != id_count) { + PRINT_ERR("Error with rte_dmadev_copy, got %u, expected %u\n", + id, id_count); + return -1; + } + + /* give time for copy to finish, then check it was done */ + await_hw(dev_id, vchan); + + for (i = 0; i < COPY_LEN; i++) { + if (dst_data[i] != src_data[i]) { + PRINT_ERR("Data mismatch at char %u [Got %02x not %02x]\n", i, + dst_data[i], src_data[i]); + rte_dmadev_dump(dev_id, stderr); + return -1; + } + } + + /* now check completion works */ + if (rte_dmadev_completed(dev_id, vchan, 1, &id, NULL) != 1) { + PRINT_ERR("Error with rte_dmadev_completed\n"); + return -1; + } + if (id != id_count) { + PRINT_ERR("Error:incorrect job id received, %u [expected %u]\n", + id, id_count); + return -1; + } + + rte_pktmbuf_free(src); + rte_pktmbuf_free(dst); + + /* now check completion works */ + if (rte_dmadev_completed(dev_id, 0, 1, NULL, NULL) != 0) { + PRINT_ERR("Error with rte_dmadev_completed in empty check\n"); + return -1; + } + id_count++; + + } while (0); + + /* test doing a multiple single copies */ + do { + const uint16_t max_ops = 4; + struct rte_mbuf *src, *dst; + char *src_data, *dst_data; + + src = rte_pktmbuf_alloc(pool); + dst = rte_pktmbuf_alloc(pool); + src_data = rte_pktmbuf_mtod(src, char *); + dst_data = rte_pktmbuf_mtod(dst, char *); + + for (i = 0; i < COPY_LEN; i++) + src_data[i] = rte_rand() & 0xFF; + + /* perform the same copy times */ + for (i = 0; i < max_ops; i++) { + if (rte_dmadev_copy(dev_id, vchan, + src->buf_iova + src->data_off, + dst->buf_iova + dst->data_off, + COPY_LEN, RTE_DMA_OP_FLAG_SUBMIT) != id_count++) { + PRINT_ERR("Error with rte_dmadev_copy\n"); + return -1; + } + } + await_hw(dev_id, vchan); + + if ((i = rte_dmadev_completed(dev_id, vchan, max_ops * 2, &id, NULL)) != max_ops) { + PRINT_ERR("Error with rte_dmadev_completed, got %u not %u\n", i, max_ops); + return -1; + } + if (id != id_count - 1) { + PRINT_ERR("Error, incorrect job id returned: got %u not %u\n", + id, id_count - 1); + return -1; + } + for (i = 0; i < COPY_LEN; i++) { + if (dst_data[i] != src_data[i]) { + PRINT_ERR("Data mismatch at char %u\n", i); + return -1; + } + } + rte_pktmbuf_free(src); + rte_pktmbuf_free(dst); + } while (0); + + return 0; +} + static int test_dmadev_instance(uint16_t dev_id) { @@ -43,6 +179,7 @@ test_dmadev_instance(uint16_t dev_id) .nb_desc = TEST_RINGSIZE, }; const int vchan = 0; + int i; printf("\n### Test dmadev instance %u\n", dev_id); @@ -79,10 +216,47 @@ test_dmadev_instance(uint16_t dev_id) stats.completed, stats.submitted, stats.errors); return -1; } + id_count = 0; + + /* create a mempool for running tests */ + pool = rte_pktmbuf_pool_create("TEST_DMADEV_POOL", + TEST_RINGSIZE * 2, /* n == num elements */ + 32, /* cache size */ + 0, /* priv size */ + 2048, /* data room size */ + info.device->numa_node); + if (pool == NULL) { + PRINT_ERR("Error with mempool creation\n"); + return -1; + } + + /* run the test cases, use many iterations to ensure UINT16_MAX id wraparound */ + printf("DMA Dev: %u, Running Copy Tests\n", dev_id); + for (i = 0; i < 640; i++) { + + if (test_enqueue_copies(dev_id, vchan) != 0) { + printf("Error with iteration %d\n", i); + rte_dmadev_dump(dev_id, stdout); + goto err; + } + rte_dmadev_stats_get(dev_id, 0, &stats); + printf("Ops submitted: %"PRIu64"\t", stats.submitted); + printf("Ops completed: %"PRIu64"\t", stats.completed); + printf("Errors: %"PRIu64"\r", stats.errors); + } + printf("\n"); + + + rte_mempool_free(pool); rte_dmadev_stop(dev_id); rte_dmadev_stats_reset(dev_id, vchan); return 0; + +err: + rte_mempool_free(pool); + rte_dmadev_stop(dev_id); + return -1; } static int From patchwork Wed Sep 1 16:32:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 97709 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 380A9A0C47; Wed, 1 Sep 2021 18:32:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A9F04116F; Wed, 1 Sep 2021 18:32:41 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 0BA694116F for ; Wed, 1 Sep 2021 18:32:39 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10094"; a="198359900" X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="198359900" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 09:32:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="645812868" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:38 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Wed, 1 Sep 2021 17:32:14 +0100 Message-Id: <20210901163216.120087-5-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901163216.120087-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210901163216.120087-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 4/6] app/test: add more comprehensive dmadev copy tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add unit tests for various combinations of use for dmadev, copying bursts of packets in various formats, e.g. 1. enqueuing two smaller bursts and completing them as one burst 2. enqueuing one burst and gathering completions in smaller bursts 3. using completed_status() function to gather completions rather than just completed() Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh Reviewed-by: Kevin Laatz --- app/test/test_dmadev.c | 142 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 2 deletions(-) diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 261f45db71..7a808a9cba 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -39,6 +39,20 @@ print_err(const char *func, int lineno, const char *format, ...) return ret; } +static inline int +check_stats(struct rte_dmadev_stats *stats, bool check_errors) +{ + if (stats->completed != stats->submitted) { + PRINT_ERR("Error, not all submitted jobs are reported as completed\n"); + return -1; + } + if (check_errors && stats->errors != 0) { + PRINT_ERR("Errors reported during copy processing, aborting tests\n"); + return -1; + } + return 0; +} + static inline void await_hw(int dev_id, uint16_t vchan) { @@ -57,6 +71,120 @@ await_hw(int dev_id, uint16_t vchan) } } +/* run a series of copy tests just using some different options for enqueues and completions */ +static int +do_multi_copies(int dev_id, uint16_t vchan, + int split_batches, /* submit 2 x 16 or 1 x 32 burst */ + int split_completions, /* gather 2 x 16 or 1 x 32 completions */ + int use_completed_status) /* use completed or completed_status function */ +{ + struct rte_mbuf *srcs[32], *dsts[32]; + enum rte_dma_status_code sc[32]; + unsigned int i, j; + bool dma_err = false; + + /* Enqueue burst of copies and hit doorbell */ + for (i = 0; i < RTE_DIM(srcs); i++) { + uint64_t *src_data; + + if (split_batches && i == RTE_DIM(srcs) / 2) + rte_dmadev_submit(dev_id, vchan); + + srcs[i] = rte_pktmbuf_alloc(pool); + dsts[i] = rte_pktmbuf_alloc(pool); + if (srcs[i] == NULL || dsts[i] == NULL) { + PRINT_ERR("Error allocating buffers\n"); + return -1; + } + src_data = rte_pktmbuf_mtod(srcs[i], uint64_t *); + + for (j = 0; j < COPY_LEN/sizeof(uint64_t); j++) + src_data[j] = rte_rand(); + + if (rte_dmadev_copy(dev_id, vchan, srcs[i]->buf_iova + srcs[i]->data_off, + dsts[i]->buf_iova + dsts[i]->data_off, COPY_LEN, 0) != id_count++) { + PRINT_ERR("Error with rte_dmadev_copy for buffer %u\n", i); + return -1; + } + } + rte_dmadev_submit(dev_id, vchan); + + await_hw(dev_id, vchan); + + if (split_completions) { + /* gather completions in two halves */ + uint16_t half_len = RTE_DIM(srcs) / 2; + int ret = rte_dmadev_completed(dev_id, vchan, half_len, NULL, &dma_err); + if (ret != half_len || dma_err) { + PRINT_ERR("Error with rte_dmadev_completed - first half. ret = %d, expected ret = %u, dma_err = %d\n", + ret, half_len, dma_err); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + ret = rte_dmadev_completed(dev_id, vchan, half_len, NULL, &dma_err); + if (ret != half_len || dma_err) { + PRINT_ERR("Error with rte_dmadev_completed - second half. ret = %d, expected ret = %u, dma_err = %d\n", + ret, half_len, dma_err); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + } else { + /* gather all completions in one go, using either + * completed or completed_status fns + */ + if (!use_completed_status) { + int n = rte_dmadev_completed(dev_id, vchan, RTE_DIM(srcs), NULL, &dma_err); + if (n != RTE_DIM(srcs) || dma_err) { + PRINT_ERR("Error with rte_dmadev_completed, %u [expected: %zu], dma_err = %d\n", + n, RTE_DIM(srcs), dma_err); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + } else { + int n = rte_dmadev_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc); + if (n != RTE_DIM(srcs)) { + PRINT_ERR("Error with rte_dmadev_completed_status, %u [expected: %zu]\n", + n, RTE_DIM(srcs)); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + for (j = 0; j < (uint16_t)n; j++) { + if (sc[j] != RTE_DMA_STATUS_SUCCESSFUL) { + PRINT_ERR("Error with rte_dmadev_completed_status, job %u reports failure [code %u]\n", + j, sc[j]); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + } + } + } + + /* check for empty */ + int ret = use_completed_status ? + rte_dmadev_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc) : + rte_dmadev_completed(dev_id, vchan, RTE_DIM(srcs), NULL, &dma_err); + if (ret != 0) { + PRINT_ERR("Error with completion check - ops unexpectedly returned\n"); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + + for (i = 0; i < RTE_DIM(srcs); i++) { + char *src_data, *dst_data; + + src_data = rte_pktmbuf_mtod(srcs[i], char *); + dst_data = rte_pktmbuf_mtod(dsts[i], char *); + for (j = 0; j < COPY_LEN; j++) + if (src_data[j] != dst_data[j]) { + PRINT_ERR("Error with copy of packet %u, byte %u\n", i, j); + return -1; + } + rte_pktmbuf_free(srcs[i]); + rte_pktmbuf_free(dsts[i]); + } + return 0; +} + static int test_enqueue_copies(int dev_id, uint16_t vchan) { @@ -164,7 +292,14 @@ test_enqueue_copies(int dev_id, uint16_t vchan) rte_pktmbuf_free(dst); } while (0); - return 0; + /* test doing multiple copies */ + return do_multi_copies(dev_id, vchan, 0, 0, 0) /* enqueue and complete 1 batch at a time */ + /* enqueue 2 batches and then complete both */ + || do_multi_copies(dev_id, vchan, 1, 0, 0) + /* enqueue 1 batch, then complete in two halves */ + || do_multi_copies(dev_id, vchan, 0, 1, 0) + /* test using completed_status in place of regular completed API */ + || do_multi_copies(dev_id, vchan, 0, 0, 1); } static int @@ -216,6 +351,8 @@ test_dmadev_instance(uint16_t dev_id) stats.completed, stats.submitted, stats.errors); return -1; } + + rte_dmadev_stats_reset(dev_id, vchan); id_count = 0; /* create a mempool for running tests */ @@ -246,7 +383,8 @@ test_dmadev_instance(uint16_t dev_id) printf("Errors: %"PRIu64"\r", stats.errors); } printf("\n"); - + if (check_stats(&stats, true) < 0) + goto err; rte_mempool_free(pool); rte_dmadev_stop(dev_id); From patchwork Wed Sep 1 16:32:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 97710 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 148F4A0C47; Wed, 1 Sep 2021 18:32:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 513E241178; Wed, 1 Sep 2021 18:32:45 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 3D825410E9 for ; Wed, 1 Sep 2021 18:32:43 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10094"; a="198359913" X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="198359913" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 09:32:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="645812885" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:41 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Wed, 1 Sep 2021 17:32:15 +0100 Message-Id: <20210901163216.120087-6-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901163216.120087-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210901163216.120087-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 5/6] app/test: test dmadev instance failure handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a series of tests to inject bad copy operations into a dmadev to test the error handling and reporting capabilities. Various combinations of errors in various positions in a burst are tested, as are errors in bursts with fence flag set, and multiple errors in a single burst. Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh Reviewed-by: Kevin Laatz --- app/test/test_dmadev.c | 427 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 427 insertions(+) diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 7a808a9cba..5d7b6ddd87 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -302,6 +302,414 @@ test_enqueue_copies(int dev_id, uint16_t vchan) || do_multi_copies(dev_id, vchan, 0, 0, 1); } +/* Failure handling test cases - global macros and variables for those tests*/ +#define COMP_BURST_SZ 16 +#define OPT_FENCE(idx) ((fence && idx == 8) ? RTE_DMA_OP_FLAG_FENCE : 0) + +static int +test_failure_in_full_burst(int dev_id, uint16_t vchan, bool fence, + struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) +{ + /* Test single full batch statuses with failures */ + enum rte_dma_status_code status[COMP_BURST_SZ]; + struct rte_dmadev_stats baseline, stats; + uint16_t invalid_addr_id = 0; + uint16_t idx; + uint16_t count, status_count; + unsigned int i; + bool error = 0; + int err_count = 0; + + rte_dmadev_stats_get(dev_id, vchan, &baseline); /* get a baseline set of stats */ + for (i = 0; i < COMP_BURST_SZ; i++) { + int id = rte_dmadev_copy(dev_id, vchan, + (i == fail_idx ? 0 : (srcs[i]->buf_iova + srcs[i]->data_off)), + dsts[i]->buf_iova + dsts[i]->data_off, + COPY_LEN, OPT_FENCE(i)); + if (id < 0) { + PRINT_ERR("Error with rte_dmadev_copy for buffer %u\n", i); + return -1; + } + if (i == fail_idx) + invalid_addr_id = id; + } + rte_dmadev_submit(dev_id, vchan); + rte_dmadev_stats_get(dev_id, vchan, &stats); + if (stats.submitted != baseline.submitted + COMP_BURST_SZ) { + PRINT_ERR("Submitted stats value not as expected, %"PRIu64" not %"PRIu64"\n", + stats.submitted, baseline.submitted + COMP_BURST_SZ); + return -1; + } + + await_hw(dev_id, vchan); + + count = rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); + if (count != fail_idx) { + PRINT_ERR("Error with rte_dmadev_completed for failure test. Got returned %u not %u.\n", + count, fail_idx); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + if (error == false) { + PRINT_ERR("Error, missing expected failed copy, %u. has_error is not set\n", + fail_idx); + return -1; + } + if (idx != invalid_addr_id - 1) { + PRINT_ERR("Error, missing expected failed copy, %u. Got last idx %u, not %u\n", + fail_idx, idx, invalid_addr_id - 1); + return -1; + } + + /* all checks ok, now verify calling completed() again always returns 0 */ + for (i = 0; i < 10; i++) { + if (rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error) != 0 + || error == false || idx != (invalid_addr_id - 1)) { + PRINT_ERR("Error with follow-up completed calls for fail idx %u\n", + fail_idx); + return -1; + } + } + + status_count = rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ, + &idx, status); + /* some HW may stop on error and be restarted after getting error status for single value + * To handle this case, if we get just one error back, wait for more completions and get + * status for rest of the burst + */ + if (status_count == 1) { + await_hw(dev_id, vchan); + status_count += rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ - 1, + &idx, &status[1]); + } + /* check that at this point we have all status values */ + if (status_count != COMP_BURST_SZ - count) { + PRINT_ERR("Error with completed_status calls for fail idx %u. Got %u not %u\n", + fail_idx, status_count, COMP_BURST_SZ - count); + return -1; + } + /* now verify just one failure followed by multiple successful or skipped entries */ + if (status[0] == RTE_DMA_STATUS_SUCCESSFUL) { + PRINT_ERR("Error with status returned for fail idx %u. First status was not failure\n", + fail_idx); + return -1; + } + for (i = 1; i < status_count; i++) { + /* after a failure in a burst, depending on ordering/fencing, + * operations may be successful or skipped because of previous error. + */ + if (status[i] != RTE_DMA_STATUS_SUCCESSFUL + && status[i] != RTE_DMA_STATUS_NOT_ATTEMPTED) { + PRINT_ERR("Error with status calls for fail idx %u. Status for job %u (of %u) is not successful\n", + fail_idx, count + i, COMP_BURST_SZ); + return -1; + } + } + + /* check the completed + errors stats are as expected */ + rte_dmadev_stats_get(dev_id, vchan, &stats); + if (stats.completed != baseline.completed + COMP_BURST_SZ) { + PRINT_ERR("Completed stats value not as expected, %"PRIu64" not %"PRIu64"\n", + stats.completed, baseline.completed + COMP_BURST_SZ); + return -1; + } + for (i = 0; i < status_count; i++) + err_count += (status[i] != RTE_DMA_STATUS_SUCCESSFUL); + if (stats.errors != baseline.errors + err_count) { + PRINT_ERR("'Errors' stats value not as expected, %"PRIu64" not %"PRIu64"\n", + stats.errors, baseline.errors + err_count); + return -1; + } + + return 0; +} + +static int +test_individual_status_query_with_failure(int dev_id, uint16_t vchan, bool fence, + struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) +{ + /* Test gathering batch statuses one at a time */ + enum rte_dma_status_code status[COMP_BURST_SZ]; + uint16_t invalid_addr_id = 0; + uint16_t idx; + uint16_t count = 0, status_count = 0; + unsigned int j; + bool error = false; + + for (j = 0; j < COMP_BURST_SZ; j++) { + int id = rte_dmadev_copy(dev_id, vchan, + (j == fail_idx ? 0 : (srcs[j]->buf_iova + srcs[j]->data_off)), + dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, OPT_FENCE(j)); + if (id < 0) { + PRINT_ERR("Error with rte_dmadev_copy for buffer %u\n", j); + return -1; + } + if (j == fail_idx) + invalid_addr_id = id; + } + rte_dmadev_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + /* use regular "completed" until we hit error */ + while (!error) { + uint16_t n = rte_dmadev_completed(dev_id, vchan, 1, &idx, &error); + count += n; + if (n > 1 || count >= COMP_BURST_SZ) { + PRINT_ERR("Error - too many completions got\n"); + return -1; + } + if (n == 0 && !error) { + PRINT_ERR("Error, unexpectedly got zero completions after %u completed\n", + count); + return -1; + } + } + if (idx != invalid_addr_id - 1) { + PRINT_ERR("Error, last successful index not as expected, got %u, expected %u\n", + idx, invalid_addr_id - 1); + return -1; + } + + /* use completed_status until we hit end of burst */ + while (count + status_count < COMP_BURST_SZ) { + uint16_t n = rte_dmadev_completed_status(dev_id, vchan, 1, &idx, + &status[status_count]); + await_hw(dev_id, vchan); /* allow delay to ensure jobs are completed */ + status_count += n; + if (n != 1) { + PRINT_ERR("Error: unexpected number of completions received, %u, not 1\n", + n); + return -1; + } + } + + /* check for single failure */ + if (status[0] == RTE_DMA_STATUS_SUCCESSFUL) { + PRINT_ERR("Error, unexpected successful DMA transaction\n"); + return -1; + } + for (j = 1; j < status_count; j++) { + if (status[j] != RTE_DMA_STATUS_SUCCESSFUL + && status[j] != RTE_DMA_STATUS_NOT_ATTEMPTED) { + PRINT_ERR("Error, unexpected DMA error reported\n"); + return -1; + } + } + + return 0; +} + +static int +test_single_item_status_query_with_failure(int dev_id, uint16_t vchan, + struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) +{ + /* When error occurs just collect a single error using "completed_status()" + * before going to back to completed() calls + */ + enum rte_dma_status_code status; + uint16_t invalid_addr_id = 0; + uint16_t idx; + uint16_t count, status_count, count2; + unsigned int j; + bool error = 0; + + for (j = 0; j < COMP_BURST_SZ; j++) { + int id = rte_dmadev_copy(dev_id, vchan, + (j == fail_idx ? 0 : (srcs[j]->buf_iova + srcs[j]->data_off)), + dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, 0); + if (id < 0) { + PRINT_ERR("Error with rte_dmadev_copy for buffer %u\n", j); + return -1; + } + if (j == fail_idx) + invalid_addr_id = id; + } + rte_dmadev_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + /* get up to the error point */ + count = rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); + if (count != fail_idx) { + PRINT_ERR("Error with rte_dmadev_completed for failure test. Got returned %u not %u.\n", + count, fail_idx); + rte_dmadev_dump(dev_id, stdout); + return -1; + } + if (error == false) { + PRINT_ERR("Error, missing expected failed copy, %u. has_error is not set\n", + fail_idx); + return -1; + } + if (idx != invalid_addr_id - 1) { + PRINT_ERR("Error, missing expected failed copy, %u. Got last idx %u, not %u\n", + fail_idx, idx, invalid_addr_id - 1); + return -1; + } + + /* get the error code */ + status_count = rte_dmadev_completed_status(dev_id, vchan, 1, &idx, &status); + if (status_count != 1) { + PRINT_ERR("Error with completed_status calls for fail idx %u. Got %u not %u\n", + fail_idx, status_count, COMP_BURST_SZ - count); + return -1; + } + if (status == RTE_DMA_STATUS_SUCCESSFUL) { + PRINT_ERR("Error with status returned for fail idx %u. First status was not failure\n", + fail_idx); + return -1; + } + /* delay in case time needed after err handled to complete other jobs */ + await_hw(dev_id, vchan); + + /* get the rest of the completions without status */ + count2 = rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); + if (error == true) { + PRINT_ERR("Error, got further errors post completed_status() call, for failure case %u.\n", + fail_idx); + return -1; + } + if (count + status_count + count2 != COMP_BURST_SZ) { + PRINT_ERR("Error, incorrect number of completions received, got %u not %u\n", + count + status_count + count2, COMP_BURST_SZ); + return -1; + } + + return 0; +} + +static int +test_multi_failure(int dev_id, uint16_t vchan, struct rte_mbuf **srcs, struct rte_mbuf **dsts, + const unsigned int *fail, size_t num_fail) +{ + /* test having multiple errors in one go */ + enum rte_dma_status_code status[COMP_BURST_SZ]; + unsigned int i, j; + uint16_t count, err_count = 0; + bool error = 0; + + /* enqueue and gather completions in one go */ + for (j = 0; j < COMP_BURST_SZ; j++) { + uintptr_t src = srcs[j]->buf_iova + srcs[j]->data_off; + /* set up for failure if the current index is anywhere is the fails array */ + for (i = 0; i < num_fail; i++) + if (j == fail[i]) + src = 0; + + int id = rte_dmadev_copy(dev_id, vchan, + src, dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, 0); + if (id < 0) { + PRINT_ERR("Error with rte_dmadev_copy for buffer %u\n", j); + return -1; + } + } + rte_dmadev_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + count = rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ, NULL, status); + while (count < COMP_BURST_SZ) { + await_hw(dev_id, vchan); + + uint16_t ret = rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ - count, + NULL, &status[count]); + if (ret == 0) { + PRINT_ERR("Error getting all completions for jobs. Got %u of %u\n", + count, COMP_BURST_SZ); + return -1; + } + count += ret; + } + for (i = 0; i < count; i++) { + if (status[i] != RTE_DMA_STATUS_SUCCESSFUL) + err_count++; + } + if (err_count != num_fail) { + PRINT_ERR("Error: Invalid number of failed completions returned, %u; expected %zu\n", + err_count, num_fail); + return -1; + } + + /* enqueue and gather completions in bursts, but getting errors one at a time */ + for (j = 0; j < COMP_BURST_SZ; j++) { + uintptr_t src = srcs[j]->buf_iova + srcs[j]->data_off; + /* set up for failure if the current index is anywhere is the fails array */ + for (i = 0; i < num_fail; i++) + if (j == fail[i]) + src = 0; + + int id = rte_dmadev_copy(dev_id, vchan, + src, dsts[j]->buf_iova + dsts[j]->data_off, + COPY_LEN, 0); + if (id < 0) { + PRINT_ERR("Error with rte_dmadev_copy for buffer %u\n", j); + return -1; + } + } + rte_dmadev_submit(dev_id, vchan); + await_hw(dev_id, vchan); + + count = 0; + err_count = 0; + while (count + err_count < COMP_BURST_SZ) { + count += rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, NULL, &error); + if (error) { + uint16_t ret = rte_dmadev_completed_status(dev_id, vchan, 1, + NULL, status); + if (ret != 1) { + PRINT_ERR("Error getting error-status for completions\n"); + return -1; + } + err_count += ret; + await_hw(dev_id, vchan); + } + } + if (err_count != num_fail) { + PRINT_ERR("Error: Incorrect number of failed completions received, got %u not %zu\n", + err_count, num_fail); + return -1; + } + + return 0; +} + +static int +test_completion_status(int dev_id, uint16_t vchan, bool fence) +{ + const unsigned int fail[] = {0, 7, 14, 15}; + struct rte_mbuf *srcs[COMP_BURST_SZ], *dsts[COMP_BURST_SZ]; + unsigned int i; + + for (i = 0; i < COMP_BURST_SZ; i++) { + srcs[i] = rte_pktmbuf_alloc(pool); + dsts[i] = rte_pktmbuf_alloc(pool); + } + + for (i = 0; i < RTE_DIM(fail); i++) { + if (test_failure_in_full_burst(dev_id, vchan, fence, srcs, dsts, fail[i]) < 0) + return -1; + + if (test_individual_status_query_with_failure(dev_id, vchan, fence, + srcs, dsts, fail[i]) < 0) + return -1; + + /* test is run the same fenced, or unfenced, but no harm in running it twice */ + if (test_single_item_status_query_with_failure(dev_id, vchan, + srcs, dsts, fail[i]) < 0) + return -1; + } + + if (test_multi_failure(dev_id, vchan, srcs, dsts, fail, RTE_DIM(fail)) < 0) + return -1; + + for (i = 0; i < COMP_BURST_SZ; i++) { + rte_pktmbuf_free(srcs[i]); + rte_pktmbuf_free(dsts[i]); + } + return 0; +} + static int test_dmadev_instance(uint16_t dev_id) { @@ -386,6 +794,25 @@ test_dmadev_instance(uint16_t dev_id) if (check_stats(&stats, true) < 0) goto err; + /* to test error handling we can provide null pointers for source or dest in copies. This + * requires VA mode in DPDK, since NULL(0) is a valid physical address. + */ + if (rte_eal_iova_mode() == RTE_IOVA_VA) { + rte_dmadev_stats_reset(dev_id, vchan); + printf("DMA Dev: %u, Running Completion Handling Tests (errors expected)\n", + dev_id); + if (test_completion_status(dev_id, vchan, false) != 0) /* without fences */ + goto err; + if (test_completion_status(dev_id, vchan, true) != 0) /* with fences */ + goto err; + rte_dmadev_stats_get(dev_id, 0, &stats); + printf("Ops submitted: %"PRIu64"\t", stats.submitted); + printf("Ops completed: %"PRIu64"\t", stats.completed); + printf("Errors: %"PRIu64"\n", stats.errors); + if (check_stats(&stats, false) < 0) /* don't check stats.errors this time */ + goto err; + } + rte_mempool_free(pool); rte_dmadev_stop(dev_id); rte_dmadev_stats_reset(dev_id, vchan); From patchwork Wed Sep 1 16:32:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 97711 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B092A0C47; Wed, 1 Sep 2021 18:33:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B8EA841188; Wed, 1 Sep 2021 18:32:47 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id EABD54117E for ; Wed, 1 Sep 2021 18:32:45 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10094"; a="198359922" X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="198359922" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 09:32:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="645812891" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:43 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Wed, 1 Sep 2021 17:32:16 +0100 Message-Id: <20210901163216.120087-7-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901163216.120087-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210901163216.120087-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 6/6] app/test: add dmadev fill tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kevin Laatz For dma devices which support the fill operation, run unit tests to verify fill behaviour is correct. Signed-off-by: Kevin Laatz Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 73 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index 5d7b6ddd87..c44c3ad9db 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -710,6 +710,62 @@ test_completion_status(int dev_id, uint16_t vchan, bool fence) return 0; } +static int +test_enqueue_fill(int dev_id, uint16_t vchan) +{ + const unsigned int lengths[] = {8, 64, 1024, 50, 100, 89}; + struct rte_mbuf *dst; + char *dst_data; + uint64_t pattern = 0xfedcba9876543210; + unsigned int i, j; + + dst = rte_pktmbuf_alloc(pool); + if (dst == NULL) { + PRINT_ERR("Failed to allocate mbuf\n"); + return -1; + } + dst_data = rte_pktmbuf_mtod(dst, char *); + + for (i = 0; i < RTE_DIM(lengths); i++) { + /* reset dst_data */ + memset(dst_data, 0, rte_pktmbuf_data_len(dst)); + + /* perform the fill operation */ + int id = rte_dmadev_fill(dev_id, vchan, pattern, + rte_pktmbuf_iova(dst), lengths[i], RTE_DMA_OP_FLAG_SUBMIT); + if (id < 0) { + PRINT_ERR("Error with rte_ioat_enqueue_fill\n"); + return -1; + } + await_hw(dev_id, vchan); + + if (rte_dmadev_completed(dev_id, vchan, 1, NULL, NULL) != 1) { + PRINT_ERR("Error: fill operation failed (length: %u)\n", lengths[i]); + return -1; + } + /* check the data from the fill operation is correct */ + for (j = 0; j < lengths[i]; j++) { + char pat_byte = ((char *)&pattern)[j % 8]; + if (dst_data[j] != pat_byte) { + PRINT_ERR("Error with fill operation (lengths = %u): got (%x), not (%x)\n", + lengths[i], dst_data[j], pat_byte); + return -1; + } + } + /* check that the data after the fill operation was not written to */ + for (; j < rte_pktmbuf_data_len(dst); j++) { + if (dst_data[j] != 0) { + PRINT_ERR("Error, fill operation wrote too far (lengths = %u): got (%x), not (%x)\n", + lengths[i], dst_data[j], 0); + return -1; + } + } + } + + rte_pktmbuf_free(dst); + return 0; +} + static int test_dmadev_instance(uint16_t dev_id) { @@ -813,6 +869,23 @@ test_dmadev_instance(uint16_t dev_id) goto err; } + if ((info.dev_capa & RTE_DMADEV_CAPA_OPS_FILL) == 0) + printf("DMA Dev: %u, No device fill support - skipping fill tests\n", dev_id); + else { + rte_dmadev_stats_reset(dev_id, vchan); + printf("DMA Dev: %u, Running Fill Tests\n", dev_id); + + if (test_enqueue_fill(dev_id, vchan) != 0) + goto err; + + rte_dmadev_stats_get(dev_id, 0, &stats); + printf("Ops submitted: %"PRIu64"\t", stats.submitted); + printf("Ops completed: %"PRIu64"\t", stats.completed); + printf("Errors: %"PRIu64"\n", stats.errors); + if (check_stats(&stats, true) < 0) + goto err; + } + rte_mempool_free(pool); rte_dmadev_stop(dev_id); rte_dmadev_stats_reset(dev_id, vchan);