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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT036.mail.protection.outlook.com (10.13.174.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4373.18 via Frontend Transport; Thu, 29 Jul 2021 14:11:44 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Jul 2021 14:11:42 +0000 From: Raja Zidane To: CC: , Date: Thu, 29 Jul 2021 17:11:08 +0300 Message-ID: <20210729141108.20908-1-rzidane@nvidia.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c6ed21de-1676-4b97-60d9-08d9529acbef X-MS-TrafficTypeDiagnostic: DM5PR12MB1723: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3276; 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CAT:NONE; SFS:(4636009)(346002)(39860400002)(376002)(136003)(396003)(46966006)(36840700001)(70206006)(2616005)(5660300002)(54906003)(7696005)(356005)(336012)(450100002)(16526019)(36756003)(2906002)(82310400003)(8676002)(55016002)(83380400001)(478600001)(7636003)(6286002)(6666004)(1076003)(8936002)(82740400003)(70586007)(316002)(186003)(47076005)(4326008)(36860700001)(426003)(36906005)(26005)(86362001)(6916009); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2021 14:11:44.8460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6ed21de-1676-4b97-60d9-08d9529acbef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1723 Subject: [dpdk-dev] [PATCH] compress/mlx5: fix level translation in xform API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Compression Level is interpreted by each PMD differently. However, lower numbers give faster compression at the expense of compression ratio, while higher numbers may give better compression ratios but are likely slower. The level affects the block size, which affects performance, the bigger the block, the faster the compression is. The problem was that higher levels caused bigger blocks: size = min_block_size - 1 + level. the solution is to reverse the above: size = max_block_size + 1 - level. Fixes: 39a2c8715f8f ("compress/mlx5: add transformation operations") Cc: matan@nvidia.com Cc: stable@dpdk.org Signed-off-by: Raja Zidane Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 5c2b9dc859..883e720ec1 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -316,12 +316,19 @@ mlx5_compress_xform_create(struct rte_compressdev *dev, size /= MLX5_GGA_COMP_WIN_SIZE_UNITS; xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size), MLX5_COMP_MAX_WIN_SIZE_CONF) << - WQE_GGA_COMP_WIN_SIZE_OFFSET; - if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT) + WQE_GGA_COMP_WIN_SIZE_OFFSET; + switch (xform->compress.level) { + case RTE_COMP_LEVEL_PMD_DEFAULT: size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX; - else - size = priv->min_block_size - 1 + - xform->compress.level; + break; + case RTE_COMP_LEVEL_MAX: + size = priv->min_block_size; + break; + default: + size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX + + 1 - xform->compress.level, + priv->min_block_size); + } xfrm->gga_ctrl1 += RTE_MIN(size, MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) << WQE_GGA_COMP_BLOCK_SIZE_OFFSET;