From patchwork Wed Jul 28 14:23:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 96354 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80909A0A0C; Wed, 28 Jul 2021 16:23:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0001B410F0; Wed, 28 Jul 2021 16:23:55 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2046.outbound.protection.outlook.com [40.107.94.46]) by mails.dpdk.org (Postfix) with ESMTP id E7EA8410ED; Wed, 28 Jul 2021 16:23:53 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZaPxyw1iGa/3mWrSPU/SlTeqLCVFmLVgvMJJgSxuGrf+SnPhdi/SCYwIdYbzcw5MoVOPeyy91/fqv/cAQr83A6kFuOonPlZQd9XDWuZMpT4qhqAT89nZzytYXFj8Lf25n3hz3RsfYkl/8N5UFodOmspNTs7O0cEuMAAOXqmxdlY8dJoTDYjOkm8qhp9Hk31I7y3+qrRrKIRl3rWn5mi/ZlWLwCevcTiurwCXQ/g9Aui7W0xkI+p9ErmKoEkBuW3nryCzVk3XAuejmhFU2JOdkPUwP581b8RdlAvbnohCN+skRNlWrfLaxa/Q3ahszmofl4ZFMx9tilfvpsSiuhS4QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kH1F2ldZSVxlDrdXFaTFIVM4xpF2Afm5gsvxI+6vEsk=; b=RKieDGKpoy1b64WA5oVz1jP5dcfxAfFU9q5O0Acycu5yOFv3nW+fUDE4I66CtdVEA4yXM0u2vZ0/LLkxo04lJXpdDwnsCX3LCOmjYHZKDrjHjEB9JSqLzhUsizBDK83/T2JVvH6E+2d+jq0v7f15ZneDjvwFbbZiYbZXFbbPwMcXULvOUfangRdLNuxd9EnKYJZtTfDAbZTs0+Zd34AATpNFjLv+1JgkqtHwGjwh9opqn/Yac4iJoca8+6XerGm4czdzKq5/hUcrbuW5o9dxMmCn7VtpN7CmLS8rjL969HnphKKfBu3dJq9kNJfXvZoloWpuu5diUED9yzt7jTNqXA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kH1F2ldZSVxlDrdXFaTFIVM4xpF2Afm5gsvxI+6vEsk=; b=IvGsjq/6TbSXlELGSmxqpNMhykWMmRgUIFXeL4jL+1+gpB5wsYB5mr5khUxs9r9JbkCMHApB24khvNdQwoihkc+oomyVv5ed0Ke8a4ncdjsM1pPV7vb9maWylfgd7651oQLS1XhNnOnulnsTQFblGiiI65nkou8RAjPy8Cn4tSl5yU5IEk28FoAmg/9CDSe/sS5FKNOmjM7e0p3I8yTyCqxRf19nsYTnJ3NZZPMO3Nvy+jYhPl5k2mxJ5CUF21V5Fdu0lXciyA4PryTilERAViqukPhQfMZdo+Og2W4w8W9VpVb9ql0pJzEZualSPSrTB0BzQCAWeUZSIgpr+nJCyg== Received: from BN0PR04CA0034.namprd04.prod.outlook.com (2603:10b6:408:e8::9) by BYAPR12MB3029.namprd12.prod.outlook.com (2603:10b6:a03:ab::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.25; Wed, 28 Jul 2021 14:23:52 +0000 Received: from BN8NAM11FT065.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e8:cafe::36) by BN0PR04CA0034.outlook.office365.com (2603:10b6:408:e8::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.17 via Frontend Transport; Wed, 28 Jul 2021 14:23:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4373.18 via Frontend Transport; Wed, 28 Jul 2021 14:23:51 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 28 Jul 2021 14:23:49 +0000 From: Viacheslav Ovsiienko To: CC: , , Date: Wed, 28 Jul 2021 17:23:35 +0300 Message-ID: <20210728142335.31324-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3556b1fb-775d-4470-3940-08d951d352c5 X-MS-TrafficTypeDiagnostic: BYAPR12MB3029: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dqvDQA3Q9bwPEpjVRVBk05gjzfrIPbTdqfFZuOpCuF3dmxR9prxAnV4gjNMYtDp/xLogcbT+m2IVizHjRZOzeNzLEFs0ejDbXAvk94a9hAy36Lho6+DDfU9qSyxJAq81dBc5cxVuyNa9T9t74t4giGJcrLMwAwEuTyNx3XKnBMNXrwrXTldXMT7e4qp/7RwzcU3IS5ngM0WsbuqaKlIh4g+klcMjIUT3YgfyPPkWWVu1aCBfJO1m/LwioHmuw2z8lAVlJfx7eVwEjcocJOrOZiqxxklg/GTTSIjuyp+N9UmHVgy6JtZ0NVdi3CPXP+R6ZNNMrzm70tR/UH/TGgI8frjpx/tYB+kPCNoNLDl4ER24FGDHLRLmriyQCTM8xwp5CgwbHP0fjzgd36bgwNoGfruPvehda6EWNKCq6DOGP4hup5XG8T5tJveIx9z8hhS8Lw6fvFjlvL9yCod9h5Fr9lzWCOMcr0rAq/SQV81/xSvO6GXxV8C6fJvyPv7VxSLiCoEmbHcmK6dvAXdLJPJAz0jGEPm+VGjN7BCyATr+/pPZ/YmdpwRa+7q6mEcWdv6weBUF3z4ye+BsKLHCq51O3FkZ6hywjI0KlG//+wvnjuriTrjnk54XE6OjM4Ys23UDIBrJ1XifAljcrX4YP9yVnNOlrIFu3hg8GAgTJyvSM5W0seKcf+x5OTRBXSU9Wlqt57RqWPEt+cgpuyvi7n9FnQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(396003)(39860400002)(376002)(136003)(36840700001)(46966006)(2906002)(54906003)(6916009)(86362001)(36906005)(316002)(336012)(6286002)(55016002)(8676002)(450100002)(6666004)(1076003)(478600001)(8936002)(4326008)(2616005)(426003)(36756003)(186003)(70586007)(356005)(82310400003)(5660300002)(26005)(70206006)(7696005)(47076005)(16526019)(36860700001)(82740400003)(83380400001)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2021 14:23:51.6652 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3556b1fb-775d-4470-3940-08d951d352c5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3029 Subject: [dpdk-dev] [PATCH] net/mlx5: fix timestamp initialization on empty clock queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The committing completions by clock queue might be delayed after queue initialization done and the only Clock Queue completion entry (CQE) might keep the invalid status till the CQE first update happens. The mlx5_txpp_update_timestamp() wrongly recognized invalid status as error and reported about lost synchronization. The patch recognizes the invalid status as "not updated yet" and accurate scheduling initialization routine waits till CQE first update happens. Some collateral typos in comment are fixed as well. Fixes: 77522be0a56d ("net/mlx5: introduce clock queue service routine") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_txpp.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index d90399afb5..4f6da9f2d1 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -530,8 +530,8 @@ mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts) { /* * The only CQE of Clock Queue is being continuously - * update by hardware with soecified rate. We have to - * read timestump and WQE completion index atomically. + * updated by hardware with specified rate. We must + * read timestamp and WQE completion index atomically. */ #if defined(RTE_ARCH_X86_64) rte_int128_t src; @@ -592,13 +592,22 @@ mlx5_txpp_update_timestamp(struct mlx5_dev_ctx_shared *sh) } to; uint64_t ts; uint16_t ci; + uint8_t opcode; mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128); - if (to.cts.op_own >> 4) { - DRV_LOG(DEBUG, "Clock Queue error sync lost."); - __atomic_fetch_add(&sh->txpp.err_clock_queue, + opcode = MLX5_CQE_OPCODE(to.cts.op_own); + if (opcode) { + if (opcode != MLX5_CQE_INVALID) { + /* + * Commit the error state if and only if + * we have got at least one actual completion. + */ + DRV_LOG(DEBUG, + "Clock Queue error sync lost (%X).", opcode); + __atomic_fetch_add(&sh->txpp.err_clock_queue, 1, __ATOMIC_RELAXED); - sh->txpp.sync_lost = 1; + sh->txpp.sync_lost = 1; + } return; } ci = rte_be_to_cpu_16(to.cts.wqe_counter);