From patchwork Thu Jul 8 09:44:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 95547 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E0A2A0C4A; Thu, 8 Jul 2021 11:44:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BBBF4410DF; Thu, 8 Jul 2021 11:44:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3AD244069C for ; Thu, 8 Jul 2021 11:44:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1689exnG025884 for ; Thu, 8 Jul 2021 02:44:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QQfv6w3cfBaWeVv+ZIDi5J3H6RYHZMoSBBlClRIQgMg=; b=S2FYKloodpJHrXhxd2CUmenmTOsgye4slrX6IGWAuF4U80KAv3Av/5V7OihNlXsgKUth r254+pS4tMO0YhpfbgF13SuL8X/HWJcqicWCKImbTndYRryJeS8oS+xwLYuFsM5p76M/ bPm9qWLhG4fKmvNRgRGhVFlWv2atiSTQWXQl9jWll/oV+k2788eaG0+WRv9g8KN9tims kFBYaiDNyJt9e+s0hP34FSRKQLjB6vtXpaOaHIEZm1MtmrEn7uVjBukqL1tmV2LEKKHa zelzgLZv++hd9iw2Fgj37opcofVmcoiqZL0keft5zjkFcD/kGURRBAVUQSPCLtWG2zUo ug== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 39nrnu1bu7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 08 Jul 2021 02:44:55 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 8 Jul 2021 02:44:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 8 Jul 2021 02:44:53 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.65.234]) by maili.marvell.com (Postfix) with ESMTP id 94CB63F703F; Thu, 8 Jul 2021 02:44:51 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Anoob Joseph , Ankur Dwivedi , Tejasree Kondoj , Date: Thu, 8 Jul 2021 15:14:37 +0530 Message-ID: <1625737477-403-1-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NZWnguZhoQ58eEakSw9DiW7nanFsn_0b X-Proofpoint-GUID: NZWnguZhoQ58eEakSw9DiW7nanFsn_0b X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-08_04:2021-07-06, 2021-07-08 signatures=0 Subject: [dpdk-dev] [PATCH] crypto/cnxk: reset feature flags on reconfigure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Feature flag in dev would be updated during config. On reconfigure, the field need to be set again to original value. Signed-off-by: Anoob Joseph Acked-by: Akhil Goyal --- drivers/crypto/cnxk/cn10k_cryptodev.c | 14 +------------- drivers/crypto/cnxk/cn9k_cryptodev.c | 13 +------------ drivers/crypto/cnxk/cnxk_cryptodev.c | 23 +++++++++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev.h | 1 + drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 4 ++-- 5 files changed, 28 insertions(+), 27 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c index f278604..c53f514 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev.c @@ -98,19 +98,7 @@ cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, dev->dev_ops = &cn10k_cpt_ops; dev->driver_id = cn10k_cryptodev_driver_id; - - dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | - RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | - RTE_CRYPTODEV_FF_HW_ACCELERATED | - RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT | - RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | - RTE_CRYPTODEV_FF_IN_PLACE_SGL | - RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | - RTE_CRYPTODEV_FF_SYM_SESSIONLESS | - RTE_CRYPTODEV_FF_SECURITY | - RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED; + dev->feature_flags = cnxk_cpt_default_ff_get(); cn10k_cpt_set_enqdeq_fns(dev); cn10k_sec_ops_override(); diff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c index 71d144f..9ff2383 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev.c @@ -81,21 +81,10 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, dev->dev_ops = &cn9k_cpt_ops; dev->driver_id = cn9k_cryptodev_driver_id; + dev->feature_flags = cnxk_cpt_default_ff_get(); cnxk_cpt_caps_populate(vf); - dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | - RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | - RTE_CRYPTODEV_FF_HW_ACCELERATED | - RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | - RTE_CRYPTODEV_FF_IN_PLACE_SGL | - RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | - RTE_CRYPTODEV_FF_SYM_SESSIONLESS | - RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED | - RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT; - cn9k_cpt_set_enqdeq_fns(dev); return 0; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.c b/drivers/crypto/cnxk/cnxk_cryptodev.c index 0ffe9d0..9c7dc62 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev.c @@ -2,10 +2,33 @@ * Copyright(C) 2021 Marvell. */ +#include + #include "roc_cpt.h" #include "cnxk_cryptodev.h" +uint64_t +cnxk_cpt_default_ff_get(void) +{ + uint64_t ff = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED | + RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT | + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | + RTE_CRYPTODEV_FF_IN_PLACE_SGL | + RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | + RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | + RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | + RTE_CRYPTODEV_FF_SYM_SESSIONLESS | + RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED; + + if (roc_model_is_cn10k()) + ff |= RTE_CRYPTODEV_FF_SECURITY; + + return ff; +} + int cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt) { diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index 5e38933..ff46d16 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -27,6 +27,7 @@ struct cnxk_cpt_vf { struct roc_ae_ec_group *ec_grp[CNXK_AE_EC_ID_MAX]; }; +uint64_t cnxk_cpt_default_ff_get(void); int cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt); #endif /* _CNXK_CRYPTODEV_H_ */ diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 7d8d98e..694eef7 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -58,7 +58,7 @@ cnxk_cpt_dev_config(struct rte_cryptodev *dev, uint16_t nb_lf_avail, nb_lf; int ret; - dev->feature_flags &= ~conf->ff_disable; + dev->feature_flags = cnxk_cpt_default_ff_get() & ~conf->ff_disable; nb_lf_avail = roc_cpt->nb_lf_avail; nb_lf = conf->nb_queue_pairs; @@ -151,7 +151,7 @@ cnxk_cpt_dev_info_get(struct rte_cryptodev *dev, struct roc_cpt *roc_cpt = &vf->cpt; info->max_nb_queue_pairs = roc_cpt->nb_lf_avail; - info->feature_flags = dev->feature_flags; + info->feature_flags = cnxk_cpt_default_ff_get(); info->capabilities = cnxk_crypto_capabilities_get(vf); info->sym.max_nb_sessions = 0; info->min_mbuf_headroom_req = CNXK_CPT_MIN_HEADROOM_REQ;