From patchwork Tue Jul 6 10:47:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 95367 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFEAEA0C4B; Tue, 6 Jul 2021 13:12:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4633D4129B; Tue, 6 Jul 2021 12:47:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 022AC4129A for ; Tue, 6 Jul 2021 12:47:41 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 166AkQsZ027305 for ; Tue, 6 Jul 2021 03:47:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZkfjuVqyqb4Qse1UnGgBgJoXWijeeCo1EJoHNQcNybM=; b=Km3aRFuClRWBPOVCun8gnXvBYScrn1ejeJML7VAfRm51zEcDlBqTh1ASDEsX53jQr/ov 2zZQktgV9ZjWqo0tfvr3BZMeWXKiO2f/ooF3/lZ325vzmPdBPi/vEPvu/ekNRKO6ycR3 JyQBPkQAXYHSiY04Sap/Z+KBriG5bOgtF2OgWMl/IeH26x5sUS3xJtGsaj9p7xGPba7x 6ayJa9o087yQcsAj/3+MBUm1HSyp85jM9KokoE7r9Ig1myfPiC9nLLbOYHpVoCjCopas q/4XC/BYS881gXhZ2Gr9ulYjIDcyA0n3NGDfxRkxjtpwPjoAplBjHDazRPSXcBUrZHV7 6w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 39md8phmfb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 06 Jul 2021 03:47:41 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 6 Jul 2021 03:47:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 6 Jul 2021 03:47:39 -0700 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id C94403F7069; Tue, 6 Jul 2021 03:47:37 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Date: Tue, 6 Jul 2021 16:17:29 +0530 Message-ID: <20210706104729.1598149-2-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210706104729.1598149-1-psatheesh@marvell.com> References: <20210705040942.1524345-1-psatheesh@marvell.com> <20210706104729.1598149-1-psatheesh@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: jPng8-RNIDrtq73tqmDk5RZwK_modFDP X-Proofpoint-ORIG-GUID: jPng8-RNIDrtq73tqmDk5RZwK_modFDP X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-06_05:2021-07-02, 2021-07-06 signatures=0 Subject: [dpdk-dev] [PATCH v2 2/2] net/cnxk: add support for rte flow item raw X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul Add support for rte_flow_item_raw to parse custom L2 and L3 protocols. Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar Kokkilagadda --- doc/guides/nics/cnxk.rst | 37 +++++++++++++++++++++++++- drivers/net/cnxk/cnxk_ethdev_devargs.c | 7 +++++ drivers/net/cnxk/cnxk_rte_flow.c | 12 ++++----- 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index cb2a51e1d..90d27dbaa 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -165,7 +165,7 @@ Runtime Config Options With the above configuration, higig2 will be enabled on that port and the traffic on this port should be higig2 traffic only. Supported switch header - types are "higig2", "dsa", "chlen90b" and "chlen24b". + types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa". - ``RSS tag as XOR`` (default ``0``) @@ -215,6 +215,41 @@ RTE flow GRE support - ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing bits in the GRE header are equal to 0. +Custom protocols supported in RTE Flow +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols. + +* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level. +* ``NGIO`` can be parsed at L3 level. + +For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the +respective switch header. + +For example:: + + -a 0002:02:00.0,switch_header="vlan_exdsa" + +The below fields of ``struct rte_flow_item_raw`` shall be used to specify the +pattern. + +- ``relative`` Selects the layer at which parsing is done. + + - 0 for ``exdsa`` and ``vlan_exdsa``. + + - 1 for ``NGIO``. + +- ``offset`` The offset in the header where the pattern should be matched. +- ``length`` Length of the pattern. +- ``pattern`` Pattern as a byte string. + +Example usage in testpmd:: + + ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \ + --rx-offloads=0x00080000 --rxq 8 --txq 8 + testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \ + spec ab pattern mask ab offset is 4 / end actions queue index 1 / end + Debugging Options ----------------- diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index c76b6281c..36b437a18 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -99,6 +99,13 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args) if (strcmp(value, "chlen90b") == 0) *(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B; + + if (strcmp(value, "exdsa") == 0) + *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA; + + if (strcmp(value, "vlan_exdsa") == 0) + *(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA; + return 0; } diff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c index 213125b56..32c1b5dee 100644 --- a/drivers/net/cnxk/cnxk_rte_flow.c +++ b/drivers/net/cnxk/cnxk_rte_flow.c @@ -15,8 +15,8 @@ const struct cnxk_rte_flow_term_info term[] = { [RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6, sizeof(struct rte_flow_item_ipv6)}, [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = { - ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4, - sizeof(struct rte_flow_item_arp_eth_ipv4)}, + ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4, + sizeof(struct rte_flow_item_arp_eth_ipv4)}, [RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS, sizeof(struct rte_flow_item_mpls)}, [RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP, @@ -50,10 +50,10 @@ const struct cnxk_rte_flow_term_info term[] = { [RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0}, [RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY, sizeof(uint32_t)}, - [RTE_FLOW_ITEM_TYPE_HIGIG2] = { - ROC_NPC_ITEM_TYPE_HIGIG2, - sizeof(struct rte_flow_item_higig2_hdr)} -}; + [RTE_FLOW_ITEM_TYPE_HIGIG2] = {ROC_NPC_ITEM_TYPE_HIGIG2, + sizeof(struct rte_flow_item_higig2_hdr)}, + [RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW, + sizeof(struct rte_flow_item_raw)}}; static int npc_rss_action_validate(struct rte_eth_dev *eth_dev,