From patchwork Tue Jul 6 10:12:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 95365 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 114C3A0C47; Tue, 6 Jul 2021 12:13:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D411C4120E; Tue, 6 Jul 2021 12:13:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1B02040688 for ; Tue, 6 Jul 2021 12:13:08 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 166A6Z0p018615 for ; Tue, 6 Jul 2021 03:13:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=uld+GfrrkXuIOzk/R0y0tM1xTX+CFKVPjm9jauvKgCY=; b=Xt97pRVM5eHwARL3uXIhmk7RHD740vfAn1wbpVHQIGNOOZ3eYWcUM9/ScbLHuT2coS44 FuXTVeWwxteto5I+y8XYd+2aRtz/I1SOvhi1JDksuRzwkNWM+PvYddM+dNip1Qnm35Ye xvTnJD6oeczaNmE6aK02fBGW+2nr6fFnGgB3LukWeJN/S9QySjI2VXx4ojTKYzOLIV8l 0BmG0FrX7+Dux6j7RpgUw669HIkQQWmik5i9FZ+B01o1HPks1EcqD1KFR/ClpV+n8dtL sFMtyuA63zbOrm5bBNeYmLUhRTC0UZ0uyG+NH4cywerq2DYGLKSaDgKv541UVdkSAopo rg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39kt2mckj1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 06 Jul 2021 03:13:07 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 6 Jul 2021 03:13:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 6 Jul 2021 03:13:05 -0700 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id DDA783F7068; Tue, 6 Jul 2021 03:13:02 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Date: Tue, 6 Jul 2021 15:42:58 +0530 Message-ID: <20210706101259.1598009-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: _O-DoNzmKiXFCIh22UmQQkrs80OIeOsm X-Proofpoint-GUID: _O-DoNzmKiXFCIh22UmQQkrs80OIeOsm X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-06_05:2021-07-02, 2021-07-06 signatures=0 Subject: [dpdk-dev] [PATCH v2 1/2] common/cnxk: add support for rte flow item raw X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul Add roc API for rte_flow_item_raw to parse custom L2 and L3 protocols. Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar Kokkilagadda --- drivers/common/cnxk/roc_mbox.h | 24 ++++++-- drivers/common/cnxk/roc_nix_ops.c | 14 +++++ drivers/common/cnxk/roc_npc.h | 11 ++++ drivers/common/cnxk/roc_npc_parse.c | 86 +++++++++++++++++++++++++++-- drivers/common/cnxk/roc_npc_priv.h | 9 +-- drivers/common/cnxk/roc_npc_utils.c | 6 +- drivers/common/cnxk/roc_utils.c | 2 +- 7 files changed, 136 insertions(+), 16 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 9c529d754..b254f005a 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -278,14 +278,28 @@ struct ready_msg_rsp { uint16_t __io rclk_freq; /* RCLK frequency */ }; +enum npc_pkind_type { + NPC_RX_VLAN_EXDSA_PKIND = 56ULL, + NPC_RX_CHLEN24B_PKIND, + NPC_RX_CPT_HDR_PKIND, + NPC_RX_CHLEN90B_PKIND, + NPC_TX_HIGIG_PKIND, + NPC_RX_HIGIG_PKIND, + NPC_RX_EXDSA_PKIND, + NPC_RX_EDSA_PKIND, + NPC_TX_DEF_PKIND, +}; + /* Struct to set pkind */ struct npc_set_pkind { struct mbox_msghdr hdr; -#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0) -#define ROC_PRIV_FLAGS_EDSA BIT_ULL(1) -#define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2) -#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3) -#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63) +#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0) +#define ROC_PRIV_FLAGS_EDSA BIT_ULL(1) +#define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2) +#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3) +#define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4) +#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5) +#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63) uint64_t __io mode; #define PKIND_TX BIT_ULL(0) #define PKIND_RX BIT_ULL(1) diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c index eeb85a54f..0e28302e7 100644 --- a/drivers/common/cnxk/roc_nix_ops.c +++ b/drivers/common/cnxk/roc_nix_ops.c @@ -378,6 +378,8 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type) switch_header_type != ROC_PRIV_FLAGS_EDSA && switch_header_type != ROC_PRIV_FLAGS_HIGIG && switch_header_type != ROC_PRIV_FLAGS_LEN_90B && + switch_header_type != ROC_PRIV_FLAGS_EXDSA && + switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA && switch_header_type != ROC_PRIV_FLAGS_CUSTOM) { plt_err("switch header type is not supported"); return NIX_ERR_PARAM; @@ -399,6 +401,18 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type) if (req == NULL) return rc; req->mode = switch_header_type; + + if (switch_header_type == ROC_PRIV_FLAGS_LEN_90B) { + req->mode = ROC_PRIV_FLAGS_CUSTOM; + req->pkind = NPC_RX_CHLEN90B_PKIND; + } else if (switch_header_type == ROC_PRIV_FLAGS_EXDSA) { + req->mode = ROC_PRIV_FLAGS_CUSTOM; + req->pkind = NPC_RX_EXDSA_PKIND; + } else if (switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) { + req->mode = ROC_PRIV_FLAGS_CUSTOM; + req->pkind = NPC_RX_VLAN_EXDSA_PKIND; + } + req->dir = PKIND_RX; rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h index 2c0a536c9..bab25fd72 100644 --- a/drivers/common/cnxk/roc_npc.h +++ b/drivers/common/cnxk/roc_npc.h @@ -36,6 +36,7 @@ enum roc_npc_item_type { ROC_NPC_ITEM_TYPE_CPT_HDR, ROC_NPC_ITEM_TYPE_L3_CUSTOM, ROC_NPC_ITEM_TYPE_QINQ, + ROC_NPC_ITEM_TYPE_RAW, ROC_NPC_ITEM_TYPE_END, }; @@ -47,6 +48,16 @@ struct roc_npc_item_info { const void *last; /* For range */ }; +struct roc_npc_flow_item_raw { + uint32_t relative : 1; /**< Look for pattern after the previous item. */ + uint32_t search : 1; /**< Search pattern from offset. */ + uint32_t reserved : 30; /**< Reserved, must be set to zero. */ + int32_t offset; /**< Absolute or relative offset for pattern. */ + uint16_t limit; /**< Search area limit for start of pattern. */ + uint16_t length; /**< Pattern length. */ + const uint8_t *pattern; /**< Byte string to look for. */ +}; + #define ROC_NPC_MAX_ACTION_COUNT 12 enum roc_npc_action_type { diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c index d07f91db3..8125035dd 100644 --- a/drivers/common/cnxk/roc_npc_parse.c +++ b/drivers/common/cnxk/roc_npc_parse.c @@ -136,14 +136,46 @@ npc_parse_la(struct npc_parse_state *pst) return npc_update_parse_state(pst, &info, lid, lt, 0); } +static int +npc_flow_raw_item_prepare(const struct roc_npc_flow_item_raw *raw_spec, + const struct roc_npc_flow_item_raw *raw_mask, + struct npc_parse_item_info *info, uint8_t *spec_buf, + uint8_t *mask_buf) +{ + uint32_t custom_hdr_size = 0; + + memset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN); + memset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN); + custom_hdr_size = raw_spec->offset + raw_spec->length; + + memcpy(spec_buf + raw_spec->offset, raw_spec->pattern, + raw_spec->length); + + if (raw_mask->pattern) { + memcpy(mask_buf + raw_spec->offset, raw_mask->pattern, + raw_spec->length); + } else { + memset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length); + } + + info->len = custom_hdr_size; + info->spec = spec_buf; + info->mask = mask_buf; + + return 0; +} + int npc_parse_lb(struct npc_parse_state *pst) { const struct roc_npc_item_info *pattern = pst->pattern; const struct roc_npc_item_info *last_pattern; + const struct roc_npc_flow_item_raw *raw_spec; + uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN]; + uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN]; char hw_mask[NPC_MAX_EXTRACT_HW_LEN]; struct npc_parse_item_info info; - int lid, lt, lflags; + int lid, lt, lflags, len = 0; int nr_vlans = 0; int rc; @@ -221,13 +253,35 @@ npc_parse_lb(struct npc_parse_state *pst) info.len = pst->pattern->size; lt = NPC_LT_LB_STAG_QINQ; lflags = NPC_F_STAG_CTAG; + } else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) { + raw_spec = pst->pattern->spec; + if (raw_spec->relative) + return 0; + len = raw_spec->length + raw_spec->offset; + if (len > NPC_MAX_RAW_ITEM_LEN) + return -EINVAL; + + if (pst->npc->switch_header_type == ROC_PRIV_FLAGS_VLAN_EXDSA) { + lt = NPC_LT_LB_VLAN_EXDSA; + } else if (pst->npc->switch_header_type == + ROC_PRIV_FLAGS_EXDSA) { + lt = NPC_LT_LB_EXDSA; + } else { + return -EINVAL; + } + + npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *) + pst->pattern->spec, + (const struct roc_npc_flow_item_raw *) + pst->pattern->mask, + &info, raw_spec_buf, raw_mask_buf); + + info.hw_hdr_len = 0; } else { return 0; } info.hw_mask = &hw_mask; - info.spec = NULL; - info.mask = NULL; npc_get_hw_supp_mask(pst, &info, lid, lt); rc = npc_parse_item_basic(pst->pattern, &info); @@ -340,9 +394,12 @@ npc_check_lc_ip_tunnel(struct npc_parse_state *pst) int npc_parse_lc(struct npc_parse_state *pst) { + const struct roc_npc_flow_item_raw *raw_spec; + uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN]; + uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN]; uint8_t hw_mask[NPC_MAX_EXTRACT_HW_LEN]; struct npc_parse_item_info info; - int lid, lt; + int lid, lt, len = 0; int rc; if (pst->pattern->type == ROC_NPC_ITEM_TYPE_MPLS) @@ -378,6 +435,26 @@ npc_parse_lc(struct npc_parse_state *pst) lt = NPC_LT_LC_CUSTOM0; info.len = pst->pattern->size; break; + case ROC_NPC_ITEM_TYPE_RAW: + raw_spec = pst->pattern->spec; + if (!raw_spec->relative) + return 0; + + len = raw_spec->length + raw_spec->offset; + if (len > NPC_MAX_RAW_ITEM_LEN) + return -EINVAL; + + npc_flow_raw_item_prepare((const struct roc_npc_flow_item_raw *) + pst->pattern->spec, + (const struct roc_npc_flow_item_raw *) + pst->pattern->mask, + &info, raw_spec_buf, raw_mask_buf); + + lid = NPC_LID_LC; + lt = NPC_LT_LC_NGIO; + info.hw_mask = &hw_mask; + npc_get_hw_supp_mask(pst, &info, lid, lt); + break; default: /* No match at this layer */ return 0; @@ -388,6 +465,7 @@ npc_parse_lc(struct npc_parse_state *pst) npc_get_hw_supp_mask(pst, &info, lid, lt); rc = npc_parse_item_basic(pst->pattern, &info); + if (rc != 0) return rc; diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h index 484c3aeb1..5b884e3fd 100644 --- a/drivers/common/cnxk/roc_npc_priv.h +++ b/drivers/common/cnxk/roc_npc_priv.h @@ -5,10 +5,11 @@ #ifndef _ROC_NPC_PRIV_H_ #define _ROC_NPC_PRIV_H_ -#define NPC_IH_LENGTH 8 -#define NPC_TPID_LENGTH 2 -#define NPC_HIGIG2_LENGTH 16 -#define NPC_COUNTER_NONE (-1) +#define NPC_IH_LENGTH 8 +#define NPC_TPID_LENGTH 2 +#define NPC_HIGIG2_LENGTH 16 +#define NPC_MAX_RAW_ITEM_LEN 16 +#define NPC_COUNTER_NONE (-1) #define NPC_RSS_GRPS 8 diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c index 5c97588e6..5fcb56c35 100644 --- a/drivers/common/cnxk/roc_npc_utils.c +++ b/drivers/common/cnxk/roc_npc_utils.c @@ -130,7 +130,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item, } /* We have valid spec */ - info->spec = item->spec; + if (item->type != ROC_NPC_ITEM_TYPE_RAW) + info->spec = item->spec; /* If mask is not set, use default mask, err if default mask is * also NULL. @@ -140,7 +141,8 @@ npc_parse_item_basic(const struct roc_npc_item_info *item, return NPC_ERR_PARAM; info->mask = info->def_mask; } else { - info->mask = item->mask; + if (item->type != ROC_NPC_ITEM_TYPE_RAW) + info->mask = item->mask; } /* mask specified must be subset of hw supported mask diff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c index 542252fe4..9cb8708a7 100644 --- a/drivers/common/cnxk/roc_utils.c +++ b/drivers/common/cnxk/roc_utils.c @@ -113,7 +113,7 @@ roc_error_msg_get(int errorcode) err_msg = "NPC invalid spec"; break; case NPC_ERR_INVALID_MASK: - err_msg = "NPC invalid mask"; + err_msg = "NPC invalid mask"; break; case NPC_ERR_INVALID_KEX: err_msg = "NPC invalid key"; From patchwork Tue Jul 6 10:12:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 95366 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A371EA0C47; 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Tue, 06 Jul 2021 03:13:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 6 Jul 2021 03:13:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 6 Jul 2021 03:13:09 -0700 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id B9D403F706C; Tue, 6 Jul 2021 03:13:07 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Date: Tue, 6 Jul 2021 15:42:59 +0530 Message-ID: <20210706101259.1598009-2-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210706101259.1598009-1-psatheesh@marvell.com> References: <20210706101259.1598009-1-psatheesh@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: I-z2DGfRdflFmKzfddYG_v_ANnuzU9hr X-Proofpoint-GUID: I-z2DGfRdflFmKzfddYG_v_ANnuzU9hr X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-06_05:2021-07-02, 2021-07-06 signatures=0 Subject: [dpdk-dev] [PATCH v2 2/2] net/cnxk: add support for rte flow item raw X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul Add support for rte_flow_item_raw to parse custom L2 and L3 protocols. Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar Kokkilagadda --- doc/guides/nics/cnxk.rst | 37 +++++++++++++++++++++++++- drivers/net/cnxk/cnxk_ethdev_devargs.c | 7 +++++ drivers/net/cnxk/cnxk_rte_flow.c | 12 ++++----- 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index cb2a51e1d..90d27dbaa 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -165,7 +165,7 @@ Runtime Config Options With the above configuration, higig2 will be enabled on that port and the traffic on this port should be higig2 traffic only. Supported switch header - types are "higig2", "dsa", "chlen90b" and "chlen24b". + types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa". - ``RSS tag as XOR`` (default ``0``) @@ -215,6 +215,41 @@ RTE flow GRE support - ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing bits in the GRE header are equal to 0. +Custom protocols supported in RTE Flow +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols. + +* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level. +* ``NGIO`` can be parsed at L3 level. + +For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the +respective switch header. + +For example:: + + -a 0002:02:00.0,switch_header="vlan_exdsa" + +The below fields of ``struct rte_flow_item_raw`` shall be used to specify the +pattern. + +- ``relative`` Selects the layer at which parsing is done. + + - 0 for ``exdsa`` and ``vlan_exdsa``. + + - 1 for ``NGIO``. + +- ``offset`` The offset in the header where the pattern should be matched. +- ``length`` Length of the pattern. +- ``pattern`` Pattern as a byte string. + +Example usage in testpmd:: + + ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \ + --rx-offloads=0x00080000 --rxq 8 --txq 8 + testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \ + spec ab pattern mask ab offset is 4 / end actions queue index 1 / end + Debugging Options ----------------- diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index c76b6281c..36b437a18 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -99,6 +99,13 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args) if (strcmp(value, "chlen90b") == 0) *(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B; + + if (strcmp(value, "exdsa") == 0) + *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA; + + if (strcmp(value, "vlan_exdsa") == 0) + *(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA; + return 0; } diff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c index 213125b56..32c1b5dee 100644 --- a/drivers/net/cnxk/cnxk_rte_flow.c +++ b/drivers/net/cnxk/cnxk_rte_flow.c @@ -15,8 +15,8 @@ const struct cnxk_rte_flow_term_info term[] = { [RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6, sizeof(struct rte_flow_item_ipv6)}, [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = { - ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4, - sizeof(struct rte_flow_item_arp_eth_ipv4)}, + ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4, + sizeof(struct rte_flow_item_arp_eth_ipv4)}, [RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS, sizeof(struct rte_flow_item_mpls)}, [RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP, @@ -50,10 +50,10 @@ const struct cnxk_rte_flow_term_info term[] = { [RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0}, [RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY, sizeof(uint32_t)}, - [RTE_FLOW_ITEM_TYPE_HIGIG2] = { - ROC_NPC_ITEM_TYPE_HIGIG2, - sizeof(struct rte_flow_item_higig2_hdr)} -}; + [RTE_FLOW_ITEM_TYPE_HIGIG2] = {ROC_NPC_ITEM_TYPE_HIGIG2, + sizeof(struct rte_flow_item_higig2_hdr)}, + [RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW, + sizeof(struct rte_flow_item_raw)}}; static int npc_rss_action_validate(struct rte_eth_dev *eth_dev,