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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT032.mail.protection.outlook.com (10.13.173.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4264.18 via Frontend Transport; Mon, 28 Jun 2021 19:24:11 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Jun 2021 19:24:10 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Mon, 28 Jun 2021 22:23:45 +0300 Message-ID: <20210628192347.1825713-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 20003ede-c794-46ec-07c3-08d93a6a4f39 X-MS-TrafficTypeDiagnostic: SN1PR12MB2511: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(346002)(396003)(39860400002)(376002)(46966006)(36840700001)(7696005)(5660300002)(2616005)(2906002)(478600001)(47076005)(82310400003)(70206006)(1076003)(86362001)(6916009)(8936002)(36756003)(8676002)(36860700001)(70586007)(336012)(26005)(966005)(6666004)(450100002)(316002)(4326008)(83380400001)(54906003)(7636003)(6286002)(356005)(426003)(55016002)(186003)(82740400003)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2021 19:24:11.8448 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20003ede-c794-46ec-07c3-08d93a6a4f39 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2511 Subject: [dpdk-dev] [PATCH 1/3] regex/mlx5: fix memory region unregistration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The issue can cause illegal physical address access while a huge-page A is released and huge-page B is allocated on the same virtual address. The old MR can be matched using the virtual address of huge-page B but the HW will access the physical address of huge-page A which is no more part of the DPDK process. Register a driver callback for memory event in order to free out all the MRs of memory that is going to be freed from the dpdk process. Fixes: cda883bbb655 ("regex/mlx5: add dynamic memory registration to datapath") Cc: stable@dpdk.org Signed-off-by: Michael Baum --- This series depends on this patch: https://patchwork.dpdk.org/project/dpdk/patch/20210628150614.1769507-1-michaelba@nvidia.com/ Please don't apply it only before this patch is integrated. drivers/regex/mlx5/mlx5_regex.c | 55 ++++++++++++++++++++++++ drivers/regex/mlx5/mlx5_regex.h | 2 + drivers/regex/mlx5/mlx5_regex_fastpath.c | 39 +++++++++++++++-- 3 files changed, 92 insertions(+), 4 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index dcb2ced88e..0f12d94d7e 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -24,6 +25,10 @@ int mlx5_regex_logtype; +TAILQ_HEAD(regex_mem_event, mlx5_regex_priv) mlx5_mem_event_list = + TAILQ_HEAD_INITIALIZER(mlx5_mem_event_list); +static pthread_mutex_t mem_event_list_lock = PTHREAD_MUTEX_INITIALIZER; + const struct rte_regexdev_ops mlx5_regexdev_ops = { .dev_info_get = mlx5_regex_info_get, .dev_configure = mlx5_regex_configure, @@ -82,6 +87,40 @@ mlx5_regex_get_name(char *name, struct rte_pci_device *pci_dev __rte_unused) pci_dev->addr.devid, pci_dev->addr.function); } +/** + * Callback for memory event. + * + * @param event_type + * Memory event type. + * @param addr + * Address of memory. + * @param len + * Size of memory. + */ +static void +mlx5_regex_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, + size_t len, void *arg __rte_unused) +{ + struct mlx5_regex_priv *priv; + + /* Must be called from the primary process. */ + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); + switch (event_type) { + case RTE_MEM_EVENT_FREE: + pthread_mutex_lock(&mem_event_list_lock); + /* Iterate all the existing mlx5 devices. */ + TAILQ_FOREACH(priv, &mlx5_mem_event_list, mem_event_cb) + mlx5_free_mr_by_addr(&priv->mr_scache, + priv->ctx->device->name, + addr, len); + pthread_mutex_unlock(&mem_event_list_lock); + break; + case RTE_MEM_EVENT_ALLOC: + default: + break; + } +} + static int mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) @@ -193,6 +232,15 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, rte_errno = ENOMEM; goto error; } + /* Register callback function for global shared MR cache management. */ + if (TAILQ_EMPTY(&mlx5_mem_event_list)) + rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", + mlx5_regex_mr_mem_event_cb, + NULL); + /* Add device to memory callback list. */ + pthread_mutex_lock(&mem_event_list_lock); + TAILQ_INSERT_TAIL(&mlx5_mem_event_list, priv, mem_event_cb); + pthread_mutex_unlock(&mem_event_list_lock); DRV_LOG(INFO, "RegEx GGA is %s.", priv->has_umr ? "supported" : "unsupported"); return 0; @@ -225,6 +273,13 @@ mlx5_regex_pci_remove(struct rte_pci_device *pci_dev) return 0; priv = dev->data->dev_private; if (priv) { + /* Remove from memory callback device list. */ + pthread_mutex_lock(&mem_event_list_lock); + TAILQ_REMOVE(&mlx5_mem_event_list, priv, mem_event_cb); + pthread_mutex_unlock(&mem_event_list_lock); + if (TAILQ_EMPTY(&mlx5_mem_event_list)) + rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", + NULL); if (priv->pd) mlx5_glue->dealloc_pd(priv->pd); if (priv->uar) diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 51a2101e53..61f59ba873 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -70,6 +70,8 @@ struct mlx5_regex_priv { uint32_t nb_engines; /* Number of RegEx engines. */ struct mlx5dv_devx_uar *uar; /* UAR object. */ struct ibv_pd *pd; + TAILQ_ENTRY(mlx5_regex_priv) mem_event_cb; + /**< Called by memory event callback. */ struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ uint8_t is_bf2; /* The device is BF2 device. */ uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index b57e7d7794..437009dcb6 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -109,6 +109,40 @@ set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, seg->imm = imm; } +/** + * Query LKey from a packet buffer for QP. If not found, add the mempool. + * + * @param priv + * Pointer to the priv object. + * @param mr_ctrl + * Pointer to per-queue MR control structure. + * @param op + * Pointer to the RegEx operations object. + * + * @return + * Searched LKey on success, UINT32_MAX on no match. + */ +static inline uint32_t +mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl, + struct rte_regex_ops *op) +{ + uintptr_t addr = rte_pktmbuf_mtod(op->mbuf, uintptr_t); + uint32_t lkey; + + /* Check generation bit to see if there's any change on existing MRs. */ + if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) + mlx5_mr_flush_local_cache(mr_ctrl); + /* Linear search on MR cache array. */ + lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, + MLX5_MR_CACHE_N, addr); + if (likely(lkey != UINT32_MAX)) + return lkey; + /* Take slower bottom-half on miss. */ + return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr, + !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); +} + + static inline void __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, struct rte_regex_ops *op, struct mlx5_regex_job *job, @@ -160,10 +194,7 @@ prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, struct mlx5_klm klm; klm.byte_count = rte_pktmbuf_data_len(op->mbuf); - klm.mkey = mlx5_mr_addr2mr_bh(priv->pd, 0, - &priv->mr_scache, &qp->mr_ctrl, - rte_pktmbuf_mtod(op->mbuf, uintptr_t), - !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); + klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, op); klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t); __prep_one(priv, sq, op, job, sq->pi, &klm); sq->db_pi = sq->pi; From patchwork Mon Jun 28 19:23:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 94925 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D606EA0A0C; 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Mon, 28 Jun 2021 19:24:11 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Mon, 28 Jun 2021 22:23:46 +0300 Message-ID: <20210628192347.1825713-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210628192347.1825713-1-michaelba@nvidia.com> References: <20210628192347.1825713-1-michaelba@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4f076ea2-3a85-448f-21a5-08d93a6a516c X-MS-TrafficTypeDiagnostic: CY4PR12MB1848: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1850; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aq9QXb6XBX3FuOOfuUr7wLAUyNtXBQwAgEEQiukwI0rFKNCkWrHgVUEIcmMTAici231Yw0uDN0CElnAZ3Lmf9huIS8p8n4RFydKRyE2O0ZsnWPrD4gT7pr/6cgBGyglRn0nMhcWL/64iddbRcaboWQDzaYiL6b7DwhRsrh64VnWPfCx5JVkfHDOhlE/Q9GsekteKeSTO5rgepvJz3WopN03YxR1YP58Tf72HCmobjOVRurfc9cQKWKp6MSlISKHcVZkZPcRSPFuJZQcfmvDgEBgsHB3iDKUbnyj10Fi7dQUXxBqswXxiQU+NTgVDfHTf61dp+NN5ENosfec3hefV9yl+aNVpA//2JtG3E7dIPdqz03cjUl2DETCzBbC6fZnWjyVOI78mz9zQ0+EhE5v/rMt2/g5P6dmYRD3LwjkU1DwZMefz4XUQM9Gs5oPr5/GC24Kp37hENZTpNUUXrJJ9e3TVP2o19fBvFTvLHzicleR4ykib5pK2Ntqi9IH5W8JV/4gwDwVICj0QfR/ool07hZkBMQfNABhPb8UPd+4hoKylGkixAubYM2vU6Bx3QiXSeYIJBUvpzFAhOC+bUxl40ufYh+UIdauSslEFdAcBABcVu70PObSAYxhrvQWNjT202sJj7Lmg/Cefrpxg7E759LqC2A0Xvn2D55Hqpl3Isy2XzzwLLaKIbB3n4+JdjiuNy/h7lJO9pJUJinBETqHd0w== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(396003)(39860400002)(376002)(346002)(46966006)(36840700001)(1076003)(5660300002)(6286002)(7696005)(86362001)(6666004)(186003)(6916009)(2906002)(16526019)(478600001)(8676002)(26005)(82310400003)(2616005)(4744005)(55016002)(8936002)(7636003)(54906003)(47076005)(82740400003)(36860700001)(316002)(4326008)(426003)(36906005)(36756003)(70206006)(336012)(70586007)(356005)(450100002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2021 19:24:15.5521 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f076ea2-3a85-448f-21a5-08d93a6a516c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1848 Subject: [dpdk-dev] [PATCH 2/3] regex/mlx5: fix leak in PCI remove function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the PCI removal function, PMD releases all driver resources allocated in the probe function. The MR btree memory is allocated in the probe function, but it is not freed in remove function what caused a memory leak. Release it. Fixes: cda883bbb655 ("regex/mlx5: add dynamic memory registration to datapath") Cc: stable@dpdk.org Signed-off-by: Michael Baum --- drivers/regex/mlx5/mlx5_regex.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index 0f12d94d7e..f64dc2824c 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -280,6 +280,8 @@ mlx5_regex_pci_remove(struct rte_pci_device *pci_dev) if (TAILQ_EMPTY(&mlx5_mem_event_list)) rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", NULL); + if (priv->mr_scache.cache.table) + mlx5_mr_release_cache(&priv->mr_scache); if (priv->pd) mlx5_glue->dealloc_pd(priv->pd); if (priv->uar) From patchwork Mon Jun 28 19:23:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 94926 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1AB2A0A0C; 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Mon, 28 Jun 2021 19:24:13 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Mon, 28 Jun 2021 22:23:47 +0300 Message-ID: <20210628192347.1825713-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210628192347.1825713-1-michaelba@nvidia.com> References: <20210628192347.1825713-1-michaelba@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9dd59f70-f9b9-4430-58c6-08d93a6a5202 X-MS-TrafficTypeDiagnostic: MWHPR12MB1552: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1169; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pH83Ob3wXcta9L18V7bmjNjw6cdue6WynnRIYmmW5tyMyrF6+4NOk0+ULO0HfM/h0slOnvQ0DXtzSJ5Aj2+rV54Nc/TXUFdrECbxqQRuZ982tXKhgwalyPtBRZ3sVHW0hxxK1tYskmi4BVMJviIackq5nkgaU2cypyoEPoje3IfJ5tISr5IGQqHWyQCChffJ6f/vW7ibcqSKnTRcRL+s0WA2I8QCiraSoFAdZBvjnBUHOzuuThCynukuuuKO1tjYVkoLV2vuWdFMC8A00RyLHu/rMXkGvcyVG7WTQjMaDFfl8PTZzNlx/1Supoiskg2d2mTI9N+SA+w9jLDVrYBUQzSvZqll8YJ8vJ8Sy4ImpmdCEisipst4w8r4QZOp8nu5q2AWNIocDF80+Hu4Cr/M1KEaujUDvHI5eCkwgP0yRgNnG4Mdx6amNHLhZlrIksPiYj+lskZ6DgBaDSPWNPeFatEE6p4v4wD1uJEfmmSAunxj+FRYA3UXn7e+A79ejBTdJ8QMKf9UWSDNr4juSpsuqcx5yoLA3dVj+sVYd9Uj7w3Y7HUK/I/WhFSVSHWDUVgrHtIUhwM3w2oygP6xK3B8W5ORejsCR2W2dznLyqMx8kmAP7M0Q8+2QFahc8qW/GjkST045O9VnRzfvahJTowEX+OOn/nHvGDwCnYuQSv70MYjje86kAHEyzY5s79g7D2yBUN47nO63nNm9maRaE0fXg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(376002)(346002)(39860400002)(396003)(36840700001)(46966006)(4326008)(26005)(8676002)(6916009)(70586007)(70206006)(47076005)(1076003)(4744005)(7696005)(450100002)(8936002)(6666004)(5660300002)(6286002)(55016002)(7636003)(356005)(426003)(82310400003)(478600001)(16526019)(186003)(2616005)(83380400001)(336012)(82740400003)(86362001)(36756003)(316002)(2906002)(54906003)(36906005)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2021 19:24:16.5316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dd59f70-f9b9-4430-58c6-08d93a6a5202 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1552 Subject: [dpdk-dev] [PATCH 3/3] regex/mlx5: fix redundancy in PCI remove function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the PCI removal function, PMD releases all driver resources and cancels the regexdev registry. However, regexdev registration is accidentally canceled twice. Remove one of them. Fixes: b34d816363b5 ("regex/mlx5: support rules import") Cc: stable@dpdk.org Signed-off-by: Michael Baum --- drivers/regex/mlx5/mlx5_regex.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index f64dc2824c..1c5bf930ad 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -290,8 +290,6 @@ mlx5_regex_pci_remove(struct rte_pci_device *pci_dev) rte_regexdev_unregister(priv->regexdev); if (priv->ctx) mlx5_glue->close_device(priv->ctx); - if (priv->regexdev) - rte_regexdev_unregister(priv->regexdev); rte_free(priv); } return 0;