From patchwork Tue Jun 1 07:11:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 93690 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66EF0A0A02; Tue, 1 Jun 2021 09:36:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AAF11410E5; Tue, 1 Jun 2021 09:11:52 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2050.outbound.protection.outlook.com [40.107.220.50]) by mails.dpdk.org (Postfix) with ESMTP id 2985540040; Tue, 1 Jun 2021 09:11:51 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EdwJ7pfwB0pFtI5yzIFfu3R8dEjmq4ZEcwMnSNqbEt8Zzz1fM6sXyBq/hO7j4fJ4lxcX1QklAK5AvXD2Wvvs3fteg+LeR0ugPhiA9NuamMamnNGURcKctsfbXH4N45iaECduOvNKNFaExzPKxmftYkMmLrLEbMWADWfNMUFuF6OAh7LUHnENYHiHo4gCpNBVmX3gJMZYLWqMqV5p2levuds41o9ws0cX9knDUL2/FS0SMSnoZfEqGmOZBtfqAcBHhKEGFlzIiCHnKTtFjDdrG/tgIzpLG3ySWV1LKkhpq7GbS9WIZqH4fkc2B0k77+Lth2RK36QTB46pee9A7L6dIg== ARC-Message-Signature: i=1; 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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT025.mail.protection.outlook.com (10.13.177.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4150.30 via Frontend Transport; Tue, 1 Jun 2021 07:11:49 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 1 Jun 2021 07:11:47 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Tue, 1 Jun 2021 10:11:19 +0300 Message-ID: <20210601071122.1612432-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 807d3e4a-2e92-42db-788c-08d924cc8660 X-MS-TrafficTypeDiagnostic: DM5PR12MB1819: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2021 07:11:49.4254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 807d3e4a-2e92-42db-788c-08d924cc8660 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1819 Subject: [dpdk-dev] [PATCH 1/4] regex/mlx5: fix size of setup constants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The constant representing the size of the metadata is defined as a unsigned int variable with 32-bit. Similarly the constant representing the maximal output is also defined as a unsigned int variable with 32-bit. There is potentially overflowing expression when those constants are evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type size_t (64 bits, unsigned). Change the size of the above constants to 64-bit. Fixes: 30d604bb1504 ("regex/mlx5: fix type of setup constants") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/regex/mlx5/mlx5_regex_fastpath.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index b57e7d7794..3ef5e6c1eb 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -25,8 +25,8 @@ #include "mlx5_regex.h" #define MLX5_REGEX_MAX_WQE_INDEX 0xffff -#define MLX5_REGEX_METADATA_SIZE UINT32_C(64) -#define MLX5_REGEX_MAX_OUTPUT RTE_BIT32(11) +#define MLX5_REGEX_METADATA_SIZE UINT64_C(64) +#define MLX5_REGEX_MAX_OUTPUT RTE_BIT64(11) #define MLX5_REGEX_WQE_CTRL_OFFSET 12 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 From patchwork Tue Jun 1 07:11:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 93688 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00A13A0A0E; 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Tue, 1 Jun 2021 07:11:49 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Tue, 1 Jun 2021 10:11:20 +0300 Message-ID: <20210601071122.1612432-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601071122.1612432-1-michaelba@nvidia.com> References: <20210601071122.1612432-1-michaelba@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 92cfd506-00ef-452c-e202-08d924cc876d X-MS-TrafficTypeDiagnostic: BYAPR12MB3000: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sbbVKqOu2NAS7WPbNxC+HyAloLme8ZCm+b0WnkW+wl04iJyJ8diCP3aAOXkzHysWgGrzYPtoqcwKRCoxwJtkY9gGDWPU1Yeo77QjrEQ/CACX24lMI7gGcaVjRda2SC33z5BdEH9lyt1coCti/VTw1Ku5zONaZSC+f6M1OobUKU2iaEu3dJArbuSbUb3t/WwxJovseLCwI/NhObWZC3Ll6SeJjnBlMqbz4dQYPrOP0om9v5VFpkOi8w6v2Z/ClTPgnlMDuR1OLSr0F1Iu2OIodidNl9CF58XNvcU7te0BXmMSjhkDmBKPRTeLXW/Sy8lf4x1HzHym8D2KBfzEuh8wfc746ERkbFOa8lt3mIsccGQ6uMGsRibQS6JoVnLI6LpXrewUnvYUFBnS2v/nZcO9ALncNVf5mHaC/sDTIS7d39Ji9T4NrZhx5VB1MGUUAa+StcYCKHIXTH4QbH6Gru5frjkRgF/NvPn7xcfPjvCeweute8QLMoN0pqiFJTFJEvv/KmqE37doB5B7aXgmJ2FLrh7MieWkgpmyiLlkbzEku4l7sqXaoRV4pNfJ08jy6/CuGjT79RTNbsW0btLnf0PSwNTCJ8sPVnyOxbF96rFIGlbsLwTgwhrMJe72RrtAsuV8QcVpQS5GBuFtlucR39ozxg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(376002)(396003)(136003)(346002)(36840700001)(46966006)(5660300002)(36756003)(26005)(7636003)(426003)(6916009)(6286002)(16526019)(36906005)(7696005)(316002)(8676002)(82310400003)(336012)(70586007)(450100002)(36860700001)(4326008)(55016002)(8936002)(86362001)(83380400001)(82740400003)(2906002)(1076003)(478600001)(2616005)(186003)(54906003)(6666004)(356005)(70206006)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2021 07:11:51.1950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92cfd506-00ef-452c-e202-08d924cc876d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3000 Subject: [dpdk-dev] [PATCH 2/4] compress/mlx5: fix constant size in QP creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5_compress_qp_setup function makes shifting to the numeric constant 1, then sends it as a parameter to rte_calloc function. The rte_calloc function expects to get size_t (64 bits, unsigned) and instead gets a 32-bit variable, because the numeric constant size is a 32-bit. In case the shift is greater than 32 the variable will lose its value even though the function can get 64-bit argument. Change the size of the numeric constant 1 to 64-bit. Fixes: 8619fcd5161b ("compress/mlx5: support queue pair operations") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 80c564f10b..90d009c56b 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -209,7 +209,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, return -rte_errno; } dev->data->queue_pairs[qp_id] = qp; - opaq_buf = rte_calloc(__func__, 1u << log_ops_n, + opaq_buf = rte_calloc(__func__, RTE_BIT64(log_ops_n), sizeof(struct mlx5_gga_compress_opaque), sizeof(struct mlx5_gga_compress_opaque)); if (opaq_buf == NULL) { From patchwork Tue Jun 1 07:11:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 93687 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F00BAA0A0C; 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Tue, 1 Jun 2021 07:11:53 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 1 Jun 2021 07:11:51 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Tue, 1 Jun 2021 10:11:21 +0300 Message-ID: <20210601071122.1612432-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601071122.1612432-1-michaelba@nvidia.com> References: <20210601071122.1612432-1-michaelba@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3833df6c-8a5f-4be0-f24b-08d924cc8892 X-MS-TrafficTypeDiagnostic: BY5PR12MB4904: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cMVhd2BKd5GUp2DwHmt+96EoEjZ4Xpm1QK0arJPxdu29EAyVM+/ihbFc8IXyVzwRc95QfgLdlwhIdq1hAUIfmugskG3xFdQu9100nsjGOGwUwfHRwi8rZNdtxlSZ0evP7d8F9NnloAv1UvTh3cwpD/hnZljxeLDNc3LhIo/UaufgGP+LmSOl96lqXSE7riuAAerHP5tnZvT1ceHlgmLLwJ5CEDguFFnlCYmSJfYCWXqXe2BPI2l28CewnNVSPjvJaG+h27JAEUyD1oPNg8HmuDBr1OD25DBp7CJrQ7IBheQcWotKBOWY7rbHmvtpnz8QbJdA76WF9ZC2oWbPMmxqPQOJ3n6Lzvswx4Gl6X13OLzReFV8fsDHT8Q4VspPEGGUai6epW6MB4aGIwtSl/CzdMGx1wXBUv12ScaPYiEAdGlLythsaPVDiRgI+KgOKJv129VqnBWgdIbx1R8xnx3C9Ml4Zy174GcAOGrPVWjVegoQExV5WfxK4CoY505L624XWbcGVqH8jKGKje+aMLRg+wbuuwpG8rmkgFl0Dbic9IQt/Tturmg8qTogsJC3BBuQtwC4b7QSuEIFOZv5MVyUF1W00SwgugRrFokFolcmcVSRoQPTE9pHwYsGyjWYXR+yYK7DDCcQhRDA9MNE0aS8cg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(396003)(136003)(39860400002)(346002)(46966006)(36840700001)(36906005)(36860700001)(426003)(7696005)(4326008)(82310400003)(54906003)(83380400001)(450100002)(316002)(8676002)(7636003)(47076005)(478600001)(55016002)(82740400003)(70206006)(6286002)(2906002)(6666004)(6916009)(356005)(5660300002)(26005)(70586007)(86362001)(16526019)(8936002)(2616005)(1076003)(336012)(36756003)(186003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2021 07:11:53.0956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3833df6c-8a5f-4be0-f24b-08d924cc8892 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4904 Subject: [dpdk-dev] [PATCH 3/4] vdpa/mlx5: fix constant type in QP creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5_vdpa_event_qp_create function makes shifting to the numeric constant 1, then multiplies it by another constant and finally assigns it into a uint64_t variable. The numeric constant type is an int with a 32-bit sign. if after shifting , its MSB (bit of sign) will change, the uint64 variable will get into it a different value than what the function intended it to get. Set the numeric constant 1 to be uint64_t in the first place. Fixes: 8395927cdfaf ("vdpa/mlx5: prepare HW queues") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index 88f6a4256d..3541c652ce 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -629,8 +629,8 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, attr.wq_umem_id = eqp->umem_obj->umem_id; attr.wq_umem_offset = 0; attr.dbr_umem_id = eqp->umem_obj->umem_id; - attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE; attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); + attr.dbr_address = RTE_BIT64(log_desc_n) * MLX5_WSEG_SIZE; eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (!eqp->sw_qp) { DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno); From patchwork Tue Jun 1 07:11:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 93689 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0AF0AA0A0A; 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Tue, 1 Jun 2021 07:11:52 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Tue, 1 Jun 2021 10:11:22 +0300 Message-ID: <20210601071122.1612432-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601071122.1612432-1-michaelba@nvidia.com> References: <20210601071122.1612432-1-michaelba@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9e88416b-686d-4c9e-3996-08d924cc899c X-MS-TrafficTypeDiagnostic: MW2PR12MB2460: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rmNshEij0XD4s+g950Rf7kXcF014JDD+vJanVlBzCqep+LKpokXkrov8Xl3xrADhqk1c8ReMPHQLQoKYJWQI+8QCZWI/Tpx3B5mWV71qWbh4enLfOOdQwjdxapbGhs6AxYxMo/pS85IJuK9zGGOy2U7h/KKpo8BivWjzlM/kPoOv5LHRmACUKZBlyLf+qfNOmg6Nt+D3B0XJsEyL+STBDhIQ2WMKiKntsH4HL7Gm2cRXOJBFG/ZjFOrP1uylZvZe771AcFD7bviIYnAclf1Ty/TI9IoAKCEQrpajYMOCneu1kqdi8t3hxW1Sq0S4gsoHA4OT1agctr7clAxW884bTRn9wChHiiwfTZRfNXRzjUgq6q9I4Q5m/KZAqg0BkH05bfs1PCzQK0VRvFtPbHJB3Bh/1hMNUQhS4RlHPtZTKe3ITLcOr862lNRiy08eGHPNy3lwoArVGMZ3AXTjQhSVDGIy5o/tpMic+bF+eppbuEEJrAuJi3v8+2ZF8sFY3EJa5VmsdIpT+mUsC/4XcaxsJOSkQw0wuK0R1LbSW2LUtfudWN5lL3mY2ek0gVm7QErZhIf//1FXVAu5OufHF2E/Vx4Dd0JKnaHyqn55MpS4cSom/zYRgR5RKgwRuLk9tgmEC+oEAiDfcpKA2rABWgFtNUnj7D8w2TWO2bRkvM4vGy0= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(376002)(346002)(396003)(136003)(36840700001)(46966006)(36756003)(6916009)(16526019)(186003)(450100002)(6286002)(7636003)(7696005)(82740400003)(2616005)(336012)(55016002)(316002)(47076005)(26005)(356005)(478600001)(4326008)(36906005)(70206006)(70586007)(36860700001)(8936002)(83380400001)(1076003)(6666004)(2906002)(426003)(5660300002)(86362001)(82310400003)(8676002)(54906003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2021 07:11:54.8552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e88416b-686d-4c9e-3996-08d924cc899c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2460 Subject: [dpdk-dev] [PATCH 4/4] net/mlx5: fix constant type in MP allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5_mprq_alloc_mp function makes shifting to the numeric constant 1, for sending it as a parameter to rte_mempool_create function. The rte_mempool_create function expects to get void pointer (64 bits, uintptr_t) and instead gets a 32-bit variable, because the numeric constant size is a 32-bit. In case the shift is greater than 32 the variable will lose its value even though the function can get 64-bit argument. Change the size of the numeric constant 1 to 64-bit. Fixes: 3a22f3877c9d ("net/mlx5: replace external mbuf shared memory") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index bb9a908087..950f327f03 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -1240,7 +1240,7 @@ mlx5_mprq_alloc_mp(struct rte_eth_dev *dev) snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id); mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ, 0, NULL, NULL, mlx5_mprq_buf_init, - (void *)(uintptr_t)(1 << strd_num_n), + (void *)(uintptr_t)RTE_BIT64(strd_num_n), dev->device->numa_node, 0); if (mp == NULL) { DRV_LOG(ERR,