From patchwork Mon May 31 21:41:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93640 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 89727A0524; Mon, 31 May 2021 23:42:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 31D2440E3C; Mon, 31 May 2021 23:42:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 013C340E32 for ; Mon, 31 May 2021 23:41:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeTnM002867; Mon, 31 May 2021 14:41:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=P+LOOPU1RA+IZn1deFCgB9yL0ga4k7I07ZQEtQzRpsU=; b=R1zBjmpt5bwnL7jxivlaQsJEetbpxrzbGKRrxplvRiSmQpuK6OV5+L93KDL40S5ch4ic OoixQG0Tjke6+76Cxw/6DFg9apHfnzzO4zqbZ0bQskytmzVVELS932fT93RmF5WTtdXS a3ZPwJYN6ZGK31T2rq9O16Bot5dwEKXvC4/KIiFOQSOZt3YXV83e4FVFgw/lTqCy7S4r fcgAWapilQeVy7fQ8otrvUnfpmclpni/CQWiHKPwpMOXDM0iFs6BATfpjhT5VPJZzwmW dkA/ysDKKfYztuouYXVmv+grUjEUDzYogKXzHjmuWzcUrXNk/3uxluIo7zQxBAyTrafe oQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja11p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:41:56 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:41:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:41:54 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 27BC53F7041; Mon, 31 May 2021 14:41:51 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:15 +0200 Message-ID: <20210531214142.30167-2-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: NcXrtYsUotmYv1236KHC8S8vOXSyKZZa X-Proofpoint-ORIG-GUID: NcXrtYsUotmYv1236KHC8S8vOXSyKZZa X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 01/28] common/cnxk: add bphy cgx/rpm initialization and cleanup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for low level initialization and cleanup of baseband phy cgx/rpm blocks. Initialization and cleanup are related hence are in the same patch. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_api.h | 3 ++ drivers/common/cnxk/roc_bphy_cgx.c | 62 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 20 ++++++++++ drivers/common/cnxk/version.map | 2 + 5 files changed, 88 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 178bce7ab..59975fd34 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -11,6 +11,7 @@ endif config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( + 'roc_bphy_cgx.c', 'roc_dev.c', 'roc_idev.c', 'roc_irq.c', diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 67f5d13f0..256d8c68d 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -100,4 +100,7 @@ /* Idev */ #include "roc_idev.h" +/* Baseband phy cgx */ +#include "roc_bphy_cgx.h" + #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c new file mode 100644 index 000000000..029d4102e --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" + +/* + * CN10K stores number of lmacs in 4 bit filed + * in contraty to CN9K which uses only 3 bits. + * + * In theory masks should differ yet on CN9K + * bits beyond specified range contain zeros. + * + * Hence common longer mask may be used. + */ +#define CGX_CMRX_RX_LMACS 0x128 +#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) + +static uint64_t +roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) +{ + int shift = roc_model_is_cn10k() ? 20 : 18; + uint64_t base = (uint64_t)roc_cgx->bar0_va; + + return plt_read64(base + (lmac << shift) + offset); +} + +static unsigned int +roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx) +{ + uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) : + GENMASK_ULL(25, 24); + + return FIELD_GET(cgx_id, roc_cgx->bar0_pa); +} + +int +roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx) +{ + uint64_t val; + + if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa) + return -EINVAL; + + val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS); + val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val); + if (roc_model_is_cn9k()) + val = GENMASK_ULL(val - 1, 0); + roc_cgx->lmac_bmap = val; + roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx); + + return 0; +} + +int +roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx) +{ + if (!roc_cgx) + return -EINVAL; + + return 0; +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h new file mode 100644 index 000000000..aac2c262c --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BPHY_CGX_H_ +#define _ROC_BPHY_CGX_H_ + +#include "roc_api.h" + +struct roc_bphy_cgx { + uint64_t bar0_pa; + void *bar0_va; + uint64_t lmac_bmap; + unsigned int id; +} __plt_cache_aligned; + +__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); +__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); + +#endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 8e67c83a6..1db4d104a 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -9,6 +9,8 @@ INTERNAL { cnxk_logtype_sso; cnxk_logtype_tim; cnxk_logtype_tm; + roc_bphy_cgx_dev_fini; + roc_bphy_cgx_dev_init; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93641 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 77A05A0524; Mon, 31 May 2021 23:42:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4E8BD40E6E; Mon, 31 May 2021 23:42:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9BFEF40E32 for ; Mon, 31 May 2021 23:41:59 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLf2vH003782 for ; Mon, 31 May 2021 14:41:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=xC2wQMH2dDFZ2hjY448ggDImstQj6wbizP4PfxF6oxM=; b=FpaViK4DWdlF3YsCkKU0GMth714B5idoadK9J8448X1vrIBbyihKz3yAXVxwEo8FknpS de5aIgJWB4fXLyVU8M4jkZBRa3bs9v5CKMuSKXaOyACqiovAGlvfZnI0Q6FBh3rpHJ7G WSmUzp7gReQNnFb72g3ZzSQizHKOUphHG/v0kEzUv0cyVXwQUQ8IC9pnBOmDtHFk2l3G QG0Kx6mlrf0lzbUCa/OGJLWnK8J9ECh3QEoBLUtLFHNz9/QwDAF7jej8jX5Q4mNECFw0 kA/D395CEV0wNsnORj3mwI7V6yEKa58skvshyLAvtVtYsdkH5zkCvWpYc4Y58DMeFaQx gQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja11s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 May 2021 14:41:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:41:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:41:56 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id E046B3F7040; Mon, 31 May 2021 14:41:54 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao Date: Mon, 31 May 2021 23:41:16 +0200 Message-ID: <20210531214142.30167-3-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: NKFr3X6uaKvja2bqihKKNfjUl4AmTCzv X-Proofpoint-ORIG-GUID: NKFr3X6uaKvja2bqihKKNfjUl4AmTCzv X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 02/28] common/cnxk: add support for communication with atf X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Messages can be exchanged between userspace software and firmware via set of two dedicated registers, namely scratch1 and scratch0. scratch1 acts as a command register i.e message is sent to firmware, while scratch0 holds response to previously sent message. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 145 ++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 4 + drivers/common/cnxk/roc_bphy_cgx_priv.h | 54 +++++++++ drivers/common/cnxk/roc_priv.h | 3 + 4 files changed, 206 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 029d4102e..5048a90de 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -2,8 +2,13 @@ * Copyright(C) 2021 Marvell. */ +#include + #include "roc_api.h" +#include "roc_priv.h" +#define CGX_CMRX_INT 0x40 +#define CGX_CMRX_INT_OVERFLW BIT_ULL(1) /* * CN10K stores number of lmacs in 4 bit filed * in contraty to CN9K which uses only 3 bits. @@ -15,6 +20,8 @@ */ #define CGX_CMRX_RX_LMACS 0x128 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) +#define CGX_CMRX_SCRATCH0 0x1050 +#define CGX_CMRX_SCRATCH1 0x1058 static uint64_t roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) @@ -25,6 +32,137 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) return plt_read64(base + (lmac << shift) + offset); } +static void +roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset, + uint64_t value) +{ + int shift = roc_model_is_cn10k() ? 20 : 18; + uint64_t base = (uint64_t)roc_cgx->bar0_va; + + plt_write64(value, base + (lmac << shift) + offset); +} + +static void +roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + uint64_t *scr0) +{ + uint64_t val; + + /* clear interrupt */ + val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT); + val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1); + roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val); + + /* ack fw response */ + *scr0 &= ~SCR0_ETH_EVT_STS_S_ACK; + roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0); +} + +static int +roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + uint64_t scr0, scr1; + int tries = 5000; + + do { + scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0); + scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1); + + if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW && + FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0) == 0) + break; + + /* clear async events if any */ + if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, scr0) == ETH_EVT_ASYNC && + FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0)) + roc_bphy_cgx_ack(roc_cgx, lmac, &scr0); + + plt_delay_ms(1); + } while (--tries); + + return tries ? 0 : -ETIMEDOUT; +} + +static int +roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + uint64_t scr0, scr1; + int tries = 5000; + + do { + scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0); + scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1); + + if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW && + FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0)) + break; + + plt_delay_ms(1); + } while (--tries); + + return tries ? 0 : -ETIMEDOUT; +} + +static int +roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + uint64_t scr1, uint64_t *scr0) +{ + uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1); + int ret; + + pthread_mutex_lock(&roc_cgx->lock); + + /* wait for ownership */ + ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac); + if (ret) { + plt_err("timed out waiting for ownership"); + goto out; + } + + /* write command */ + scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE); + roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1); + + /* wait for command ack */ + ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac); + if (ret) { + plt_err("timed out waiting for response"); + goto out; + } + + if (cmd_id == ETH_CMD_INTF_SHUTDOWN) + goto out; + + *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0); + + if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) { + plt_err("received async event instead of cmd resp event"); + ret = -EIO; + goto out; + } + + if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) { + plt_err("received resp for cmd %d expected for cmd %d", + (int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id); + ret = -EIO; + goto out; + } + + if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) { + plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id, + roc_cgx->id, lmac, + (int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0)); + ret = -EIO; + } + +out: + roc_bphy_cgx_ack(roc_cgx, lmac, scr0); + + pthread_mutex_unlock(&roc_cgx->lock); + + return ret; +} + static unsigned int roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx) { @@ -38,10 +176,15 @@ int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx) { uint64_t val; + int ret; if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa) return -EINVAL; + ret = pthread_mutex_init(&roc_cgx->lock, NULL); + if (ret) + return ret; + val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS); val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val); if (roc_model_is_cn9k()) @@ -58,5 +201,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx) if (!roc_cgx) return -EINVAL; + pthread_mutex_destroy(&roc_cgx->lock); + return 0; } diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index aac2c262c..37b5c2742 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -5,6 +5,8 @@ #ifndef _ROC_BPHY_CGX_H_ #define _ROC_BPHY_CGX_H_ +#include + #include "roc_api.h" struct roc_bphy_cgx { @@ -12,6 +14,8 @@ struct roc_bphy_cgx { void *bar0_va; uint64_t lmac_bmap; unsigned int id; + /* serialize access to the whole structure */ + pthread_mutex_t lock; } __plt_cache_aligned; __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h new file mode 100644 index 000000000..42d0bce7a --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BPHY_CGX_PRIV_H_ +#define _ROC_BPHY_CGX_PRIV_H_ + +/* REQUEST ID types. Input to firmware */ +enum eth_cmd_id { + ETH_CMD_INTF_SHUTDOWN = 12, +}; + +/* event types - cause of interrupt */ +enum eth_evt_type { + ETH_EVT_ASYNC, + ETH_EVT_CMD_RESP, +}; + +enum eth_stat { + ETH_STAT_SUCCESS, + ETH_STAT_FAIL, +}; + +enum eth_cmd_own { + /* default ownership with kernel/uefi/u-boot */ + ETH_OWN_NON_SECURE_SW, + /* set by kernel/uefi/u-boot after posting a new request to ATF */ + ETH_OWN_FIRMWARE, +}; + +/* scratchx(0) CSR used for ATF->non-secure SW communication. + * This acts as the status register + * Provides details on command ack/status, link status, error details + */ + +/* struct eth_evt_sts_s */ +#define SCR0_ETH_EVT_STS_S_ACK BIT_ULL(0) +#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1) +#define SCR0_ETH_EVT_STS_S_STAT BIT_ULL(2) +#define SCR0_ETH_EVT_STS_S_ID GENMASK_ULL(8, 3) + +/* struct eth_lnk_sts_s */ +#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15) + +/* scratchx(1) CSR used for non-secure SW->ATF communication + * This CSR acts as a command register + */ + +/* struct eth_cmd */ +#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2) + +#define SCR1_OWN_STATUS GENMASK_ULL(1, 0) + +#endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h index 5e7564ce5..feca732a9 100644 --- a/drivers/common/cnxk/roc_priv.h +++ b/drivers/common/cnxk/roc_priv.h @@ -32,4 +32,7 @@ /* TIM */ #include "roc_tim_priv.h" +/* BPHY CGX */ +#include "roc_bphy_cgx_priv.h" + #endif /* _ROC_PRIV_H_ */ From patchwork Mon May 31 21:41:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93642 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56339A0524; Mon, 31 May 2021 23:42:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5B36C410E2; Mon, 31 May 2021 23:42:05 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BD3BE410D7 for ; Mon, 31 May 2021 23:42:03 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeJBF002825; Mon, 31 May 2021 14:42:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=M1s4SIMWI1PSoSUatIQPj2YV3K0RjAIlp+pugI9LUqQ=; b=NTAU1PCSM5QY8OjFkqmzPN9NcSh/apg19A7tAcNNV6D86iJCvH80G57eWSeC3VqSBqOS kz7N+ybt2Rcki++UYluN8H2TnCpl2E/ZGxXYy/1+l1UFDwLW6dPm/KM0zwdc6f8mlWuW fhD5FHTJlXmJagtrWEsXNMIgIL3j8FO8iAyTfDqleU8918gcqFX5MMPxJCHAab2CTG/7 qndgIosKCCbd19da/E770krqOQzF+p+AS1tPZ9RZM2amvMH7CP2LElGH+1MPUdM6FzaK qxVpSNjfFZT/842tsYsKFf6MA7PhTs0+7815pjTHZaSveF8Z7TAxrXaVqr+pdn7oe+BJ nA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja11w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:01 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:41:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:41:59 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 44FDC3F7041; Mon, 31 May 2021 14:41:57 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:17 +0200 Message-ID: <20210531214142.30167-4-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: qt32av-jSSHnSPrsmYcoTSlJPUNtpG4H X-Proofpoint-ORIG-GUID: qt32av-jSSHnSPrsmYcoTSlJPUNtpG4H X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 03/28] common/cnxk: add support for getting link information X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for retrieving link information. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 38 ++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 70 +++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 9 ++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 118 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 5048a90de..c7ba53ede 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -205,3 +205,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx) return 0; } + +static bool +roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return (lmac < MAX_LMACS_PER_CGX) && + (roc_cgx->lmac_bmap & BIT_ULL(lmac)); +} + +int +roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_link_info *info) +{ + uint64_t scr1, scr0; + int ret; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -EINVAL; + + if (!info) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS); + ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); + if (ret) + return ret; + + info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0); + info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0); + info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0); + info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0); + info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0); + info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0); + + return 0; +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 37b5c2742..bb1d903eb 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -9,6 +9,8 @@ #include "roc_api.h" +#define MAX_LMACS_PER_CGX 4 + struct roc_bphy_cgx { uint64_t bar0_pa; void *bar0_va; @@ -18,7 +20,75 @@ struct roc_bphy_cgx { pthread_mutex_t lock; } __plt_cache_aligned; +enum roc_bphy_cgx_eth_link_speed { + ROC_BPHY_CGX_ETH_LINK_SPEED_NONE, + ROC_BPHY_CGX_ETH_LINK_SPEED_10M, + ROC_BPHY_CGX_ETH_LINK_SPEED_100M, + ROC_BPHY_CGX_ETH_LINK_SPEED_1G, + ROC_BPHY_CGX_ETH_LINK_SPEED_2HG, + ROC_BPHY_CGX_ETH_LINK_SPEED_5G, + ROC_BPHY_CGX_ETH_LINK_SPEED_10G, + ROC_BPHY_CGX_ETH_LINK_SPEED_20G, + ROC_BPHY_CGX_ETH_LINK_SPEED_25G, + ROC_BPHY_CGX_ETH_LINK_SPEED_40G, + ROC_BPHY_CGX_ETH_LINK_SPEED_50G, + ROC_BPHY_CGX_ETH_LINK_SPEED_80G, + ROC_BPHY_CGX_ETH_LINK_SPEED_100G, + __MAX_ROC_BPHY_CGX_ETH_LINK_SPEED +}; + +enum roc_bphy_cgx_eth_link_fec { + ROC_BPHY_CGX_ETH_LINK_FEC_NONE, + ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R, + ROC_BPHY_CGX_ETH_LINK_FEC_RS, + __MAX_ROC_BPHY_CGX_ETH_LINK_FEC +}; + +enum roc_bphy_cgx_eth_link_mode { + ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, + ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + __MAX_ROC_BPHY_CGX_ETH_LINK_MODE +}; + +struct roc_bphy_cgx_link_info { + bool link_up; + bool full_duplex; + enum roc_bphy_cgx_eth_link_speed speed; + bool an; + enum roc_bphy_cgx_eth_link_fec fec; + enum roc_bphy_cgx_eth_link_mode mode; +}; + __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); +__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac, + struct roc_bphy_cgx_link_info *info); + #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index 42d0bce7a..c0550ae87 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -7,6 +7,7 @@ /* REQUEST ID types. Input to firmware */ enum eth_cmd_id { + ETH_CMD_GET_LINK_STS = 4, ETH_CMD_INTF_SHUTDOWN = 12, }; @@ -41,6 +42,14 @@ enum eth_cmd_own { /* struct eth_lnk_sts_s */ #define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15) +#define SCR0_ETH_LNK_STS_S_LINK_UP BIT_ULL(9) +#define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10) +#define SCR0_ETH_LNK_STS_S_SPEED GENMASK_ULL(14, 11) +#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15) +#define SCR0_ETH_LNK_STS_S_AN BIT_ULL(25) +#define SCR0_ETH_LNK_STS_S_FEC GENMASK_ULL(27, 26) +#define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28) +#define SCR0_ETH_LNK_STS_S_MODE GENMASK_ULL(43, 36) /* scratchx(1) CSR used for non-secure SW->ATF communication * This CSR acts as a command register diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 1db4d104a..466207f9d 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -11,6 +11,7 @@ INTERNAL { cnxk_logtype_tm; roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; + roc_bphy_cgx_get_linkinfo; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93643 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6D3E9A0524; Mon, 31 May 2021 23:42:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB453410F2; Mon, 31 May 2021 23:42:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 29EF9410F2 for ; Mon, 31 May 2021 23:42:07 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeEPu025923; Mon, 31 May 2021 14:42:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/dsNVBeplkUkGGLvkxiQKCw6ZuhSqThxOF4wZcVgDhs=; b=WQEWtmiq8qZxPYRFL44kfbM86Sr96AFFsaLQdiPnw2B/eWHEq5QTXg+XkqIS35ADaN49 HSvcuuXKntCBUqoLmrZ4P2oZb3hE8Rc1VmS/jH/n1Td78YPR5NCH7lLUR93Kg1BYAs43 4+JOn79Ip4+tfgyIYl0Frn/pc9JSXrAlwUYgS6clxQ9M3W1y/FYavef5I115iOY42xoa PhMUskcPAjvs0tLD+e4/MSHBtjYWEci1dlK/MwU24DYviBEwxOeUov9kvbqozk38N4eH 77SvGukle4W2skgmy62UDIe7fecNVp7XajAQxSAFWzhtYvwQvd109vsyfxMGLblyBVJi EQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj3381-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:03 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:02 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 09EA03F703F; Mon, 31 May 2021 14:41:59 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:18 +0200 Message-ID: <20210531214142.30167-5-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: WRhLPkf_buRx4vY-3H9FW3oBbBllBYFr X-Proofpoint-ORIG-GUID: WRhLPkf_buRx4vY-3H9FW3oBbBllBYFr X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 04/28] common/cnxk: add support for changing internal loopback X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for enabling or disabling internal loopback. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 30 +++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 4 ++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 4 ++++ drivers/common/cnxk/version.map | 2 ++ 4 files changed, 40 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index c7ba53ede..45088d5d4 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -213,6 +213,24 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) (roc_cgx->lmac_bmap & BIT_ULL(lmac)); } +static int +roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + bool enable) +{ + uint64_t scr1, scr0; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) | + FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} + int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_link_info *info) @@ -243,3 +261,15 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return 0; } + +int +roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true); +} + +int +roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false); +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index bb1d903eb..3bb9d49ed 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -90,5 +90,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_link_info *info); +__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac); +__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac); #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index c0550ae87..cb59cac09 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -8,6 +8,7 @@ /* REQUEST ID types. Input to firmware */ enum eth_cmd_id { ETH_CMD_GET_LINK_STS = 4, + ETH_CMD_INTERNAL_LBK = 7, ETH_CMD_INTF_SHUTDOWN = 12, }; @@ -58,6 +59,9 @@ enum eth_cmd_own { /* struct eth_cmd */ #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2) +/* struct eth_ctl_args */ +#define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 466207f9d..71437a6c5 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -12,6 +12,8 @@ INTERNAL { roc_bphy_cgx_dev_fini; roc_bphy_cgx_dev_init; roc_bphy_cgx_get_linkinfo; + roc_bphy_cgx_intlbk_disable; + roc_bphy_cgx_intlbk_enable; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93644 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B20FEA0524; Mon, 31 May 2021 23:42:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDB2B410EE; Mon, 31 May 2021 23:42:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 41F30410ED for ; Mon, 31 May 2021 23:42:09 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeNm7025956; Mon, 31 May 2021 14:42:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=yH1YDKzOU3gDfDmM7XRQKOfor5ExtG4GVbvAvP29t6M=; b=H/rbVfcaERozXLObdjhZMiFx47c6jDQZPYxerlAXzwKtKd/e1BWqYWtLG6izsZuCSm1K DxbvX7YYk5qpq8XVA6dFwPZHDuW14a++Ox44rW4qAWzAUQyy7s8D1gaMy6TBGme9GmJq 12fP3vA372KPRsuQtoEELBVgp/AV/gmrw2EYZ8rtZqzLfFNvUXvSzR4glHmwRZ39JpaW RTJcrpDGNGLpbQcQ+O+IprP/+FxZpQaJyFXfqiScOSCzWh6SO/C2Xa19WhMxzjwAhwjP 4zfgYWG0xkSYp0OvuKANx52+XjOwVBqL+rC+D+nj/HuTsAvwj0HtuKBNcBcYJbS33okp Ng== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj3387-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:06 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:05 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id BBA0E3F7041; Mon, 31 May 2021 14:42:02 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:19 +0200 Message-ID: <20210531214142.30167-6-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: eR8M-rK3sQGGG2125BaZdnyAY6nji-tt X-Proofpoint-ORIG-GUID: eR8M-rK3sQGGG2125BaZdnyAY6nji-tt X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 05/28] common/cnxk: add support for changing ptp mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for enabling or disablig ptp mode. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 33 +++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 5 ++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 1 + drivers/common/cnxk/version.map | 2 ++ 4 files changed, 41 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 45088d5d4..dbdaddcd0 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -231,6 +231,27 @@ roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); } +static int +roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + bool enable) +{ + uint64_t scr1, scr0; + + if (roc_model_is_cn10k()) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) | + FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} + int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_link_info *info) @@ -273,3 +294,15 @@ roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) { return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false); } + +int +roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true); +} + +int +roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false); +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 3bb9d49ed..a5e18565d 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -94,5 +94,10 @@ __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac); __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac); +__roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac); +__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac); + #endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index cb59cac09..4e86ae4ea 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -10,6 +10,7 @@ enum eth_cmd_id { ETH_CMD_GET_LINK_STS = 4, ETH_CMD_INTERNAL_LBK = 7, ETH_CMD_INTF_SHUTDOWN = 12, + ETH_CMD_SET_PTP_MODE = 34, }; /* event types - cause of interrupt */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 71437a6c5..205a0602b 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -14,6 +14,8 @@ INTERNAL { roc_bphy_cgx_get_linkinfo; roc_bphy_cgx_intlbk_disable; roc_bphy_cgx_intlbk_enable; + roc_bphy_cgx_ptp_rx_disable; + roc_bphy_cgx_ptp_rx_enable; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93645 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 840C1A0524; Mon, 31 May 2021 23:42:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 171C0410FD; Mon, 31 May 2021 23:42:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1B6D0410FB for ; Mon, 31 May 2021 23:42:11 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdlQs025666; Mon, 31 May 2021 14:42:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=R+ZNahac7m6EZCLCANbNLERwDIx9v0ntF6fMCOxmSXE=; b=ZWLz1ZWDmnocj2bjMD6kIwHXqGE4mTyJl1Enp12o1YmVrcsSaui1P2GsdPBFYvmQZHOW XtjcbSHIGZskkBolijhfuZLy+NG34CRb0ZkgqEhCumR9Hdx6lc9JdxCSk9ifoYuzg1MX tSa+FLYE0TeBs27STaITc8BEDB6swHyVmEnvYWLADT8A0ls8XNlaKEUfPYDLdHKoaESI jZR3JWHmAa79KFAEkVTBMgqqLCHTifU2c4nFkShWdQQSFhWaspYyvLu63KUNGXhBGiHc UCfICwGcuH7BaJ8+s0lD8OSRFzubRdBCxUw0asaj6cLLudVexo7K0+Ox2J9fhjD3Qi46 aA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj338c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:09 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:07 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 7CAB03F7043; Mon, 31 May 2021 14:42:05 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:20 +0200 Message-ID: <20210531214142.30167-7-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: kvcSnyIz-iJC4EI2FJIZ3Wiod4Z_vV0j X-Proofpoint-ORIG-GUID: kvcSnyIz-iJC4EI2FJIZ3Wiod4Z_vV0j X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 06/28] common/cnxk: add support for setting link mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for setting link mode. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 28 ++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 11 +++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 101 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index dbdaddcd0..930057bb0 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -283,6 +283,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return 0; } +int +roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_link_mode *mode) +{ + uint64_t scr1, scr0; + + if (roc_model_is_cn10k()) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -EINVAL; + + if (!mode) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode)); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} + int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) { diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index a5e18565d..f68ddfcc9 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode { __MAX_ROC_BPHY_CGX_ETH_LINK_MODE }; +struct roc_bphy_cgx_link_mode { + bool full_duplex; + bool an; + unsigned int port; + enum roc_bphy_cgx_eth_link_speed speed; + enum roc_bphy_cgx_eth_link_mode mode; +}; + struct roc_bphy_cgx_link_info { bool link_up; bool full_duplex; @@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_link_info *info); +__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac, + struct roc_bphy_cgx_link_mode *mode); __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac); __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index 4e86ae4ea..ee7578423 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -5,10 +5,64 @@ #ifndef _ROC_BPHY_CGX_PRIV_H_ #define _ROC_BPHY_CGX_PRIV_H_ +/* LINK speed types */ +enum eth_link_speed { + ETH_LINK_NONE, + ETH_LINK_10M, + ETH_LINK_100M, + ETH_LINK_1G, + ETH_LINK_2HG, /* 2.5 Gbps */ + ETH_LINK_5G, + ETH_LINK_10G, + ETH_LINK_20G, + ETH_LINK_25G, + ETH_LINK_40G, + ETH_LINK_50G, + ETH_LINK_80G, + ETH_LINK_100G, + ETH_LINK_MAX, +}; + +/* Supported LINK MODE enums + * Each link mode is a bit mask of these + * enums which are represented as bits + */ +enum eth_mode { + ETH_MODE_SGMII_BIT = 0, + ETH_MODE_1000_BASEX_BIT, + ETH_MODE_QSGMII_BIT, + ETH_MODE_10G_C2C_BIT, + ETH_MODE_10G_C2M_BIT, + ETH_MODE_10G_KR_BIT, /* = 5 */ + ETH_MODE_20G_C2C_BIT, + ETH_MODE_25G_C2C_BIT, + ETH_MODE_25G_C2M_BIT, + ETH_MODE_25G_2_C2C_BIT, + ETH_MODE_25G_CR_BIT, /* = 10 */ + ETH_MODE_25G_KR_BIT, + ETH_MODE_40G_C2C_BIT, + ETH_MODE_40G_C2M_BIT, + ETH_MODE_40G_CR4_BIT, + ETH_MODE_40G_KR4_BIT, /* = 15 */ + ETH_MODE_40GAUI_C2C_BIT, + ETH_MODE_50G_C2C_BIT, + ETH_MODE_50G_C2M_BIT, + ETH_MODE_50G_4_C2C_BIT, + ETH_MODE_50G_CR_BIT, /* = 20 */ + ETH_MODE_50G_KR_BIT, + ETH_MODE_80GAUI_C2C_BIT, + ETH_MODE_100G_C2C_BIT, + ETH_MODE_100G_C2M_BIT, + ETH_MODE_100G_CR4_BIT, /* = 25 */ + ETH_MODE_100G_KR4_BIT, + ETH_MODE_MAX_BIT /* = 27 */ +}; + /* REQUEST ID types. Input to firmware */ enum eth_cmd_id { ETH_CMD_GET_LINK_STS = 4, ETH_CMD_INTERNAL_LBK = 7, + ETH_CMD_MODE_CHANGE = 11, /* hot plug support */ ETH_CMD_INTF_SHUTDOWN = 12, ETH_CMD_SET_PTP_MODE = 34, }; @@ -63,6 +117,13 @@ enum eth_cmd_own { /* struct eth_ctl_args */ #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8) +/* struct eth_mode_change_args */ +#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8) +#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12) +#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13) +#define SCR1_ETH_MODE_CHANGE_ARGS_PORT GENMASK_ULL(21, 14) +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 205a0602b..15a6d3a3b 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -16,6 +16,7 @@ INTERNAL { roc_bphy_cgx_intlbk_enable; roc_bphy_cgx_ptp_rx_disable; roc_bphy_cgx_ptp_rx_enable; + roc_bphy_cgx_set_link_mode; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93646 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F75EA0524; Mon, 31 May 2021 23:42:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 20BD7410FC; Mon, 31 May 2021 23:42:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C1AD8410FC for ; Mon, 31 May 2021 23:42:14 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeTnN002867; Mon, 31 May 2021 14:42:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=NttRpRdkx7ke+S/73HAIQCO0SQtiWIwRAj8yzB+jQ2g=; b=RRM6K704TvigQo0SQ6ZnRV7n7+De1O0yR2ZqVvrOmOhoDWvOHp1HstJWQ0WoWULb7oom Rny2ikkHsMkadTz409CWgbdKZh8nFurBWCHVNk5UuVIbgpq8Hb/IR8XE9DCMEUzf9Dts EA8EzsKW+f9HBAUFjb9Q91O5NEObZ6gk0/9VyidEidNeqrsXloRtQNaPOUsVHvsE1L1S 9Kq0Gat/DDUGpuyJPTX5W2xBow2lOpnRrRLqYky/0t8tp56NiNUkN5G3EITqBF7F9sXI /6v+3MkDJuHyNUuiC9C2jvaAplkg5Lzjy+oUZ1MG47meT21m7nVJ0Ob4OU7yWeFF7CPZ yw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja129-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:12 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:10 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 421283F703F; Mon, 31 May 2021 14:42:08 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:21 +0200 Message-ID: <20210531214142.30167-8-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: iRcDE04VSMlA0MpNRBFK4dA252mNgezk X-Proofpoint-ORIG-GUID: iRcDE04VSMlA0MpNRBFK4dA252mNgezk X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 07/28] common/cnxk: add support for changing link state X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for setting link up or down. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 18 ++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 2 ++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 2 ++ drivers/common/cnxk/version.map | 1 + 4 files changed, 23 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 930057bb0..d1701eaa7 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -252,6 +252,24 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); } +int +roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + bool state) +{ + uint64_t scr1, scr0; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -EINVAL; + + scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) : + FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} + int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_link_info *info) diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index f68ddfcc9..74f7465e7 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -95,6 +95,8 @@ struct roc_bphy_cgx_link_info { __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); +__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac, bool state); __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_link_info *info); diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index ee7578423..71a277fff 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -61,6 +61,8 @@ enum eth_mode { /* REQUEST ID types. Input to firmware */ enum eth_cmd_id { ETH_CMD_GET_LINK_STS = 4, + ETH_CMD_LINK_BRING_UP = 5, + ETH_CMD_LINK_BRING_DOWN = 6, ETH_CMD_INTERNAL_LBK = 7, ETH_CMD_MODE_CHANGE = 11, /* hot plug support */ ETH_CMD_INTF_SHUTDOWN = 12, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 15a6d3a3b..7766f52e0 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -17,6 +17,7 @@ INTERNAL { roc_bphy_cgx_ptp_rx_disable; roc_bphy_cgx_ptp_rx_enable; roc_bphy_cgx_set_link_mode; + roc_bphy_cgx_set_link_state; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93647 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 69C0BA0524; Mon, 31 May 2021 23:42:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3AC8D410E3; Mon, 31 May 2021 23:42:19 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9796641101 for ; Mon, 31 May 2021 23:42:17 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdlCn025682; Mon, 31 May 2021 14:42:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=IYwLHqiB7u6LTtyJ67Q9+dEZHMBdHAe6On7dRt1toxQ=; b=OWJY5NvxS/Fi2dwYKNyKWNloDHcjz1iJdBh3rXd7Qxy/taM4kcpy23qwQNNm4pUyS4Mw EX/52m5/HF5Ci/lJG0jGsThNcjXY77fjGwXmnq3HBkKYTyeNnSv64ZxQiH95irkwJFK7 Sfxi0CQFawojU12M1c9El6bsIGv2IqJ2AB7kXlrsGKneXZngkN4vn5x6PvGk/tC1D3yx kcUfGRu7uPpIvwXZCFsQvA/CxdUxzNSFBdksONtYgAFhs8+f0iR2APASH0yc+sgINgtF mQHQuAf9/5u6pb72PHKXDWULC8smfgoHJizm6FpJVZxQszaxFxmv7YKYXgoUMjMjNL+O BQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj338j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:14 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:13 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 03D153F7041; Mon, 31 May 2021 14:42:10 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:22 +0200 Message-ID: <20210531214142.30167-9-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 8IdyyOo96xE0ZzOqKpgKO5X5YAzYTOrq X-Proofpoint-ORIG-GUID: 8IdyyOo96xE0ZzOqKpgKO5X5YAzYTOrq X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 08/28] common/cnxk: add support for lmac start/stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for starting or stopping specific lmac. Start enables rx/tx traffic while stop does the opposite. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 42 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 4 +++ drivers/common/cnxk/version.map | 2 ++ 3 files changed, 48 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index d1701eaa7..886f8d65d 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -7,6 +7,9 @@ #include "roc_api.h" #include "roc_priv.h" +#define CGX_CMRX_CONFIG 0x00 +#define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54) +#define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53) #define CGX_CMRX_INT 0x40 #define CGX_CMRX_INT_OVERFLW BIT_ULL(1) /* @@ -213,6 +216,33 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) (roc_cgx->lmac_bmap & BIT_ULL(lmac)); } +static int +roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + bool start) +{ + uint64_t val; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -EINVAL; + + pthread_mutex_lock(&roc_cgx->lock); + val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG); + val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN | + CGX_CMRX_CONFIG_DATA_PKT_TX_EN); + + if (start) + val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) | + FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1); + + roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val); + pthread_mutex_unlock(&roc_cgx->lock); + + return 0; +} + static int roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, bool enable) @@ -252,6 +282,18 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); } +int +roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true); +} + +int +roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false); +} + int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, bool state) diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 74f7465e7..1f49de8fd 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -95,6 +95,10 @@ struct roc_bphy_cgx_link_info { __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); +__roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac); +__roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac); __roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, bool state); __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 7766f52e0..0ad805dba 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -18,6 +18,8 @@ INTERNAL { roc_bphy_cgx_ptp_rx_enable; roc_bphy_cgx_set_link_mode; roc_bphy_cgx_set_link_state; + roc_bphy_cgx_start_rxtx; + roc_bphy_cgx_stop_rxtx; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93649 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13169A0524; Mon, 31 May 2021 23:42:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C7B3541122; Mon, 31 May 2021 23:42:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0048B40E5A for ; Mon, 31 May 2021 23:42:19 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdkrw025644; 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Mon, 31 May 2021 14:42:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:15 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id C23CD3F7044; Mon, 31 May 2021 14:42:13 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Thomas Monjalon , Ray Kinsella , Neil Horman , Anatoly Burakov Date: Mon, 31 May 2021 23:41:23 +0200 Message-ID: <20210531214142.30167-10-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 7xiSvjmPcQi2-gv8NJU5IjGvBxJmIBnI X-Proofpoint-ORIG-GUID: 7xiSvjmPcQi2-gv8NJU5IjGvBxJmIBnI X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 09/28] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add baseband phy cgx/rpm skeleton driver. At this point it merely probes a matching device. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- MAINTAINERS | 5 + doc/guides/rawdevs/cnxk_bphy.rst | 50 +++++++++ doc/guides/rawdevs/index.rst | 1 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 151 ++++++++++++++++++++++++++ drivers/raw/cnxk_bphy/meson.build | 8 ++ drivers/raw/cnxk_bphy/version.map | 3 + drivers/raw/meson.build | 1 + usertools/dpdk-devbind.py | 4 +- 8 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c create mode 100644 drivers/raw/cnxk_bphy/meson.build create mode 100644 drivers/raw/cnxk_bphy/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 5877a1697..863b028fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1307,6 +1307,11 @@ F: doc/guides/rawdevs/ntb.rst F: examples/ntb/ F: doc/guides/sample_app_ug/ntb.rst +Marvell CNXK BPHY +M: Tomasz Duszynski +M: Jakub Palider +F: drivers/raw/cnxk_bphy/ +F: doc/guides/rawdevs/cnxk_bphy.rst Packet processing ----------------- diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst new file mode 100644 index 000000000..1b117a0e8 --- /dev/null +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -0,0 +1,50 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2021 Marvell International Ltd. + +Marvell CNXK BPHY Driver +========================================== + +CN10K/CN9K Fusion product families offer an internal BPHY unit which provides +set of hardware accelerators for performing baseband related operations. Connectivity +to the outside world happens through a block called RFOE which is backed by +ethernet I/O block called CGX or RPM (depending on the chip version). RFOE +stands for Radio Frequency Over Ethernet and provides support for +IEEE 1904.3 (RoE) standard. + +Features +-------- + +The BPHY CGX/RPM implements following features in the rawdev API: + +- Access to BPHY CGX/RPM via set of predefined messages. + +Device Setup +------------ + +The BPHY CGX/RPM devices will need to be bound to a user-space IO driver for +use. The script ``dpdk-devbind.py`` script included with DPDK can be used to +view the state of the devices and to bind them to a suitable DPDK-supported +kernel driver. When querying the status of the devices, they will appear under +the category of "Misc (rawdev) devices", i.e. the command +``dpdk-devbind.py --status-dev misc`` can be used to see the state of those +devices alone. + +To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and +``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible +responses hence dequeueing is not always necessary. + +Self test +--------- + +On EAL initialization, BPHY CGX/RPM devices will be probed and populated into +the raw devices. The rawdev ID of the device can be obtained using invocation +of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where: + +- NAME is the desired subsystem: use "BPHY_CGX" for + RFOE module, +- x is the device's bus id specified in "bus:device.func" (BDF) format. + +Use this identifier for further rawdev function calls. + +The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM +functionality. diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst index f64ec4427..7fbae40ea 100644 --- a/doc/guides/rawdevs/index.rst +++ b/doc/guides/rawdevs/index.rst @@ -11,6 +11,7 @@ application through rawdev API. :maxdepth: 2 :numbered: + cnxk_bphy dpaa2_cmdif dpaa2_qdma ifpga diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c new file mode 100644 index 000000000..e537888f9 --- /dev/null +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#include +#include +#include + +#include + +struct cnxk_bphy_cgx_queue { + unsigned int lmac; + /* queue holds up to one response */ + void *rsp; +}; + +struct cnxk_bphy_cgx { + struct roc_bphy_cgx *rcgx; + struct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX]; + unsigned int num_queues; +}; + +static void +cnxk_bphy_cgx_format_name(char *name, unsigned int len, + struct rte_pci_device *pci_dev) +{ + snprintf(name, len, "BPHY_CGX:%x:%02x.%x", pci_dev->addr.bus, + pci_dev->addr.devid, pci_dev->addr.function); +} + +static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { +}; + +static void +cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx) +{ + struct roc_bphy_cgx *rcgx = cgx->rcgx; + unsigned int i; + + for (i = 0; i < RTE_DIM(cgx->queues); i++) { + if (!(rcgx->lmac_bmap & BIT_ULL(i))) + continue; + + cgx->queues[cgx->num_queues++].lmac = i; + } +} + +static void +cnxk_bphy_cgx_fini_queues(struct cnxk_bphy_cgx *cgx) +{ + unsigned int i; + + for (i = 0; i < cgx->num_queues; i++) { + if (cgx->queues[i].rsp) + rte_free(cgx->queues[i].rsp); + } + + cgx->num_queues = 0; +} + +static int +cnxk_bphy_cgx_rawdev_probe(struct rte_pci_driver *pci_drv, + struct rte_pci_device *pci_dev) +{ + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *rawdev; + struct cnxk_bphy_cgx *cgx; + struct roc_bphy_cgx *rcgx; + int ret; + + RTE_SET_USED(pci_drv); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + if (!pci_dev->mem_resource[0].addr) + return -ENODEV; + + ret = roc_plt_init(); + if (ret) + return ret; + + cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev); + rawdev = rte_rawdev_pmd_allocate(name, sizeof(*cgx), rte_socket_id()); + if (!rawdev) + return -ENOMEM; + + rawdev->dev_ops = &cnxk_bphy_cgx_rawdev_ops; + rawdev->device = &pci_dev->device; + rawdev->driver_name = pci_dev->driver->driver.name; + + cgx = rawdev->dev_private; + cgx->rcgx = rte_zmalloc(NULL, sizeof(*rcgx), 0); + if (!cgx->rcgx) { + ret = -ENOMEM; + goto out_pmd_release; + } + + rcgx = cgx->rcgx; + rcgx->bar0_pa = pci_dev->mem_resource[0].phys_addr; + rcgx->bar0_va = pci_dev->mem_resource[0].addr; + ret = roc_bphy_cgx_dev_init(rcgx); + if (ret) + goto out_free; + + cnxk_bphy_cgx_init_queues(cgx); + + return 0; +out_free: + rte_free(rcgx); +out_pmd_release: + rte_rawdev_pmd_release(rawdev); + + return ret; +} + +static int +cnxk_bphy_cgx_rawdev_remove(struct rte_pci_device *pci_dev) +{ + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *rawdev; + struct cnxk_bphy_cgx *cgx; + + cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev); + rawdev = rte_rawdev_pmd_get_named_dev(name); + if (!rawdev) + return -ENODEV; + + cgx = rawdev->dev_private; + cnxk_bphy_cgx_fini_queues(cgx); + roc_bphy_cgx_dev_fini(cgx->rcgx); + rte_free(cgx->rcgx); + + return rte_rawdev_pmd_release(rawdev); +} + +static const struct rte_pci_id cnxk_bphy_cgx_map[] = { + {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_CGX)}, + {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM)}, + {} /* sentinel */ +}; + +static struct rte_pci_driver bphy_cgx_rawdev_pmd = { + .id_table = cnxk_bphy_cgx_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = cnxk_bphy_cgx_rawdev_probe, + .remove = cnxk_bphy_cgx_rawdev_remove, +}; + +RTE_PMD_REGISTER_PCI(cnxk_bphy_cgx_rawdev_pci_driver, bphy_cgx_rawdev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(cnxk_bphy_cgx_rawdev_pci_driver, cnxk_bphy_cgx_map); +RTE_PMD_REGISTER_KMOD_DEP(cnxk_bphy_cgx_rawdev_pci_driver, "vfio-pci"); diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build new file mode 100644 index 000000000..a85c9774b --- /dev/null +++ b/drivers/raw/cnxk_bphy/meson.build @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2021 Marvell International Ltd. +# + +deps += ['bus_pci', 'common_cnxk', 'rawdev'] +sources = files( + 'cnxk_bphy_cgx.c', +) diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map new file mode 100644 index 000000000..4a76d1d52 --- /dev/null +++ b/drivers/raw/cnxk_bphy/version.map @@ -0,0 +1,3 @@ +DPDK_21 { + local: *; +}; diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build index c33a7c5f3..b51536f8a 100644 --- a/drivers/raw/meson.build +++ b/drivers/raw/meson.build @@ -6,6 +6,7 @@ if is_windows endif drivers = [ + 'cnxk_bphy', 'dpaa2_cmdif', 'dpaa2_qdma', 'ifpga', diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py index 2fe0c6a6a..be43befd6 100755 --- a/usertools/dpdk-devbind.py +++ b/usertools/dpdk-devbind.py @@ -45,6 +45,8 @@ 'SVendor': None, 'SDevice': None} octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4', 'SVendor': None, 'SDevice': None} +cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059', 'a060' + 'SVendor': None, 'SDevice': None} intel_dlb = {'Class': '0b', 'Vendor': '8086', 'Device': '270b,2710,2714', 'SVendor': None, 'SDevice': None} @@ -69,7 +71,7 @@ mempool_devices = [cavium_fpa, octeontx2_npa] compress_devices = [cavium_zip] regex_devices = [octeontx2_ree] -misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr, +misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr, intel_ntb_skx, intel_ntb_icx, octeontx2_dma] From patchwork Mon May 31 21:41:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93648 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B0A35A0524; Mon, 31 May 2021 23:42:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA55A4111B; Mon, 31 May 2021 23:42:21 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C5FA341103 for ; Mon, 31 May 2021 23:42:19 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeTnO002867 for ; Mon, 31 May 2021 14:42:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=mWoYQST8u4ikk/WSWb6oUSOqYfNCwgcl1vUkOBZtfPQ=; b=iYQSPeho1By6E1+ixL0hW+hkrlneCx/rloTw+uWsJ6SY+h+x3EynXZvozmP2xZEfCVE/ nW4EdjMLKI2LWghw1YNdf2/kNTwjy/j1wKrGthSgmnuLGB/AGUNmqEwLkR7EKox15DjP Cgdv9y/JQrvlMpKNu7tVxyGNQ2Hpw+sgNVolbAsPin0Y0H20OpT0Qb/P/f+O3JJWm44D 6rDcPSIP3ikWd2MeXIvgT19dNr028d8uT3seugARE6pyCLyKb3S4LyNK7UAmp+xgzjq8 m0glyVXUJJfec7gp/2E0C6cFQ3OTzgnEobSjWyWtfyu9mpYdQ77tzm5m+GNxLTOOHWwB OA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja12h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 May 2021 14:42:19 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:17 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:17 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 1E6913F7053; Mon, 31 May 2021 14:42:15 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Date: Mon, 31 May 2021 23:41:24 +0200 Message-ID: <20210531214142.30167-11-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 5yias1FjXPuNCDWcYygwz_TuyYJLJgr4 X-Proofpoint-ORIG-GUID: 5yias1FjXPuNCDWcYygwz_TuyYJLJgr4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 10/28] raw/cnxk_bphy: add support for reading queue configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for reading queue configuration. Single queue represents a logical mac available on rpm/cgx. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index e537888f9..016f9f02c 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -27,7 +27,27 @@ cnxk_bphy_cgx_format_name(char *name, unsigned int len, pci_dev->addr.devid, pci_dev->addr.function); } +static int +cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id, + rte_rawdev_obj_t queue_conf, + size_t queue_conf_size) +{ + unsigned int *conf; + + RTE_SET_USED(dev); + RTE_SET_USED(queue_id); + + if (queue_conf_size != sizeof(*conf)) + return -EINVAL; + + conf = (unsigned int *)queue_conf; + *conf = 1; + + return 0; +} + static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { + .queue_def_conf = cnxk_bphy_cgx_queue_def_conf, }; static void From patchwork Mon May 31 21:41:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93650 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B009A0524; Mon, 31 May 2021 23:43:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 016D841120; Mon, 31 May 2021 23:42:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DCC8940E5A for ; Mon, 31 May 2021 23:42:20 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdlQu025666 for ; Mon, 31 May 2021 14:42:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=acZAWtdwsW40yzblI4/TTA5Lca1mPTK9qQbzpZrMpq0=; b=eoq6uBcBYahFnkMVIrgSkBMd1+hiw2UbRrczgLyEBqVx1PzoQGkUqz8BfnAwdDgI2o6X pmmZsBkwWC19vFwF2AUMvd5ReT0zMPx7qpk3Pq5JZHvZOUvTBEoPcWINOCJuLpSAu6Gh gTaPrEKzYgpUff7MROuWpl/xfmFXqjdFJfT6h/xjSVz2aborA4ZsfqGyByBd9yaKCAtO 6JIU9OpUCBOFnp13GCejUKAJaL4v8SLotrLAM647/VaH/ixovWBwalq2/WOXJgWgw6oO Fn4ioKaNvpIkMucxTXwe53MPlUDYqIR+qML4xjcpEWMkaSlnfGr3uRGQuH//2ElD0DaP NA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj338t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 May 2021 14:42:20 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:18 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 9B2B13F703F; Mon, 31 May 2021 14:42:17 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Date: Mon, 31 May 2021 23:41:25 +0200 Message-ID: <20210531214142.30167-12-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 8TiNRvbaJuEy93bYUaIdyqLdA2RotA05 X-Proofpoint-ORIG-GUID: 8TiNRvbaJuEy93bYUaIdyqLdA2RotA05 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 11/28] raw/cnxk_bphy: add support for reading queue count X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for reading number of available queues i.e number of available logical macs (LMACs). Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index 016f9f02c..da4372642 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -46,8 +46,17 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id, return 0; } +static uint16_t +cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev) +{ + struct cnxk_bphy_cgx *cgx = dev->dev_private; + + return cgx->num_queues; +} + static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { .queue_def_conf = cnxk_bphy_cgx_queue_def_conf, + .queue_count = cnxk_bphy_cgx_queue_count, }; static void From patchwork Mon May 31 21:41:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93651 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D468EA0524; Mon, 31 May 2021 23:43:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 30C9E41137; Mon, 31 May 2021 23:42:25 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7E13E4111E for ; Mon, 31 May 2021 23:42:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdlCu025682 for ; Mon, 31 May 2021 14:42:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Y/xFesmoML7CkN7Pc1l/2tBsxQ98HtFdZ2ivqFeWI0U=; b=S6A5m/iAn1Y4BeVXRln7G63z0a/8uAk6ynHDWsjMdgiBSaxQBEjLzRYeII+4hoh+Lo55 ofHylZncjbGH5rYjs5cK5nz3AY5tOajweDuR+AbQXLRtee3cLDwuE3sMYxtBnobelQL3 aeUoNcq2BNhXN2jbFFYixv3T1i9LIFfgIvAUhrKmiIR1M/hgczOTj23kGm47xCJt8Wx9 FxnWJk7OsPWJug+Gu0gTUXFBLDGDGLzty4UxIygqfEffF1gsO/zu7mZTz7BTxxNXbr0l tLQwnM18j3TymJJhNTqM261MQVZGjLoqp1RFfaQRNU19fQkrLO0zB6/c1Qvdg70HOj5S pQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj338v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 May 2021 14:42:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:20 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 293CA3F7040; Mon, 31 May 2021 14:42:18 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Date: Mon, 31 May 2021 23:41:26 +0200 Message-ID: <20210531214142.30167-13-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ATZNUwY5Fjd4bQAG9D-847u33SFVVuI5 X-Proofpoint-ORIG-GUID: ATZNUwY5Fjd4bQAG9D-847u33SFVVuI5 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 12/28] raw/cnxk_bphy: add support for enqueue operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for enqueueing messages. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++++++++++++++++++++++++++ drivers/raw/cnxk_bphy/meson.build | 1 + drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 104 ++++++++++++++++++++++++ 3 files changed, 217 insertions(+) create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index da4372642..637514406 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -1,12 +1,16 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(C) 2021 Marvell. */ +#include + #include #include #include #include +#include "rte_pmd_bphy.h" + struct cnxk_bphy_cgx_queue { unsigned int lmac; /* queue holds up to one response */ @@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id, return 0; } +static int +cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, + struct rte_rawdev_buf *buf) +{ + struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue]; + struct cnxk_bphy_cgx_msg_set_link_state *link_state; + struct cnxk_bphy_cgx_msg *msg = buf->buf_addr; + struct cnxk_bphy_cgx_msg_link_mode *link_mode; + struct cnxk_bphy_cgx_msg_link_info *link_info; + struct roc_bphy_cgx_link_info rlink_info; + struct roc_bphy_cgx_link_mode rlink_mode; + unsigned int lmac = qp->lmac; + void *rsp = NULL; + int ret; + + switch (msg->type) { + case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO: + memset(&rlink_info, 0, sizeof(rlink_info)); + ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info); + if (ret) + break; + + link_info = rte_zmalloc(NULL, sizeof(*link_info), 0); + if (!link_info) + return -ENOMEM; + + link_info->link_up = rlink_info.link_up; + link_info->full_duplex = rlink_info.full_duplex; + link_info->speed = + (enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed; + link_info->autoneg = rlink_info.an; + link_info->fec = + (enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec; + link_info->mode = + (enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode; + rsp = link_info; + break; + case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE: + ret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE: + ret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE: + ret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE: + ret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE: + link_mode = msg->data; + memset(&rlink_mode, 0, sizeof(rlink_mode)); + rlink_mode.full_duplex = link_mode->full_duplex; + rlink_mode.an = link_mode->autoneg; + rlink_mode.speed = + (enum roc_bphy_cgx_eth_link_speed)link_mode->speed; + rlink_mode.mode = + (enum roc_bphy_cgx_eth_link_mode)link_mode->mode; + ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode); + break; + case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE: + link_state = msg->data; + ret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac, + link_state->state); + break; + case CNXK_BPHY_CGX_MSG_TYPE_START_RXTX: + ret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX: + ret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac); + break; + default: + return -EINVAL; + } + + /* get rid of last response if any */ + if (qp->rsp) { + RTE_LOG(WARNING, PMD, "Previous response got overwritten\n"); + rte_free(qp->rsp); + } + qp->rsp = rsp; + + return ret; +} + +static int +cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev, + struct rte_rawdev_buf **buffers, unsigned int count, + rte_rawdev_obj_t context) +{ + struct cnxk_bphy_cgx *cgx = dev->dev_private; + unsigned int queue = (size_t)context; + int ret; + + if (queue >= cgx->num_queues) + return -EINVAL; + + if (count == 0) + return 0; + + ret = cnxk_bphy_cgx_process_buf(cgx, queue, buffers[0]); + if (ret) + return ret; + + return 1; +} + static uint16_t cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev) { @@ -56,6 +167,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev) static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { .queue_def_conf = cnxk_bphy_cgx_queue_def_conf, + .enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs, .queue_count = cnxk_bphy_cgx_queue_count, }; diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build index a85c9774b..c47ba2449 100644 --- a/drivers/raw/cnxk_bphy/meson.build +++ b/drivers/raw/cnxk_bphy/meson.build @@ -6,3 +6,4 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev'] sources = files( 'cnxk_bphy_cgx.c', ) +headers = files('rte_pmd_bphy.h') diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h new file mode 100644 index 000000000..84176ff22 --- /dev/null +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#ifndef _CNXK_BPHY_H_ +#define _CNXK_BPHY_H_ + +enum cnxk_bphy_cgx_msg_type { + CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO, + CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE, + CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE, + CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE, + CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE, + CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE, + CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE, + CNXK_BPHY_CGX_MSG_TYPE_START_RXTX, + CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX, +}; + +enum cnxk_bphy_cgx_eth_link_speed { + CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE, + CNXK_BPHY_CGX_ETH_LINK_SPEED_10M, + CNXK_BPHY_CGX_ETH_LINK_SPEED_100M, + CNXK_BPHY_CGX_ETH_LINK_SPEED_1G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG, + CNXK_BPHY_CGX_ETH_LINK_SPEED_5G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_10G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_20G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_25G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_40G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_50G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_80G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_100G, + __MAX_CNXK_BPHY_CGX_ETH_LINK_SPEED +}; + +enum cnxk_bphy_cgx_eth_link_fec { + CNXK_BPHY_CGX_ETH_LINK_FEC_NONE, + CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R, + CNXK_BPHY_CGX_ETH_LINK_FEC_RS, + __MAX_CNXK_BPHY_CGX_ETH_LINK_FEC +}; + +enum cnxk_bphy_cgx_eth_link_mode { + CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + __MAX_CNXK_BPHY_CGX_ETH_LINK_MODE +}; + +struct cnxk_bphy_cgx_msg_link_mode { + bool full_duplex; + bool autoneg; + enum cnxk_bphy_cgx_eth_link_speed speed; + enum cnxk_bphy_cgx_eth_link_mode mode; +}; + +struct cnxk_bphy_cgx_msg_link_info { + bool link_up; + bool full_duplex; + enum cnxk_bphy_cgx_eth_link_speed speed; + bool autoneg; + enum cnxk_bphy_cgx_eth_link_fec fec; + enum cnxk_bphy_cgx_eth_link_mode mode; +}; + +struct cnxk_bphy_cgx_msg_set_link_state { + bool state; /* up or down */ +}; + +struct cnxk_bphy_cgx_msg { + enum cnxk_bphy_cgx_msg_type type; + /* + * data depends on message type and whether + * it's a request or a response + */ + void *data; +}; + +#endif /* _CNXK_BPHY_H_ */ From patchwork Mon May 31 21:41:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93652 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36C30A0524; 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Mon, 31 May 2021 14:42:22 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:21 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id A53313F703F; Mon, 31 May 2021 14:42:20 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Date: Mon, 31 May 2021 23:41:27 +0200 Message-ID: <20210531214142.30167-14-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: njXNJezJWvDqJ3aIt0OFesEtSn6EhS62 X-Proofpoint-ORIG-GUID: njXNJezJWvDqJ3aIt0OFesEtSn6EhS62 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 13/28] raw/cnxk_bphy: add support for dequeue operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for dequeueing responses to previously enqueued messages. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index 637514406..a8eafae1b 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -157,6 +157,32 @@ cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev, return 1; } +static int +cnxk_bphy_cgx_dequeue_bufs(struct rte_rawdev *dev, + struct rte_rawdev_buf **buffers, unsigned int count, + rte_rawdev_obj_t context) +{ + struct cnxk_bphy_cgx *cgx = dev->dev_private; + unsigned int queue = (size_t)context; + struct cnxk_bphy_cgx_queue *qp; + + if (queue >= cgx->num_queues) + return -EINVAL; + + if (count == 0) + return 0; + + qp = &cgx->queues[queue]; + if (qp->rsp) { + buffers[0]->buf_addr = qp->rsp; + qp->rsp = NULL; + + return 1; + } + + return 0; +} + static uint16_t cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev) { @@ -168,6 +194,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev) static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { .queue_def_conf = cnxk_bphy_cgx_queue_def_conf, .enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs, + .dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs, .queue_count = cnxk_bphy_cgx_queue_count, }; From patchwork Mon May 31 21:41:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93653 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 00B43A0524; Mon, 31 May 2021 23:43:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B99EA4114A; Mon, 31 May 2021 23:42:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E1018410E8 for ; Mon, 31 May 2021 23:42:25 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeJBH002825 for ; Mon, 31 May 2021 14:42:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=YjGu4J17HN8RysSh+i4WQuh75C4cEL8HTmf5ZEh1IUs=; b=aV2+xJ0+qnxX/YT/uNZWYO32yGrdNNnSlPYf3Eq9t4TPFBBOYLzSm95uBjk52HHoHVVm f/+0MtOZTZci3y9Iz+ce47v+/z8JWevte2NVqfWwpm7vk2g9OPLJGuRzKzezNU2TqK7x dX12rOeN40dRHqQy9Izft1KoqyFvE2MK26tZ/GYcNmpcsTdsQmBuwCDac+ThccwiafwO RORDw4SzeipEQ0l24ovS/ESWycarj5jVTacbMqMxcwy0HQDSjZU5wgiVSkdCyEl7LQX4 aOnXO/IAZCgTaWUtk/BCZMp9IJ/uQy6wqTfj2dfmCOLSsXKa7rnFGMSMCOoo/We3mN5S 3w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja12v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 May 2021 14:42:25 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:23 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 3278E3F7040; Mon, 31 May 2021 14:42:22 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Date: Mon, 31 May 2021 23:41:28 +0200 Message-ID: <20210531214142.30167-15-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: msJ_9t7DyT5DRqrtXn1xUD7OmgcTnagS X-Proofpoint-ORIG-GUID: msJ_9t7DyT5DRqrtXn1xUD7OmgcTnagS X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 14/28] raw/cnxk_bphy: add support for performing selftest X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for performing selftest operation. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 2 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h | 10 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 +++++++++++++++++++++ drivers/raw/cnxk_bphy/meson.build | 1 + 4 files changed, 219 insertions(+) create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index a8eafae1b..3da224414 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -9,6 +9,7 @@ #include +#include "cnxk_bphy_cgx.h" #include "rte_pmd_bphy.h" struct cnxk_bphy_cgx_queue { @@ -196,6 +197,7 @@ static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { .enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs, .dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs, .queue_count = cnxk_bphy_cgx_queue_count, + .dev_selftest = cnxk_bphy_cgx_dev_selftest, }; static void diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h new file mode 100644 index 000000000..cd14a3850 --- /dev/null +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#ifndef _CNXK_BPHY_CGX_H_ +#define _CNXK_BPHY_CGX_H_ + +int cnxk_bphy_cgx_dev_selftest(uint16_t dev_id); + +#endif /* _CNXK_BPHY_CGX_H_ */ diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c new file mode 100644 index 000000000..cb4dd4b22 --- /dev/null +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#include + +#include +#include +#include +#include + +#include "cnxk_bphy_cgx.h" +#include "rte_pmd_bphy.h" + +static int +cnxk_bphy_cgx_enq_msg(uint16_t dev_id, unsigned int queue, void *msg) +{ + struct rte_rawdev_buf *bufs[1]; + struct rte_rawdev_buf buf; + void *q; + int ret; + + q = (void *)(size_t)queue; + buf.buf_addr = msg; + bufs[0] = &buf; + + ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, q); + if (ret < 0) + return ret; + if (ret != 1) + return -EIO; + + return 0; +} + +static int +cnxk_bphy_cgx_deq_msg(uint16_t dev_id, unsigned int queue, void **msg) +{ + struct rte_rawdev_buf *bufs[1]; + struct rte_rawdev_buf buf; + void *q; + int ret; + + q = (void *)(size_t)queue; + bufs[0] = &buf; + + ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, q); + if (ret < 0) + return ret; + if (ret != 1) + return -EIO; + + *msg = buf.buf_addr; + + return 0; +} + +static int +cnxk_bphy_cgx_link_cond(uint16_t dev_id, unsigned int queue, int cond) +{ + int tries = 10, ret; + + do { + struct cnxk_bphy_cgx_msg_link_info *link_info = NULL; + struct cnxk_bphy_cgx_msg msg; + + msg.type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO; + ret = cnxk_bphy_cgx_enq_msg(dev_id, queue, &msg); + if (ret) + return ret; + + ret = cnxk_bphy_cgx_deq_msg(dev_id, queue, (void **)&link_info); + if (ret) + return ret; + + if (link_info->link_up == cond) { + rte_free(link_info); + break; + } + + rte_free(link_info); + rte_delay_ms(500); + } while (--tries); + + if (tries) + return !!cond; + + return -ETIMEDOUT; +} + +int +cnxk_bphy_cgx_dev_selftest(uint16_t dev_id) +{ + unsigned int queues, i; + int ret; + + queues = rte_rawdev_queue_count(dev_id); + if (queues == 0) + return -ENODEV; + + ret = rte_rawdev_start(dev_id); + if (ret) + return ret; + + for (i = 0; i < queues; i++) { + struct cnxk_bphy_cgx_msg_set_link_state link_state; + struct cnxk_bphy_cgx_msg msg; + unsigned int descs; + + ret = rte_rawdev_queue_conf_get(dev_id, i, &descs, + sizeof(descs)); + if (ret) + break; + if (descs != 1) { + RTE_LOG(ERR, PMD, "Wrong number of descs reported\n"); + ret = -ENODEV; + break; + } + + RTE_LOG(INFO, PMD, "Testing queue %d\n", i); + + /* stop rx/tx */ + msg.type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to stop rx/tx\n"); + break; + } + + /* start rx/tx */ + msg.type = CNXK_BPHY_CGX_MSG_TYPE_START_RXTX; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to start rx/tx\n"); + break; + } + + /* set link down */ + link_state.state = false; + msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE; + msg.data = &link_state; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to set link down\n"); + break; + } + + ret = cnxk_bphy_cgx_link_cond(dev_id, i, 0); + if (ret != 0) + RTE_LOG(ERR, PMD, + "Timed out waiting for a link down\n"); + + /* set link up */ + link_state.state = true; + msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE; + msg.data = &link_state; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to set link up\n"); + break; + } + + ret = cnxk_bphy_cgx_link_cond(dev_id, i, 1); + if (ret != 1) + RTE_LOG(ERR, PMD, "Timed out waiting for a link up\n"); + + /* enable internal loopback */ + msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to enable internal lbk\n"); + break; + } + + /* disable internal loopback */ + msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to disable internal lbk\n"); + break; + } + + /* enable ptp */ + msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + /* ptp not available on RPM */ + if (ret < 0 && ret != -ENOTSUP) { + RTE_LOG(ERR, PMD, "Failed to enable ptp\n"); + break; + } + ret = 0; + + /* disable ptp */ + msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE; + ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg); + /* ptp not available on RPM */ + if (ret < 0 && ret != -ENOTSUP) { + RTE_LOG(ERR, PMD, "Failed to disable ptp\n"); + break; + } + ret = 0; + } + + rte_rawdev_stop(dev_id); + + return ret; +} diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build index c47ba2449..2fab7c0ec 100644 --- a/drivers/raw/cnxk_bphy/meson.build +++ b/drivers/raw/cnxk_bphy/meson.build @@ -5,5 +5,6 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev'] sources = files( 'cnxk_bphy_cgx.c', + 'cnxk_bphy_cgx_test.c' ) headers = files('rte_pmd_bphy.h') From patchwork Mon May 31 21:41:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93654 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B97CBA0524; Mon, 31 May 2021 23:43:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0260241121; Mon, 31 May 2021 23:42:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4ED7641121 for ; Mon, 31 May 2021 23:42:30 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLf2vK003782; Mon, 31 May 2021 14:42:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Mon, 31 May 2021 14:42:23 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:29 +0200 Message-ID: <20210531214142.30167-16-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: LY7Y3flDWc4YSRWFWiVbgcYwGf6Tce3V X-Proofpoint-ORIG-GUID: LY7Y3flDWc4YSRWFWiVbgcYwGf6Tce3V X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 15/28] common/cnxk: add support for device init and fini X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for device init and fini. It merely saves baseband phy state container in a globally accessible resource chest. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_api.h | 4 +++ drivers/common/cnxk/roc_bphy.c | 40 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy.h | 17 ++++++++++++ drivers/common/cnxk/roc_idev.c | 1 + drivers/common/cnxk/roc_idev_priv.h | 2 ++ drivers/common/cnxk/version.map | 2 ++ 7 files changed, 67 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy.c create mode 100644 drivers/common/cnxk/roc_bphy.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 59975fd34..946b98f46 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -11,6 +11,7 @@ endif config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( + 'roc_bphy.c', 'roc_bphy_cgx.c', 'roc_dev.c', 'roc_idev.c', diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 256d8c68d..dd0047873 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -50,6 +50,7 @@ #define PCI_DEVID_CNXK_EP_VF 0xB203 #define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6 #define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7 +#define PCI_DEVID_CNXK_BPHY 0xA089 #define PCI_DEVID_CN9K_CGX 0xA059 #define PCI_DEVID_CN10K_RPM 0xA060 @@ -103,4 +104,7 @@ /* Baseband phy cgx */ #include "roc_bphy_cgx.h" +/* Baseband phy */ +#include "roc_bphy.h" + #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_bphy.c b/drivers/common/cnxk/roc_bphy.c new file mode 100644 index 000000000..77606d646 --- /dev/null +++ b/drivers/common/cnxk/roc_bphy.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +int +roc_bphy_dev_init(struct roc_bphy *roc_bphy) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (!idev) + return -ENODEV; + + if (!roc_bphy || !roc_bphy->pci_dev) + return -EINVAL; + + idev->bphy = roc_bphy; + + return 0; +} + +int +roc_bphy_dev_fini(struct roc_bphy *roc_bphy) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (!idev) + return -ENODEV; + + if (!roc_bphy) + return -EINVAL; + + idev->bphy = NULL; + + return 0; +} diff --git a/drivers/common/cnxk/roc_bphy.h b/drivers/common/cnxk/roc_bphy.h new file mode 100644 index 000000000..0579c6c44 --- /dev/null +++ b/drivers/common/cnxk/roc_bphy.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2020 Marvell. + */ + +#ifndef _ROC_BPHY_ +#define _ROC_BPHY_ + +#include "roc_api.h" + +struct roc_bphy { + struct plt_pci_device *pci_dev; +} __plt_cache_aligned; + +int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy); +int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy); + +#endif /* _ROC_BPHY_ */ diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index 63cc04044..4d7b53422 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev) idev->lmt_pf_func = 0; idev->lmt_base_addr = 0; idev->num_lmtlines = 0; + idev->bphy = NULL; __atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE); } diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index ff10a905c..384f667ea 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -7,6 +7,7 @@ /* Intra device related functions */ struct npa_lf; +struct roc_bphy; struct idev_cfg { uint16_t sso_pf_func; uint16_t npa_pf_func; @@ -16,6 +17,7 @@ struct idev_cfg { uint16_t lmt_pf_func; uint16_t num_lmtlines; uint64_t lmt_base_addr; + struct roc_bphy *bphy; }; /* Generic */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 0ad805dba..25083d9d4 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -20,6 +20,8 @@ INTERNAL { roc_bphy_cgx_set_link_state; roc_bphy_cgx_start_rxtx; roc_bphy_cgx_stop_rxtx; + roc_bphy_dev_fini; + roc_bphy_dev_init; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93655 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06C88A0524; Mon, 31 May 2021 23:43:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1CFF8410E5; Mon, 31 May 2021 23:42:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 11BD44114E for ; Mon, 31 May 2021 23:42:32 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdpqv025750; Mon, 31 May 2021 14:42:30 -0700 DKIM-Signature: v=1; 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Mon, 31 May 2021 14:42:28 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 79EB73F7040; Mon, 31 May 2021 14:42:26 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:30 +0200 Message-ID: <20210531214142.30167-17-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: wlrAWHLbLslmBNRyOHocRRtAuTDE7gVw X-Proofpoint-ORIG-GUID: wlrAWHLbLslmBNRyOHocRRtAuTDE7gVw X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 16/28] common/cnxk: add support for baseband phy irq setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for initializing baseband phy irqs. While at it also add support for reverting back to the default state. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_bphy_irq.c | 96 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 27 +++++++++ drivers/common/cnxk/version.map | 2 + 4 files changed, 126 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy_irq.c create mode 100644 drivers/common/cnxk/roc_bphy_irq.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 946b98f46..c0ec54932 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -13,6 +13,7 @@ deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( 'roc_bphy.c', 'roc_bphy_cgx.c', + 'roc_bphy_irq.c', 'roc_dev.c', 'roc_idev.c', 'roc_irq.c', diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c new file mode 100644 index 000000000..c57506542 --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#include +#include +#include + +#include "roc_api.h" +#include "roc_bphy_irq.h" + +#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz" +#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr" + +#define ROC_BPHY_IOC_MAGIC 0xF3 +#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t) +#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t) + +struct roc_bphy_irq_chip * +roc_bphy_intr_init(void) +{ + struct roc_bphy_irq_chip *irq_chip; + uint64_t max_irq, i, avail_irqs; + int fd, ret; + + fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC); + if (fd < 0) { + plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH); + return NULL; + } + + ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq); + if (ret < 0) { + plt_err("Failed to get max irq number via ioctl"); + goto err_ioctl; + } + + ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs); + if (ret < 0) { + plt_err("Failed to get available irqs bitmask via ioctl"); + goto err_ioctl; + } + + irq_chip = plt_zmalloc(sizeof(*irq_chip), 0); + if (irq_chip == NULL) { + plt_err("Failed to alloc irq_chip"); + goto err_alloc_chip; + } + + irq_chip->intfd = fd; + irq_chip->max_irq = max_irq; + irq_chip->avail_irq_bmask = avail_irqs; + irq_chip->irq_vecs = + plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0); + if (irq_chip->irq_vecs == NULL) { + plt_err("Failed to alloc irq_chip irq_vecs"); + goto err_alloc_irq; + } + + irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0); + if (irq_chip->mz_name == NULL) { + plt_err("Failed to alloc irq_chip name"); + goto err_alloc_name; + } + plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME, + strlen(ROC_BPHY_MEMZONE_NAME) + 1); + + for (i = 0; i < irq_chip->max_irq; i++) { + irq_chip->irq_vecs[i].fd = -1; + irq_chip->irq_vecs[i].handler_cpu = -1; + } + + return irq_chip; + +err_alloc_name: + plt_free(irq_chip->irq_vecs); + +err_alloc_irq: + plt_free(irq_chip); + +err_ioctl: +err_alloc_chip: + close(fd); + return NULL; +} + +void +roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip) +{ + if (irq_chip == NULL) + return; + + close(irq_chip->intfd); + plt_free(irq_chip->mz_name); + plt_free(irq_chip->irq_vecs); + plt_free(irq_chip); +} diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h new file mode 100644 index 000000000..b5200786b --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BPHY_IRQ_ +#define _ROC_BPHY_IRQ_ + +struct roc_bphy_irq_vec { + int fd; + int handler_cpu; + void (*handler)(int irq_num, void *isr_data); + void *isr_data; +}; + +struct roc_bphy_irq_chip { + struct roc_bphy_irq_vec *irq_vecs; + uint64_t max_irq; + uint64_t avail_irq_bmask; + int intfd; + int n_handlers; + char *mz_name; +}; + +__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); +__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); + +#endif /* _ROC_BPHY_IRQ_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 25083d9d4..483e52018 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -22,6 +22,8 @@ INTERNAL { roc_bphy_cgx_stop_rxtx; roc_bphy_dev_fini; roc_bphy_dev_init; + roc_bphy_intr_fini; + roc_bphy_intr_init; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93656 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4512A0524; 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Mon, 31 May 2021 14:42:33 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:31 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 3C3743F703F; Mon, 31 May 2021 14:42:29 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:31 +0200 Message-ID: <20210531214142.30167-18-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: tYQtcZw2dDR7_1hcpr9mX6wNAPFMu9_e X-Proofpoint-ORIG-GUID: tYQtcZw2dDR7_1hcpr9mX6wNAPFMu9_e X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 17/28] common/cnxk: add support for checking irq availability X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for checking whether given irq is available. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 9 +++++++++ drivers/common/cnxk/roc_bphy_irq.h | 2 ++ drivers/common/cnxk/version.map | 1 + 3 files changed, 12 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index c57506542..bea2b7f73 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -94,3 +94,12 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip) plt_free(irq_chip->irq_vecs); plt_free(irq_chip); } + +bool +roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num) +{ + if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq) + return false; + + return irq_chip->avail_irq_bmask & BIT(irq_num); +} diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index b5200786b..f481f4456 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -23,5 +23,7 @@ struct roc_bphy_irq_chip { __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); +__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, + int irq_num); #endif /* _ROC_BPHY_IRQ_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 483e52018..427321c41 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -22,6 +22,7 @@ INTERNAL { roc_bphy_cgx_stop_rxtx; roc_bphy_dev_fini; roc_bphy_dev_init; + roc_bphy_intr_available; roc_bphy_intr_fini; roc_bphy_intr_init; roc_clk_freq_get; From patchwork Mon May 31 21:41:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93657 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C7CF8A0524; Mon, 31 May 2021 23:43:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4D84410F8; Mon, 31 May 2021 23:42:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 440484114F for ; Mon, 31 May 2021 23:42:38 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeW7Z002881; Mon, 31 May 2021 14:42:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=DcEcDgI1RqdeloFneLxw6joSkIaRBYEJ3eS6DjtNir8=; b=gsUSe95OBeh411YbhiHT05a2/nH8w06mYYzIQqQzbB3wkronYFTC2qi8qnLmB0hoKvKe jrC+fR4O9zuQJ2IImnThfozqNj+yQjv8MpUGR7MGQgUbrhewZQ3Vv13iOQzkrSDVKfUj ZF0AD+p53aT5ypftGIe0INc9Ho7KcZtetgHva9plzEWCexJYAbSBuZiQhzQeMZR/12Vj 8RiecbC2mB0Tzp7SSivVnYavk4jlfV0Zz/gj6nsnCOqsgMcfLiQnMDkV66lL6c0w3J+/ Q1ptQMCrP21Hz788viUg48WcpvW9fjez+ZKg0B3FiYJU/IAsbxoY+/m6iAjeTuQaZMKn 8A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja13g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:36 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:34 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 01ACD3F7040; Mon, 31 May 2021 14:42:31 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:32 +0200 Message-ID: <20210531214142.30167-19-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: hvc8d8ct1TN2YlPuecapWgz9inn-c3k0 X-Proofpoint-ORIG-GUID: hvc8d8ct1TN2YlPuecapWgz9inn-c3k0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 18/28] common/cnxk: add support for retrieving irq stack X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for retrieving irq stack. If stack does not exist then it gets created. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 62 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 1 + drivers/common/cnxk/version.map | 1 + 3 files changed, 64 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index bea2b7f73..04ad129ac 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -2,12 +2,21 @@ * Copyright(C) 2021 Marvell. */ #include +#include #include +#include #include #include "roc_api.h" #include "roc_bphy_irq.h" +struct roc_bphy_irq_stack { + STAILQ_ENTRY(roc_bphy_irq_stack) entries; + void *sp_buffer; + int cpu; + int inuse; +}; + #define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz" #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr" @@ -15,6 +24,12 @@ #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t) #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t) +static STAILQ_HEAD(slisthead, roc_bphy_irq_stack) + irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks); + +/* Note: it is assumed that as for now there is no multiprocess support */ +static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER; + struct roc_bphy_irq_chip * roc_bphy_intr_init(void) { @@ -95,6 +110,53 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip) plt_free(irq_chip); } +void * +roc_bphy_irq_stack_get(int cpu) +{ +#define ARM_STACK_ALIGNMENT (2 * sizeof(void *)) +#define IRQ_ISR_STACK_SIZE 0x200000 + + struct roc_bphy_irq_stack *curr_stack; + void *retval = NULL; + + if (pthread_mutex_lock(&stacks_mutex)) + return NULL; + + STAILQ_FOREACH(curr_stack, &irq_stacks, entries) { + if (curr_stack->cpu == cpu) { + curr_stack->inuse++; + retval = ((char *)curr_stack->sp_buffer) + + IRQ_ISR_STACK_SIZE; + goto found_stack; + } + } + + curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0); + if (curr_stack == NULL) + goto err_stack; + + curr_stack->sp_buffer = + plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT); + if (curr_stack->sp_buffer == NULL) + goto err_buffer; + + curr_stack->cpu = cpu; + curr_stack->inuse = 0; + STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries); + retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE; + +found_stack: + pthread_mutex_unlock(&stacks_mutex); + return retval; + +err_buffer: + plt_free(curr_stack); + +err_stack: + pthread_mutex_unlock(&stacks_mutex); + return NULL; +} + bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num) { diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index f481f4456..e66b2aa7c 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -23,6 +23,7 @@ struct roc_bphy_irq_chip { __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); +__roc_api void *roc_bphy_irq_stack_get(int cpu); __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 427321c41..542364926 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -25,6 +25,7 @@ INTERNAL { roc_bphy_intr_available; roc_bphy_intr_fini; roc_bphy_intr_init; + roc_bphy_irq_stack_get; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93658 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7E80A0524; Mon, 31 May 2021 23:43:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE3A44113C; Mon, 31 May 2021 23:42:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 02FAF410F7 for ; Mon, 31 May 2021 23:42:40 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeJMf002824; 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Mon, 31 May 2021 14:42:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:37 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id B7BDD3F7041; Mon, 31 May 2021 14:42:34 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:33 +0200 Message-ID: <20210531214142.30167-20-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: hAf5kcara-3-IyIb0aSgWmWj6gOLH6WQ X-Proofpoint-ORIG-GUID: hAf5kcara-3-IyIb0aSgWmWj6gOLH6WQ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 19/28] common/cnxk: add support for removing irq stack X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for removing existing irq stack. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 30 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 1 + drivers/common/cnxk/version.map | 1 + 3 files changed, 32 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index 04ad129ac..a90c055ff 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -110,6 +110,36 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip) plt_free(irq_chip); } +void +roc_bphy_irq_stack_remove(int cpu) +{ + struct roc_bphy_irq_stack *curr_stack; + + if (pthread_mutex_lock(&stacks_mutex)) + return; + + STAILQ_FOREACH(curr_stack, &irq_stacks, entries) { + if (curr_stack->cpu == cpu) + break; + } + + if (curr_stack == NULL) + goto leave; + + if (curr_stack->inuse > 0) + curr_stack->inuse--; + + if (curr_stack->inuse == 0) { + STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack, + entries); + plt_free(curr_stack->sp_buffer); + plt_free(curr_stack); + } + +leave: + pthread_mutex_unlock(&stacks_mutex); +} + void * roc_bphy_irq_stack_get(int cpu) { diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index e66b2aa7c..549a84a7d 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -23,6 +23,7 @@ struct roc_bphy_irq_chip { __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); +__roc_api void roc_bphy_irq_stack_remove(int cpu); __roc_api void *roc_bphy_irq_stack_get(int cpu); __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 542364926..78601fe31 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -26,6 +26,7 @@ INTERNAL { roc_bphy_intr_fini; roc_bphy_intr_init; roc_bphy_irq_stack_get; + roc_bphy_irq_stack_remove; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; From patchwork Mon May 31 21:41:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93659 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 84231A0524; Mon, 31 May 2021 23:43:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E8C79410FF; Mon, 31 May 2021 23:42:45 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 255EC4115B for ; Mon, 31 May 2021 23:42:44 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdks3025644; 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Mon, 31 May 2021 14:42:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:39 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 77D453F703F; Mon, 31 May 2021 14:42:37 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:34 +0200 Message-ID: <20210531214142.30167-21-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: pu2sutN4VnfVRvUsPgOsffx51oRTkyI3 X-Proofpoint-ORIG-GUID: pu2sutN4VnfVRvUsPgOsffx51oRTkyI3 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 20/28] common/cnxk: add support for setting bphy irq handler X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for setting custom baseband phy irq handler. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 121 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 5 ++ drivers/common/cnxk/roc_io.h | 9 ++ drivers/common/cnxk/roc_io_generic.h | 5 ++ drivers/common/cnxk/version.map | 2 + 5 files changed, 142 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index a90c055ff..f988abf51 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -4,12 +4,22 @@ #include #include #include +#include #include #include #include "roc_api.h" #include "roc_bphy_irq.h" +#define roc_cpuset_t cpu_set_t + +struct roc_bphy_irq_usr_data { + uint64_t isr_base; + uint64_t sp; + uint64_t cpu; + uint64_t irq_num; +}; + struct roc_bphy_irq_stack { STAILQ_ENTRY(roc_bphy_irq_stack) entries; void *sp_buffer; @@ -21,6 +31,8 @@ struct roc_bphy_irq_stack { #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr" #define ROC_BPHY_IOC_MAGIC 0xF3 +#define ROC_BPHY_IOC_SET_BPHY_HANDLER \ + _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data) #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t) #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t) @@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu) return NULL; } +void +roc_bphy_intr_handler(unsigned int irq_num) +{ + struct roc_bphy_irq_chip *irq_chip; + const struct plt_memzone *mz; + + mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME); + if (mz == NULL) + return; + + irq_chip = *(struct roc_bphy_irq_chip **)mz->addr; + if (irq_chip == NULL) + return; + + if (irq_chip->irq_vecs[irq_num].handler != NULL) + irq_chip->irq_vecs[irq_num].handler( + (int)irq_num, irq_chip->irq_vecs[irq_num].isr_data); + + roc_atf_ret(); +} + +int +roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, + void (*isr)(int irq_num, void *isr_data), + void *isr_data) +{ + roc_cpuset_t orig_cpuset, intr_cpuset; + struct roc_bphy_irq_usr_data irq_usr; + const struct plt_memzone *mz; + int i, retval, curr_cpu, rc; + char *env; + + mz = plt_memzone_lookup(chip->mz_name); + if (mz == NULL) { + /* what we want is just a pointer to chip, not object itself */ + mz = plt_memzone_reserve_cache_align(chip->mz_name, + sizeof(chip)); + if (mz == NULL) + return -ENOMEM; + } + + if (chip->irq_vecs[irq_num].handler != NULL) + return -EINVAL; + + rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (rc < 0) { + plt_err("Failed to get affinity mask"); + return rc; + } + + for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++) + if (CPU_ISSET(i, &orig_cpuset)) + curr_cpu = i; + if (curr_cpu < 0) + return -ENOENT; + + CPU_ZERO(&intr_cpuset); + CPU_SET(curr_cpu, &intr_cpuset); + retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), + &intr_cpuset); + if (rc < 0) { + plt_err("Failed to set affinity mask"); + return rc; + } + + irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler; + irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu); + irq_usr.cpu = curr_cpu; + if (irq_usr.sp == 0) { + rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (rc < 0) + plt_err("Failed to restore affinity mask"); + return rc; + } + + /* On simulator memory locking operation takes much time. We want + * to skip this when running in such an environment. + */ + env = getenv("BPHY_INTR_MLOCK_DISABLE"); + if (env == NULL) { + rc = mlockall(MCL_CURRENT | MCL_FUTURE); + if (rc < 0) + plt_warn("Failed to lock memory into RAM"); + } + + *((struct roc_bphy_irq_chip **)(mz->addr)) = chip; + irq_usr.irq_num = irq_num; + chip->irq_vecs[irq_num].handler_cpu = curr_cpu; + chip->irq_vecs[irq_num].handler = isr; + chip->irq_vecs[irq_num].isr_data = isr_data; + retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr); + if (retval != 0) { + roc_bphy_irq_stack_remove(curr_cpu); + chip->irq_vecs[irq_num].handler = NULL; + chip->irq_vecs[irq_num].handler_cpu = -1; + } else { + chip->n_handlers++; + } + + rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (rc < 0) + plt_warn("Failed to restore affinity mask"); + + return retval; +} + bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num) { diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index 549a84a7d..7dd23f4ab 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -25,6 +25,11 @@ __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); __roc_api void roc_bphy_irq_stack_remove(int cpu); __roc_api void *roc_bphy_irq_stack_get(int cpu); +__roc_api void roc_bphy_intr_handler(unsigned int irq_num); +__roc_api int +roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, + void (*handler)(int irq_num, void *isr_data), + void *isr_data); __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h index fb3d9c5e5..aee8c7f97 100644 --- a/drivers/common/cnxk/roc_io.h +++ b/drivers/common/cnxk/roc_io.h @@ -184,4 +184,13 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw) dst128[i] = src128[i]; } +static __plt_always_inline void +roc_atf_ret(void) +{ + /* This will allow wfi in EL0 to cause async exception to EL3 + * which will optionally perform necessary actions. + */ + __asm("wfi"); +} + #endif /* _ROC_IO_H_ */ diff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h index c1689b6f8..28cb0963e 100644 --- a/drivers/common/cnxk/roc_io_generic.h +++ b/drivers/common/cnxk/roc_io_generic.h @@ -119,4 +119,9 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw) PLT_SET_USED(segdw); } +static __plt_always_inline void +roc_atf_ret(void) +{ +} + #endif /* _ROC_IO_GENERIC_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 78601fe31..861a97cc0 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -24,7 +24,9 @@ INTERNAL { roc_bphy_dev_init; roc_bphy_intr_available; roc_bphy_intr_fini; + roc_bphy_intr_handler; roc_bphy_intr_init; + roc_bphy_irq_handler_set; roc_bphy_irq_stack_get; roc_bphy_irq_stack_remove; roc_clk_freq_get; From patchwork Mon May 31 21:41:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93660 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B19AA0524; Mon, 31 May 2021 23:44:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0D52E40E32; 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Mon, 31 May 2021 14:42:43 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:42 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 3B3EB3F7040; Mon, 31 May 2021 14:42:40 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:35 +0200 Message-ID: <20210531214142.30167-22-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: TL1e9MprKOF_YYTYeZIr-_3u5j34zPnM X-Proofpoint-ORIG-GUID: TL1e9MprKOF_YYTYeZIr-_3u5j34zPnM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 21/28] common/cnxk: add support for clearing bphy irq handler X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for clearing previously register baseband phy irq handler. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 66 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 2 + drivers/common/cnxk/version.map | 1 + 3 files changed, 69 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index f988abf51..4b87fc801 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -33,6 +33,7 @@ struct roc_bphy_irq_stack { #define ROC_BPHY_IOC_MAGIC 0xF3 #define ROC_BPHY_IOC_SET_BPHY_HANDLER \ _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data) +#define ROC_BPHY_IOC_CLR_BPHY_HANDLER _IO(ROC_BPHY_IOC_MAGIC, 2) #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t) #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t) @@ -316,3 +317,68 @@ roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num) return irq_chip->avail_irq_bmask & BIT(irq_num); } + +int +roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num) +{ + roc_cpuset_t orig_cpuset, intr_cpuset; + const struct plt_memzone *mz; + int retval; + + if (chip == NULL) + return -EINVAL; + if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0) + return -EINVAL; + if (!roc_bphy_intr_available(chip, irq_num)) + return -ENOTSUP; + if (chip->irq_vecs[irq_num].handler == NULL) + return -EINVAL; + mz = plt_memzone_lookup(chip->mz_name); + if (mz == NULL) + return -ENXIO; + + retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) { + plt_warn("Failed to get affinity mask"); + CPU_ZERO(&orig_cpuset); + CPU_SET(0, &orig_cpuset); + } + + CPU_ZERO(&intr_cpuset); + CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset); + retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), + &intr_cpuset); + if (retval < 0) { + plt_warn("Failed to set affinity mask"); + CPU_ZERO(&orig_cpuset); + CPU_SET(0, &orig_cpuset); + } + + retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num); + if (retval == 0) { + roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu); + chip->n_handlers--; + chip->irq_vecs[irq_num].isr_data = NULL; + chip->irq_vecs[irq_num].handler = NULL; + chip->irq_vecs[irq_num].handler_cpu = -1; + if (chip->n_handlers == 0) { + retval = plt_memzone_free(mz); + if (retval < 0) + plt_err("Failed to free memzone: irq %d", + irq_num); + } + } else { + plt_err("Failed to clear bphy interrupt handler"); + } + + retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) { + plt_warn("Failed to restore affinity mask"); + CPU_ZERO(&orig_cpuset); + CPU_SET(0, &orig_cpuset); + } + + return retval; +} diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index 7dd23f4ab..778764f68 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -32,5 +32,7 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, void *isr_data); __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); +__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, + int irq_num); #endif /* _ROC_BPHY_IRQ_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 861a97cc0..941055ba0 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -22,6 +22,7 @@ INTERNAL { roc_bphy_cgx_stop_rxtx; roc_bphy_dev_fini; roc_bphy_dev_init; + roc_bphy_handler_clear; roc_bphy_intr_available; roc_bphy_intr_fini; roc_bphy_intr_handler; From patchwork Mon May 31 21:41:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93662 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 435CDA0524; Mon, 31 May 2021 23:44:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A10B040E78; Mon, 31 May 2021 23:42:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7536140140 for ; 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Mon, 31 May 2021 14:42:46 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:45 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 00A6A3F703F; Mon, 31 May 2021 14:42:42 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:36 +0200 Message-ID: <20210531214142.30167-23-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: CznBxIvhfTSD9oACX7phL_xuL4YmFz0Q X-Proofpoint-ORIG-GUID: CznBxIvhfTSD9oACX7phL_xuL4YmFz0Q X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 22/28] common/cnxk: add support for registering bphy irq X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for registering user supplied baseband phy irq handler. Signed-off-by: Jakib Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 38 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 11 +++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 50 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index 4b87fc801..882066ef3 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -382,3 +382,41 @@ roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num) return retval; } + +int +roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip, + struct roc_bphy_intr *intr) +{ + roc_cpuset_t orig_cpuset, intr_cpuset; + int retval; + int ret; + + if (!roc_bphy_intr_available(irq_chip, intr->irq_num)) + return -ENOTSUP; + + retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) { + plt_err("Failed to get affinity mask"); + return retval; + } + + CPU_ZERO(&intr_cpuset); + CPU_SET(intr->cpu, &intr_cpuset); + retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), + &intr_cpuset); + if (retval < 0) { + plt_err("Failed to set affinity mask"); + return retval; + } + + ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num, + intr->intr_handler, intr->isr_data); + + retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) + plt_warn("Failed to restore affinity mask"); + + return ret; +} diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index 778764f68..19ec5fdc4 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -21,6 +21,15 @@ struct roc_bphy_irq_chip { char *mz_name; }; +struct roc_bphy_intr { + int irq_num; + void (*intr_handler)(int irq_num, void *isr_data); + void *isr_data; + int cpu; + /* stack for this interrupt, not supplied by a user */ + uint8_t *sp; +}; + __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); __roc_api void roc_bphy_irq_stack_remove(int cpu); @@ -34,5 +43,7 @@ __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); __roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num); +__roc_api int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip, + struct roc_bphy_intr *intr); #endif /* _ROC_BPHY_IRQ_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 941055ba0..e24766c05 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -27,6 +27,7 @@ INTERNAL { roc_bphy_intr_fini; roc_bphy_intr_handler; roc_bphy_intr_init; + roc_bphy_intr_register; roc_bphy_irq_handler_set; roc_bphy_irq_stack_get; roc_bphy_irq_stack_remove; From patchwork Mon May 31 21:41:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93661 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 262B9A0524; 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Mon, 31 May 2021 14:42:48 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:47 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id BF5303F7040; Mon, 31 May 2021 14:42:45 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Anatoly Burakov Date: Mon, 31 May 2021 23:41:37 +0200 Message-ID: <20210531214142.30167-24-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: p7aty1NrZjmctyVPN4_m-ih2iJzeYf-Q X-Proofpoint-ORIG-GUID: p7aty1NrZjmctyVPN4_m-ih2iJzeYf-Q X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 23/28] raw/cnxk_bphy: add baseband phy skeleton driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add baseband phy sekelton driver. Baseband phy is a hardware subsystem accelerating 5G/LTE related tasks. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- doc/guides/rawdevs/cnxk_bphy.rst | 14 +++- drivers/raw/cnxk_bphy/cnxk_bphy.c | 113 ++++++++++++++++++++++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 23 ++++++ drivers/raw/cnxk_bphy/meson.build | 1 + usertools/dpdk-devbind.py | 4 +- 5 files changed, 153 insertions(+), 2 deletions(-) create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst index 1b117a0e8..4e7f18c2a 100644 --- a/doc/guides/rawdevs/cnxk_bphy.rst +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -17,6 +17,8 @@ Features The BPHY CGX/RPM implements following features in the rawdev API: - Access to BPHY CGX/RPM via set of predefined messages. +- Access to BPHY memory +- Custom interrupt handlers Device Setup ------------ @@ -33,6 +35,16 @@ To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible responses hence dequeueing is not always necessary. +Other features are realized by custom API calls: + +- BPHY memory ranges are obtained with single ``rte_pmd_bphy_intr_mem_get()``, +- interrupt initialization, registration, unregistration and termination are + done with ``rte_pmd_bphy_intr_init()``, ``rte_pmd_bphy_intr_register()``, + ``rte_pmd_bphy_intr_unregister()`` and ``rte_pmd_bphy_intr_fini()``, + respectively. In order to register an interrupt prior initialization is + required. The same way, the subsystem should be terminated when no longer + used. + Self test --------- @@ -40,7 +52,7 @@ On EAL initialization, BPHY CGX/RPM devices will be probed and populated into the raw devices. The rawdev ID of the device can be obtained using invocation of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where: -- NAME is the desired subsystem: use "BPHY_CGX" for +- NAME is the desired subsystem: use "BPHY" for regular, and "BPHY_CGX" for RFOE module, - x is the device's bus id specified in "bus:device.func" (BDF) format. diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c new file mode 100644 index 000000000..51affed78 --- /dev/null +++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "cnxk_bphy_irq.h" + +static const struct rte_pci_id pci_bphy_map[] = { + {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)}, + { + .vendor_id = 0, + }, +}; + +static const struct rte_rawdev_ops bphy_rawdev_ops = { +}; + +static void +bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev) +{ + snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x", + pci_dev->addr.bus, pci_dev->addr.devid, + pci_dev->addr.function); +} + +static int +bphy_rawdev_probe(struct rte_pci_driver *pci_drv, + struct rte_pci_device *pci_dev) +{ + struct bphy_device *bphy_dev = NULL; + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *bphy_rawdev; + int ret; + + RTE_SET_USED(pci_drv); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + if (!pci_dev->mem_resource[0].addr) { + plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p", + pci_dev->mem_resource[0].addr, + pci_dev->mem_resource[2].addr); + return -ENODEV; + } + + ret = roc_plt_init(); + if (ret) + return ret; + + bphy_rawdev_get_name(name, pci_dev); + bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev), + rte_socket_id()); + if (bphy_rawdev == NULL) { + plt_err("Failed to allocate rawdev"); + return -ENOMEM; + } + + bphy_rawdev->dev_ops = &bphy_rawdev_ops; + bphy_rawdev->device = &pci_dev->device; + bphy_rawdev->driver_name = pci_dev->driver->driver.name; + + bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private; + bphy_dev->mem.res0 = pci_dev->mem_resource[0]; + bphy_dev->mem.res2 = pci_dev->mem_resource[2]; + + return 0; +} + +static int +bphy_rawdev_remove(struct rte_pci_device *pci_dev) +{ + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *rawdev; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + if (pci_dev == NULL) { + plt_err("invalid pci_dev"); + return -EINVAL; + } + + rawdev = rte_rawdev_pmd_get_named_dev(name); + if (rawdev == NULL) { + plt_err("invalid device name (%s)", name); + return -EINVAL; + } + + bphy_rawdev_get_name(name, pci_dev); + + return rte_rawdev_pmd_release(rawdev); +} + +static struct rte_pci_driver cnxk_bphy_rawdev_pmd = { + .id_table = pci_bphy_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = bphy_rawdev_probe, + .remove = bphy_rawdev_remove, +}; + +RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map); +RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, "vfio-pci"); diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h new file mode 100644 index 000000000..77169b1b7 --- /dev/null +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _CNXK_BPHY_IRQ_ +#define _CNXK_BPHY_IRQ_ + +#include +#include + +#include + +struct bphy_mem { + struct rte_mem_resource res0; + struct rte_mem_resource res2; +}; + +struct bphy_device { + struct roc_bphy_irq_chip *irq_chip; + struct bphy_mem mem; +}; + +#endif /* _CNXK_BPHY_IRQ_ */ diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build index 2fab7c0ec..23d46f11d 100644 --- a/drivers/raw/cnxk_bphy/meson.build +++ b/drivers/raw/cnxk_bphy/meson.build @@ -4,6 +4,7 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev'] sources = files( + 'cnxk_bphy.c', 'cnxk_bphy_cgx.c', 'cnxk_bphy_cgx_test.c' ) diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py index be43befd6..ed1bb906f 100755 --- a/usertools/dpdk-devbind.py +++ b/usertools/dpdk-devbind.py @@ -45,6 +45,8 @@ 'SVendor': None, 'SDevice': None} octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4', 'SVendor': None, 'SDevice': None} +cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089' + 'SVendor': None, 'SDevice': None} cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059', 'a060' 'SVendor': None, 'SDevice': None} @@ -71,7 +73,7 @@ mempool_devices = [cavium_fpa, octeontx2_npa] compress_devices = [cavium_zip] regex_devices = [octeontx2_ree] -misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr, +misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr, intel_ntb_skx, intel_ntb_icx, octeontx2_dma] From patchwork Mon May 31 21:41:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93663 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5E8C4A0524; Mon, 31 May 2021 23:44:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E08F440E46; Mon, 31 May 2021 23:42:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2CF1240DFF for ; Mon, 31 May 2021 23:42:53 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdks6025644; Mon, 31 May 2021 14:42:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Mon, 31 May 2021 14:42:47 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:38 +0200 Message-ID: <20210531214142.30167-25-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: cxy5Fy0N30NeF30MjC13xg02u3pmxV_I X-Proofpoint-ORIG-GUID: cxy5Fy0N30NeF30MjC13xg02u3pmxV_I X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 24/28] raw/cnxk_bphy: add support for interrupt init and cleanup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for interrupt initialization and cleanup. Internally interrupt initialization performs low level setup that allows custom interrupt handler registration later on. Interrupt initialization and cleanup are related hence they are in the same patch. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_bphy/cnxk_bphy.c | 13 ++++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 47 +++++++++++++++++++++++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 5 +++ drivers/raw/cnxk_bphy/meson.build | 1 + drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 7 ++++ drivers/raw/cnxk_bphy/version.map | 12 +++++++ 6 files changed, 85 insertions(+) create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c index 51affed78..e3a065b30 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c @@ -13,6 +13,7 @@ #include #include "cnxk_bphy_irq.h" +#include "rte_pmd_bphy.h" static const struct rte_pci_id pci_bphy_map[] = { {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)}, @@ -21,6 +22,18 @@ static const struct rte_pci_id pci_bphy_map[] = { }, }; +int +rte_pmd_bphy_intr_init(uint16_t dev_id) +{ + return cnxk_bphy_intr_init(dev_id); +} + +void +rte_pmd_bphy_intr_fini(uint16_t dev_id) +{ + return cnxk_bphy_intr_fini(dev_id); +} + static const struct rte_rawdev_ops bphy_rawdev_ops = { }; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c new file mode 100644 index 000000000..5d47840d6 --- /dev/null +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ +#include +#include +#include +#include + +#include +#include + +#include "cnxk_bphy_irq.h" + +static struct bphy_device * +cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id) +{ + struct rte_rawdev *rawdev; + + if (!rte_rawdev_pmd_is_valid_dev(dev_id)) + return NULL; + + rawdev = &rte_rawdevs[dev_id]; + + return (struct bphy_device *)rawdev->dev_private; +} + +int +cnxk_bphy_intr_init(uint16_t dev_id) +{ + struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id); + + bphy_dev->irq_chip = roc_bphy_intr_init(); + if (bphy_dev->irq_chip == NULL) + return -ENOMEM; + + return 0; +} + +void +cnxk_bphy_intr_fini(uint16_t dev_id) +{ + struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id); + struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip; + + roc_bphy_intr_fini(irq_chip); + bphy_dev->irq_chip = NULL; +} diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h index 77169b1b7..6e3d77768 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h @@ -20,4 +20,9 @@ struct bphy_device { struct bphy_mem mem; }; +__rte_internal +int cnxk_bphy_intr_init(uint16_t dev_id); +__rte_internal +void cnxk_bphy_intr_fini(uint16_t dev_id); + #endif /* _CNXK_BPHY_IRQ_ */ diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build index 23d46f11d..1c3e6c1b7 100644 --- a/drivers/raw/cnxk_bphy/meson.build +++ b/drivers/raw/cnxk_bphy/meson.build @@ -6,6 +6,7 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev'] sources = files( 'cnxk_bphy.c', 'cnxk_bphy_cgx.c', + 'cnxk_bphy_irq.c', 'cnxk_bphy_cgx_test.c' ) headers = files('rte_pmd_bphy.h') diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 84176ff22..edc146685 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -5,6 +5,8 @@ #ifndef _CNXK_BPHY_H_ #define _CNXK_BPHY_H_ +#include "cnxk_bphy_irq.h" + enum cnxk_bphy_cgx_msg_type { CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO, CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE, @@ -101,4 +103,9 @@ struct cnxk_bphy_cgx_msg { void *data; }; +__rte_experimental +int rte_pmd_bphy_intr_init(uint16_t dev_id); +__rte_experimental +void rte_pmd_bphy_intr_fini(uint16_t dev_id); + #endif /* _CNXK_BPHY_H_ */ diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map index 4a76d1d52..e087cd39b 100644 --- a/drivers/raw/cnxk_bphy/version.map +++ b/drivers/raw/cnxk_bphy/version.map @@ -1,3 +1,15 @@ DPDK_21 { local: *; }; +INTERNAL { + global: + + cnxk_bphy_intr_init; + cnxk_bphy_intr_fini; +}; +EXPERIMENTAL { + global: + + rte_pmd_bphy_intr_fini; + rte_pmd_bphy_intr_init; +}; From patchwork Mon May 31 21:41:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93664 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96082A0524; 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Mon, 31 May 2021 14:42:52 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:50 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 769673F7040; Mon, 31 May 2021 14:42:49 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:39 +0200 Message-ID: <20210531214142.30167-26-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: F0fAbpI56EvzzYbp_cXTrYLMWNJDUtIO X-Proofpoint-ORIG-GUID: F0fAbpI56EvzzYbp_cXTrYLMWNJDUtIO X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 25/28] raw/cnxk_bphy: add support for reading number of irqs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for retrieving maximum number of interrupts. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 12 ++++++++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 2 ++ drivers/raw/cnxk_bphy/version.map | 1 + 3 files changed, 15 insertions(+) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c index 5d47840d6..6a68db8a9 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c @@ -24,6 +24,18 @@ cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id) return (struct bphy_device *)rawdev->dev_private; } +uint64_t +cnxk_bphy_irq_max_get(uint16_t dev_id) +{ + struct roc_bphy_irq_chip *irq_chip; + struct bphy_device *bphy_dev; + + bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id); + irq_chip = bphy_dev->irq_chip; + + return irq_chip->max_irq; +} + int cnxk_bphy_intr_init(uint16_t dev_id) { diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h index 6e3d77768..d18fbd69e 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h @@ -24,5 +24,7 @@ __rte_internal int cnxk_bphy_intr_init(uint16_t dev_id); __rte_internal void cnxk_bphy_intr_fini(uint16_t dev_id); +__rte_internal +uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id); #endif /* _CNXK_BPHY_IRQ_ */ diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map index e087cd39b..6c5e9639a 100644 --- a/drivers/raw/cnxk_bphy/version.map +++ b/drivers/raw/cnxk_bphy/version.map @@ -6,6 +6,7 @@ INTERNAL { cnxk_bphy_intr_init; cnxk_bphy_intr_fini; + cnxk_bphy_irq_max_get; }; EXPERIMENTAL { global: From patchwork Mon May 31 21:41:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93665 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13010A0524; Mon, 31 May 2021 23:44:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2782B4116D; Mon, 31 May 2021 23:42:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D1B914116B for ; Mon, 31 May 2021 23:42:56 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLeJBQ002825; Mon, 31 May 2021 14:42:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=oSGSHFeYgxcuerirOXqESOg43oIRhE2jFL1q9SCsFhI=; b=JjKbMCrH2ZZ5tazoltKBByjNfbDws0B2te8xUH5unNZsrtjFBQHFgymvt5W9ZdGim0jD 80hDnKSkzZeJN/6r160NES0GyO7J4b1J9eHrY9Crb6P3ttXIfDG+i23/VAxsjqWE3vef NYHAcnXiMO3SNSt5VLhI/x+EpWG41WoMRK639MR21GMdOiMSxmYKuFaMuLBq8TUTUr81 YxsQm2+c3k6lpCX+2xXAXEHWyfuxTW7VOb1ibqra6rT9R+REHpiMmZHrywCdkP/vuNMd zfcI9mIorSM8BVhMJs0ywYLumpd0LpUTE4wLKYxC2n0QSFL/oYM2w3Oa+riPbc7Uvinx cw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja14g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 May 2021 14:42:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:52 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 6D8743F703F; Mon, 31 May 2021 14:42:51 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:40 +0200 Message-ID: <20210531214142.30167-27-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Cd0CPT02LtsQJ8s6pD-Rv6Lsedq0-AmE X-Proofpoint-ORIG-GUID: Cd0CPT02LtsQJ8s6pD-Rv6Lsedq0-AmE X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 26/28] raw/cnxk_bphy: add support for retrieving device memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Allow user to retrieve bphy memory resources. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_bphy/cnxk_bphy.c | 6 ++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 8 ++++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 2 ++ drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 4 ++++ drivers/raw/cnxk_bphy/version.map | 2 ++ 5 files changed, 22 insertions(+) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c index e3a065b30..c3aed3018 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c @@ -34,6 +34,12 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id) return cnxk_bphy_intr_fini(dev_id); } +struct cnxk_bphy_mem * +rte_pmd_bphy_intr_mem_get(uint16_t dev_id) +{ + return cnxk_bphy_mem_get(dev_id); +} + static const struct rte_rawdev_ops bphy_rawdev_ops = { }; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c index 6a68db8a9..5a7698f23 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c @@ -57,3 +57,11 @@ cnxk_bphy_intr_fini(uint16_t dev_id) roc_bphy_intr_fini(irq_chip); bphy_dev->irq_chip = NULL; } + +struct bphy_mem * +cnxk_bphy_mem_get(uint16_t dev_id) +{ + struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id); + + return &bphy_dev->mem; +} diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h index d18fbd69e..e52106bc8 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h @@ -26,5 +26,7 @@ __rte_internal void cnxk_bphy_intr_fini(uint16_t dev_id); __rte_internal uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id); +__rte_internal +struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id); #endif /* _CNXK_BPHY_IRQ_ */ diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index edc146685..783b63471 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -103,9 +103,13 @@ struct cnxk_bphy_cgx_msg { void *data; }; +#define cnxk_bphy_mem bphy_mem + __rte_experimental int rte_pmd_bphy_intr_init(uint16_t dev_id); __rte_experimental +struct cnxk_bphy_mem *rte_pmd_bphy_intr_mem_get(uint16_t dev_id); +__rte_experimental void rte_pmd_bphy_intr_fini(uint16_t dev_id); #endif /* _CNXK_BPHY_H_ */ diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map index 6c5e9639a..c7600a863 100644 --- a/drivers/raw/cnxk_bphy/version.map +++ b/drivers/raw/cnxk_bphy/version.map @@ -7,10 +7,12 @@ INTERNAL { cnxk_bphy_intr_init; cnxk_bphy_intr_fini; cnxk_bphy_irq_max_get; + cnxk_bphy_mem_get; }; EXPERIMENTAL { global: rte_pmd_bphy_intr_fini; rte_pmd_bphy_intr_init; + rte_pmd_bphy_intr_mem_get; }; From patchwork Mon May 31 21:41:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93667 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7A9E2A0524; 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Mon, 31 May 2021 14:42:56 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:54 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 5E6723F7040; Mon, 31 May 2021 14:42:53 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Ray Kinsella , Neil Horman Date: Mon, 31 May 2021 23:41:41 +0200 Message-ID: <20210531214142.30167-28-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: tctk09Ysh3tROpiNmcWd_3lQPwKmkqE2 X-Proofpoint-ORIG-GUID: tctk09Ysh3tROpiNmcWd_3lQPwKmkqE2 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 27/28] raw/cnxk_bphy: add support for registering irq handlers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Custom irq handlers may be registered/removed on demand. This adds support for doing that. Since registration and removal are related they are in the same patch. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_bphy/cnxk_bphy.c | 14 ++++++++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 33 +++++++++++++++++++++++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 12 ++++++++-- drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 6 +++++ drivers/raw/cnxk_bphy/version.map | 4 ++++ 5 files changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c index c3aed3018..a6bbdd986 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c @@ -40,6 +40,20 @@ rte_pmd_bphy_intr_mem_get(uint16_t dev_id) return cnxk_bphy_mem_get(dev_id); } +int +rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num, + cnxk_bphy_intr_handler_t handler, void *data, + int cpu) +{ + return cnxk_bphy_intr_register(dev_id, irq_num, handler, data, cpu); +} + +void +rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num) +{ + cnxk_bphy_intr_unregister(dev_id, irq_num); +} + static const struct rte_rawdev_ops bphy_rawdev_ops = { }; diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c index 5a7698f23..45aada7bf 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c @@ -58,6 +58,39 @@ cnxk_bphy_intr_fini(uint16_t dev_id) bphy_dev->irq_chip = NULL; } +int +cnxk_bphy_intr_register(uint16_t dev_id, int irq_num, + cnxk_bphy_intr_handler_t handler, void *data, int cpu) +{ + struct roc_bphy_intr intr = { + .irq_num = irq_num, + .intr_handler = handler, + .isr_data = data, + .cpu = cpu + }; + + struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id); + struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip; + + if (!irq_chip) + return -ENODEV; + if (!handler || !data) + return -EINVAL; + + return roc_bphy_intr_register(irq_chip, &intr); +} + +void +cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num) +{ + struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id); + + if (bphy_dev->irq_chip) + roc_bphy_handler_clear(bphy_dev->irq_chip, irq_num); + else + plt_err("Missing irq chip"); +} + struct bphy_mem * cnxk_bphy_mem_get(uint16_t dev_id) { diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h index e52106bc8..6eeb567ed 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h @@ -10,6 +10,8 @@ #include +typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data); + struct bphy_mem { struct rte_mem_resource res0; struct rte_mem_resource res2; @@ -25,8 +27,14 @@ int cnxk_bphy_intr_init(uint16_t dev_id); __rte_internal void cnxk_bphy_intr_fini(uint16_t dev_id); __rte_internal -uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id); -__rte_internal struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id); +__rte_internal +int cnxk_bphy_intr_register(uint16_t dev_id, int irq_num, + cnxk_bphy_intr_handler_t handler, void *isr_data, + int cpu); +__rte_internal +void cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num); +__rte_internal +uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id); #endif /* _CNXK_BPHY_IRQ_ */ diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index 783b63471..d77bb3b23 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -110,6 +110,12 @@ int rte_pmd_bphy_intr_init(uint16_t dev_id); __rte_experimental struct cnxk_bphy_mem *rte_pmd_bphy_intr_mem_get(uint16_t dev_id); __rte_experimental +int rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num, + cnxk_bphy_intr_handler_t handler, void *isr_data, + int cpu); +__rte_experimental void rte_pmd_bphy_intr_fini(uint16_t dev_id); +__rte_experimental +void rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num); #endif /* _CNXK_BPHY_H_ */ diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map index c7600a863..c4f9b20d0 100644 --- a/drivers/raw/cnxk_bphy/version.map +++ b/drivers/raw/cnxk_bphy/version.map @@ -6,6 +6,8 @@ INTERNAL { cnxk_bphy_intr_init; cnxk_bphy_intr_fini; + cnxk_bphy_intr_register; + cnxk_bphy_intr_unregister; cnxk_bphy_irq_max_get; cnxk_bphy_mem_get; }; @@ -15,4 +17,6 @@ EXPERIMENTAL { rte_pmd_bphy_intr_fini; rte_pmd_bphy_intr_init; rte_pmd_bphy_intr_mem_get; + rte_pmd_bphy_intr_register; + rte_pmd_bphy_intr_unregister; }; From patchwork Mon May 31 21:41:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 93666 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 269B1A0524; Mon, 31 May 2021 23:44:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 84F0341103; Mon, 31 May 2021 23:43:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id DF48941103 for ; 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Mon, 31 May 2021 14:42:58 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:56 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 4A2353F703F; Mon, 31 May 2021 14:42:55 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Date: Mon, 31 May 2021 23:41:42 +0200 Message-ID: <20210531214142.30167-29-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 09aqPZ6kJcR9D4mKM6-NWi-_JMUkFOPB X-Proofpoint-ORIG-GUID: 09aqPZ6kJcR9D4mKM6-NWi-_JMUkFOPB X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 28/28] raw/cnxk_bphy: add support for selftest X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for performing selftest. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/raw/cnxk_bphy/cnxk_bphy.c | 104 ++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c index a6bbdd986..640405242 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c @@ -11,6 +11,7 @@ #include #include +#include #include "cnxk_bphy_irq.h" #include "rte_pmd_bphy.h" @@ -22,6 +23,25 @@ static const struct rte_pci_id pci_bphy_map[] = { }, }; +struct bphy_test { + int irq_num; + cnxk_bphy_intr_handler_t handler; + void *data; + int cpu; + bool handled_intr; + int handled_data; + int test_data; +}; + +static struct bphy_test *test; + +static void +bphy_test_handler_fn(int irq_num, void *isr_data) +{ + test[irq_num].handled_intr = true; + test[irq_num].handled_data = *((int *)isr_data); +} + int rte_pmd_bphy_intr_init(uint16_t dev_id) { @@ -54,7 +74,91 @@ rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num) cnxk_bphy_intr_unregister(dev_id, irq_num); } +static int +bphy_rawdev_selftest(uint16_t dev_id) +{ + unsigned int i; + uint64_t max_irq; + int ret = 0; + + ret = rte_pmd_bphy_intr_init(dev_id); + if (ret) { + plt_err("intr init failed"); + return ret; + } + + max_irq = cnxk_bphy_irq_max_get(dev_id); + + test = rte_zmalloc("BPHY", max_irq * sizeof(*test), 0); + if (test == NULL) { + plt_err("intr alloc failed"); + goto err_alloc; + } + + for (i = 0; i < max_irq; i++) { + test[i].test_data = i; + test[i].irq_num = i; + test[i].handler = bphy_test_handler_fn; + test[i].data = &test[i].test_data; + } + + for (i = 0; i < max_irq; i++) { + ret = rte_pmd_bphy_intr_register(dev_id, test[i].irq_num, + test[i].handler, test[i].data, + 0); + if (ret == -ENOTSUP) { + /* In the test we iterate over all irq numbers + * so if some of them are not supported by given + * platform we treat respective results as valid + * ones. This way they have no impact on overall + * test results. + */ + test[i].handled_intr = true; + test[i].handled_data = test[i].test_data; + ret = 0; + continue; + } + + if (ret) { + plt_err("intr register failed at irq %d", i); + goto err_register; + } + } + + for (i = 0; i < max_irq; i++) + roc_bphy_intr_handler(i); + + for (i = 0; i < max_irq; i++) { + if (!test[i].handled_intr) { + plt_err("intr %u not handled", i); + ret = -1; + break; + } + if (test[i].handled_data != test[i].test_data) { + plt_err("intr %u has wrong handler", i); + ret = -1; + break; + } + } + +err_register: + /* + * In case of registration failure the loop goes over all + * interrupts which is safe due to internal guards in + * rte_pmd_bphy_intr_unregister(). + */ + for (i = 0; i < max_irq; i++) + rte_pmd_bphy_intr_unregister(dev_id, i); + + rte_free(test); +err_alloc: + rte_pmd_bphy_intr_fini(dev_id); + + return ret; +} + static const struct rte_rawdev_ops bphy_rawdev_ops = { + .dev_selftest = bphy_rawdev_selftest, }; static void