From patchwork Sat May 15 17:27:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 93278 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D4840A0548; Sat, 15 May 2021 19:29:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 51F0440042; Sat, 15 May 2021 19:29:22 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id DA67440041 for ; Sat, 15 May 2021 19:29:20 +0200 (CEST) IronPort-SDR: /JBxxJFafNrtSc70UCvpHWs1SV3QOOzSAMdPIqwmjs9Zs6D+xNqGlkfUcAKRrSUi47tWjbvH36 obPa3R6/IEPg== X-IronPort-AV: E=McAfee;i="6200,9189,9985"; a="200344563" X-IronPort-AV: E=Sophos;i="5.82,303,1613462400"; d="scan'208";a="200344563" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2021 10:29:18 -0700 IronPort-SDR: x6Tik1bmciOAu95+JZYoivofmHYcqqgyVkg1LxW7IWITKRTxDs1QQIV/+h23LEUH6yFEkg8o5n upF4Skd2+hFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,303,1613462400"; d="scan'208";a="625776554" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by fmsmga006.fm.intel.com with ESMTP; 15 May 2021 10:29:17 -0700 From: Timothy McDaniel To: Cc: dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net, timothy.mcdaniel@intel.com Date: Sat, 15 May 2021 12:27:34 -0500 Message-Id: <1621099654-25535-1-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 Subject: [dpdk-dev] [PATCH] doc: fix guide for DLB v2.5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" - Remove references to deferred scheduling. That feature applies to DLB v1.0 only. - Replace vdev references with the pci devargs equivalent - Add section for new "vector_opts_enabled" devarg Fixes: 7c6cc633fc7d ("doc: update guide for DLB v2.5") Cc: timothy.mcdaniel@intel.com Signed-off-by: Timothy McDaniel --- doc/guides/eventdevs/dlb2.rst | 54 +++++++++++++++-------------------- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/doc/guides/eventdevs/dlb2.rst b/doc/guides/eventdevs/dlb2.rst index 31de6bc47..bce984ca0 100644 --- a/doc/guides/eventdevs/dlb2.rst +++ b/doc/guides/eventdevs/dlb2.rst @@ -152,19 +152,19 @@ These pools' sizes are controlled by the nb_events_limit field in struct rte_event_dev_config. The load-balanced pool is sized to contain nb_events_limit credits, and the directed pool is sized to contain nb_events_limit/4 credits. The directed pool size can be overridden with the -num_dir_credits vdev argument, like so: +num_dir_credits devargs argument, like so: .. code-block:: console - --vdev=dlb2_event,num_dir_credits= + --allow ea:00.0,num_dir_credits= This can be used if the default allocation is too low or too high for the -specific application needs. The PMD also supports a vdev arg that limits the +specific application needs. The PMD also supports a devarg that limits the max_num_events reported by rte_event_dev_info_get(): .. code-block:: console - --vdev=dlb2_event,max_num_events= + --allow ea:00.0,max_num_events= By default, max_num_events is reported as the total available load-balanced credits. If multiple DLB-based applications are being used, it may be desirable @@ -293,27 +293,6 @@ The PMD does not support the following configuration sequences: This sequence is not supported because the event device must be reconfigured before its ports or queues can be. -Deferred Scheduling -~~~~~~~~~~~~~~~~~~~ - -The DLB PMD's default behavior for managing a CQ is to "pop" the CQ once per -dequeued event before returning from rte_event_dequeue_burst(). This frees the -corresponding entries in the CQ, which enables the DLB to schedule more events -to it. - -To support applications seeking finer-grained scheduling control -- for example -deferring scheduling to get the best possible priority scheduling and -load-balancing -- the PMD supports a deferred scheduling mode. In this mode, -the CQ entry is not popped until the *subsequent* rte_event_dequeue_burst() -call. This mode only applies to load-balanced event ports with dequeue depth of -1. - -To enable deferred scheduling, use the defer_sched vdev argument like so: - - .. code-block:: console - - --vdev=dlb2_event,defer_sched=on - Atomic Inflights Allocation ~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -336,11 +315,11 @@ buffer space (e.g. if not all queues are used, or aren't used for atomic scheduling). The PMD provides a dev arg to override the default per-queue allocation. To -increase a vdev's per-queue atomic-inflight allocation to (for example) 64: +increase per-queue atomic-inflight allocation to (for example) 64: .. code-block:: console - --vdev=dlb2_event,atm_inflights=64 + --allow ea:00.0,atm_inflights=64 QID Depth Threshold ~~~~~~~~~~~~~~~~~~~ @@ -363,9 +342,9 @@ shown below. .. code-block:: console - --vdev=dlb2_event,qid_depth_thresh=all: - --vdev=dlb2_event,qid_depth_thresh=qidA-qidB: - --vdev=dlb2_event,qid_depth_thresh=qid: + --allow ea:00.0,qid_depth_thresh=all: + --allow ea:00.0,qid_depth_thresh=qidA-qidB: + --allow ea:00.0,qid_depth_thresh=qid: Class of service ~~~~~~~~~~~~~~~~ @@ -387,4 +366,17 @@ Class of service can be specified in the devargs, as follows .. code-block:: console - --vdev=dlb2_event,cos=<0..4> + --allow ea:00.0,cos=<0..4> + +Use X86 Vector Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +DLB supports using x86 vector instructions to optimize the data path. + +The default mode of operation is to use scalar instructions, but +the use of vector instructions can be enabled in the devargs, as +follows + + .. code-block:: console + + --allow ea:00.0,vector_opts_enabled=