From patchwork Wed May 12 10:11:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 93197 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3DFCCA0C43; Wed, 12 May 2021 11:16:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B4B134003F; Wed, 12 May 2021 11:16:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0D3294003E for ; Wed, 12 May 2021 11:16:21 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14C9AWXk019809 for ; Wed, 12 May 2021 02:16:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jBx9RF6pIzcqbMatmuDwgLnL1MNii1/F2fuaTyAl+vU=; b=IsBxVsSA3mI6M+V4cYgC2gw/GFYoRlD0XpMtCrHVXOSB2uFlEpE98UFDW+EdEn8QmsjS 8t8MbR/MpL9sGNpMAWtJhHvTNR2ulTxGJQEnkz2JhF9n/gKUO9DLDSJEKCdfhj2Cw089 HawSkbmlex6PbJgqadJZt8h5lMW3perlvbgkME7BymigUvbCq5zLIqagxZb6EqO5KPK2 4iomqHX4iCXb9K4b48iWBXIOYl6J76zjnDCiPIFBvc/7xIJMZJ8AVORXcC6kybBuBicM ftf3XWQfLN2bfwe3hqwWO/qkRtYM30RTtTs4tVHnewNQiRpSbE7SXU8AvftHqVD/CUDs jA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38fw8yb55j-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 12 May 2021 02:16:20 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 May 2021 02:16:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 May 2021 02:16:19 -0700 Received: from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 6D7045B693F; Wed, 12 May 2021 02:16:17 -0700 (PDT) From: Tejasree Kondoj To: Jerin Jacob CC: Tejasree Kondoj , Nithin Dabilpuram , Anoob Joseph , Date: Wed, 12 May 2021 15:41:43 +0530 Message-ID: <20210512101143.7937-1-ktejasree@marvell.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Proofpoint-GUID: _yDcUzTCsXBEHrH-2BwTQYaUcHR5pFtU X-Proofpoint-ORIG-GUID: _yDcUzTCsXBEHrH-2BwTQYaUcHR5pFtU X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-12_04:2021-05-12, 2021-05-12 signatures=0 Subject: [dpdk-dev] [PATCH] net/octeontx2: support Inline IPsec without MBUF_FAST_FREE offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding support for Inline IPsec without DEV_TX_OFFLOAD_MBUF_FAST_FREE. Signed-off-by: Tejasree Kondoj Reviewed-by: Jerin Jacob --- drivers/net/octeontx2/otx2_ethdev_sec_tx.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/octeontx2/otx2_ethdev_sec_tx.h b/drivers/net/octeontx2/otx2_ethdev_sec_tx.h index c8eae3d628..623a2a841e 100644 --- a/drivers/net/octeontx2/otx2_ethdev_sec_tx.h +++ b/drivers/net/octeontx2/otx2_ethdev_sec_tx.h @@ -59,8 +59,7 @@ otx2_sec_event_tx(uint64_t base, struct rte_event *ev, struct rte_mbuf *m, sa = &sess->out_sa; RTE_ASSERT(sess->cpt_lmtline != NULL); - RTE_ASSERT(!(offload_flags & (NIX_TX_OFFLOAD_MBUF_NOFF_F | - NIX_TX_OFFLOAD_VLAN_QINQ_F))); + RTE_ASSERT(!(offload_flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)); dlen = rte_pktmbuf_pkt_len(m) + sizeof(*hdr) - RTE_ETHER_HDR_LEN; rlen = otx2_ipsec_fp_out_rlen_get(sess, dlen - sizeof(*hdr)); @@ -135,6 +134,8 @@ otx2_sec_event_tx(uint64_t base, struct rte_event *ev, struct rte_mbuf *m, sd->nix_hdr.w0.sizem1 = 1; sd->nix_hdr.w0.total = rte_pktmbuf_data_len(m); sd->nix_hdr.w0.aura = npa_lf_aura_handle_to_aura(m->pool->pool_id); + if (offload_flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) + sd->nix_hdr.w0.df = otx2_nix_prefree_seg(m); sd->nix_sg.u = 0; sd->nix_sg.subdc = NIX_SUBDC_SG;