From patchwork Mon May 10 15:03:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ferruh Yigit X-Patchwork-Id: 93104 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B85ABA0A0E; Mon, 10 May 2021 17:03:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 382CE4014E; Mon, 10 May 2021 17:03:50 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id CC4FF4003E; Mon, 10 May 2021 17:03:47 +0200 (CEST) IronPort-SDR: zZDyFOwYl4oBMFtYpwyuqAEzDkpi0FZKsYVCyZQfnKKwtlyqHiNRsvekBsmRJKRDS9XhUmlDkV DhiJhkL5R5fQ== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="186659434" X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="186659434" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 08:03:22 -0700 IronPort-SDR: 8QcT5K09V0abJx5iT7MlTMUKZCLJ8RB0BJOBCO/yCyHmwvZvQfESS7ocyFAH1h5AhZ1PcqcZPZ BGk894K8/Slg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="541247374" Received: from silpixa00399752.ir.intel.com (HELO silpixa00399752.ger.corp.intel.com) ([10.237.222.27]) by orsmga004.jf.intel.com with ESMTP; 10 May 2021 08:03:21 -0700 From: Ferruh Yigit To: Rasesh Mody , Shahed Shaikh Cc: Ferruh Yigit , dev@dpdk.org, stable@dpdk.org, Kevin Traynor , Ajit Khaparde Date: Mon, 10 May 2021 16:03:16 +0100 Message-Id: <20210510150319.1496105-1-ferruh.yigit@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/4] net/bnx2x: fix build with gcc11 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reproduced with '--buildtype=debugoptimized' config, compiler version: gcc (GCC) 12.0.0 20210509 (experimental) Build error: In file included from ../drivers/net/bnx2x/bnx2x_rxtx.c:8: ../drivers/net/bnx2x/bnx2x_rxtx.c: In function ‘bnx2x_upd_rx_prod_fast’: ../drivers/net/bnx2x/bnx2x.h:1528:35: warning: ‘rx_prods’ is used uninitialized [-Wuninitialized] #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/net/bnx2x/bnx2x.h:1531:33: note: in expansion of macro ‘REG_WR32’ 1531 | #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) | ^~~~~~~~ ../drivers/net/bnx2x/bnx2x_rxtx.c:331:9: note: in expansion of macro ‘REG_WR’ 331 | REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]); | ^~~~~~ ../drivers/net/bnx2x/bnx2x_rxtx.c:324:40: note: ‘rx_prods’ declared here 324 | struct ustorm_eth_rx_producers rx_prods = { 0 }; | ^~~~~~~~ REG_WR32 requires 'uint32_t', use union instead of cast to 'uint32_t'. Fixes: 38dff79ba736 ("net/bnx2x: update HSI") Cc: stable@dpdk.org Signed-off-by: Ferruh Yigit --- Cc: rmody@marvell.com Cc: Kevin Traynor Cc: Ajit Khaparde --- drivers/net/bnx2x/bnx2x_rxtx.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c index 57e2ce504587..fdd6eeed8c1a 100644 --- a/drivers/net/bnx2x/bnx2x_rxtx.c +++ b/drivers/net/bnx2x/bnx2x_rxtx.c @@ -321,14 +321,15 @@ static inline void bnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint16_t rx_bd_prod, uint16_t rx_cq_prod) { - struct ustorm_eth_rx_producers rx_prods = { 0 }; - uint32_t *val = NULL; + union { + struct ustorm_eth_rx_producers rx_prods; + uint32_t val; + } val = { 0 }; - rx_prods.bd_prod = rx_bd_prod; - rx_prods.cqe_prod = rx_cq_prod; + val.rx_prods.bd_prod = rx_bd_prod; + val.rx_prods.cqe_prod = rx_cq_prod; - val = (uint32_t *)&rx_prods; - REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]); + REG_WR(sc, fp->ustorm_rx_prods_offset, val.val); } static uint16_t From patchwork Mon May 10 15:03:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ferruh Yigit X-Patchwork-Id: 93105 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74A3AA0A0E; Mon, 10 May 2021 17:03:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4D0BC410FF; Mon, 10 May 2021 17:03:52 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 057B140140; Mon, 10 May 2021 17:03:48 +0200 (CEST) IronPort-SDR: 3Rp+qGDmb7fGBACGByxl229iDR68E5QGxDOQvEFB8FS3FaWEP9y0atpy+oil4tp2JIwWE2S2OZ SklZIEK+NxQw== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="186659449" X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="186659449" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 08:03:26 -0700 IronPort-SDR: iEHT2eCQ0JjKLgYnLwqBZW05TO1WprcJMqRkBlRbiAYprosEmhTgDYo5YYif83RzoSjZACV2U2 3Sp90Q3uNB8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="541247393" Received: from silpixa00399752.ir.intel.com (HELO silpixa00399752.ger.corp.intel.com) ([10.237.222.27]) by orsmga004.jf.intel.com with ESMTP; 10 May 2021 08:03:24 -0700 From: Ferruh Yigit To: Rasesh Mody , Shahed Shaikh Cc: Ferruh Yigit , dev@dpdk.org, stable@dpdk.org, Kevin Traynor , Ajit Khaparde Date: Mon, 10 May 2021 16:03:17 +0100 Message-Id: <20210510150319.1496105-2-ferruh.yigit@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510150319.1496105-1-ferruh.yigit@intel.com> References: <20210510150319.1496105-1-ferruh.yigit@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/4] net/bnx2x: fix build with gcc11 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reproduced with '--buildtype=debugoptimized' config, compiler version: gcc (GCC) 12.0.0 20210509 (experimental) Build error: In file included from ../drivers/net/bnx2x/bnx2x.c:16: ../drivers/net/bnx2x/bnx2x.c: In function ‘bnx2x_hc_ack_sb’: ../drivers/net/bnx2x/bnx2x.h:1528:35: warning: ‘igu_ack’ is used uninitialized [-Wuninitialized] #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/net/bnx2x/bnx2x.h:1531:33: note: in expansion of macro ‘REG_WR32’ 1531 | #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) | ^~~~~~~~ ../drivers/net/bnx2x/bnx2x.h:1916:9: note: in expansion of macro ‘REG_WR’ 1916 | REG_WR(sc, hc_addr, *val); | ^~~~~~ ../drivers/net/bnx2x/bnx2x.h:1905:33: note: ‘igu_ack’ declared here 1905 | struct igu_ack_register igu_ack; | ^~~~~~~ REG_WR32 requires 'uint32_t', use union instead of cast to 'uint32_t'. Fixes: 38dff79ba736 ("net/bnx2x: update HSI") Cc: stable@dpdk.org Signed-off-by: Ferruh Yigit --- Cc: rmody@marvell.com Cc: Kevin Traynor Cc: Ajit Khaparde --- drivers/net/bnx2x/bnx2x.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index e13ab1557418..80d19cbfd665 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -1902,18 +1902,19 @@ bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm, { uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 + COMMAND_REG_INT_ACK); - struct igu_ack_register igu_ack; - uint32_t *val = NULL; + union { + struct igu_ack_register igu_ack; + uint32_t val; + } val; - igu_ack.status_block_index = index; - igu_ack.sb_id_and_flags = + val.igu_ack.status_block_index = index; + val.igu_ack.sb_id_and_flags = ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); - val = (uint32_t *)&igu_ack; - REG_WR(sc, hc_addr, *val); + REG_WR(sc, hc_addr, val.val); /* Make sure that ACK is written */ mb(); From patchwork Mon May 10 15:03:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ferruh Yigit X-Patchwork-Id: 93106 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85780A0A0E; Mon, 10 May 2021 17:04:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9C18C4110B; Mon, 10 May 2021 17:03:53 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id EFFBC4003E; Mon, 10 May 2021 17:03:48 +0200 (CEST) IronPort-SDR: LR5SXYuHBizjmwEPYihKnCuxHhn8DusqyLgXsAlqjOa88iTpu4Jfs3NQuwcTqeYM+DukcuVQrG l+y2aTKMjowQ== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="186659465" X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="186659465" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 08:03:30 -0700 IronPort-SDR: E/O8uH9ySc7icXERFtO6/1oNp0x35b9ex2XiyJq+GN9RHbiz64EuNXLeFcUcRgVnarN8Nv9Qha fPqBGdpLSiOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="541247416" Received: from silpixa00399752.ir.intel.com (HELO silpixa00399752.ger.corp.intel.com) ([10.237.222.27]) by orsmga004.jf.intel.com with ESMTP; 10 May 2021 08:03:27 -0700 From: Ferruh Yigit To: Qiming Yang , Qi Zhang , Paul M Stillwell Jr , Wenzhuo Lu , Leyi Rong , Shivanshu Shukla Cc: Ferruh Yigit , dev@dpdk.org, stable@dpdk.org, Kevin Traynor , Ajit Khaparde Date: Mon, 10 May 2021 16:03:18 +0100 Message-Id: <20210510150319.1496105-3-ferruh.yigit@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510150319.1496105-1-ferruh.yigit@intel.com> References: <20210510150319.1496105-1-ferruh.yigit@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/4] net/ice/base: fix build with gcc11 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reproduced with '--buildtype=debugoptimized' config, compiler version: gcc (GCC) 12.0.0 20210509 (experimental) There are multiple build errors, like: ../drivers/net/ice/base/ice_switch.c: In function ‘ice_add_marker_act’: ../drivers/net/ice/base/ice_switch.c:3727:15: warning: array subscript ‘struct ice_aqc_sw_rules_elem[0]’ is partly outside array bounds of ‘unsigned char[52]’ [-Warray-bounds] 3727 | lg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT); | ^~ In file included from ../drivers/net/ice/base/ice_type.h:52, from ../drivers/net/ice/base/ice_common.h:8, from ../drivers/net/ice/base/ice_switch.h:8, from ../drivers/net/ice/base/ice_switch.c:5: ../drivers/net/ice/base/ice_osdep.h:209:29: note: referencing an object of size 52 allocated by ‘rte_zmalloc’ 209 | #define ice_malloc(h, s) rte_zmalloc(NULL, s, 0) | ^~~~~~~~~~~~~~~~~~~~~~~ ../drivers/net/ice/base/ice_switch.c:3720:50: note: in expansion of macro ‘ice_malloc’ lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size); These errors are mainly because allocated memory is cast to "struct ice_aqc_sw_rules_elem *" but allocated size is less than the size of "struct ice_aqc_sw_rules_elem". "struct ice_aqc_sw_rules_elem" has multiple other structs has unions, based on which one is used allocated memory being less than the size of "struct ice_aqc_sw_rules_elem" is logically correct but compiler is complaining about it. As a solution making sure allocated memory size is at least size of "struct ice_aqc_sw_rules_elem". The function to use the struct is 'ice_aq_sw_rules()', and it already has parameter for size of the rule, allocating more than needed shouldn't cause any problem. Fixes: c7dd15931183 ("net/ice/base: add virtual switch code") Fixes: 02acdce2f553 ("net/ice/base: add MAC filter with marker and counter") Fixes: f89aa3affa9e ("net/ice/base: support removing advanced rule") Cc: stable@dpdk.org Signed-off-by: Ferruh Yigit --- Cc: paul.m.stillwell.jr@intel.com Cc: qi.z.zhang@intel.com Cc: leyi.rong@intel.com Cc: Kevin Traynor Cc: Ajit Khaparde --- drivers/net/ice/base/ice_switch.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 229b355c62c5..fa2a623aff8c 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -3704,6 +3704,7 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, enum ice_status status; u16 lg_act_size; u16 rules_size; + u16 max_size; u32 act; u16 id; @@ -3717,7 +3718,9 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, */ lg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_lg_acts); rules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE; - lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size); + max_size = sizeof(struct ice_aqc_sw_rules_elem) * 2; + lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, + rules_size < max_size ? max_size : rules_size); if (!lg_act) return ICE_ERR_NO_MEMORY; @@ -3803,6 +3806,7 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, u16 lg_act_size; u16 rules_size; u16 f_rule_id; + u16 max_size; u32 act; u16 id; @@ -3816,7 +3820,9 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, */ lg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_acts); rules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE; - lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size); + max_size = sizeof(struct ice_aqc_sw_rules_elem) * 2; + lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, + rules_size < max_size ? max_size : rules_size); if (!lg_act) return ICE_ERR_NO_MEMORY; @@ -4009,12 +4015,14 @@ static enum ice_status ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list, struct ice_fltr_list_entry *f_entry) { + u16 max_size = sizeof(struct ice_aqc_sw_rules_elem); struct ice_fltr_mgmt_list_entry *fm_entry; struct ice_aqc_sw_rules_elem *s_rule; enum ice_status status; s_rule = (struct ice_aqc_sw_rules_elem *) - ice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE); + ice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE < max_size ? + max_size : ICE_SW_RULE_RX_TX_ETH_HDR_SIZE); if (!s_rule) return ICE_ERR_NO_MEMORY; fm_entry = (struct ice_fltr_mgmt_list_entry *) @@ -4068,11 +4076,13 @@ ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list, static enum ice_status ice_update_pkt_fwd_rule(struct ice_hw *hw, struct ice_fltr_info *f_info) { + u16 max_size = sizeof(struct ice_aqc_sw_rules_elem); struct ice_aqc_sw_rules_elem *s_rule; enum ice_status status; s_rule = (struct ice_aqc_sw_rules_elem *) - ice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE); + ice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE < max_size ? + max_size : ICE_SW_RULE_RX_TX_ETH_HDR_SIZE); if (!s_rule) return ICE_ERR_NO_MEMORY; @@ -4545,11 +4555,13 @@ ice_remove_rule_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list, } if (remove_rule) { + u16 max_size = sizeof(struct ice_aqc_sw_rules_elem); /* Remove the lookup rule */ struct ice_aqc_sw_rules_elem *s_rule; s_rule = (struct ice_aqc_sw_rules_elem *) - ice_malloc(hw, ICE_SW_RULE_RX_TX_NO_HDR_SIZE); + ice_malloc(hw, ICE_SW_RULE_RX_TX_NO_HDR_SIZE < max_size + ? max_size : ICE_SW_RULE_RX_TX_NO_HDR_SIZE); if (!s_rule) { status = ICE_ERR_NO_MEMORY; goto exit; @@ -5264,6 +5276,7 @@ enum ice_status ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set, u8 direction) { + u16 max_size = sizeof(struct ice_aqc_sw_rules_elem); struct ice_aqc_sw_rules_elem *s_rule; struct ice_fltr_info f_info; struct ice_hw *hw = pi->hw; @@ -5279,7 +5292,8 @@ ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set, s_rule_size = set ? ICE_SW_RULE_RX_TX_ETH_HDR_SIZE : ICE_SW_RULE_RX_TX_NO_HDR_SIZE; - s_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size); + s_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size < + max_size ? max_size : s_rule_size); if (!s_rule) return ICE_ERR_NO_MEMORY; @@ -8998,12 +9012,14 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, } ice_release_lock(rule_lock); if (remove_rule) { + u16 max_size = sizeof(struct ice_aqc_sw_rules_elem); struct ice_aqc_sw_rules_elem *s_rule; u16 rule_buf_sz; rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE; s_rule = (struct ice_aqc_sw_rules_elem *) - ice_malloc(hw, rule_buf_sz); + ice_malloc(hw, rule_buf_sz < max_size ? max_size : + rule_buf_sz); if (!s_rule) return ICE_ERR_NO_MEMORY; s_rule->pdata.lkup_tx_rx.act = 0; From patchwork Mon May 10 15:03:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ferruh Yigit X-Patchwork-Id: 93107 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 311FCA0A0E; Mon, 10 May 2021 17:04:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E6BD241119; Mon, 10 May 2021 17:03:54 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 59A1E410FE; Mon, 10 May 2021 17:03:51 +0200 (CEST) IronPort-SDR: J3dDPnNu6qj3teVT8SP8akDfxMD85E7Hj7jAQKlaqscbbhOXTQ0pQ12sP2CEaB0cZPTVusoNAc Eg3KZPU4jiaA== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="186659471" X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="186659471" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2021 08:03:32 -0700 IronPort-SDR: j68QzCmfnYVxKtz5fb0/yjMkmdtGilTgtSTxfrvCrmhbZNV8gpFXtEI5Y5xVmTGMtWdQgH229X KZ0GJq09NsnQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,287,1613462400"; d="scan'208";a="541247425" Received: from silpixa00399752.ir.intel.com (HELO silpixa00399752.ger.corp.intel.com) ([10.237.222.27]) by orsmga004.jf.intel.com with ESMTP; 10 May 2021 08:03:31 -0700 From: Ferruh Yigit To: Keith Wiles , Pascal Mazon , Olga Shern Cc: Ferruh Yigit , dev@dpdk.org, stable@dpdk.org Date: Mon, 10 May 2021 16:03:19 +0100 Message-Id: <20210510150319.1496105-4-ferruh.yigit@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510150319.1496105-1-ferruh.yigit@intel.com> References: <20210510150319.1496105-1-ferruh.yigit@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/4] net/tap: fix build with gcc11 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reproduced with '--buildtype=debugoptimized' config, compiler version: gcc (GCC) 12.0.0 20210509 (experimental) There are multiple build errors, like: In file included from ../drivers/net/tap/tap_flow.c:13: In function ‘rte_jhash_2hashes’, inlined from ‘rte_jhash’ at ../lib/hash/rte_jhash.h:284:2, inlined from ‘tap_flow_set_handle’ at ../drivers/net/tap/tap_flow.c:1306:12, inlined from ‘rss_enable’ at ../drivers/net/tap/tap_flow.c:1909:3, inlined from ‘priv_flow_process’ at ../drivers/net/tap/tap_flow.c:1228:11: ../lib/hash/rte_jhash.h:238:9: warning: ‘flow’ may be used uninitialized [-Wmaybe-uninitialized] 238 | __rte_jhash_2hashes(key, length, pc, pb, 1); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/net/tap/tap_flow.c: In function ‘priv_flow_process’: ../lib/hash/rte_jhash.h:81:1: note: by argument 1 of type ‘const void *’ to ‘__rte_jhash_2hashes.constprop’ declared here 81 | __rte_jhash_2hashes(const void *key, uint32_t length, uint32_t *pc, | ^~~~~~~~~~~~~~~~~~~ ../drivers/net/tap/tap_flow.c:1028:1: note: ‘flow’ declared here 1028 | priv_flow_process(struct pmd_internals *pmd, | ^~~~~~~~~~~~~~~~~ Fix strict aliasing rule by using union. Fixes: de96fe68ae95 ("net/tap: add basic flow API patterns and actions") Cc: stable@dpdk.org Signed-off-by: Ferruh Yigit Acked-by: Kevin Traynor --- Cc: pascal.mazon@6wind.com --- drivers/net/tap/tap_flow.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/tap/tap_flow.c b/drivers/net/tap/tap_flow.c index 1ee6fb30ab2d..c4f60ce98e5e 100644 --- a/drivers/net/tap/tap_flow.c +++ b/drivers/net/tap/tap_flow.c @@ -1300,10 +1300,16 @@ tap_flow_validate(struct rte_eth_dev *dev, static void tap_flow_set_handle(struct rte_flow *flow) { + union { + struct rte_flow *flow; + const void *key; + } tmp; uint32_t handle = 0; + tmp.flow = flow; + if (sizeof(flow) > 4) - handle = rte_jhash(&flow, sizeof(flow), 1); + handle = rte_jhash(tmp.key, sizeof(flow), 1); else handle = (uintptr_t)flow; /* must be at least 1 to avoid letting the kernel choose one for us */