From patchwork Tue May 4 00:26:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92679 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1AE6EA0562; Tue, 4 May 2021 02:28:07 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F1356410F3; Tue, 4 May 2021 02:28:04 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id CFCB2410F0 for ; Tue, 4 May 2021 02:28:03 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OtxC025090 for ; Mon, 3 May 2021 17:28:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=pgMLxdVVUSrIEq8DC+WQqhdXBIDshtvmJQw+b1IN/dw=; b=BNqKh7TcfOTvdxPER4jYT/QrQ2qM4JomLEMeOXpzGvERdOWsptOn+m7+grs2Hbgjgoqu YPyzAPcWvcKhQJn+jolP3iQQLIbWUjlBetuYhtYbpgd6QWQRbH893frMilz82j26XL59 VKhgY7iIQrdJ+DhPmyo/OS5mxKuM0i2abDlov/Yo9gYWvyKP/xqFCTBeyH57nkQYQcKM lR5hiMqa4BjQiycFen0sxbx8pHboIlZzIY1+hA8esxWcHjOhQU6wqvip5f5gJacEvS8W QWWEwzREBw8GyHTCb5psc+SDm89yxsV6ger1oQLjmgtNwIrsajlIz6My3M1X9tw+2BOe 7w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnmj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:02 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:00 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id EECE33F703F; Mon, 3 May 2021 17:27:58 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Date: Tue, 4 May 2021 05:56:51 +0530 Message-ID: <20210504002726.525-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Nf_mEImA866IChNhDhUX9YqncDbb1KZn X-Proofpoint-ORIG-GUID: Nf_mEImA866IChNhDhUX9YqncDbb1KZn X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 01/35] common/cnxk: rename deprecated constant X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh The PCI_ANY_ID constant is deprecated and renamed as RTE_PCI_ANY_ID. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_platform.h | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 97600e56f..29ab71240 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -165,22 +165,18 @@ extern int cnxk_logtype_tm; #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) #ifdef __cplusplus -#define CNXK_PCI_ID(subsystem_dev, dev) \ - { \ - RTE_CLASS_ANY_ID, \ - PCI_VENDOR_ID_CAVIUM, \ - (dev), \ - PCI_ANY_ID, \ - (subsystem_dev), \ +#define CNXK_PCI_ID(subsystem_dev, dev) \ + { \ + RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ + (subsystem_dev), \ } #else -#define CNXK_PCI_ID(subsystem_dev, dev) \ - { \ - .class_id = RTE_CLASS_ANY_ID, \ - .vendor_id = PCI_VENDOR_ID_CAVIUM, \ - .device_id = (dev), \ - .subsystem_vendor_id = PCI_ANY_ID, \ - .subsystem_device_id = (subsystem_dev), \ +#define CNXK_PCI_ID(subsystem_dev, dev) \ + { \ + .class_id = RTE_CLASS_ANY_ID, \ + .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ + .subsystem_vendor_id = RTE_PCI_ANY_ID, \ + .subsystem_device_id = (subsystem_dev), \ } #endif From patchwork Tue May 4 00:26:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92680 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6283BA0562; Tue, 4 May 2021 02:28:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 319F6410FB; Tue, 4 May 2021 02:28:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DDFF8410FA for ; Tue, 4 May 2021 02:28:06 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OuhR025154 for ; Mon, 3 May 2021 17:28:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=nJplr7JWkN5D6gTcwW5CW5vjCbqP90uzAxRrSJIA+z4=; b=KjqycTtoQ4Rw7VVZ1dRekBzWCHQ34pIJqAP5MThe6iktNKgRDmnb7jzVVA73NkAW6mDH 5m3ox8VnmkCDaHO/vNTowcMsC4uJObGWY+Z9sknWVtJBxwmms27k+FXpJtRtRV6Os4Ht 3SWMxkDzWTEQMI9/ia8r1xH4vxsdFpD1zgseTtKvHG54eQPQKleTZU+I11A6wCsRvpe/ LY1ffUP/O3jxvXUYm4FgbkJTGB3XSvuvwouii2mW9pgosT/4fTwXfRzrSxgXncc3zNs0 oABQ6oQCQcSS1Eu5tQDgLaipbMqP2JbHDfQY7dTDjO3rc+BzpCjTSuBVYlQxJbc0svQh vA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnmt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:05 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:04 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 552C23F7041; Mon, 3 May 2021 17:28:02 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Date: Tue, 4 May 2021 05:56:52 +0530 Message-ID: <20210504002726.525-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: qYlPYrhqxpdUeMydGq2RRvWngjL1fbRG X-Proofpoint-ORIG-GUID: qYlPYrhqxpdUeMydGq2RRvWngjL1fbRG X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 02/35] common/cnxk: update inline asm prefix X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Update inline asm prefix to prevent overriding cpu type, instead express the additional extensions required. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_platform.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 29ab71240..7864fa4ff 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -23,9 +23,14 @@ #include "roc_bits.h" #if defined(__ARM_FEATURE_SVE) -#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse+sve\n" +#define PLT_CPU_FEATURE_PREAMBLE \ + ".arch_extension crc\n" \ + ".arch_extension lse\n" \ + ".arch_extension sve\n" #else -#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse\n" +#define PLT_CPU_FEATURE_PREAMBLE \ + ".arch_extension crc\n" \ + ".arch_extension lse\n" #endif #define PLT_ASSERT RTE_ASSERT From patchwork Tue May 4 00:26:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92681 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1FD66A0562; Tue, 4 May 2021 02:28:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66EFB410F4; Tue, 4 May 2021 02:28:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D95E04014D for ; Tue, 4 May 2021 02:28:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OuhS025154; Mon, 3 May 2021 17:28:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=eiYNNAZ149K1Fw0fpZiYmJUXnnKE/Exr48ezat2qre0=; b=UBMQgAZDbI5Fw0hV1Rn9SvYf3HTiLHACv1v3GXyUAl3v5sl02/+kTNCS2291Nud9h8OF SVpLlwOUD+SMTe+qOK4zyxSss6hbBLkArOMFXFV9FObb/m0C8Pdkwpdu/Gigg81MGvTM Kxo6vTwfa0yzcGzQwi+JRmAI/eSus/Xq/YCkcpl76dQKp1a3gX3Aqh/Q809i8MLm9Lte ChbkcQEh/eEshGW8xnMXf/hi9vxwG1zOfzQSn8HtDkcR1WLwrTJREf1ThsNesUCNLM2m 6jbGAklgx3t2w/RmBIfLpw7fAqFrL10lTExT1O9xJnxzw2YJnbPANMjQ43H2J6Q/KrOV mw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnmx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 03 May 2021 17:28:09 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:08 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:07 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id C90FB3F7043; Mon, 3 May 2021 17:28:05 -0700 (PDT) From: To: , Thomas Monjalon , "Pavan Nikhilesh" , Shijith Thotton , Ray Kinsella , Neil Horman , "Anatoly Burakov" CC: Date: Tue, 4 May 2021 05:56:53 +0530 Message-ID: <20210504002726.525-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: myMnJVLKwCJBCrrxx97G1uKqw1qC51z5 X-Proofpoint-ORIG-GUID: myMnJVLKwCJBCrrxx97G1uKqw1qC51z5 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 03/35] event/cnxk: add build infra and device setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add meson build infra structure along with the event device SSO initialization and teardown functions. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh Acked-by: Ray Kinsella --- MAINTAINERS | 6 +++ doc/guides/eventdevs/cnxk.rst | 55 +++++++++++++++++++++ doc/guides/eventdevs/index.rst | 1 + doc/guides/rel_notes/release_21_05.rst | 2 + drivers/event/cnxk/cnxk_eventdev.c | 68 ++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 39 +++++++++++++++ drivers/event/cnxk/meson.build | 13 +++++ drivers/event/cnxk/version.map | 3 ++ drivers/event/meson.build | 1 + 9 files changed, 188 insertions(+) create mode 100644 doc/guides/eventdevs/cnxk.rst create mode 100644 drivers/event/cnxk/cnxk_eventdev.c create mode 100644 drivers/event/cnxk/cnxk_eventdev.h create mode 100644 drivers/event/cnxk/meson.build create mode 100644 drivers/event/cnxk/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 44f3d322e..5a2297e99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1224,6 +1224,12 @@ M: Jerin Jacob F: drivers/event/octeontx2/ F: doc/guides/eventdevs/octeontx2.rst +Marvell cnxk +M: Pavan Nikhilesh +M: Shijith Thotton +F: drivers/event/cnxk/ +F: doc/guides/eventdevs/cnxk.rst + NXP DPAA eventdev M: Hemant Agrawal M: Nipun Gupta diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst new file mode 100644 index 000000000..148280b85 --- /dev/null +++ b/doc/guides/eventdevs/cnxk.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2021 Marvell. + +Marvell cnxk SSO Eventdev Driver +================================ + +The SSO PMD (**librte_event_cnxk**) and provides poll mode +eventdev driver support for the inbuilt event device found in the +**Marvell OCTEON cnxk** SoC family. + +More information about OCTEON cnxk SoC can be found at `Marvell Official Website +`_. + +Supported OCTEON cnxk SoCs +-------------------------- + +- CN9XX +- CN10XX + +Features +-------- + +Features of the OCTEON cnxk SSO PMD are: + +- 256 Event queues +- 26 (dual) and 52 (single) Event ports on CN9XX +- 52 Event ports on CN10XX +- HW event scheduler +- Supports 1M flows per event queue +- Flow based event pipelining +- Flow pinning support in flow based event pipelining +- Queue based event pipelining +- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow +- Event scheduling QoS based on event queue priority +- Open system with configurable amount of outstanding events limited only by + DRAM +- HW accelerated dequeue timeout support to enable power management + +Prerequisites and Compilation procedure +--------------------------------------- + + See :doc:`../platform/cnxk` for setup information. + +Debugging Options +----------------- + +.. _table_octeon_cnxk_event_debug_options: + +.. table:: OCTEON cnxk event device debug options + + +---+------------+-------------------------------------------------------+ + | # | Component | EAL log command | + +===+============+=======================================================+ + | 1 | SSO | --log-level='pmd\.event\.cnxk,8' | + +---+------------+-------------------------------------------------------+ diff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst index 738788d9e..214302539 100644 --- a/doc/guides/eventdevs/index.rst +++ b/doc/guides/eventdevs/index.rst @@ -11,6 +11,7 @@ application through the eventdev API. :maxdepth: 2 :numbered: + cnxk dlb2 dpaa dpaa2 diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index b3224dc33..428615e4f 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -75,6 +75,8 @@ New Features net, crypto and event PMD's. * Added mempool/cnxk driver which provides the support for the integrated mempool device. + * Added event/cnxk driver which provides the support for integrated event + device. * **Enhanced ethdev representor syntax.** diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c new file mode 100644 index 000000000..7ea782eaa --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" + +int +cnxk_sso_init(struct rte_eventdev *event_dev) +{ + const struct rte_memzone *mz = NULL; + struct rte_pci_device *pci_dev; + struct cnxk_sso_evdev *dev; + int rc; + + mz = rte_memzone_reserve(CNXK_SSO_MZ_NAME, sizeof(uint64_t), + SOCKET_ID_ANY, 0); + if (mz == NULL) { + plt_err("Failed to create eventdev memzone"); + return -ENOMEM; + } + + dev = cnxk_sso_pmd_priv(event_dev); + pci_dev = container_of(event_dev->dev, struct rte_pci_device, device); + dev->sso.pci_dev = pci_dev; + + *(uint64_t *)mz->addr = (uint64_t)dev; + + /* Initialize the base cnxk_dev object */ + rc = roc_sso_dev_init(&dev->sso); + if (rc < 0) { + plt_err("Failed to initialize RoC SSO rc=%d", rc); + goto error; + } + + dev->is_timeout_deq = 0; + dev->min_dequeue_timeout_ns = USEC2NSEC(1); + dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF); + dev->max_num_events = -1; + dev->nb_event_queues = 0; + dev->nb_event_ports = 0; + + return 0; + +error: + rte_memzone_free(mz); + return rc; +} + +int +cnxk_sso_fini(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + /* For secondary processes, nothing to be done */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + roc_sso_rsrc_fini(&dev->sso); + roc_sso_dev_fini(&dev->sso); + + return 0; +} + +int +cnxk_sso_remove(struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_remove(pci_dev, cnxk_sso_fini); +} diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h new file mode 100644 index 000000000..74d0990fa --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CNXK_EVENTDEV_H__ +#define __CNXK_EVENTDEV_H__ + +#include + +#include + +#include "roc_api.h" + +#define USEC2NSEC(__us) ((__us)*1E3) + +#define CNXK_SSO_MZ_NAME "cnxk_evdev_mz" + +struct cnxk_sso_evdev { + struct roc_sso sso; + uint8_t is_timeout_deq; + uint8_t nb_event_queues; + uint8_t nb_event_ports; + uint32_t min_dequeue_timeout_ns; + uint32_t max_dequeue_timeout_ns; + int32_t max_num_events; +} __rte_cache_aligned; + +static inline struct cnxk_sso_evdev * +cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) +{ + return event_dev->data->dev_private; +} + +/* Common ops API. */ +int cnxk_sso_init(struct rte_eventdev *event_dev); +int cnxk_sso_fini(struct rte_eventdev *event_dev); +int cnxk_sso_remove(struct rte_pci_device *pci_dev); + +#endif /* __CNXK_EVENTDEV_H__ */ diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build new file mode 100644 index 000000000..fbe245fca --- /dev/null +++ b/drivers/event/cnxk/meson.build @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2021 Marvell. +# + +if not is_linux or not dpdk_conf.get('RTE_ARCH_64') + build = false + reason = 'only supported on 64-bit Linux' + subdir_done() +endif + +sources = files('cnxk_eventdev.c') + +deps += ['bus_pci', 'common_cnxk'] diff --git a/drivers/event/cnxk/version.map b/drivers/event/cnxk/version.map new file mode 100644 index 000000000..ee80c5172 --- /dev/null +++ b/drivers/event/cnxk/version.map @@ -0,0 +1,3 @@ +INTERNAL { + local: *; +}; diff --git a/drivers/event/meson.build b/drivers/event/meson.build index 539c5aeb9..63d6b410b 100644 --- a/drivers/event/meson.build +++ b/drivers/event/meson.build @@ -6,6 +6,7 @@ if is_windows endif drivers = [ + 'cnxk', 'dlb2', 'dpaa', 'dpaa2', From patchwork Tue May 4 00:26:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92682 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0EC49A0562; Tue, 4 May 2021 02:28:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9E05A4110D; Tue, 4 May 2021 02:28:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D2B444014D for ; Tue, 4 May 2021 02:28:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AUBw002411 for ; Mon, 3 May 2021 17:28:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2ECxKpzhMfJGae+BunAv7D5vYFYHGE53+esIFAKQnv4=; b=N1NfYhGAqU0BFps1IJgWShVQJhjEnNxmHE863fLJcwmuk8nwIWqBn81UCqo3T19P6RxA +VyZoKcLe+uX973wRWjxdPUbegBY6D2TLEMZejEq/ufEQI5rYyiy2RLA7h63/Irc488w Ilr2n1c2tEN7+PfPd69tDglQa021p09dK5O6HSKxRMpkHxYtuuSLyz4ML17sttNNTse4 rb2XbKqZSALQWIpPmZ7qgGQZKz2U/UteBH8fe3csyTnqHLZWTjhokQ8+ETZyfXLiOYc4 Vx0fZc0kBigoyJNZ/KgcMhycrQ02t6mslgnFZBVjnIaHYsotBWQsYrGzopyrMq2oZ/ct Qw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6jc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:12 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:11 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 861D53F7040; Mon, 3 May 2021 17:28:09 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:56:54 +0530 Message-ID: <20210504002726.525-5-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: cPNNrx0K73DrN1G9Oot0UWhPv4Aguh4y X-Proofpoint-ORIG-GUID: cPNNrx0K73DrN1G9Oot0UWhPv4Aguh4y X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 04/35] event/cnxk: add device capabilities function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add the info_get function to return details on the queues, flow, prioritization capabilities, etc. which this device has. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cnxk_eventdev.c | 24 ++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 4 ++++ 2 files changed, 28 insertions(+) diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 7ea782eaa..3a7053af6 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -4,6 +4,30 @@ #include "cnxk_eventdev.h" +void +cnxk_sso_info_get(struct cnxk_sso_evdev *dev, + struct rte_event_dev_info *dev_info) +{ + + dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns; + dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns; + dev_info->max_event_queues = dev->max_event_queues; + dev_info->max_event_queue_flows = (1ULL << 20); + dev_info->max_event_queue_priority_levels = 8; + dev_info->max_event_priority_levels = 1; + dev_info->max_event_ports = dev->max_event_ports; + dev_info->max_event_port_dequeue_depth = 1; + dev_info->max_event_port_enqueue_depth = 1; + dev_info->max_num_events = dev->max_num_events; + dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS | + RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED | + RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES | + RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK | + RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT | + RTE_EVENT_DEV_CAP_NONSEQ_MODE | + RTE_EVENT_DEV_CAP_CARRY_FLOW_ID; +} + int cnxk_sso_init(struct rte_eventdev *event_dev) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 74d0990fa..9745bfd3e 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -17,6 +17,8 @@ struct cnxk_sso_evdev { struct roc_sso sso; + uint8_t max_event_queues; + uint8_t max_event_ports; uint8_t is_timeout_deq; uint8_t nb_event_queues; uint8_t nb_event_ports; @@ -35,5 +37,7 @@ cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) int cnxk_sso_init(struct rte_eventdev *event_dev); int cnxk_sso_fini(struct rte_eventdev *event_dev); int cnxk_sso_remove(struct rte_pci_device *pci_dev); +void cnxk_sso_info_get(struct cnxk_sso_evdev *dev, + struct rte_event_dev_info *dev_info); #endif /* __CNXK_EVENTDEV_H__ */ From patchwork Tue May 4 00:26:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92683 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6AF93A0562; Tue, 4 May 2021 02:28:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 50CD44112F; Tue, 4 May 2021 02:28:17 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 51AB141117 for ; Tue, 4 May 2021 02:28:16 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OuhT025154; Mon, 3 May 2021 17:28:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=XR9d7ZPDfrEuil37AjRldJqgyTEAYv2hbbGzee67u58=; b=cLc5qHFD2JD0sajHT8qvE+DCnn71hzHKoZblJ5o458oLW72V+Ul3c2AQDTwAgzvoviTc F1MgtaTn1vRXXByVaTRsJEnOmPstmi5u/AF426quV5mIz2uPqsl9Eg5UZpTutYHHx0ZR SZDfbjjrMUb9yG9qsfdG9jBQZQdJBBbrYAeGcYU57aosNuzZqR/UNotWVz1Ki7gENAt8 GuIl47PTqplCU+ZgkRGVPsaKliY/ty25v9AvMQXvSep6HCTdk/D+lKBs7f+Sws7ei8mF gmGu53Uc1rxmbSFHvr0VzZhBThqXBFE8A9KbbqWlUYltBXkf/PFhdQCR8b38WUcpDkcB 0Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnnd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 03 May 2021 17:28:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:14 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 5369B3F7040; Mon, 3 May 2021 17:28:12 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" , Anatoly Burakov CC: Date: Tue, 4 May 2021 05:56:55 +0530 Message-ID: <20210504002726.525-6-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: _dex17SUbt5r-AWRhKiIxqAv40bDKIgH X-Proofpoint-ORIG-GUID: _dex17SUbt5r-AWRhKiIxqAv40bDKIgH X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 05/35] event/cnxk: add platform specific device probe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add platform specific event device probe and remove, also add event device info get function. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cn10k_eventdev.c | 101 +++++++++++++++++++++++++++ drivers/event/cnxk/cn9k_eventdev.c | 102 ++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 2 + drivers/event/cnxk/meson.build | 5 +- 4 files changed, 209 insertions(+), 1 deletion(-) create mode 100644 drivers/event/cnxk/cn10k_eventdev.c create mode 100644 drivers/event/cnxk/cn9k_eventdev.c diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c new file mode 100644 index 000000000..1216acaad --- /dev/null +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" + +static void +cn10k_sso_set_rsrc(void *arg) +{ + struct cnxk_sso_evdev *dev = arg; + + dev->max_event_ports = dev->sso.max_hws; + dev->max_event_queues = + dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ? + RTE_EVENT_MAX_QUEUES_PER_DEV : + dev->sso.max_hwgrp; +} + +static void +cn10k_sso_info_get(struct rte_eventdev *event_dev, + struct rte_event_dev_info *dev_info) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD); + cnxk_sso_info_get(dev, dev_info); +} + +static struct rte_eventdev_ops cn10k_sso_dev_ops = { + .dev_infos_get = cn10k_sso_info_get, +}; + +static int +cn10k_sso_init(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int rc; + + if (RTE_CACHE_LINE_SIZE != 64) { + plt_err("Driver not compiled for CN9K"); + return -EFAULT; + } + + rc = roc_plt_init(); + if (rc < 0) { + plt_err("Failed to initialize platform model"); + return rc; + } + + event_dev->dev_ops = &cn10k_sso_dev_ops; + /* For secondary processes, the primary has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rc = cnxk_sso_init(event_dev); + if (rc < 0) + return rc; + + cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev)); + if (!dev->max_event_ports || !dev->max_event_queues) { + plt_err("Not enough eventdev resource queues=%d ports=%d", + dev->max_event_queues, dev->max_event_ports); + cnxk_sso_fini(event_dev); + return -ENODEV; + } + + plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d", + event_dev->data->name, dev->max_event_queues, + dev->max_event_ports); + + return 0; +} + +static int +cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_probe(pci_drv, pci_dev, + sizeof(struct cnxk_sso_evdev), + cn10k_sso_init); +} + +static const struct rte_pci_id cn10k_pci_sso_map[] = { + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF), + { + .vendor_id = 0, + }, +}; + +static struct rte_pci_driver cn10k_pci_sso = { + .id_table = cn10k_pci_sso_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = cn10k_sso_probe, + .remove = cnxk_sso_remove, +}; + +RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso); +RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); +RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c new file mode 100644 index 000000000..988d2425f --- /dev/null +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" + +#define CN9K_DUAL_WS_NB_WS 2 +#define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id) + +static void +cn9k_sso_set_rsrc(void *arg) +{ + struct cnxk_sso_evdev *dev = arg; + + if (dev->dual_ws) + dev->max_event_ports = dev->sso.max_hws / CN9K_DUAL_WS_NB_WS; + else + dev->max_event_ports = dev->sso.max_hws; + dev->max_event_queues = + dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ? + RTE_EVENT_MAX_QUEUES_PER_DEV : + dev->sso.max_hwgrp; +} + +static void +cn9k_sso_info_get(struct rte_eventdev *event_dev, + struct rte_event_dev_info *dev_info) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN9K_PMD); + cnxk_sso_info_get(dev, dev_info); +} + +static struct rte_eventdev_ops cn9k_sso_dev_ops = { + .dev_infos_get = cn9k_sso_info_get, +}; + +static int +cn9k_sso_init(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int rc; + + if (RTE_CACHE_LINE_SIZE != 128) { + plt_err("Driver not compiled for CN9K"); + return -EFAULT; + } + + rc = roc_plt_init(); + if (rc < 0) { + plt_err("Failed to initialize platform model"); + return rc; + } + + event_dev->dev_ops = &cn9k_sso_dev_ops; + /* For secondary processes, the primary has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rc = cnxk_sso_init(event_dev); + if (rc < 0) + return rc; + + cn9k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev)); + if (!dev->max_event_ports || !dev->max_event_queues) { + plt_err("Not enough eventdev resource queues=%d ports=%d", + dev->max_event_queues, dev->max_event_ports); + cnxk_sso_fini(event_dev); + return -ENODEV; + } + + plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d", + event_dev->data->name, dev->max_event_queues, + dev->max_event_ports); + + return 0; +} + +static int +cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) +{ + return rte_event_pmd_pci_probe( + pci_drv, pci_dev, sizeof(struct cnxk_sso_evdev), cn9k_sso_init); +} + +static const struct rte_pci_id cn9k_pci_sso_map[] = { + { + .vendor_id = 0, + }, +}; + +static struct rte_pci_driver cn9k_pci_sso = { + .id_table = cn9k_pci_sso_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA, + .probe = cn9k_sso_probe, + .remove = cnxk_sso_remove, +}; + +RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso); +RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); +RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 9745bfd3e..6bdf0b347 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -25,6 +25,8 @@ struct cnxk_sso_evdev { uint32_t min_dequeue_timeout_ns; uint32_t max_dequeue_timeout_ns; int32_t max_num_events; + /* CN9K */ + uint8_t dual_ws; } __rte_cache_aligned; static inline struct cnxk_sso_evdev * diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index fbe245fca..22eb28345 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -8,6 +8,9 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64') subdir_done() endif -sources = files('cnxk_eventdev.c') +sources = files('cn10k_eventdev.c', + 'cn9k_eventdev.c', + 'cnxk_eventdev.c', + ) deps += ['bus_pci', 'common_cnxk'] From patchwork Tue May 4 00:26:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92684 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E3A3A0562; Tue, 4 May 2021 02:28:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92EAF41127; Tue, 4 May 2021 02:28:20 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4FABC4111D for ; Tue, 4 May 2021 02:28:19 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440Algu002713 for ; Mon, 3 May 2021 17:28:18 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=InuxCcz6qd7A7MiGlNB8Uit2E73/EZskGRyZV6uD3fU=; b=NCtmrOLJ5FjItawJXjl+ZVYOiHvs5MqK2L8M8HiN6qQGbkSNyxmtbHBxS+VUkpFtQubc 0G6Tm8xafqOMnkZluDUd4SwN+0WuINemAgZhgvnDcqzW2lX7GOTU88Yey6AyLL2WewR+ uIqY0xXcpxvVfthrnshLoCZ8u1d1mkO24g/co+MhqmVho5BySdMIJKrx1sAhxz5NnHrS EuOvmQoD4a8TRYSPSkaVPVyc2dsNpgowMmLTm3fX8x/NyyOI3iRf8l42z7IwrSoqhqOI WInvPZtcEGvthLHJDdwxi5CyqxURq5HcZJVrs8F8xxKgXMGqNypx20nn38bpL/f61E7G ZQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6jm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:18 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:16 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 42ED03F7048; Mon, 3 May 2021 17:28:15 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:56:56 +0530 Message-ID: <20210504002726.525-7-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: vboz1szEKX5TUc1ZWlhp9_rr0MDiDCP4 X-Proofpoint-ORIG-GUID: vboz1szEKX5TUc1ZWlhp9_rr0MDiDCP4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 06/35] event/cnxk: add common configuration validation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add configuration validation, port and queue configuration functions. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_eventdev.c | 70 ++++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 6 +++ 2 files changed, 76 insertions(+) diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 3a7053af6..3eab1ed29 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -28,6 +28,76 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev, RTE_EVENT_DEV_CAP_CARRY_FLOW_ID; } +int +cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) +{ + struct rte_event_dev_config *conf = &event_dev->data->dev_conf; + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint32_t deq_tmo_ns; + + deq_tmo_ns = conf->dequeue_timeout_ns; + + if (deq_tmo_ns == 0) + deq_tmo_ns = dev->min_dequeue_timeout_ns; + if (deq_tmo_ns < dev->min_dequeue_timeout_ns || + deq_tmo_ns > dev->max_dequeue_timeout_ns) { + plt_err("Unsupported dequeue timeout requested"); + return -EINVAL; + } + + if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) + dev->is_timeout_deq = 1; + + dev->deq_tmo_ns = deq_tmo_ns; + + if (!conf->nb_event_queues || !conf->nb_event_ports || + conf->nb_event_ports > dev->max_event_ports || + conf->nb_event_queues > dev->max_event_queues) { + plt_err("Unsupported event queues/ports requested"); + return -EINVAL; + } + + if (conf->nb_event_port_dequeue_depth > 1) { + plt_err("Unsupported event port deq depth requested"); + return -EINVAL; + } + + if (conf->nb_event_port_enqueue_depth > 1) { + plt_err("Unsupported event port enq depth requested"); + return -EINVAL; + } + + dev->nb_event_queues = conf->nb_event_queues; + dev->nb_event_ports = conf->nb_event_ports; + + return 0; +} + +void +cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, + struct rte_event_queue_conf *queue_conf) +{ + RTE_SET_USED(event_dev); + RTE_SET_USED(queue_id); + + queue_conf->nb_atomic_flows = (1ULL << 20); + queue_conf->nb_atomic_order_sequences = (1ULL << 20); + queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES; + queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL; +} + +void +cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, + struct rte_event_port_conf *port_conf) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + RTE_SET_USED(port_id); + port_conf->new_event_threshold = dev->max_num_events; + port_conf->dequeue_depth = 1; + port_conf->enqueue_depth = 1; +} + int cnxk_sso_init(struct rte_eventdev *event_dev) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 6bdf0b347..59d96a08f 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -22,6 +22,7 @@ struct cnxk_sso_evdev { uint8_t is_timeout_deq; uint8_t nb_event_queues; uint8_t nb_event_ports; + uint32_t deq_tmo_ns; uint32_t min_dequeue_timeout_ns; uint32_t max_dequeue_timeout_ns; int32_t max_num_events; @@ -41,5 +42,10 @@ int cnxk_sso_fini(struct rte_eventdev *event_dev); int cnxk_sso_remove(struct rte_pci_device *pci_dev); void cnxk_sso_info_get(struct cnxk_sso_evdev *dev, struct rte_event_dev_info *dev_info); +int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev); +void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, + struct rte_event_queue_conf *queue_conf); +void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, + struct rte_event_port_conf *port_conf); #endif /* __CNXK_EVENTDEV_H__ */ From patchwork Tue May 4 00:26:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92685 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 734C4A0562; Tue, 4 May 2021 02:28:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C8EF94113C; Tue, 4 May 2021 02:28:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id AEA914113C for ; Tue, 4 May 2021 02:28:21 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OujY025116 for ; Mon, 3 May 2021 17:28:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=UWqhpDk7eZ9D/eFaqHZKhebiRASFAXWqvRhbn402lVk=; b=eX64huUTwXBt7cGqnj5+ibxiFchoIQbifEFBSjHykt1+AsLLXvJPBoX2ViKxE82/3pGx WkC4AaC0sJ4YojCpMbYRyXC6ePL5kd+R8ATLuUL5CdDXplEMkQJpt/V6dam7O3OO78mp RXEdsoWetfM9xT4l1e40EoAf2dz3cyrJG2bE4QzMprEyi5UyJZCMjt6g4D/YG1LJTyAe hOYBODfQ0zpX8+UDEkDHEEb0M64H+cvs8kKkgSOGKZkNyxWrHo/JTV/fMi/OLvHN28AA fjrmJkUqwQgJ0xtX66SlHs+LHwYMDKsDYRdX15pZCB3kVV2iBfbGKR5dLBit0shAbB73 Eg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnnm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:20 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:19 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id F3CD53F7041; Mon, 3 May 2021 17:28:17 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:56:57 +0530 Message-ID: <20210504002726.525-8-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: BIILGFTmm8jRphXrCIiYgoOB4o88JLiG X-Proofpoint-ORIG-GUID: BIILGFTmm8jRphXrCIiYgoOB4o88JLiG X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 07/35] event/cnxk: add platform specific device config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add platform specific event device configuration that attaches the requested number of SSO HWS(event ports) and HWGRP(event queues) LFs to the RVU PF/VF. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 35 +++++++++++++++++++++++++++ drivers/event/cnxk/cn9k_eventdev.c | 37 +++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 1216acaad..779a2e026 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -16,6 +16,14 @@ cn10k_sso_set_rsrc(void *arg) dev->sso.max_hwgrp; } +static int +cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp) +{ + struct cnxk_sso_evdev *dev = arg; + + return roc_sso_rsrc_init(&dev->sso, hws, hwgrp); +} + static void cn10k_sso_info_get(struct rte_eventdev *event_dev, struct rte_event_dev_info *dev_info) @@ -26,8 +34,35 @@ cn10k_sso_info_get(struct rte_eventdev *event_dev, cnxk_sso_info_get(dev, dev_info); } +static int +cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int rc; + + rc = cnxk_sso_dev_validate(event_dev); + if (rc < 0) { + plt_err("Invalid event device configuration"); + return -EINVAL; + } + + roc_sso_rsrc_fini(&dev->sso); + + rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports, + dev->nb_event_queues); + if (rc < 0) { + plt_err("Failed to initialize SSO resources"); + return -ENODEV; + } + + return rc; +} + static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, + .dev_configure = cn10k_sso_dev_configure, + .queue_def_conf = cnxk_sso_queue_def_conf, + .port_def_conf = cnxk_sso_port_def_conf, }; static int diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 988d2425f..d042f58da 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -22,6 +22,17 @@ cn9k_sso_set_rsrc(void *arg) dev->sso.max_hwgrp; } +static int +cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp) +{ + struct cnxk_sso_evdev *dev = arg; + + if (dev->dual_ws) + hws = hws * CN9K_DUAL_WS_NB_WS; + + return roc_sso_rsrc_init(&dev->sso, hws, hwgrp); +} + static void cn9k_sso_info_get(struct rte_eventdev *event_dev, struct rte_event_dev_info *dev_info) @@ -32,8 +43,34 @@ cn9k_sso_info_get(struct rte_eventdev *event_dev, cnxk_sso_info_get(dev, dev_info); } +static int +cn9k_sso_dev_configure(const struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int rc; + + rc = cnxk_sso_dev_validate(event_dev); + if (rc < 0) { + plt_err("Invalid event device configuration"); + return -EINVAL; + } + + roc_sso_rsrc_fini(&dev->sso); + + rc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues); + if (rc < 0) { + plt_err("Failed to initialize SSO resources"); + return -ENODEV; + } + + return rc; +} + static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, + .dev_configure = cn9k_sso_dev_configure, + .queue_def_conf = cnxk_sso_queue_def_conf, + .port_def_conf = cnxk_sso_port_def_conf, }; static int From patchwork Tue May 4 00:26:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92686 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA4DDA0562; Tue, 4 May 2021 02:28:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1FC3F41143; Tue, 4 May 2021 02:28:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B198541143 for ; Tue, 4 May 2021 02:28:24 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGT0002336 for ; Mon, 3 May 2021 17:28:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=4H3Ezz0pv06UMIJ3vTjZYB4amzmQZFPkqOobl/N+WPA=; b=AtJmeRwXiyDBQMCs0/o3tzPSCnRjSvdxuUibLt9BzPzoXBXAfczUKeOUsJY38tHXiN85 GZ+z7SFCz5c+D3Ry+PqvRZGCe8MEDBLBgkJ+1gUtFMWIvFQKHqknBT+tNkolLk17+Uo5 28zKzr6GRGRXpq2VjYoNWnshVqSY3AphRLCQQv6fDhmIelEwzpAhqba69KdJnXM4HWIW +w9kPggWteeXEv1tDCNrQ/CBOegASIBVe4iJsNNByMb3GP6YC78QgWhGoYMuR0MxV5tA TSgVVWQjwqZSgxgItdSLDgqiiQeBjKl4aGQtXU2ugVGy97+DYpNU4fA8q8lVMIHXQYL6 sg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6jy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:24 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:21 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id B4DF03F703F; Mon, 3 May 2021 17:28:20 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:56:58 +0530 Message-ID: <20210504002726.525-9-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xBaV1XYU6OUyHz1vhIX9Da8E-bglYJrQ X-Proofpoint-ORIG-GUID: xBaV1XYU6OUyHz1vhIX9Da8E-bglYJrQ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 08/35] event/cnxk: add event queue config functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add setup and release functions for event queues i.e. SSO HWGRPs. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 2 ++ drivers/event/cnxk/cn9k_eventdev.c | 2 ++ drivers/event/cnxk/cnxk_eventdev.c | 19 +++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 3 +++ 4 files changed, 26 insertions(+) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 779a2e026..557f26b8f 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -62,6 +62,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, + .queue_setup = cnxk_sso_queue_setup, + .queue_release = cnxk_sso_queue_release, .port_def_conf = cnxk_sso_port_def_conf, }; diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index d042f58da..eba1bfbf0 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -70,6 +70,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, + .queue_setup = cnxk_sso_queue_setup, + .queue_release = cnxk_sso_queue_release, .port_def_conf = cnxk_sso_port_def_conf, }; diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 3eab1ed29..e22479a19 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -86,6 +86,25 @@ cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL; } +int +cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, + const struct rte_event_queue_conf *queue_conf) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + plt_sso_dbg("Queue=%d prio=%d", queue_id, queue_conf->priority); + /* Normalize <0-255> to <0-7> */ + return roc_sso_hwgrp_set_priority(&dev->sso, queue_id, 0xFF, 0xFF, + queue_conf->priority / 32); +} + +void +cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id) +{ + RTE_SET_USED(event_dev); + RTE_SET_USED(queue_id); +} + void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, struct rte_event_port_conf *port_conf) diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 59d96a08f..426219c85 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -45,6 +45,9 @@ void cnxk_sso_info_get(struct cnxk_sso_evdev *dev, int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev); void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, struct rte_event_queue_conf *queue_conf); +int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, + const struct rte_event_queue_conf *queue_conf); +void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id); void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, struct rte_event_port_conf *port_conf); From patchwork Tue May 4 00:26:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92687 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 99F97A0562; Tue, 4 May 2021 02:28:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A263341147; Tue, 4 May 2021 02:28:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 13E7A41148 for ; Tue, 4 May 2021 02:28:26 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OtxF025090 for ; Mon, 3 May 2021 17:28:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=3tIr2Kh/yIqlFHouNnghqhDpqhpu/G5rYo4o5HQGfF8=; b=Nv8cDagJqSmOlFfJf3fFBjURjz/bVMHQ4tGbQajosuIbNFp6gHGoDlyyVYU/FWZwnQm4 giYGriUMfHMZYB7nWpLUJJpRxas/SPtwsRIn2YT6dWAjFM9+OV1oOMoLZttUQlRDznLP Jki6cykQdJRq9ThLiy488nDy/BFzq9nyztpC4Z+ltW63APNaj3Nfs+0/xVcz50/IkU/x rX9e4ILhN59hUcSD79YAHVRIr0GYi4zEw42n6/6zF6qLqTXzd4PRvSweKRmLecqJlEzU VxyVVNHJ3yHnSlxHemsFAEWOO+fL35byHCk/RtJuxyt7zxu/Fkq95mZEdnY4TuWU5eM4 IA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnnu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:26 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:24 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 831CF3F703F; Mon, 3 May 2021 17:28:23 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:56:59 +0530 Message-ID: <20210504002726.525-10-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xBFDqCjMA6QaM7L6X6OfVybt-pJ771bB X-Proofpoint-ORIG-GUID: xBFDqCjMA6QaM7L6X6OfVybt-pJ771bB X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 09/35] event/cnxk: allocate event inflight buffers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Allocate buffers in DRAM that hold inflight events. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 7 ++ drivers/event/cnxk/cn9k_eventdev.c | 7 ++ drivers/event/cnxk/cnxk_eventdev.c | 105 ++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 14 +++- 4 files changed, 132 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 557f26b8f..9c5ddea76 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -55,6 +55,13 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) return -ENODEV; } + rc = cnxk_sso_xaq_allocate(dev); + if (rc < 0) + goto cnxk_rsrc_fini; + + return 0; +cnxk_rsrc_fini: + roc_sso_rsrc_fini(&dev->sso); return rc; } diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index eba1bfbf0..954fea01f 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -63,6 +63,13 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev) return -ENODEV; } + rc = cnxk_sso_xaq_allocate(dev); + if (rc < 0) + goto cnxk_rsrc_fini; + + return 0; +cnxk_rsrc_fini: + roc_sso_rsrc_fini(&dev->sso); return rc; } diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index e22479a19..34a8bce05 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -28,12 +28,107 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev, RTE_EVENT_DEV_CAP_CARRY_FLOW_ID; } +int +cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev) +{ + char pool_name[RTE_MEMZONE_NAMESIZE]; + uint32_t xaq_cnt, npa_aura_id; + const struct rte_memzone *mz; + struct npa_aura_s *aura; + static int reconfig_cnt; + int rc; + + if (dev->xaq_pool) { + rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues); + if (rc < 0) { + plt_err("Failed to release XAQ %d", rc); + return rc; + } + rte_mempool_free(dev->xaq_pool); + dev->xaq_pool = NULL; + } + + /* + * Allocate memory for Add work backpressure. + */ + mz = rte_memzone_lookup(CNXK_SSO_FC_NAME); + if (mz == NULL) + mz = rte_memzone_reserve_aligned(CNXK_SSO_FC_NAME, + sizeof(struct npa_aura_s) + + RTE_CACHE_LINE_SIZE, + 0, 0, RTE_CACHE_LINE_SIZE); + if (mz == NULL) { + plt_err("Failed to allocate mem for fcmem"); + return -ENOMEM; + } + + dev->fc_iova = mz->iova; + dev->fc_mem = mz->addr; + + aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + + RTE_CACHE_LINE_SIZE); + memset(aura, 0, sizeof(struct npa_aura_s)); + + aura->fc_ena = 1; + aura->fc_addr = dev->fc_iova; + aura->fc_hyst_bits = 0; /* Store count on all updates */ + + /* Taken from HRM 14.3.3(4) */ + xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT; + xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) + + (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); + + plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt); + /* Setup XAQ based on number of nb queues. */ + snprintf(pool_name, 30, "cnxk_xaq_buf_pool_%d", reconfig_cnt); + dev->xaq_pool = (void *)rte_mempool_create_empty( + pool_name, xaq_cnt, dev->sso.xaq_buf_size, 0, 0, + rte_socket_id(), 0); + + if (dev->xaq_pool == NULL) { + plt_err("Unable to create empty mempool."); + rte_memzone_free(mz); + return -ENOMEM; + } + + rc = rte_mempool_set_ops_byname(dev->xaq_pool, + rte_mbuf_platform_mempool_ops(), aura); + if (rc != 0) { + plt_err("Unable to set xaqpool ops."); + goto alloc_fail; + } + + rc = rte_mempool_populate_default(dev->xaq_pool); + if (rc < 0) { + plt_err("Unable to set populate xaqpool."); + goto alloc_fail; + } + reconfig_cnt++; + /* When SW does addwork (enqueue) check if there is space in XAQ by + * comparing fc_addr above against the xaq_lmt calculated below. + * There should be a minimum headroom (CNXK_SSO_XAQ_SLACK / 2) for SSO + * to request XAQ to cache them even before enqueue is called. + */ + dev->xaq_lmt = + xaq_cnt - (CNXK_SSO_XAQ_SLACK / 2 * dev->nb_event_queues); + dev->nb_xaq_cfg = xaq_cnt; + + npa_aura_id = roc_npa_aura_handle_to_aura(dev->xaq_pool->pool_id); + return roc_sso_hwgrp_alloc_xaq(&dev->sso, npa_aura_id, + dev->nb_event_queues); +alloc_fail: + rte_mempool_free(dev->xaq_pool); + rte_memzone_free(mz); + return rc; +} + int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) { struct rte_event_dev_config *conf = &event_dev->data->dev_conf; struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); uint32_t deq_tmo_ns; + int rc; deq_tmo_ns = conf->dequeue_timeout_ns; @@ -67,6 +162,16 @@ cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) return -EINVAL; } + if (dev->xaq_pool) { + rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues); + if (rc < 0) { + plt_err("Failed to release XAQ %d", rc); + return rc; + } + rte_mempool_free(dev->xaq_pool); + dev->xaq_pool = NULL; + } + dev->nb_event_queues = conf->nb_event_queues; dev->nb_event_ports = conf->nb_event_ports; diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 426219c85..4abe4548d 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -5,6 +5,7 @@ #ifndef __CNXK_EVENTDEV_H__ #define __CNXK_EVENTDEV_H__ +#include #include #include @@ -13,7 +14,10 @@ #define USEC2NSEC(__us) ((__us)*1E3) -#define CNXK_SSO_MZ_NAME "cnxk_evdev_mz" +#define CNXK_SSO_FC_NAME "cnxk_evdev_xaq_fc" +#define CNXK_SSO_MZ_NAME "cnxk_evdev_mz" +#define CNXK_SSO_XAQ_CACHE_CNT (0x7) +#define CNXK_SSO_XAQ_SLACK (8) struct cnxk_sso_evdev { struct roc_sso sso; @@ -26,6 +30,11 @@ struct cnxk_sso_evdev { uint32_t min_dequeue_timeout_ns; uint32_t max_dequeue_timeout_ns; int32_t max_num_events; + uint64_t *fc_mem; + uint64_t xaq_lmt; + uint64_t nb_xaq_cfg; + rte_iova_t fc_iova; + struct rte_mempool *xaq_pool; /* CN9K */ uint8_t dual_ws; } __rte_cache_aligned; @@ -36,6 +45,9 @@ cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) return event_dev->data->dev_private; } +/* Configuration functions */ +int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev); + /* Common ops API. */ int cnxk_sso_init(struct rte_eventdev *event_dev); int cnxk_sso_fini(struct rte_eventdev *event_dev); From patchwork Tue May 4 00:27:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92688 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E499A0562; Tue, 4 May 2021 02:29:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D842541156; Tue, 4 May 2021 02:28:31 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 13C774114E for ; Tue, 4 May 2021 02:28:29 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OuhV025154 for ; Mon, 3 May 2021 17:28:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=+mNsMoZwk9EZW80MNmznwQXfRJT1pONNTNhf7MfXqhE=; b=SNL+BcrXMM6IVPtmI24DtDlNkKPEmHZybe+10GCRbNpmMH4IpFcp7PFCZMh2ckPvLUnL /EVHkR/9ZH4hN+KkKnZvoSBvyUdqbo7Egv9cZg2OMNSXb8BGHudf4XAIAmwsZTt7Ln6o LrTuf2tmx7KGbAklGRfAOcMAieIHuNxhJtc+pm05GE1nF1TJo9SpGs+nREm+1V8wSm3p tiHWJaP1GMnxJ0wQ7ojCj9Px7snBjbxoyR4LLSpaQbJ9ZYqcq0p1TqWYQSHOVweJsmUA Vhpf6cFUcJNxF74hSAITZ44Igl6iDMM0pzSJZ9VF/vtwppzpfwcxdWeV3fa3SIJkxz/2 TA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnny-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:29 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:27 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 4656F3F703F; Mon, 3 May 2021 17:28:26 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:00 +0530 Message-ID: <20210504002726.525-11-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: w55MjfeifZXT8sAR7sMhzQ4oPnrdWlIj X-Proofpoint-ORIG-GUID: w55MjfeifZXT8sAR7sMhzQ4oPnrdWlIj X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 10/35] event/cnxk: add devargs for inflight buffer count X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton The number of events for a *open system* event device is specified as -1 as per the eventdev specification. Since, SSO inflight events are only limited by DRAM size, the xae_cnt devargs parameter is introduced to provide upper limit for in-flight events. Example: --dev "0002:0e:00.0,xae_cnt=8192" Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/cnxk.rst | 14 ++++++++++++++ drivers/event/cnxk/cn10k_eventdev.c | 1 + drivers/event/cnxk/cn9k_eventdev.c | 1 + drivers/event/cnxk/cnxk_eventdev.c | 24 ++++++++++++++++++++++-- drivers/event/cnxk/cnxk_eventdev.h | 15 +++++++++++++++ 5 files changed, 53 insertions(+), 2 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index 148280b85..b556681ff 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -41,6 +41,20 @@ Prerequisites and Compilation procedure See :doc:`../platform/cnxk` for setup information. + +Runtime Config Options +---------------------- + +- ``Maximum number of in-flight events`` (default ``8192``) + + In **Marvell OCTEON cnxk** the max number of in-flight events are only limited + by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide + upper limit for in-flight events. + + For example:: + + -a 0002:0e:00.0,xae_cnt=16384 + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 9c5ddea76..020905290 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -143,3 +143,4 @@ static struct rte_pci_driver cn10k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "="); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 954fea01f..50f6fef01 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -146,3 +146,4 @@ static struct rte_pci_driver cn9k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "="); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 34a8bce05..fddd71a8d 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -75,8 +75,11 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev) /* Taken from HRM 14.3.3(4) */ xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT; - xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) + - (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); + if (dev->xae_cnt) + xaq_cnt += dev->xae_cnt / dev->sso.xae_waes; + else + xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) + + (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt); /* Setup XAQ based on number of nb queues. */ @@ -222,6 +225,22 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, port_conf->enqueue_depth = 1; } +static void +cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) +{ + struct rte_kvargs *kvlist; + + if (devargs == NULL) + return; + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + return; + + rte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value, + &dev->xae_cnt); + rte_kvargs_free(kvlist); +} + int cnxk_sso_init(struct rte_eventdev *event_dev) { @@ -242,6 +261,7 @@ cnxk_sso_init(struct rte_eventdev *event_dev) dev->sso.pci_dev = pci_dev; *(uint64_t *)mz->addr = (uint64_t)dev; + cnxk_sso_parse_devargs(dev, pci_dev->device.devargs); /* Initialize the base cnxk_dev object */ rc = roc_sso_dev_init(&dev->sso); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 4abe4548d..202c6e6a7 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -5,6 +5,8 @@ #ifndef __CNXK_EVENTDEV_H__ #define __CNXK_EVENTDEV_H__ +#include +#include #include #include @@ -12,6 +14,8 @@ #include "roc_api.h" +#define CNXK_SSO_XAE_CNT "xae_cnt" + #define USEC2NSEC(__us) ((__us)*1E3) #define CNXK_SSO_FC_NAME "cnxk_evdev_xaq_fc" @@ -35,10 +39,21 @@ struct cnxk_sso_evdev { uint64_t nb_xaq_cfg; rte_iova_t fc_iova; struct rte_mempool *xaq_pool; + /* Dev args */ + uint32_t xae_cnt; /* CN9K */ uint8_t dual_ws; } __rte_cache_aligned; +static inline int +parse_kvargs_value(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + *(uint32_t *)opaque = (uint32_t)atoi(value); + return 0; +} + static inline struct cnxk_sso_evdev * cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) { From patchwork Tue May 4 00:27:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92689 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 59030A0562; Tue, 4 May 2021 02:29:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2028641160; Tue, 4 May 2021 02:28:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8000141158 for ; Tue, 4 May 2021 02:28:33 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGT2002336 for ; Mon, 3 May 2021 17:28:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=UhWlThFO/2a0xytd+I/rT+giTY9q/PCIj2t/n8iIcnE=; b=j5hma37/bYrU42Mywm2JOS+gFJGtenY0u47JMaIJWSCGPWtcBVZ6offCJuB52zXyiyXJ c56hHk+QBhod7QDZ5AOUuxeKB9wY57FXvwN5tvTVJwn/FlmhdcEVPYuHF1kvgZfPxZzb dOrLsEMKjFOcJyFE445EOyQ3/Bn+ZSFALzMBq7MAcmzFYwVuOJyNkAzTpn0LkyZqlfc6 C9ZhWBDY4+n4v+km3dqkToD0bRa2mp0rNV09qLfjK9dNSDcuNE7moTfyGoVLetayaIdQ yQMqy4jTjRX3cE/6teKP7dQHW1RLb2ktFVS9X5dpexQANwxGPKlHQXpRuImfqJVWMahP xQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6kd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:32 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:29 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id F30C63F703F; Mon, 3 May 2021 17:28:28 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:01 +0530 Message-ID: <20210504002726.525-12-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: eERXKLqqWKIAQzwjDw8byeXfHWdzP5ua X-Proofpoint-ORIG-GUID: eERXKLqqWKIAQzwjDw8byeXfHWdzP5ua X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 11/35] event/cnxk: add devargs to control SSO HWGRP QoS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton SSO HWGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight events. By default the buffers are assigned to the SSO HWGRPs to satisfy minimum HW requirements. SSO is free to assign the remaining buffers to HWGRPs based on a preconfigured threshold. We can control the QoS of SSO HWGRP by modifying the above mentioned thresholds. HWGRPs that have higher importance can be assigned higher thresholds than the rest. Example: --dev "0002:0e:00.0,qos=[1-50-50-50]" // [Qx-XAQ-TAQ-IAQ] Qx -> Event queue Aka SSO GGRP. XAQ -> DRAM In-flights. TAQ & IAQ -> SRAM In-flights. The values need to be expressed in terms of percentages, 0 represents default. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 16 ++++++ drivers/event/cnxk/cn10k_eventdev.c | 3 +- drivers/event/cnxk/cn9k_eventdev.c | 3 +- drivers/event/cnxk/cnxk_eventdev.c | 78 +++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 12 ++++- 5 files changed, 109 insertions(+), 3 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index b556681ff..0583e5fdd 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -55,6 +55,22 @@ Runtime Config Options -a 0002:0e:00.0,xae_cnt=16384 +- ``Event Group QoS support`` + + SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight + events. By default the buffers are assigned to the SSO GGRPs to + satisfy minimum HW requirements. SSO is free to assign the remaining + buffers to GGRPs based on a preconfigured threshold. + We can control the QoS of SSO GGRP by modifying the above mentioned + thresholds. GGRPs that have higher importance can be assigned higher + thresholds than the rest. The dictionary format is as follows + [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] expressed in percentages, 0 represents + default. + + For example:: + + -a 0002:0e:00.0,qos=[1-50-50-50] + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 020905290..0b39c6c09 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -143,4 +143,5 @@ static struct rte_pci_driver cn10k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); -RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "="); +RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" + CNXK_SSO_GGRP_QOS "="); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 50f6fef01..ab165c850 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -146,4 +146,5 @@ static struct rte_pci_driver cn9k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); -RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "="); +RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" + CNXK_SSO_GGRP_QOS "="); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index fddd71a8d..e93aaccd8 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -225,6 +225,82 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, port_conf->enqueue_depth = 1; } +static void +parse_queue_param(char *value, void *opaque) +{ + struct cnxk_sso_qos queue_qos = {0}; + uint8_t *val = (uint8_t *)&queue_qos; + struct cnxk_sso_evdev *dev = opaque; + char *tok = strtok(value, "-"); + struct cnxk_sso_qos *old_ptr; + + if (!strlen(value)) + return; + + while (tok != NULL) { + *val = atoi(tok); + tok = strtok(NULL, "-"); + val++; + } + + if (val != (&queue_qos.iaq_prcnt + 1)) { + plt_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]"); + return; + } + + dev->qos_queue_cnt++; + old_ptr = dev->qos_parse_data; + dev->qos_parse_data = rte_realloc( + dev->qos_parse_data, + sizeof(struct cnxk_sso_qos) * dev->qos_queue_cnt, 0); + if (dev->qos_parse_data == NULL) { + dev->qos_parse_data = old_ptr; + dev->qos_queue_cnt--; + return; + } + dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos; +} + +static void +parse_qos_list(const char *value, void *opaque) +{ + char *s = strdup(value); + char *start = NULL; + char *end = NULL; + char *f = s; + + while (*s) { + if (*s == '[') + start = s; + else if (*s == ']') + end = s; + + if (start && start < end) { + *end = 0; + parse_queue_param(start + 1, opaque); + s = end; + start = end; + } + s++; + } + + free(f); +} + +static int +parse_sso_kvargs_dict(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ',' + * isn't allowed. Everything is expressed in percentages, 0 represents + * default. + */ + parse_qos_list(value, opaque); + + return 0; +} + static void cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) { @@ -238,6 +314,8 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) rte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value, &dev->xae_cnt); + rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict, + dev); rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 202c6e6a7..b96a6a908 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -14,7 +14,8 @@ #include "roc_api.h" -#define CNXK_SSO_XAE_CNT "xae_cnt" +#define CNXK_SSO_XAE_CNT "xae_cnt" +#define CNXK_SSO_GGRP_QOS "qos" #define USEC2NSEC(__us) ((__us)*1E3) @@ -23,6 +24,13 @@ #define CNXK_SSO_XAQ_CACHE_CNT (0x7) #define CNXK_SSO_XAQ_SLACK (8) +struct cnxk_sso_qos { + uint16_t queue; + uint8_t xaq_prcnt; + uint8_t taq_prcnt; + uint8_t iaq_prcnt; +}; + struct cnxk_sso_evdev { struct roc_sso sso; uint8_t max_event_queues; @@ -41,6 +49,8 @@ struct cnxk_sso_evdev { struct rte_mempool *xaq_pool; /* Dev args */ uint32_t xae_cnt; + uint8_t qos_queue_cnt; + struct cnxk_sso_qos *qos_parse_data; /* CN9K */ uint8_t dual_ws; } __rte_cache_aligned; From patchwork Tue May 4 00:27:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92690 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 572C7A0562; Tue, 4 May 2021 02:29:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5113B4111C; Tue, 4 May 2021 02:28:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 18BE541164 for ; Tue, 4 May 2021 02:28:35 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AUKA002424 for ; Mon, 3 May 2021 17:28:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0CvCilzLAo6P/a+yQnAWloq4vPjOzaMKIvX0KAUIpbs=; b=NtYxUl9qU1coFhKCqwieBK5GYHWMi8p2HMoYgcGE3j3Pq8SIi32JfFQ3jTDSHjxyh9m0 FqgoohIzP64FI2pvtEUJJjEwanznRIGtbeyp458nrAF0eX2/KKZltsVaP8njSauJ0gMj fQUgr/YSsPPY7HzTgvwbyQVhIKhH82Qa1HXGghCelR+Ucyd1BIXIsp+2flHQCA/xvsF3 ew87Yk2EFoeTwPV4bcO3k8af/fH+DeQd0QfHX9t+Z0b2vSNY6jgT44CuoPSJ2yhDlwlH N3gjpWihyUqF/s81U1X5jbFoJ74I8/5ruT6p4e+J+Oj7fIpD1LiVwIb+HHLWamXzYiZD dQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6kg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:32 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id DF59C3F703F; Mon, 3 May 2021 17:28:31 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:02 +0530 Message-ID: <20210504002726.525-13-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 2vK_dBd9KCemmlA4mm_hy83mpuozTitJ X-Proofpoint-ORIG-GUID: 2vK_dBd9KCemmlA4mm_hy83mpuozTitJ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 12/35] event/cnxk: add port config functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add SSO HWS a.k.a event port setup and release functions. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 121 +++++++++++++++++++++++ drivers/event/cnxk/cn9k_eventdev.c | 147 ++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.c | 65 ++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 91 +++++++++++++++++ 4 files changed, 424 insertions(+) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 0b39c6c09..fcdc1cf84 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -4,6 +4,91 @@ #include "cnxk_eventdev.h" +static void +cn10k_init_hws_ops(struct cn10k_sso_hws *ws, uintptr_t base) +{ + ws->tag_wqe_op = base + SSOW_LF_GWS_WQE0; + ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0; + ws->updt_wqe_op = base + SSOW_LF_GWS_OP_UPD_WQP_GRP1; + ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM; + ws->swtag_untag_op = base + SSOW_LF_GWS_OP_SWTAG_UNTAG; + ws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH; + ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED; +} + +static uint32_t +cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev) +{ + uint32_t wdata = BIT(16) | 1; + + switch (dev->gw_mode) { + case CN10K_GW_MODE_NONE: + default: + break; + case CN10K_GW_MODE_PREF: + wdata |= BIT(19); + break; + case CN10K_GW_MODE_PREF_WFE: + wdata |= BIT(20) | BIT(19); + break; + } + + return wdata; +} + +static void * +cn10k_sso_init_hws_mem(void *arg, uint8_t port_id) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn10k_sso_hws *ws; + + /* Allocate event port memory */ + ws = rte_zmalloc("cn10k_ws", + sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE, + RTE_CACHE_LINE_SIZE); + if (ws == NULL) { + plt_err("Failed to alloc memory for port=%d", port_id); + return NULL; + } + + /* First cache line is reserved for cookie */ + ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE); + ws->base = roc_sso_hws_base_get(&dev->sso, port_id); + cn10k_init_hws_ops(ws, ws->base); + ws->hws_id = port_id; + ws->swtag_req = 0; + ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev); + ws->lmt_base = dev->sso.lmt_base; + + return ws; +} + +static void +cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn10k_sso_hws *ws = hws; + uint64_t val; + + rte_memcpy(ws->grps_base, grps_base, + sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); + ws->fc_mem = dev->fc_mem; + ws->xaq_lmt = dev->xaq_lmt; + + /* Set get_work timeout for HWS */ + val = NSEC2USEC(dev->deq_tmo_ns) - 1; + plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM); +} + +static void +cn10k_sso_hws_release(void *arg, void *hws) +{ + struct cn10k_sso_hws *ws = hws; + + RTE_SET_USED(arg); + memset(ws, 0, sizeof(*ws)); +} + static void cn10k_sso_set_rsrc(void *arg) { @@ -59,12 +144,46 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem, + cn10k_sso_hws_setup); + if (rc < 0) + goto cnxk_rsrc_fini; + return 0; cnxk_rsrc_fini: roc_sso_rsrc_fini(&dev->sso); + dev->nb_event_ports = 0; return rc; } +static int +cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, + const struct rte_event_port_conf *port_conf) +{ + + RTE_SET_USED(port_conf); + return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup); +} + +static void +cn10k_sso_port_release(void *port) +{ + struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port); + struct cnxk_sso_evdev *dev; + + if (port == NULL) + return; + + dev = cnxk_sso_pmd_priv(gws_cookie->event_dev); + if (!gws_cookie->configured) + goto free; + + cn10k_sso_hws_release(dev, port); + memset(gws_cookie, 0, sizeof(*gws_cookie)); +free: + rte_free(gws_cookie); +} + static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -72,6 +191,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .queue_setup = cnxk_sso_queue_setup, .queue_release = cnxk_sso_queue_release, .port_def_conf = cnxk_sso_port_def_conf, + .port_setup = cn10k_sso_port_setup, + .port_release = cn10k_sso_port_release, }; static int diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index ab165c850..b8c74633b 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -7,6 +7,63 @@ #define CN9K_DUAL_WS_NB_WS 2 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id) +static void +cn9k_init_hws_ops(struct cn9k_sso_hws_state *ws, uintptr_t base) +{ + ws->tag_op = base + SSOW_LF_GWS_TAG; + ws->wqp_op = base + SSOW_LF_GWS_WQP; + ws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0; + ws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH; + ws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM; + ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED; +} + +static void +cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + uint64_t val; + + /* Set get_work tmo for HWS */ + val = NSEC2USEC(dev->deq_tmo_ns) - 1; + if (dev->dual_ws) { + dws = hws; + rte_memcpy(dws->grps_base, grps_base, + sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); + dws->fc_mem = dev->fc_mem; + dws->xaq_lmt = dev->xaq_lmt; + + plt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM); + plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM); + } else { + ws = hws; + rte_memcpy(ws->grps_base, grps_base, + sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); + ws->fc_mem = dev->fc_mem; + ws->xaq_lmt = dev->xaq_lmt; + + plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM); + } +} + +static void +cn9k_sso_hws_release(void *arg, void *hws) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + + if (dev->dual_ws) { + dws = hws; + memset(dws, 0, sizeof(*dws)); + } else { + ws = hws; + memset(ws, 0, sizeof(*ws)); + } +} + static void cn9k_sso_set_rsrc(void *arg) { @@ -33,6 +90,60 @@ cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp) return roc_sso_rsrc_init(&dev->sso, hws, hwgrp); } +static void * +cn9k_sso_init_hws_mem(void *arg, uint8_t port_id) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + void *data; + + if (dev->dual_ws) { + dws = rte_zmalloc("cn9k_dual_ws", + sizeof(struct cn9k_sso_hws_dual) + + RTE_CACHE_LINE_SIZE, + RTE_CACHE_LINE_SIZE); + if (dws == NULL) { + plt_err("Failed to alloc memory for port=%d", port_id); + return NULL; + } + + dws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie)); + dws->base[0] = roc_sso_hws_base_get( + &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0)); + dws->base[1] = roc_sso_hws_base_get( + &dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1)); + cn9k_init_hws_ops(&dws->ws_state[0], dws->base[0]); + cn9k_init_hws_ops(&dws->ws_state[1], dws->base[1]); + dws->hws_id = port_id; + dws->swtag_req = 0; + dws->vws = 0; + + data = dws; + } else { + /* Allocate event port memory */ + ws = rte_zmalloc("cn9k_ws", + sizeof(struct cn9k_sso_hws) + + RTE_CACHE_LINE_SIZE, + RTE_CACHE_LINE_SIZE); + if (ws == NULL) { + plt_err("Failed to alloc memory for port=%d", port_id); + return NULL; + } + + /* First cache line is reserved for cookie */ + ws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie)); + ws->base = roc_sso_hws_base_get(&dev->sso, port_id); + cn9k_init_hws_ops((struct cn9k_sso_hws_state *)ws, ws->base); + ws->hws_id = port_id; + ws->swtag_req = 0; + + data = ws; + } + + return data; +} + static void cn9k_sso_info_get(struct rte_eventdev *event_dev, struct rte_event_dev_info *dev_info) @@ -67,12 +178,46 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + rc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem, + cn9k_sso_hws_setup); + if (rc < 0) + goto cnxk_rsrc_fini; + return 0; cnxk_rsrc_fini: roc_sso_rsrc_fini(&dev->sso); + dev->nb_event_ports = 0; return rc; } +static int +cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, + const struct rte_event_port_conf *port_conf) +{ + + RTE_SET_USED(port_conf); + return cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup); +} + +static void +cn9k_sso_port_release(void *port) +{ + struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port); + struct cnxk_sso_evdev *dev; + + if (port == NULL) + return; + + dev = cnxk_sso_pmd_priv(gws_cookie->event_dev); + if (!gws_cookie->configured) + goto free; + + cn9k_sso_hws_release(dev, port); + memset(gws_cookie, 0, sizeof(*gws_cookie)); +free: + rte_free(gws_cookie); +} + static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, @@ -80,6 +225,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .queue_setup = cnxk_sso_queue_setup, .queue_release = cnxk_sso_queue_release, .port_def_conf = cnxk_sso_port_def_conf, + .port_setup = cn9k_sso_port_setup, + .port_release = cn9k_sso_port_release, }; static int diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index e93aaccd8..daf24d84a 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -125,6 +125,42 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev) return rc; } +int +cnxk_setup_event_ports(const struct rte_eventdev *event_dev, + cnxk_sso_init_hws_mem_t init_hws_fn, + cnxk_sso_hws_setup_t setup_hws_fn) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int i; + + for (i = 0; i < dev->nb_event_ports; i++) { + struct cnxk_sso_hws_cookie *ws_cookie; + void *ws; + + /* Free memory prior to re-allocation if needed */ + if (event_dev->data->ports[i] != NULL) + ws = event_dev->data->ports[i]; + else + ws = init_hws_fn(dev, i); + if (ws == NULL) + goto hws_fini; + ws_cookie = cnxk_sso_hws_get_cookie(ws); + ws_cookie->event_dev = event_dev; + ws_cookie->configured = 1; + event_dev->data->ports[i] = ws; + cnxk_sso_port_setup((struct rte_eventdev *)(uintptr_t)event_dev, + i, setup_hws_fn); + } + + return 0; +hws_fini: + for (i = i - 1; i >= 0; i--) { + event_dev->data->ports[i] = NULL; + rte_free(cnxk_sso_hws_get_cookie(event_dev->data->ports[i])); + } + return -ENOMEM; +} + int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) { @@ -225,6 +261,35 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, port_conf->enqueue_depth = 1; } +int +cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, + cnxk_sso_hws_setup_t hws_setup_fn) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uintptr_t grps_base[CNXK_SSO_MAX_HWGRP] = {0}; + uint16_t q; + + plt_sso_dbg("Port=%d", port_id); + if (event_dev->data->ports[port_id] == NULL) { + plt_err("Invalid port Id %d", port_id); + return -EINVAL; + } + + for (q = 0; q < dev->nb_event_queues; q++) { + grps_base[q] = roc_sso_hwgrp_base_get(&dev->sso, q); + if (grps_base[q] == 0) { + plt_err("Failed to get grp[%d] base addr", q); + return -EINVAL; + } + } + + hws_setup_fn(dev, event_dev->data->ports[port_id], grps_base); + plt_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]); + rte_mb(); + + return 0; +} + static void parse_queue_param(char *value, void *opaque) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index b96a6a908..79eab1829 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -17,13 +17,23 @@ #define CNXK_SSO_XAE_CNT "xae_cnt" #define CNXK_SSO_GGRP_QOS "qos" +#define NSEC2USEC(__ns) ((__ns) / 1E3) #define USEC2NSEC(__us) ((__us)*1E3) +#define CNXK_SSO_MAX_HWGRP (RTE_EVENT_MAX_QUEUES_PER_DEV + 1) #define CNXK_SSO_FC_NAME "cnxk_evdev_xaq_fc" #define CNXK_SSO_MZ_NAME "cnxk_evdev_mz" #define CNXK_SSO_XAQ_CACHE_CNT (0x7) #define CNXK_SSO_XAQ_SLACK (8) +#define CN10K_GW_MODE_NONE 0 +#define CN10K_GW_MODE_PREF 1 +#define CN10K_GW_MODE_PREF_WFE 2 + +typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id); +typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base); +typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws); + struct cnxk_sso_qos { uint16_t queue; uint8_t xaq_prcnt; @@ -53,6 +63,76 @@ struct cnxk_sso_evdev { struct cnxk_sso_qos *qos_parse_data; /* CN9K */ uint8_t dual_ws; + /* CN10K */ + uint8_t gw_mode; +} __rte_cache_aligned; + +/* CN10K HWS ops */ +#define CN10K_SSO_HWS_OPS \ + uintptr_t swtag_desched_op; \ + uintptr_t swtag_flush_op; \ + uintptr_t swtag_untag_op; \ + uintptr_t swtag_norm_op; \ + uintptr_t updt_wqe_op; \ + uintptr_t tag_wqe_op; \ + uintptr_t getwrk_op + +struct cn10k_sso_hws { + /* Get Work Fastpath data */ + CN10K_SSO_HWS_OPS; + uint32_t gw_wdata; + uint8_t swtag_req; + uint8_t hws_id; + /* Add Work Fastpath data */ + uint64_t xaq_lmt __rte_cache_aligned; + uint64_t *fc_mem; + uintptr_t grps_base[CNXK_SSO_MAX_HWGRP]; + uint64_t base; + uintptr_t lmt_base; +} __rte_cache_aligned; + +/* CN9K HWS ops */ +#define CN9K_SSO_HWS_OPS \ + uintptr_t swtag_desched_op; \ + uintptr_t swtag_flush_op; \ + uintptr_t swtag_norm_op; \ + uintptr_t getwrk_op; \ + uintptr_t tag_op; \ + uintptr_t wqp_op + +/* Event port a.k.a GWS */ +struct cn9k_sso_hws { + /* Get Work Fastpath data */ + CN9K_SSO_HWS_OPS; + uint8_t swtag_req; + uint8_t hws_id; + /* Add Work Fastpath data */ + uint64_t xaq_lmt __rte_cache_aligned; + uint64_t *fc_mem; + uintptr_t grps_base[CNXK_SSO_MAX_HWGRP]; + uint64_t base; +} __rte_cache_aligned; + +struct cn9k_sso_hws_state { + CN9K_SSO_HWS_OPS; +}; + +struct cn9k_sso_hws_dual { + /* Get Work Fastpath data */ + struct cn9k_sso_hws_state ws_state[2]; /* Ping and Pong */ + uint8_t swtag_req; + uint8_t vws; /* Ping pong bit */ + uint8_t hws_id; + /* Add Work Fastpath data */ + uint64_t xaq_lmt __rte_cache_aligned; + uint64_t *fc_mem; + uintptr_t grps_base[CNXK_SSO_MAX_HWGRP]; + uint64_t base[2]; +} __rte_cache_aligned; + +struct cnxk_sso_hws_cookie { + const struct rte_eventdev *event_dev; + bool configured; } __rte_cache_aligned; static inline int @@ -70,6 +150,12 @@ cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) return event_dev->data->dev_private; } +static inline struct cnxk_sso_hws_cookie * +cnxk_sso_hws_get_cookie(void *ws) +{ + return RTE_PTR_SUB(ws, sizeof(struct cnxk_sso_hws_cookie)); +} + /* Configuration functions */ int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev); @@ -80,6 +166,9 @@ int cnxk_sso_remove(struct rte_pci_device *pci_dev); void cnxk_sso_info_get(struct cnxk_sso_evdev *dev, struct rte_event_dev_info *dev_info); int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev); +int cnxk_setup_event_ports(const struct rte_eventdev *event_dev, + cnxk_sso_init_hws_mem_t init_hws_mem, + cnxk_sso_hws_setup_t hws_setup); void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, struct rte_event_queue_conf *queue_conf); int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, @@ -87,5 +176,7 @@ int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id); void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, struct rte_event_port_conf *port_conf); +int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, + cnxk_sso_hws_setup_t hws_setup_fn); #endif /* __CNXK_EVENTDEV_H__ */ From patchwork Tue May 4 00:27:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92691 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F75CA0562; Tue, 4 May 2021 02:29:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE1B041175; Tue, 4 May 2021 02:28:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7343041168 for ; Tue, 4 May 2021 02:28:38 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440P25T025320 for ; Mon, 3 May 2021 17:28:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jU/2bj/lg040KVdWj4Wunhh3j4axtFy1iNF4f+iBrw0=; b=f3o8Yir0Z7NfKR/9VCpbvPsxZ9KD+eQ/5QxA5kaGZOWEUesqUV2sbT8JBIj2rz1snvrb KX+PoRDhldOPEB2i8dO4LTmgiuRJkbdVpPyR0Ry4kOfj/oOpSClhIP+BKGLnVN5dkEik xKyNScBwWm9e+OIHfikwjIegdzlIym76rfQVY5Z+Ro9CG/8GJSdFSFfK1/PkbPN93sB/ PhhzhDTMoOO/Ok8Kcht8ElylFtdoq1ZkVnIFfm3u3gOHB7BWdqMnuaKCcmZPxth03+MY /PxEGA/WG90pbN3gM2t9cNGQqYM4FoamWubRG0v5tO7TxnuDdNtjUIPOc9kXXCxkP4Oo 6A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnpe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:36 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 9A89E3F703F; Mon, 3 May 2021 17:28:34 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:03 +0530 Message-ID: <20210504002726.525-14-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ohHWN9kOcuPG4rYHKG0LWE5hQYl8RfA4 X-Proofpoint-ORIG-GUID: ohHWN9kOcuPG4rYHKG0LWE5hQYl8RfA4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 13/35] event/cnxk: add event port link and unlink X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add platform specific event port, queue link and unlink APIs. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 64 +++++++++++++++++- drivers/event/cnxk/cn9k_eventdev.c | 101 ++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.c | 36 ++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 12 +++- 4 files changed, 210 insertions(+), 3 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index fcdc1cf84..db8fe8169 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -63,6 +63,24 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id) return ws; } +static int +cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn10k_sso_hws *ws = port; + + return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link); +} + +static int +cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn10k_sso_hws *ws = port; + + return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link); +} + static void cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) { @@ -83,9 +101,12 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) static void cn10k_sso_hws_release(void *arg, void *hws) { + struct cnxk_sso_evdev *dev = arg; struct cn10k_sso_hws *ws = hws; + int i; - RTE_SET_USED(arg); + for (i = 0; i < dev->nb_event_queues; i++) + roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1); memset(ws, 0, sizeof(*ws)); } @@ -149,6 +170,12 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + /* Restore any prior port-queue mapping. */ + cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link); + + dev->configured = 1; + rte_mb(); + return 0; cnxk_rsrc_fini: roc_sso_rsrc_fini(&dev->sso); @@ -184,6 +211,38 @@ cn10k_sso_port_release(void *port) rte_free(gws_cookie); } +static int +cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port, + const uint8_t queues[], const uint8_t priorities[], + uint16_t nb_links) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_links]; + uint16_t link; + + RTE_SET_USED(priorities); + for (link = 0; link < nb_links; link++) + hwgrp_ids[link] = queues[link]; + nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links); + + return (int)nb_links; +} + +static int +cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, + uint8_t queues[], uint16_t nb_unlinks) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_unlinks]; + uint16_t unlink; + + for (unlink = 0; unlink < nb_unlinks; unlink++) + hwgrp_ids[unlink] = queues[unlink]; + nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks); + + return (int)nb_unlinks; +} + static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -193,6 +252,9 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .port_def_conf = cnxk_sso_port_def_conf, .port_setup = cn10k_sso_port_setup, .port_release = cn10k_sso_port_release, + .port_link = cn10k_sso_port_link, + .port_unlink = cn10k_sso_port_unlink, + .timeout_ticks = cnxk_sso_timeout_ticks, }; static int diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index b8c74633b..a0d76335f 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -18,6 +18,54 @@ cn9k_init_hws_ops(struct cn9k_sso_hws_state *ws, uintptr_t base) ws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED; } +static int +cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + int rc; + + if (dev->dual_ws) { + dws = port; + rc = roc_sso_hws_link(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map, + nb_link); + rc |= roc_sso_hws_link(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), + map, nb_link); + } else { + ws = port; + rc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link); + } + + return rc; +} + +static int +cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + int rc; + + if (dev->dual_ws) { + dws = port; + rc = roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), + map, nb_link); + rc |= roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), + map, nb_link); + } else { + ws = port; + rc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link); + } + + return rc; +} + static void cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) { @@ -54,12 +102,24 @@ cn9k_sso_hws_release(void *arg, void *hws) struct cnxk_sso_evdev *dev = arg; struct cn9k_sso_hws_dual *dws; struct cn9k_sso_hws *ws; + int i; if (dev->dual_ws) { dws = hws; + for (i = 0; i < dev->nb_event_queues; i++) { + roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), + (uint16_t *)&i, 1); + roc_sso_hws_unlink(&dev->sso, + CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), + (uint16_t *)&i, 1); + } memset(dws, 0, sizeof(*dws)); } else { ws = hws; + for (i = 0; i < dev->nb_event_queues; i++) + roc_sso_hws_unlink(&dev->sso, ws->hws_id, + (uint16_t *)&i, 1); memset(ws, 0, sizeof(*ws)); } } @@ -183,6 +243,12 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + /* Restore any prior port-queue mapping. */ + cnxk_sso_restore_links(event_dev, cn9k_sso_hws_link); + + dev->configured = 1; + rte_mb(); + return 0; cnxk_rsrc_fini: roc_sso_rsrc_fini(&dev->sso); @@ -218,6 +284,38 @@ cn9k_sso_port_release(void *port) rte_free(gws_cookie); } +static int +cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port, + const uint8_t queues[], const uint8_t priorities[], + uint16_t nb_links) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_links]; + uint16_t link; + + RTE_SET_USED(priorities); + for (link = 0; link < nb_links; link++) + hwgrp_ids[link] = queues[link]; + nb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links); + + return (int)nb_links; +} + +static int +cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, + uint8_t queues[], uint16_t nb_unlinks) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_unlinks]; + uint16_t unlink; + + for (unlink = 0; unlink < nb_unlinks; unlink++) + hwgrp_ids[unlink] = queues[unlink]; + nb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks); + + return (int)nb_unlinks; +} + static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, @@ -227,6 +325,9 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .port_def_conf = cnxk_sso_port_def_conf, .port_setup = cn9k_sso_port_setup, .port_release = cn9k_sso_port_release, + .port_link = cn9k_sso_port_link, + .port_unlink = cn9k_sso_port_unlink, + .timeout_ticks = cnxk_sso_timeout_ticks, }; static int diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index daf24d84a..e68079997 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -161,6 +161,32 @@ cnxk_setup_event_ports(const struct rte_eventdev *event_dev, return -ENOMEM; } +void +cnxk_sso_restore_links(const struct rte_eventdev *event_dev, + cnxk_sso_link_t link_fn) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t *links_map, hwgrp[CNXK_SSO_MAX_HWGRP]; + int i, j; + + for (i = 0; i < dev->nb_event_ports; i++) { + uint16_t nb_hwgrp = 0; + + links_map = event_dev->data->links_map; + /* Point links_map to this port specific area */ + links_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV); + + for (j = 0; j < dev->nb_event_queues; j++) { + if (links_map[j] == 0xdead) + continue; + hwgrp[nb_hwgrp] = j; + nb_hwgrp++; + } + + link_fn(dev, event_dev->data->ports[i], hwgrp, nb_hwgrp); + } +} + int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev) { @@ -290,6 +316,16 @@ cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, return 0; } +int +cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, + uint64_t *tmo_ticks) +{ + RTE_SET_USED(event_dev); + *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz()); + + return 0; +} + static void parse_queue_param(char *value, void *opaque) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 79eab1829..97a944d88 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -17,8 +17,9 @@ #define CNXK_SSO_XAE_CNT "xae_cnt" #define CNXK_SSO_GGRP_QOS "qos" -#define NSEC2USEC(__ns) ((__ns) / 1E3) -#define USEC2NSEC(__us) ((__us)*1E3) +#define NSEC2USEC(__ns) ((__ns) / 1E3) +#define USEC2NSEC(__us) ((__us)*1E3) +#define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9) #define CNXK_SSO_MAX_HWGRP (RTE_EVENT_MAX_QUEUES_PER_DEV + 1) #define CNXK_SSO_FC_NAME "cnxk_evdev_xaq_fc" @@ -33,6 +34,8 @@ typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id); typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base); typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws); +typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map, + uint16_t nb_link); struct cnxk_sso_qos { uint16_t queue; @@ -48,6 +51,7 @@ struct cnxk_sso_evdev { uint8_t is_timeout_deq; uint8_t nb_event_queues; uint8_t nb_event_ports; + uint8_t configured; uint32_t deq_tmo_ns; uint32_t min_dequeue_timeout_ns; uint32_t max_dequeue_timeout_ns; @@ -169,6 +173,8 @@ int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev); int cnxk_setup_event_ports(const struct rte_eventdev *event_dev, cnxk_sso_init_hws_mem_t init_hws_mem, cnxk_sso_hws_setup_t hws_setup); +void cnxk_sso_restore_links(const struct rte_eventdev *event_dev, + cnxk_sso_link_t link_fn); void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, struct rte_event_queue_conf *queue_conf); int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, @@ -178,5 +184,7 @@ void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, struct rte_event_port_conf *port_conf); int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, cnxk_sso_hws_setup_t hws_setup_fn); +int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, + uint64_t *tmo_ticks); #endif /* __CNXK_EVENTDEV_H__ */ From patchwork Tue May 4 00:27:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92692 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0CF84A0562; Tue, 4 May 2021 02:29:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2D175410FC; Tue, 4 May 2021 02:28:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 90318410FC for ; Tue, 4 May 2021 02:28:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGT3002336 for ; Mon, 3 May 2021 17:28:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZtwybFIqgn5LjLYgz4YhRDpvRrTuXcuxUEwLCdvo5ec=; b=BimMmz2Mzl6OZADl3G1HdtnMlq7NhNZBuTQDgACiqvIFNKywzbCh1gyczkpR+48mNSOG tULTMRIb27RWHK7pdwqonaFcIhluEcMk+Xh6digCCTPrOjm0R0KyBFu29IldJA3dqU0y vDtFsBcj2dFHaJbxmP8iO6RTZfYuS70nUAAZReyE32xPtYZli0l4vCRHeY5X5fDiy8oM fqKffJ6GvhHXC4qxW9LlQ3P3LLuss3YGz2B2Mx1zbX4N5bu7+DE1GucgsSJ/jG1R9twI ZkYZSITSR9GfRfxNCrdt5G/QIaXO/HSuSyuKc3WFdBnLJoZD7R4vmA5ahe4ltpKK9xsc Aw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6kn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:40 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:38 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 90A6A3F703F; Mon, 3 May 2021 17:28:37 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:04 +0530 Message-ID: <20210504002726.525-15-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: eK31LLDc2sAKVNERgKJKxfRb3HLmlFMY X-Proofpoint-ORIG-GUID: eK31LLDc2sAKVNERgKJKxfRb3HLmlFMY X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 14/35] event/cnxk: add devargs to configure getwork mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add devargs to configure the platform specific getwork mode. CN9K getwork mode by default is set to use dual workslot mode. Add option to force single workslot mode. Example: --dev "0002:0e:00.0,single_ws=1" CN10K supports multiple getwork prefetch modes, by default the prefetch mode is set to none. Add option to select getwork prefetch mode Example: --dev "0002:1e:00.0,gw_mode=1" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 18 ++++++++++++++++++ drivers/event/cnxk/cn10k_eventdev.c | 3 ++- drivers/event/cnxk/cn9k_eventdev.c | 3 ++- drivers/event/cnxk/cnxk_eventdev.c | 6 ++++++ drivers/event/cnxk/cnxk_eventdev.h | 6 ++++-- 5 files changed, 32 insertions(+), 4 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index 0583e5fdd..f48452982 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -55,6 +55,24 @@ Runtime Config Options -a 0002:0e:00.0,xae_cnt=16384 +- ``CN9K Getwork mode`` + + CN9K ``single_ws`` devargs parameter is introduced to select single workslot + mode in SSO and disable the default dual workslot mode. + + For example:: + + -a 0002:0e:00.0,single_ws=1 + +- ``CN10K Getwork mode`` + + CN10K supports multiple getwork prefetch modes, by default the prefetch + mode is set to none. + + For example:: + + -a 0002:0e:00.0,gw_mode=1 + - ``Event Group QoS support`` SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index db8fe8169..6522351ca 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -327,4 +327,5 @@ RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" - CNXK_SSO_GGRP_QOS "="); + CNXK_SSO_GGRP_QOS "=" + CN10K_SSO_GW_MODE "="); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index a0d76335f..00c5565e7 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -395,4 +395,5 @@ RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" - CNXK_SSO_GGRP_QOS "="); + CNXK_SSO_GGRP_QOS "=" + CN9K_SSO_SINGLE_WS "=1"); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index e68079997..2a387ff95 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -406,6 +406,7 @@ static void cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) { struct rte_kvargs *kvlist; + uint8_t single_ws = 0; if (devargs == NULL) return; @@ -417,6 +418,11 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) &dev->xae_cnt); rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict, dev); + rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_value, + &single_ws); + rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value, + &dev->gw_mode); + dev->dual_ws = !single_ws; rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 97a944d88..437cdf3db 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -14,8 +14,10 @@ #include "roc_api.h" -#define CNXK_SSO_XAE_CNT "xae_cnt" -#define CNXK_SSO_GGRP_QOS "qos" +#define CNXK_SSO_XAE_CNT "xae_cnt" +#define CNXK_SSO_GGRP_QOS "qos" +#define CN9K_SSO_SINGLE_WS "single_ws" +#define CN10K_SSO_GW_MODE "gw_mode" #define NSEC2USEC(__ns) ((__ns) / 1E3) #define USEC2NSEC(__us) ((__us)*1E3) From patchwork Tue May 4 00:27:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92693 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E440BA0562; Tue, 4 May 2021 02:29:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 624EF4117D; Tue, 4 May 2021 02:28:45 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id F2E624116E for ; Tue, 4 May 2021 02:28:43 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440QWsr026649 for ; Mon, 3 May 2021 17:28:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=EGr+AreJiWXOdC4brM4IUjn7GvxBYST1fsm+Fm3pg0g=; b=MWbA0/Xh4hGO+TzfSaeZdy+/65aWeqalwYKHdbAie5RgsSbhcpB4HIRfnGm6c7h1Q4Jw v4EHTdSdCVyjWXDlK7Nh4Rl48Sdb430bRTkv3uUj/9rY2OaksTla35u9u9JF7Yhe/yH+ 4YuhMBGMVyg94i9dB12rSULD3t3YaothcdaGjpklWl6BlGq1RNoGM/1YAemTXdNPeW6t s8EG+LeXTOERzq8snif4B1LYPhy6LJYDzDcoSEzeRfD5RYszmOn/+sgZ5/SlS1XyBPXa DjgIs/2/DxSW5HPVSM/gpHSOJz1YSFwKTM44U2wuG+edfIw0djjGPz8ybLFugdAEAF// ig== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnpr-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:43 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:42 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 6DFB43F703F; Mon, 3 May 2021 17:28:40 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:05 +0530 Message-ID: <20210504002726.525-16-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: lcdmbbj_MCEbx1uEMRTvbqC6RLNBv8NH X-Proofpoint-ORIG-GUID: lcdmbbj_MCEbx1uEMRTvbqC6RLNBv8NH X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 15/35] event/cnxk: add SSO HW device operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add SSO HW device operations used for enqueue/dequeue. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_worker.c | 7 + drivers/event/cnxk/cn10k_worker.h | 151 +++++++++++++++++ drivers/event/cnxk/cn9k_worker.c | 7 + drivers/event/cnxk/cn9k_worker.h | 249 +++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 10 ++ drivers/event/cnxk/cnxk_worker.h | 101 ++++++++++++ drivers/event/cnxk/meson.build | 4 +- 7 files changed, 528 insertions(+), 1 deletion(-) create mode 100644 drivers/event/cnxk/cn10k_worker.c create mode 100644 drivers/event/cnxk/cn10k_worker.h create mode 100644 drivers/event/cnxk/cn9k_worker.c create mode 100644 drivers/event/cnxk/cn9k_worker.h create mode 100644 drivers/event/cnxk/cnxk_worker.h diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c new file mode 100644 index 000000000..63b587301 --- /dev/null +++ b/drivers/event/cnxk/cn10k_worker.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cn10k_worker.h" +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h new file mode 100644 index 000000000..04517055d --- /dev/null +++ b/drivers/event/cnxk/cn10k_worker.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CN10K_WORKER_H__ +#define __CN10K_WORKER_H__ + +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +/* SSO Operations */ + +static __rte_always_inline uint8_t +cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev) +{ + const uint32_t tag = (uint32_t)ev->event; + const uint8_t new_tt = ev->sched_type; + const uint64_t event_ptr = ev->u64; + const uint16_t grp = ev->queue_id; + + rte_atomic_thread_fence(__ATOMIC_ACQ_REL); + if (ws->xaq_lmt <= *ws->fc_mem) + return 0; + + cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]); + return 1; +} + +static __rte_always_inline void +cn10k_sso_hws_fwd_swtag(struct cn10k_sso_hws *ws, const struct rte_event *ev) +{ + const uint32_t tag = (uint32_t)ev->event; + const uint8_t new_tt = ev->sched_type; + const uint8_t cur_tt = CNXK_TT_FROM_TAG(plt_read64(ws->tag_wqe_op)); + + /* CNXK model + * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED + * + * SSO_TT_ORDERED norm norm untag + * SSO_TT_ATOMIC norm norm untag + * SSO_TT_UNTAGGED norm norm NOOP + */ + + if (new_tt == SSO_TT_UNTAGGED) { + if (cur_tt != SSO_TT_UNTAGGED) + cnxk_sso_hws_swtag_untag(ws->swtag_untag_op); + } else { + cnxk_sso_hws_swtag_norm(tag, new_tt, ws->swtag_norm_op); + } + ws->swtag_req = 1; +} + +static __rte_always_inline void +cn10k_sso_hws_fwd_group(struct cn10k_sso_hws *ws, const struct rte_event *ev, + const uint16_t grp) +{ + const uint32_t tag = (uint32_t)ev->event; + const uint8_t new_tt = ev->sched_type; + + plt_write64(ev->u64, ws->updt_wqe_op); + cnxk_sso_hws_swtag_desched(tag, new_tt, grp, ws->swtag_desched_op); +} + +static __rte_always_inline void +cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws, + const struct rte_event *ev) +{ + const uint8_t grp = ev->queue_id; + + /* Group hasn't changed, Use SWTAG to forward the event */ + if (CNXK_GRP_FROM_TAG(plt_read64(ws->tag_wqe_op)) == grp) + cn10k_sso_hws_fwd_swtag(ws, ev); + else + /* + * Group has been changed for group based work pipelining, + * Use deschedule/add_work operation to transfer the event to + * new group/core + */ + cn10k_sso_hws_fwd_group(ws, ev, grp); +} + +static __rte_always_inline uint16_t +cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev) +{ + union { + __uint128_t get_work; + uint64_t u64[2]; + } gw; + + gw.get_work = ws->gw_wdata; +#if defined(RTE_ARCH_ARM64) && !defined(__clang__) + asm volatile( + PLT_CPU_FEATURE_PREAMBLE + "caspl %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n" + : [wdata] "+r"(gw.get_work) + : [gw_loc] "r"(ws->getwrk_op) + : "memory"); +#else + plt_write64(gw.u64[0], ws->getwrk_op); + do { + roc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op); + } while (gw.u64[0] & BIT_ULL(63)); +#endif + gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 | + (gw.u64[0] & (0x3FFull << 36)) << 4 | + (gw.u64[0] & 0xffffffff); + + ev->event = gw.u64[0]; + ev->u64 = gw.u64[1]; + + return !!gw.u64[1]; +} + +/* Used in cleaning up workslot. */ +static __rte_always_inline uint16_t +cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev) +{ + union { + __uint128_t get_work; + uint64_t u64[2]; + } gw; + +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldp %[tag], %[wqp], [%[tag_loc]] \n" + " tbz %[tag], 63, done%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldp %[tag], %[wqp], [%[tag_loc]] \n" + " tbnz %[tag], 63, rty%= \n" + "done%=: dmb ld \n" + : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]) + : [tag_loc] "r"(ws->tag_wqe_op) + : "memory"); +#else + do { + roc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op); + } while (gw.u64[0] & BIT_ULL(63)); +#endif + + gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 | + (gw.u64[0] & (0x3FFull << 36)) << 4 | + (gw.u64[0] & 0xffffffff); + + ev->event = gw.u64[0]; + ev->u64 = gw.u64[1]; + + return !!gw.u64[1]; +} + +#endif diff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c new file mode 100644 index 000000000..836914163 --- /dev/null +++ b/drivers/event/cnxk/cn9k_worker.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" + +#include "cn9k_worker.h" diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h new file mode 100644 index 000000000..85be742c1 --- /dev/null +++ b/drivers/event/cnxk/cn9k_worker.h @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CN9K_WORKER_H__ +#define __CN9K_WORKER_H__ + +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +/* SSO Operations */ + +static __rte_always_inline uint8_t +cn9k_sso_hws_new_event(struct cn9k_sso_hws *ws, const struct rte_event *ev) +{ + const uint32_t tag = (uint32_t)ev->event; + const uint8_t new_tt = ev->sched_type; + const uint64_t event_ptr = ev->u64; + const uint16_t grp = ev->queue_id; + + rte_atomic_thread_fence(__ATOMIC_ACQ_REL); + if (ws->xaq_lmt <= *ws->fc_mem) + return 0; + + cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]); + return 1; +} + +static __rte_always_inline void +cn9k_sso_hws_fwd_swtag(struct cn9k_sso_hws_state *vws, + const struct rte_event *ev) +{ + const uint32_t tag = (uint32_t)ev->event; + const uint8_t new_tt = ev->sched_type; + const uint8_t cur_tt = CNXK_TT_FROM_TAG(plt_read64(vws->tag_op)); + + /* CNXK model + * cur_tt/new_tt SSO_TT_ORDERED SSO_TT_ATOMIC SSO_TT_UNTAGGED + * + * SSO_TT_ORDERED norm norm untag + * SSO_TT_ATOMIC norm norm untag + * SSO_TT_UNTAGGED norm norm NOOP + */ + + if (new_tt == SSO_TT_UNTAGGED) { + if (cur_tt != SSO_TT_UNTAGGED) + cnxk_sso_hws_swtag_untag( + CN9K_SSOW_GET_BASE_ADDR(vws->getwrk_op) + + SSOW_LF_GWS_OP_SWTAG_UNTAG); + } else { + cnxk_sso_hws_swtag_norm(tag, new_tt, vws->swtag_norm_op); + } +} + +static __rte_always_inline void +cn9k_sso_hws_fwd_group(struct cn9k_sso_hws_state *ws, + const struct rte_event *ev, const uint16_t grp) +{ + const uint32_t tag = (uint32_t)ev->event; + const uint8_t new_tt = ev->sched_type; + + plt_write64(ev->u64, CN9K_SSOW_GET_BASE_ADDR(ws->getwrk_op) + + SSOW_LF_GWS_OP_UPD_WQP_GRP1); + cnxk_sso_hws_swtag_desched(tag, new_tt, grp, ws->swtag_desched_op); +} + +static __rte_always_inline void +cn9k_sso_hws_forward_event(struct cn9k_sso_hws *ws, const struct rte_event *ev) +{ + const uint8_t grp = ev->queue_id; + + /* Group hasn't changed, Use SWTAG to forward the event */ + if (CNXK_GRP_FROM_TAG(plt_read64(ws->tag_op)) == grp) { + cn9k_sso_hws_fwd_swtag((struct cn9k_sso_hws_state *)ws, ev); + ws->swtag_req = 1; + } else { + /* + * Group has been changed for group based work pipelining, + * Use deschedule/add_work operation to transfer the event to + * new group/core + */ + cn9k_sso_hws_fwd_group((struct cn9k_sso_hws_state *)ws, ev, + grp); + } +} + +/* Dual ws ops. */ + +static __rte_always_inline uint8_t +cn9k_sso_hws_dual_new_event(struct cn9k_sso_hws_dual *dws, + const struct rte_event *ev) +{ + const uint32_t tag = (uint32_t)ev->event; + const uint8_t new_tt = ev->sched_type; + const uint64_t event_ptr = ev->u64; + const uint16_t grp = ev->queue_id; + + rte_atomic_thread_fence(__ATOMIC_ACQ_REL); + if (dws->xaq_lmt <= *dws->fc_mem) + return 0; + + cnxk_sso_hws_add_work(event_ptr, tag, new_tt, dws->grps_base[grp]); + return 1; +} + +static __rte_always_inline void +cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws, + struct cn9k_sso_hws_state *vws, + const struct rte_event *ev) +{ + const uint8_t grp = ev->queue_id; + + /* Group hasn't changed, Use SWTAG to forward the event */ + if (CNXK_GRP_FROM_TAG(plt_read64(vws->tag_op)) == grp) { + cn9k_sso_hws_fwd_swtag(vws, ev); + dws->swtag_req = 1; + } else { + /* + * Group has been changed for group based work pipelining, + * Use deschedule/add_work operation to transfer the event to + * new group/core + */ + cn9k_sso_hws_fwd_group(vws, ev, grp); + } +} + +static __rte_always_inline uint16_t +cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws, + struct cn9k_sso_hws_state *ws_pair, + struct rte_event *ev) +{ + const uint64_t set_gw = BIT_ULL(16) | 1; + union { + __uint128_t get_work; + uint64_t u64[2]; + } gw; + +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + "rty%=: \n" + " ldr %[tag], [%[tag_loc]] \n" + " ldr %[wqp], [%[wqp_loc]] \n" + " tbnz %[tag], 63, rty%= \n" + "done%=: str %[gw], [%[pong]] \n" + " dmb ld \n" + : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]) + : [tag_loc] "r"(ws->tag_op), [wqp_loc] "r"(ws->wqp_op), + [gw] "r"(set_gw), [pong] "r"(ws_pair->getwrk_op)); +#else + gw.u64[0] = plt_read64(ws->tag_op); + while ((BIT_ULL(63)) & gw.u64[0]) + gw.u64[0] = plt_read64(ws->tag_op); + gw.u64[1] = plt_read64(ws->wqp_op); + plt_write64(set_gw, ws_pair->getwrk_op); +#endif + + gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 | + (gw.u64[0] & (0x3FFull << 36)) << 4 | + (gw.u64[0] & 0xffffffff); + + ev->event = gw.u64[0]; + ev->u64 = gw.u64[1]; + + return !!gw.u64[1]; +} + +static __rte_always_inline uint16_t +cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev) +{ + union { + __uint128_t get_work; + uint64_t u64[2]; + } gw; + + plt_write64(BIT_ULL(16) | /* wait for work. */ + 1, /* Use Mask set 0. */ + ws->getwrk_op); +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldr %[tag], [%[tag_loc]] \n" + " ldr %[wqp], [%[wqp_loc]] \n" + " tbz %[tag], 63, done%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldr %[tag], [%[tag_loc]] \n" + " ldr %[wqp], [%[wqp_loc]] \n" + " tbnz %[tag], 63, rty%= \n" + "done%=: dmb ld \n" + : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]) + : [tag_loc] "r"(ws->tag_op), [wqp_loc] "r"(ws->wqp_op)); +#else + gw.u64[0] = plt_read64(ws->tag_op); + while ((BIT_ULL(63)) & gw.u64[0]) + gw.u64[0] = plt_read64(ws->tag_op); + + gw.u64[1] = plt_read64(ws->wqp_op); +#endif + + gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 | + (gw.u64[0] & (0x3FFull << 36)) << 4 | + (gw.u64[0] & 0xffffffff); + + ev->event = gw.u64[0]; + ev->u64 = gw.u64[1]; + + return !!gw.u64[1]; +} + +/* Used in cleaning up workslot. */ +static __rte_always_inline uint16_t +cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev) +{ + union { + __uint128_t get_work; + uint64_t u64[2]; + } gw; + +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldr %[tag], [%[tag_loc]] \n" + " ldr %[wqp], [%[wqp_loc]] \n" + " tbz %[tag], 63, done%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldr %[tag], [%[tag_loc]] \n" + " ldr %[wqp], [%[wqp_loc]] \n" + " tbnz %[tag], 63, rty%= \n" + "done%=: dmb ld \n" + : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]) + : [tag_loc] "r"(ws->tag_op), [wqp_loc] "r"(ws->wqp_op)); +#else + gw.u64[0] = plt_read64(ws->tag_op); + while ((BIT_ULL(63)) & gw.u64[0]) + gw.u64[0] = plt_read64(ws->tag_op); + + gw.u64[1] = plt_read64(ws->wqp_op); +#endif + + gw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 | + (gw.u64[0] & (0x3FFull << 36)) << 4 | + (gw.u64[0] & 0xffffffff); + + ev->event = gw.u64[0]; + ev->u64 = gw.u64[1]; + + return !!gw.u64[1]; +} + +#endif diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 437cdf3db..0a3ab71e4 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -29,6 +29,16 @@ #define CNXK_SSO_XAQ_CACHE_CNT (0x7) #define CNXK_SSO_XAQ_SLACK (8) +#define CNXK_TT_FROM_TAG(x) (((x) >> 32) & SSO_TT_EMPTY) +#define CNXK_TT_FROM_EVENT(x) (((x) >> 38) & SSO_TT_EMPTY) +#define CNXK_EVENT_TYPE_FROM_TAG(x) (((x) >> 28) & 0xf) +#define CNXK_SUB_EVENT_FROM_TAG(x) (((x) >> 20) & 0xff) +#define CNXK_CLR_SUB_EVENT(x) (~(0xffu << 20) & x) +#define CNXK_GRP_FROM_TAG(x) (((x) >> 36) & 0x3ff) +#define CNXK_SWTAG_PEND(x) (BIT_ULL(62) & x) + +#define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0) + #define CN10K_GW_MODE_NONE 0 #define CN10K_GW_MODE_PREF 1 #define CN10K_GW_MODE_PREF_WFE 2 diff --git a/drivers/event/cnxk/cnxk_worker.h b/drivers/event/cnxk/cnxk_worker.h new file mode 100644 index 000000000..4eb46ae16 --- /dev/null +++ b/drivers/event/cnxk/cnxk_worker.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CNXK_WORKER_H__ +#define __CNXK_WORKER_H__ + +#include "cnxk_eventdev.h" + +/* SSO Operations */ + +static __rte_always_inline void +cnxk_sso_hws_add_work(const uint64_t event_ptr, const uint32_t tag, + const uint8_t new_tt, const uintptr_t grp_base) +{ + uint64_t add_work0; + + add_work0 = tag | ((uint64_t)(new_tt) << 32); + roc_store_pair(add_work0, event_ptr, grp_base); +} + +static __rte_always_inline void +cnxk_sso_hws_swtag_desched(uint32_t tag, uint8_t new_tt, uint16_t grp, + uintptr_t swtag_desched_op) +{ + uint64_t val; + + val = tag | ((uint64_t)(new_tt & 0x3) << 32) | ((uint64_t)grp << 34); + __atomic_store_n((uint64_t *)swtag_desched_op, val, __ATOMIC_RELEASE); +} + +static __rte_always_inline void +cnxk_sso_hws_swtag_norm(uint32_t tag, uint8_t new_tt, uintptr_t swtag_norm_op) +{ + uint64_t val; + + val = tag | ((uint64_t)(new_tt & 0x3) << 32); + plt_write64(val, swtag_norm_op); +} + +static __rte_always_inline void +cnxk_sso_hws_swtag_untag(uintptr_t swtag_untag_op) +{ + plt_write64(0, swtag_untag_op); +} + +static __rte_always_inline void +cnxk_sso_hws_swtag_flush(uint64_t tag_op, uint64_t flush_op) +{ + if (CNXK_TT_FROM_TAG(plt_read64(tag_op)) == SSO_TT_EMPTY) + return; + plt_write64(0, flush_op); +} + +static __rte_always_inline void +cnxk_sso_hws_swtag_wait(uintptr_t tag_op) +{ +#ifdef RTE_ARCH_ARM64 + uint64_t swtp; + + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldr %[swtb], [%[swtp_loc]] \n" + " tbz %[swtb], 62, done%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldr %[swtb], [%[swtp_loc]] \n" + " tbnz %[swtb], 62, rty%= \n" + "done%=: \n" + : [swtb] "=&r"(swtp) + : [swtp_loc] "r"(tag_op)); +#else + /* Wait for the SWTAG/SWTAG_FULL operation */ + while (plt_read64(tag_op) & BIT_ULL(62)) + ; +#endif +} + +static __rte_always_inline void +cnxk_sso_hws_head_wait(uintptr_t tag_op) +{ +#ifdef RTE_ARCH_ARM64 + uint64_t swtp; + + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldr %[swtb], [%[swtp_loc]] \n" + " tbz %[swtb], 35, done%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldr %[swtb], [%[swtp_loc]] \n" + " tbnz %[swtb], 35, rty%= \n" + "done%=: \n" + : [swtb] "=&r"(swtp) + : [swtp_loc] "r"(tag_op)); +#else + /* Wait for the SWTAG/SWTAG_FULL operation */ + while (plt_read64(tag_op) & BIT_ULL(35)) + ; +#endif +} + +#endif diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index 22eb28345..57b3f66ea 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -8,7 +8,9 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64') subdir_done() endif -sources = files('cn10k_eventdev.c', +sources = files('cn10k_worker.c', + 'cn10k_eventdev.c', + 'cn9k_worker.c', 'cn9k_eventdev.c', 'cnxk_eventdev.c', ) From patchwork Tue May 4 00:27:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92694 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C0FD8A0562; Tue, 4 May 2021 02:29:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E724E41181; Tue, 4 May 2021 02:28:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4C790410F3 for ; Tue, 4 May 2021 02:28:47 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OuhZ025154; Mon, 3 May 2021 17:28:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=PXPg161LfuF16O6MjhImUdHZ0DCiKB4Pvi4fVexjLkE=; b=gpnjOQY3ruCQq4vvvPu8NxKw/XSqSdrK1rdT/Wcz/gNw9K4iwpCyTBeC6xXKRPiLGQbP xZ7iwjBDtQxB8OTOM5BSfjtiLphPuJmApHiZdvPFXQp9biBEANVqJ2crP0BACjQeAYyx KjP5K5TJwD4M+xL6AZLMUgmKOQ2rY7L+JhXl3mn66VnvehcbxfB/tEAQaLQBJUWU+spR nA/PJHT+gtXus6fTKZ1DV5WPPa1jA+w+Mp2moZurVQOMEgYqHdZGobJaGMKgrf0bvN6c JrfNCOAr9W4rTfya+pgbgh5DnKYqJC67iw3t1dSM35/IwyKpAPo4HIBXmwSOHU87wcOi BQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnq8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 03 May 2021 17:28:46 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:44 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 35F663F703F; Mon, 3 May 2021 17:28:42 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" , Anatoly Burakov CC: Date: Tue, 4 May 2021 05:57:06 +0530 Message-ID: <20210504002726.525-17-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: XUhFFZCm4c035EQtmlcNDg2fKtFfSxZS X-Proofpoint-ORIG-GUID: XUhFFZCm4c035EQtmlcNDg2fKtFfSxZS X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 16/35] event/cnxk: add SSO GWS fastpath enqueue functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add SSO GWS fastpath event device enqueue functions. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 16 +++- drivers/event/cnxk/cn10k_worker.c | 54 ++++++++++++++ drivers/event/cnxk/cn10k_worker.h | 12 +++ drivers/event/cnxk/cn9k_eventdev.c | 25 ++++++- drivers/event/cnxk/cn9k_worker.c | 112 ++++++++++++++++++++++++++++ drivers/event/cnxk/cn9k_worker.h | 24 ++++++ 6 files changed, 241 insertions(+), 2 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 6522351ca..a1b44744b 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -2,7 +2,9 @@ * Copyright(C) 2021 Marvell. */ +#include "cn10k_worker.h" #include "cnxk_eventdev.h" +#include "cnxk_worker.h" static void cn10k_init_hws_ops(struct cn10k_sso_hws *ws, uintptr_t base) @@ -130,6 +132,16 @@ cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp) return roc_sso_rsrc_init(&dev->sso, hws, hwgrp); } +static void +cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) +{ + PLT_SET_USED(event_dev); + event_dev->enqueue = cn10k_sso_hws_enq; + event_dev->enqueue_burst = cn10k_sso_hws_enq_burst; + event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst; + event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst; +} + static void cn10k_sso_info_get(struct rte_eventdev *event_dev, struct rte_event_dev_info *dev_info) @@ -276,8 +288,10 @@ cn10k_sso_init(struct rte_eventdev *event_dev) event_dev->dev_ops = &cn10k_sso_dev_ops; /* For secondary processes, the primary has done all the work */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + cn10k_sso_fp_fns_set(event_dev); return 0; + } rc = cnxk_sso_init(event_dev); if (rc < 0) diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c index 63b587301..9b5cb7be6 100644 --- a/drivers/event/cnxk/cn10k_worker.c +++ b/drivers/event/cnxk/cn10k_worker.c @@ -5,3 +5,57 @@ #include "cn10k_worker.h" #include "cnxk_eventdev.h" #include "cnxk_worker.h" + +uint16_t __rte_hot +cn10k_sso_hws_enq(void *port, const struct rte_event *ev) +{ + struct cn10k_sso_hws *ws = port; + + switch (ev->op) { + case RTE_EVENT_OP_NEW: + return cn10k_sso_hws_new_event(ws, ev); + case RTE_EVENT_OP_FORWARD: + cn10k_sso_hws_forward_event(ws, ev); + break; + case RTE_EVENT_OP_RELEASE: + cnxk_sso_hws_swtag_flush(ws->tag_wqe_op, ws->swtag_flush_op); + break; + default: + return 0; + } + + return 1; +} + +uint16_t __rte_hot +cn10k_sso_hws_enq_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + RTE_SET_USED(nb_events); + return cn10k_sso_hws_enq(port, ev); +} + +uint16_t __rte_hot +cn10k_sso_hws_enq_new_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + struct cn10k_sso_hws *ws = port; + uint16_t i, rc = 1; + + for (i = 0; i < nb_events && rc; i++) + rc = cn10k_sso_hws_new_event(ws, &ev[i]); + + return nb_events; +} + +uint16_t __rte_hot +cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + struct cn10k_sso_hws *ws = port; + + RTE_SET_USED(nb_events); + cn10k_sso_hws_forward_event(ws, ev); + + return 1; +} diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 04517055d..48158b320 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -148,4 +148,16 @@ cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev) return !!gw.u64[1]; } +/* CN10K Fastpath functions. */ +uint16_t __rte_hot cn10k_sso_hws_enq(void *port, const struct rte_event *ev); +uint16_t __rte_hot cn10k_sso_hws_enq_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); +uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); +uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); + #endif diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 00c5565e7..61a4d0823 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -2,7 +2,9 @@ * Copyright(C) 2021 Marvell. */ +#include "cn9k_worker.h" #include "cnxk_eventdev.h" +#include "cnxk_worker.h" #define CN9K_DUAL_WS_NB_WS 2 #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id) @@ -150,6 +152,25 @@ cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp) return roc_sso_rsrc_init(&dev->sso, hws, hwgrp); } +static void +cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + event_dev->enqueue = cn9k_sso_hws_enq; + event_dev->enqueue_burst = cn9k_sso_hws_enq_burst; + event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst; + event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst; + + if (dev->dual_ws) { + event_dev->enqueue = cn9k_sso_hws_dual_enq; + event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst; + event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst; + event_dev->enqueue_forward_burst = + cn9k_sso_hws_dual_enq_fwd_burst; + } +} + static void * cn9k_sso_init_hws_mem(void *arg, uint8_t port_id) { @@ -349,8 +370,10 @@ cn9k_sso_init(struct rte_eventdev *event_dev) event_dev->dev_ops = &cn9k_sso_dev_ops; /* For secondary processes, the primary has done all the work */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + cn9k_sso_fp_fns_set(event_dev); return 0; + } rc = cnxk_sso_init(event_dev); if (rc < 0) diff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c index 836914163..538bc4b0b 100644 --- a/drivers/event/cnxk/cn9k_worker.c +++ b/drivers/event/cnxk/cn9k_worker.c @@ -5,3 +5,115 @@ #include "roc_api.h" #include "cn9k_worker.h" + +uint16_t __rte_hot +cn9k_sso_hws_enq(void *port, const struct rte_event *ev) +{ + struct cn9k_sso_hws *ws = port; + + switch (ev->op) { + case RTE_EVENT_OP_NEW: + return cn9k_sso_hws_new_event(ws, ev); + case RTE_EVENT_OP_FORWARD: + cn9k_sso_hws_forward_event(ws, ev); + break; + case RTE_EVENT_OP_RELEASE: + cnxk_sso_hws_swtag_flush(ws->tag_op, ws->swtag_flush_op); + break; + default: + return 0; + } + + return 1; +} + +uint16_t __rte_hot +cn9k_sso_hws_enq_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + RTE_SET_USED(nb_events); + return cn9k_sso_hws_enq(port, ev); +} + +uint16_t __rte_hot +cn9k_sso_hws_enq_new_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + struct cn9k_sso_hws *ws = port; + uint16_t i, rc = 1; + + for (i = 0; i < nb_events && rc; i++) + rc = cn9k_sso_hws_new_event(ws, &ev[i]); + + return nb_events; +} + +uint16_t __rte_hot +cn9k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + struct cn9k_sso_hws *ws = port; + + RTE_SET_USED(nb_events); + cn9k_sso_hws_forward_event(ws, ev); + + return 1; +} + +/* Dual ws ops. */ + +uint16_t __rte_hot +cn9k_sso_hws_dual_enq(void *port, const struct rte_event *ev) +{ + struct cn9k_sso_hws_dual *dws = port; + struct cn9k_sso_hws_state *vws; + + vws = &dws->ws_state[!dws->vws]; + switch (ev->op) { + case RTE_EVENT_OP_NEW: + return cn9k_sso_hws_dual_new_event(dws, ev); + case RTE_EVENT_OP_FORWARD: + cn9k_sso_hws_dual_forward_event(dws, vws, ev); + break; + case RTE_EVENT_OP_RELEASE: + cnxk_sso_hws_swtag_flush(vws->tag_op, vws->swtag_flush_op); + break; + default: + return 0; + } + + return 1; +} + +uint16_t __rte_hot +cn9k_sso_hws_dual_enq_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + RTE_SET_USED(nb_events); + return cn9k_sso_hws_dual_enq(port, ev); +} + +uint16_t __rte_hot +cn9k_sso_hws_dual_enq_new_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + struct cn9k_sso_hws_dual *dws = port; + uint16_t i, rc = 1; + + for (i = 0; i < nb_events && rc; i++) + rc = cn9k_sso_hws_dual_new_event(dws, &ev[i]); + + return nb_events; +} + +uint16_t __rte_hot +cn9k_sso_hws_dual_enq_fwd_burst(void *port, const struct rte_event ev[], + uint16_t nb_events) +{ + struct cn9k_sso_hws_dual *dws = port; + + RTE_SET_USED(nb_events); + cn9k_sso_hws_dual_forward_event(dws, &dws->ws_state[!dws->vws], ev); + + return 1; +} diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 85be742c1..aa321d0e4 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -246,4 +246,28 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev) return !!gw.u64[1]; } +/* CN9K Fastpath functions. */ +uint16_t __rte_hot cn9k_sso_hws_enq(void *port, const struct rte_event *ev); +uint16_t __rte_hot cn9k_sso_hws_enq_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); +uint16_t __rte_hot cn9k_sso_hws_enq_new_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); +uint16_t __rte_hot cn9k_sso_hws_enq_fwd_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); + +uint16_t __rte_hot cn9k_sso_hws_dual_enq(void *port, + const struct rte_event *ev); +uint16_t __rte_hot cn9k_sso_hws_dual_enq_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); +uint16_t __rte_hot cn9k_sso_hws_dual_enq_new_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); +uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port, + const struct rte_event ev[], + uint16_t nb_events); + #endif From patchwork Tue May 4 00:27:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92695 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A756A0562; Tue, 4 May 2021 02:29:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1ED094118C; Tue, 4 May 2021 02:28:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2B44D41186 for ; Tue, 4 May 2021 02:28:50 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440P2Ew025317 for ; Mon, 3 May 2021 17:28:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=p51zLx2ZipxyoWoKYTqfBb15r3cTTIoqVQJKD1WAVI8=; b=VlzsEdEvgEnlaMLmei4+TjYzP7SBc/ZJWbeKr0l0YS83ZJ7muF+uNMgPxiCJfcqziLck caObDXZvgoQw7EjD4MXzeg/UVKChhgF6n5Tw/27keVmy22fMbbnU9+pWW403LLSs+93N +B4hIWNRmpM/zGhQDAMzbjgbXF+GlJbpmz2tzuSv3oWue9U9Mq4dmYY7REL8QNo/zz0O FBZEejxKZIE4QsbxnKT7zTODBag8CpZ0fJjGXf0I43kVYU1P+cXmDyrC4Q/WpfDKx8QV Lh9L+DQNeag5yoV06pPe3VZt+Ri/5Nm+xWpJPEutyJOGCfR5t1viDeCOCwfTtJ9/BLP2 6g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnqe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:49 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:48 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 634123F703F; Mon, 3 May 2021 17:28:46 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:07 +0530 Message-ID: <20210504002726.525-18-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: FNRWnvuGYn_UrhvAasVbu4uXqSLb-zfp X-Proofpoint-ORIG-GUID: FNRWnvuGYn_UrhvAasVbu4uXqSLb-zfp X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 17/35] event/cnxk: add SSO GWS dequeue fastpath functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add SSO GWS event dequeue fastpath functions. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 10 ++- drivers/event/cnxk/cn10k_worker.c | 54 +++++++++++++ drivers/event/cnxk/cn10k_worker.h | 12 +++ drivers/event/cnxk/cn9k_eventdev.c | 15 ++++ drivers/event/cnxk/cn9k_worker.c | 117 ++++++++++++++++++++++++++++ drivers/event/cnxk/cn9k_worker.h | 24 ++++++ 6 files changed, 231 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index a1b44744b..37a7c8a8e 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -135,11 +135,19 @@ cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp) static void cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) { - PLT_SET_USED(event_dev); + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + event_dev->enqueue = cn10k_sso_hws_enq; event_dev->enqueue_burst = cn10k_sso_hws_enq_burst; event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst; event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst; + + event_dev->dequeue = cn10k_sso_hws_deq; + event_dev->dequeue_burst = cn10k_sso_hws_deq_burst; + if (dev->is_timeout_deq) { + event_dev->dequeue = cn10k_sso_hws_tmo_deq; + event_dev->dequeue_burst = cn10k_sso_hws_tmo_deq_burst; + } } static void diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c index 9b5cb7be6..e2aa534c6 100644 --- a/drivers/event/cnxk/cn10k_worker.c +++ b/drivers/event/cnxk/cn10k_worker.c @@ -59,3 +59,57 @@ cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[], return 1; } + +uint16_t __rte_hot +cn10k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks) +{ + struct cn10k_sso_hws *ws = port; + + RTE_SET_USED(timeout_ticks); + + if (ws->swtag_req) { + ws->swtag_req = 0; + cnxk_sso_hws_swtag_wait(ws->tag_wqe_op); + return 1; + } + + return cn10k_sso_hws_get_work(ws, ev); +} + +uint16_t __rte_hot +cn10k_sso_hws_deq_burst(void *port, struct rte_event ev[], uint16_t nb_events, + uint64_t timeout_ticks) +{ + RTE_SET_USED(nb_events); + + return cn10k_sso_hws_deq(port, ev, timeout_ticks); +} + +uint16_t __rte_hot +cn10k_sso_hws_tmo_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks) +{ + struct cn10k_sso_hws *ws = port; + uint16_t ret = 1; + uint64_t iter; + + if (ws->swtag_req) { + ws->swtag_req = 0; + cnxk_sso_hws_swtag_wait(ws->tag_wqe_op); + return ret; + } + + ret = cn10k_sso_hws_get_work(ws, ev); + for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) + ret = cn10k_sso_hws_get_work(ws, ev); + + return ret; +} + +uint16_t __rte_hot +cn10k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[], + uint16_t nb_events, uint64_t timeout_ticks) +{ + RTE_SET_USED(nb_events); + + return cn10k_sso_hws_tmo_deq(port, ev, timeout_ticks); +} diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 48158b320..2f093a8dd 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -160,4 +160,16 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[], uint16_t nb_events); +uint16_t __rte_hot cn10k_sso_hws_deq(void *port, struct rte_event *ev, + uint64_t timeout_ticks); +uint16_t __rte_hot cn10k_sso_hws_deq_burst(void *port, struct rte_event ev[], + uint16_t nb_events, + uint64_t timeout_ticks); +uint16_t __rte_hot cn10k_sso_hws_tmo_deq(void *port, struct rte_event *ev, + uint64_t timeout_ticks); +uint16_t __rte_hot cn10k_sso_hws_tmo_deq_burst(void *port, + struct rte_event ev[], + uint16_t nb_events, + uint64_t timeout_ticks); + #endif diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 61a4d0823..6ba3d1466 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -162,12 +162,27 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev) event_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst; event_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst; + event_dev->dequeue = cn9k_sso_hws_deq; + event_dev->dequeue_burst = cn9k_sso_hws_deq_burst; + if (dev->deq_tmo_ns) { + event_dev->dequeue = cn9k_sso_hws_tmo_deq; + event_dev->dequeue_burst = cn9k_sso_hws_tmo_deq_burst; + } + if (dev->dual_ws) { event_dev->enqueue = cn9k_sso_hws_dual_enq; event_dev->enqueue_burst = cn9k_sso_hws_dual_enq_burst; event_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst; event_dev->enqueue_forward_burst = cn9k_sso_hws_dual_enq_fwd_burst; + + event_dev->dequeue = cn9k_sso_hws_dual_deq; + event_dev->dequeue_burst = cn9k_sso_hws_dual_deq_burst; + if (dev->deq_tmo_ns) { + event_dev->dequeue = cn9k_sso_hws_dual_tmo_deq; + event_dev->dequeue_burst = + cn9k_sso_hws_dual_tmo_deq_burst; + } } } diff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c index 538bc4b0b..9ceacc98d 100644 --- a/drivers/event/cnxk/cn9k_worker.c +++ b/drivers/event/cnxk/cn9k_worker.c @@ -60,6 +60,60 @@ cn9k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[], return 1; } +uint16_t __rte_hot +cn9k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks) +{ + struct cn9k_sso_hws *ws = port; + + RTE_SET_USED(timeout_ticks); + + if (ws->swtag_req) { + ws->swtag_req = 0; + cnxk_sso_hws_swtag_wait(ws->tag_op); + return 1; + } + + return cn9k_sso_hws_get_work(ws, ev); +} + +uint16_t __rte_hot +cn9k_sso_hws_deq_burst(void *port, struct rte_event ev[], uint16_t nb_events, + uint64_t timeout_ticks) +{ + RTE_SET_USED(nb_events); + + return cn9k_sso_hws_deq(port, ev, timeout_ticks); +} + +uint16_t __rte_hot +cn9k_sso_hws_tmo_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks) +{ + struct cn9k_sso_hws *ws = port; + uint16_t ret = 1; + uint64_t iter; + + if (ws->swtag_req) { + ws->swtag_req = 0; + cnxk_sso_hws_swtag_wait(ws->tag_op); + return ret; + } + + ret = cn9k_sso_hws_get_work(ws, ev); + for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) + ret = cn9k_sso_hws_get_work(ws, ev); + + return ret; +} + +uint16_t __rte_hot +cn9k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[], + uint16_t nb_events, uint64_t timeout_ticks) +{ + RTE_SET_USED(nb_events); + + return cn9k_sso_hws_tmo_deq(port, ev, timeout_ticks); +} + /* Dual ws ops. */ uint16_t __rte_hot @@ -117,3 +171,66 @@ cn9k_sso_hws_dual_enq_fwd_burst(void *port, const struct rte_event ev[], return 1; } + +uint16_t __rte_hot +cn9k_sso_hws_dual_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks) +{ + struct cn9k_sso_hws_dual *dws = port; + uint16_t gw; + + RTE_SET_USED(timeout_ticks); + if (dws->swtag_req) { + dws->swtag_req = 0; + cnxk_sso_hws_swtag_wait(dws->ws_state[!dws->vws].tag_op); + return 1; + } + + gw = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], + &dws->ws_state[!dws->vws], ev); + dws->vws = !dws->vws; + return gw; +} + +uint16_t __rte_hot +cn9k_sso_hws_dual_deq_burst(void *port, struct rte_event ev[], + uint16_t nb_events, uint64_t timeout_ticks) +{ + RTE_SET_USED(nb_events); + + return cn9k_sso_hws_dual_deq(port, ev, timeout_ticks); +} + +uint16_t __rte_hot +cn9k_sso_hws_dual_tmo_deq(void *port, struct rte_event *ev, + uint64_t timeout_ticks) +{ + struct cn9k_sso_hws_dual *dws = port; + uint16_t ret = 1; + uint64_t iter; + + if (dws->swtag_req) { + dws->swtag_req = 0; + cnxk_sso_hws_swtag_wait(dws->ws_state[!dws->vws].tag_op); + return ret; + } + + ret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], + &dws->ws_state[!dws->vws], ev); + dws->vws = !dws->vws; + for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { + ret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], + &dws->ws_state[!dws->vws], ev); + dws->vws = !dws->vws; + } + + return ret; +} + +uint16_t __rte_hot +cn9k_sso_hws_dual_tmo_deq_burst(void *port, struct rte_event ev[], + uint16_t nb_events, uint64_t timeout_ticks) +{ + RTE_SET_USED(nb_events); + + return cn9k_sso_hws_dual_tmo_deq(port, ev, timeout_ticks); +} diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index aa321d0e4..38fca08fb 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -270,4 +270,28 @@ uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port, const struct rte_event ev[], uint16_t nb_events); +uint16_t __rte_hot cn9k_sso_hws_deq(void *port, struct rte_event *ev, + uint64_t timeout_ticks); +uint16_t __rte_hot cn9k_sso_hws_deq_burst(void *port, struct rte_event ev[], + uint16_t nb_events, + uint64_t timeout_ticks); +uint16_t __rte_hot cn9k_sso_hws_tmo_deq(void *port, struct rte_event *ev, + uint64_t timeout_ticks); +uint16_t __rte_hot cn9k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[], + uint16_t nb_events, + uint64_t timeout_ticks); + +uint16_t __rte_hot cn9k_sso_hws_dual_deq(void *port, struct rte_event *ev, + uint64_t timeout_ticks); +uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst(void *port, + struct rte_event ev[], + uint16_t nb_events, + uint64_t timeout_ticks); +uint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq(void *port, struct rte_event *ev, + uint64_t timeout_ticks); +uint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_burst(void *port, + struct rte_event ev[], + uint16_t nb_events, + uint64_t timeout_ticks); + #endif From patchwork Tue May 4 00:27:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92696 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 336AFA0562; Tue, 4 May 2021 02:29:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4EF7741190; Tue, 4 May 2021 02:28:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5DF4D41145 for ; Tue, 4 May 2021 02:28:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440Algx002713 for ; Mon, 3 May 2021 17:28:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=IfPFD1Q3vLhPe3hXKcfISQSWBNOzJMB2kwwShzmFkrs=; b=dJVu0AVMl7LbHN7S34HGPZdGEb5zj/+yJiWUWzxxVSPcEph8JeJkdW04Yw8AHX+YJWdI 1qDLMfiRhnrnqv2lQ3kuGKQGp4NRg46kr3lm50AYsiu0lta3KgHloCnda3Py7vxWU4J5 oXA3J/0XHFADKPhQrl2WaE51uI7mJb8sIQNWfNjnwbf0a74H+jRgOCkwKEm8ud7FhR5C pV0DQAtt6r+I9/5A0aAXORYqK76F+6mGGVXocIZK5gFKnbWDsZbm4r3sn+KFGfc9xkej vftem2FfG7Y2pTfu9RK1IrRjhVDCIfHKNdQ1qzEP2edu6OG9Ek30CIJtBnjkfN0TT/SW tw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6md-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:52 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:50 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 26DB43F703F; Mon, 3 May 2021 17:28:48 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:08 +0530 Message-ID: <20210504002726.525-19-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ySRCnHXsNLuQzswC97M9pUx6qAOcAi1s X-Proofpoint-ORIG-GUID: ySRCnHXsNLuQzswC97M9pUx6qAOcAi1s X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 18/35] event/cnxk: add device start function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add eventdev start function along with few cleanup API's to maintain sanity. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cn10k_eventdev.c | 127 ++++++++++++++++++++++++++++ drivers/event/cnxk/cn9k_eventdev.c | 113 +++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.c | 64 ++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 7 ++ 4 files changed, 311 insertions(+) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 37a7c8a8e..8d6b1e48a 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -112,6 +112,117 @@ cn10k_sso_hws_release(void *arg, void *hws) memset(ws, 0, sizeof(*ws)); } +static void +cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base, + cnxk_handle_event_t fn, void *arg) +{ + struct cn10k_sso_hws *ws = hws; + uint64_t cq_ds_cnt = 1; + uint64_t aq_cnt = 1; + uint64_t ds_cnt = 1; + struct rte_event ev; + uint64_t val, req; + + plt_write64(0, base + SSO_LF_GGRP_QCTL); + + req = queue_id; /* GGRP ID */ + req |= BIT_ULL(18); /* Grouped */ + req |= BIT_ULL(16); /* WAIT */ + + aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT); + ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT); + cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT); + cq_ds_cnt &= 0x3FFF3FFF0000; + + while (aq_cnt || cq_ds_cnt || ds_cnt) { + plt_write64(req, ws->getwrk_op); + cn10k_sso_hws_get_work_empty(ws, &ev); + if (fn != NULL && ev.u64 != 0) + fn(arg, ev); + if (ev.sched_type != SSO_TT_EMPTY) + cnxk_sso_hws_swtag_flush(ws->tag_wqe_op, + ws->swtag_flush_op); + do { + val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE); + } while (val & BIT_ULL(56)); + aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT); + ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT); + cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT); + /* Extract cq and ds count */ + cq_ds_cnt &= 0x3FFF3FFF0000; + } + + plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL); + rte_mb(); +} + +static void +cn10k_sso_hws_reset(void *arg, void *hws) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn10k_sso_hws *ws = hws; + uintptr_t base = ws->base; + uint64_t pend_state; + union { + __uint128_t wdata; + uint64_t u64[2]; + } gw; + uint8_t pend_tt; + + /* Wait till getwork/swtp/waitw/desched completes. */ + do { + pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE); + } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) | + BIT_ULL(56) | BIT_ULL(54))); + pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0)); + if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */ + if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED) + cnxk_sso_hws_swtag_untag(base + + SSOW_LF_GWS_OP_SWTAG_UNTAG); + plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED); + } + + /* Wait for desched to complete. */ + do { + pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE); + } while (pend_state & BIT_ULL(58)); + + switch (dev->gw_mode) { + case CN10K_GW_MODE_PREF: + while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63)) + ; + break; + case CN10K_GW_MODE_PREF_WFE: + while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & + SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT) + continue; + plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL); + break; + case CN10K_GW_MODE_NONE: + default: + break; + } + + if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) != + SSO_TT_EMPTY) { + plt_write64(BIT_ULL(16) | 1, ws->getwrk_op); + do { + roc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op); + } while (gw.u64[0] & BIT_ULL(63)); + pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0)); + if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */ + if (pend_tt == SSO_TT_ATOMIC || + pend_tt == SSO_TT_ORDERED) + cnxk_sso_hws_swtag_untag( + base + SSOW_LF_GWS_OP_SWTAG_UNTAG); + plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED); + } + } + + plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL); + rte_mb(); +} + static void cn10k_sso_set_rsrc(void *arg) { @@ -263,6 +374,20 @@ cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, return (int)nb_unlinks; } +static int +cn10k_sso_start(struct rte_eventdev *event_dev) +{ + int rc; + + rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset, + cn10k_sso_hws_flush_events); + if (rc < 0) + return rc; + cn10k_sso_fp_fns_set(event_dev); + + return rc; +} + static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -275,6 +400,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .port_link = cn10k_sso_port_link, .port_unlink = cn10k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + + .dev_start = cn10k_sso_start, }; static int diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 6ba3d1466..20919e3a0 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -126,6 +126,102 @@ cn9k_sso_hws_release(void *arg, void *hws) } } +static void +cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base, + cnxk_handle_event_t fn, void *arg) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg); + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws_state *st; + struct cn9k_sso_hws *ws; + uint64_t cq_ds_cnt = 1; + uint64_t aq_cnt = 1; + uint64_t ds_cnt = 1; + struct rte_event ev; + uintptr_t ws_base; + uint64_t val, req; + + plt_write64(0, base + SSO_LF_GGRP_QCTL); + + req = queue_id; /* GGRP ID */ + req |= BIT_ULL(18); /* Grouped */ + req |= BIT_ULL(16); /* WAIT */ + + aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT); + ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT); + cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT); + cq_ds_cnt &= 0x3FFF3FFF0000; + + if (dev->dual_ws) { + dws = hws; + st = &dws->ws_state[0]; + ws_base = dws->base[0]; + } else { + ws = hws; + st = (struct cn9k_sso_hws_state *)ws; + ws_base = ws->base; + } + + while (aq_cnt || cq_ds_cnt || ds_cnt) { + plt_write64(req, st->getwrk_op); + cn9k_sso_hws_get_work_empty(st, &ev); + if (fn != NULL && ev.u64 != 0) + fn(arg, ev); + if (ev.sched_type != SSO_TT_EMPTY) + cnxk_sso_hws_swtag_flush(st->tag_op, + st->swtag_flush_op); + do { + val = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE); + } while (val & BIT_ULL(56)); + aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT); + ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT); + cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT); + /* Extract cq and ds count */ + cq_ds_cnt &= 0x3FFF3FFF0000; + } + + plt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL); +} + +static void +cn9k_sso_hws_reset(void *arg, void *hws) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn9k_sso_hws_dual *dws; + struct cn9k_sso_hws *ws; + uint64_t pend_state; + uint8_t pend_tt; + uintptr_t base; + uint64_t tag; + uint8_t i; + + dws = hws; + ws = hws; + for (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) { + base = dev->dual_ws ? dws->base[i] : ws->base; + /* Wait till getwork/swtp/waitw/desched completes. */ + do { + pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE); + } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) | + BIT_ULL(56))); + + tag = plt_read64(base + SSOW_LF_GWS_TAG); + pend_tt = (tag >> 32) & 0x3; + if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */ + if (pend_tt == SSO_TT_ATOMIC || + pend_tt == SSO_TT_ORDERED) + cnxk_sso_hws_swtag_untag( + base + SSOW_LF_GWS_OP_SWTAG_UNTAG); + plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED); + } + + /* Wait for desched to complete. */ + do { + pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE); + } while (pend_state & BIT_ULL(58)); + } +} + static void cn9k_sso_set_rsrc(void *arg) { @@ -352,6 +448,21 @@ cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, return (int)nb_unlinks; } +static int +cn9k_sso_start(struct rte_eventdev *event_dev) +{ + int rc; + + rc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset, + cn9k_sso_hws_flush_events); + if (rc < 0) + return rc; + + cn9k_sso_fp_fns_set(event_dev); + + return rc; +} + static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, @@ -364,6 +475,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .port_link = cn9k_sso_port_link, .port_unlink = cn9k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + + .dev_start = cn9k_sso_start, }; static int diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 2a387ff95..5feae5288 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -326,6 +326,70 @@ cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, return 0; } +static void +cnxk_handle_event(void *arg, struct rte_event event) +{ + struct rte_eventdev *event_dev = arg; + + if (event_dev->dev_ops->dev_stop_flush != NULL) + event_dev->dev_ops->dev_stop_flush( + event_dev->data->dev_id, event, + event_dev->data->dev_stop_flush_arg); +} + +static void +cnxk_sso_cleanup(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn, + cnxk_sso_hws_flush_t flush_fn, uint8_t enable) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uintptr_t hwgrp_base; + uint16_t i; + void *ws; + + for (i = 0; i < dev->nb_event_ports; i++) { + ws = event_dev->data->ports[i]; + reset_fn(dev, ws); + } + + rte_mb(); + ws = event_dev->data->ports[0]; + + for (i = 0; i < dev->nb_event_queues; i++) { + /* Consume all the events through HWS0 */ + hwgrp_base = roc_sso_hwgrp_base_get(&dev->sso, i); + flush_fn(ws, i, hwgrp_base, cnxk_handle_event, event_dev); + /* Enable/Disable SSO GGRP */ + plt_write64(enable, hwgrp_base + SSO_LF_GGRP_QCTL); + } +} + +int +cnxk_sso_start(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn, + cnxk_sso_hws_flush_t flush_fn) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + struct roc_sso_hwgrp_qos qos[dev->qos_queue_cnt]; + int i, rc; + + plt_sso_dbg(); + for (i = 0; i < dev->qos_queue_cnt; i++) { + qos->hwgrp = dev->qos_parse_data[i].queue; + qos->iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt; + qos->taq_prcnt = dev->qos_parse_data[i].taq_prcnt; + qos->xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt; + } + rc = roc_sso_hwgrp_qos_config(&dev->sso, qos, dev->qos_queue_cnt, + dev->xae_cnt); + if (rc < 0) { + plt_sso_dbg("failed to configure HWGRP QoS rc = %d", rc); + return -EINVAL; + } + cnxk_sso_cleanup(event_dev, reset_fn, flush_fn, true); + rte_mb(); + + return 0; +} + static void parse_queue_param(char *value, void *opaque) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 0a3ab71e4..f175c23bb 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -48,6 +48,10 @@ typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base); typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws); typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map, uint16_t nb_link); +typedef void (*cnxk_handle_event_t)(void *arg, struct rte_event ev); +typedef void (*cnxk_sso_hws_reset_t)(void *arg, void *ws); +typedef void (*cnxk_sso_hws_flush_t)(void *ws, uint8_t queue_id, uintptr_t base, + cnxk_handle_event_t fn, void *arg); struct cnxk_sso_qos { uint16_t queue; @@ -198,5 +202,8 @@ int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, cnxk_sso_hws_setup_t hws_setup_fn); int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, uint64_t *tmo_ticks); +int cnxk_sso_start(struct rte_eventdev *event_dev, + cnxk_sso_hws_reset_t reset_fn, + cnxk_sso_hws_flush_t flush_fn); #endif /* __CNXK_EVENTDEV_H__ */ From patchwork Tue May 4 00:27:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92697 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D05C2A0562; Tue, 4 May 2021 02:30:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A12241195; Tue, 4 May 2021 02:28:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EA9A74119C for ; Tue, 4 May 2021 02:28:55 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440QWst026649 for ; Mon, 3 May 2021 17:28:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=56svA33UcguX6zslmbGAudMQtreMFkNFKSIgPDPtYtE=; b=RTmC5SpnA7z+AhXusr9RDB6/NucwO4/G7MmZF8EXRZDTBddSzdNJMr6+jJeRsoRc5JFo 6aCmxd+AxgG1tZPzUljPehB62ZUIbAQdUDLdUpguRWu/DiplSUe42XGFcbzQ2JLCj1oh yr2s1tDm/1m/LYJpApgXmvnAsPpR5UQsdnPxRYY/ob5An2WKcRShB10YT3SDeESp4wbm bkLRRx4/wa0Uui54FKqOB74P24UvQEkNklX+afTTv6L+B0qPoBIow4SvY0jrEFIzCX3y H7hk4hnu7GD0euDcQmwRaHH7MBybxHEQ1hS8z2CPwnYeKwlecI+A5aqU2lraSns/gGHM Yg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnqs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:53 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 15E4D3F703F; Mon, 3 May 2021 17:28:51 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:09 +0530 Message-ID: <20210504002726.525-20-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: QqxjHmgRb4T4n8DElW2B8yIkuPl4lQN1 X-Proofpoint-ORIG-GUID: QqxjHmgRb4T4n8DElW2B8yIkuPl4lQN1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 19/35] event/cnxk: add device stop and close functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add event device stop and close callback functions. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cn10k_eventdev.c | 15 +++++++++ drivers/event/cnxk/cn9k_eventdev.c | 14 +++++++++ drivers/event/cnxk/cnxk_eventdev.c | 48 +++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 6 ++++ 4 files changed, 83 insertions(+) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 8d6b1e48a..5b7cd672c 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -388,6 +388,19 @@ cn10k_sso_start(struct rte_eventdev *event_dev) return rc; } +static void +cn10k_sso_stop(struct rte_eventdev *event_dev) +{ + cnxk_sso_stop(event_dev, cn10k_sso_hws_reset, + cn10k_sso_hws_flush_events); +} + +static int +cn10k_sso_close(struct rte_eventdev *event_dev) +{ + return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink); +} + static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -402,6 +415,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .timeout_ticks = cnxk_sso_timeout_ticks, .dev_start = cn10k_sso_start, + .dev_stop = cn10k_sso_stop, + .dev_close = cn10k_sso_close, }; static int diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 20919e3a0..f13f50f42 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -463,6 +463,18 @@ cn9k_sso_start(struct rte_eventdev *event_dev) return rc; } +static void +cn9k_sso_stop(struct rte_eventdev *event_dev) +{ + cnxk_sso_stop(event_dev, cn9k_sso_hws_reset, cn9k_sso_hws_flush_events); +} + +static int +cn9k_sso_close(struct rte_eventdev *event_dev) +{ + return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink); +} + static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, @@ -477,6 +489,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .timeout_ticks = cnxk_sso_timeout_ticks, .dev_start = cn9k_sso_start, + .dev_stop = cn9k_sso_stop, + .dev_close = cn9k_sso_close, }; static int diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 5feae5288..a3900315a 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -390,6 +390,54 @@ cnxk_sso_start(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn, return 0; } +void +cnxk_sso_stop(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn, + cnxk_sso_hws_flush_t flush_fn) +{ + plt_sso_dbg(); + cnxk_sso_cleanup(event_dev, reset_fn, flush_fn, false); + rte_mb(); +} + +int +cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t all_queues[CNXK_SSO_MAX_HWGRP]; + uint16_t i; + void *ws; + + if (!dev->configured) + return 0; + + for (i = 0; i < dev->nb_event_queues; i++) + all_queues[i] = i; + + for (i = 0; i < dev->nb_event_ports; i++) { + ws = event_dev->data->ports[i]; + unlink_fn(dev, ws, all_queues, dev->nb_event_queues); + rte_free(cnxk_sso_hws_get_cookie(ws)); + event_dev->data->ports[i] = NULL; + } + + roc_sso_rsrc_fini(&dev->sso); + rte_mempool_free(dev->xaq_pool); + rte_memzone_free(rte_memzone_lookup(CNXK_SSO_FC_NAME)); + + dev->fc_iova = 0; + dev->fc_mem = NULL; + dev->xaq_pool = NULL; + dev->configured = false; + dev->is_timeout_deq = 0; + dev->nb_event_ports = 0; + dev->max_num_events = -1; + dev->nb_event_queues = 0; + dev->min_dequeue_timeout_ns = USEC2NSEC(1); + dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF); + + return 0; +} + static void parse_queue_param(char *value, void *opaque) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index f175c23bb..3011af153 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -48,6 +48,8 @@ typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base); typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws); typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map, uint16_t nb_link); +typedef int (*cnxk_sso_unlink_t)(void *dev, void *ws, uint16_t *map, + uint16_t nb_link); typedef void (*cnxk_handle_event_t)(void *arg, struct rte_event ev); typedef void (*cnxk_sso_hws_reset_t)(void *arg, void *ws); typedef void (*cnxk_sso_hws_flush_t)(void *ws, uint8_t queue_id, uintptr_t base, @@ -205,5 +207,9 @@ int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, int cnxk_sso_start(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn, cnxk_sso_hws_flush_t flush_fn); +void cnxk_sso_stop(struct rte_eventdev *event_dev, + cnxk_sso_hws_reset_t reset_fn, + cnxk_sso_hws_flush_t flush_fn); +int cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn); #endif /* __CNXK_EVENTDEV_H__ */ From patchwork Tue May 4 00:27:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92698 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0FD46A0562; Tue, 4 May 2021 02:30:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3A83841198; Tue, 4 May 2021 02:29:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 577E4410F6 for ; Tue, 4 May 2021 02:29:00 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AIFM002346 for ; Mon, 3 May 2021 17:28:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=PePTR0EUHRn7gADF/OFB3wS+a3GM0eo6FFb/y/VDFZw=; b=QAGTMrRo9rd+GDBXbVDNFIzTnljjw3XlRZpjgevnKsgZsqX34l9LhksiCETOACDcrZVm Zk8aUFvxRmrQmUaxZrQ1NAbbOmSy2a7Mwl7sii7r0elIGzmI4M3rBuXUo9SfZXAucard KrRoGxBpdNLag/UbG363TY4O0GsU5/D9Hpbr8IwLkdI++9i42XrAvWhyYn9NMOx4MbrV sQu/Xouo7ypTDDE7ubZzryfcuIMK0k04JDH62UUAIILobNqirjwGSF3PH7vlyz2+93QT l3+ojeNfnWgrqFVyNtdgVvbYvm9efKqcc6fC+4axABqgdwtJA6ZWdngEtZ9spyTUxANf JQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6mm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:56 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id D06E23F703F; Mon, 3 May 2021 17:28:54 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:10 +0530 Message-ID: <20210504002726.525-21-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ijzVw8dYWX4YtdHULgK_ztPksXEGJaHs X-Proofpoint-ORIG-GUID: ijzVw8dYWX4YtdHULgK_ztPksXEGJaHs X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 20/35] event/cnxk: add SSO selftest and dump X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add selftest to verify sanity of SSO and also add function to dump internal state of SSO. Signed-off-by: Pavan Nikhilesh --- app/test/test_eventdev.c | 14 + drivers/event/cnxk/cn10k_eventdev.c | 8 + drivers/event/cnxk/cn9k_eventdev.c | 10 +- drivers/event/cnxk/cnxk_eventdev.c | 8 + drivers/event/cnxk/cnxk_eventdev.h | 5 + drivers/event/cnxk/cnxk_eventdev_selftest.c | 1570 +++++++++++++++++++ drivers/event/cnxk/meson.build | 1 + 7 files changed, 1615 insertions(+), 1 deletion(-) create mode 100644 drivers/event/cnxk/cnxk_eventdev_selftest.c diff --git a/app/test/test_eventdev.c b/app/test/test_eventdev.c index bcfaa53cb..843d9766b 100644 --- a/app/test/test_eventdev.c +++ b/app/test/test_eventdev.c @@ -1036,6 +1036,18 @@ test_eventdev_selftest_dlb2(void) return test_eventdev_selftest_impl("dlb2_event", ""); } +static int +test_eventdev_selftest_cn9k(void) +{ + return test_eventdev_selftest_impl("event_cn9k", ""); +} + +static int +test_eventdev_selftest_cn10k(void) +{ + return test_eventdev_selftest_impl("event_cn10k", ""); +} + REGISTER_TEST_COMMAND(eventdev_common_autotest, test_eventdev_common); REGISTER_TEST_COMMAND(eventdev_selftest_sw, test_eventdev_selftest_sw); REGISTER_TEST_COMMAND(eventdev_selftest_octeontx, @@ -1044,3 +1056,5 @@ REGISTER_TEST_COMMAND(eventdev_selftest_octeontx2, test_eventdev_selftest_octeontx2); REGISTER_TEST_COMMAND(eventdev_selftest_dpaa2, test_eventdev_selftest_dpaa2); REGISTER_TEST_COMMAND(eventdev_selftest_dlb2, test_eventdev_selftest_dlb2); +REGISTER_TEST_COMMAND(eventdev_selftest_cn9k, test_eventdev_selftest_cn9k); +REGISTER_TEST_COMMAND(eventdev_selftest_cn10k, test_eventdev_selftest_cn10k); diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 5b7cd672c..a0c6d32cc 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -401,6 +401,12 @@ cn10k_sso_close(struct rte_eventdev *event_dev) return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink); } +static int +cn10k_sso_selftest(void) +{ + return cnxk_sso_selftest(RTE_STR(event_cn10k)); +} + static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, @@ -414,9 +420,11 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .port_unlink = cn10k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + .dump = cnxk_sso_dump, .dev_start = cn10k_sso_start, .dev_stop = cn10k_sso_stop, .dev_close = cn10k_sso_close, + .dev_selftest = cn10k_sso_selftest, }; static int diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index f13f50f42..48991e522 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -222,7 +222,7 @@ cn9k_sso_hws_reset(void *arg, void *hws) } } -static void +void cn9k_sso_set_rsrc(void *arg) { struct cnxk_sso_evdev *dev = arg; @@ -475,6 +475,12 @@ cn9k_sso_close(struct rte_eventdev *event_dev) return cnxk_sso_close(event_dev, cn9k_sso_hws_unlink); } +static int +cn9k_sso_selftest(void) +{ + return cnxk_sso_selftest(RTE_STR(event_cn9k)); +} + static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, @@ -488,9 +494,11 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .port_unlink = cn9k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + .dump = cnxk_sso_dump, .dev_start = cn9k_sso_start, .dev_stop = cn9k_sso_stop, .dev_close = cn9k_sso_close, + .dev_selftest = cn9k_sso_selftest, }; static int diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index a3900315a..0f084176c 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -326,6 +326,14 @@ cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns, return 0; } +void +cnxk_sso_dump(struct rte_eventdev *event_dev, FILE *f) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + roc_sso_dump(&dev->sso, dev->sso.nb_hws, dev->sso.nb_hwgrp, f); +} + static void cnxk_handle_event(void *arg, struct rte_event event) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 3011af153..9af04bc3d 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -211,5 +211,10 @@ void cnxk_sso_stop(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn, cnxk_sso_hws_flush_t flush_fn); int cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn); +int cnxk_sso_selftest(const char *dev_name); +void cnxk_sso_dump(struct rte_eventdev *event_dev, FILE *f); + +/* CN9K */ +void cn9k_sso_set_rsrc(void *arg); #endif /* __CNXK_EVENTDEV_H__ */ diff --git a/drivers/event/cnxk/cnxk_eventdev_selftest.c b/drivers/event/cnxk/cnxk_eventdev_selftest.c new file mode 100644 index 000000000..69c15b1d0 --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev_selftest.c @@ -0,0 +1,1570 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cnxk_eventdev.h" + +#define NUM_PACKETS (1024) +#define MAX_EVENTS (1024) +#define MAX_STAGES (255) + +#define CNXK_TEST_RUN(setup, teardown, test) \ + cnxk_test_run(setup, teardown, test, #test) + +static int total; +static int passed; +static int failed; +static int unsupported; + +static int evdev; +static struct rte_mempool *eventdev_test_mempool; + +struct event_attr { + uint32_t flow_id; + uint8_t event_type; + uint8_t sub_event_type; + uint8_t sched_type; + uint8_t queue; + uint8_t port; +}; + +static uint32_t seqn_list_index; +static int seqn_list[NUM_PACKETS]; + +static inline void +seqn_list_init(void) +{ + RTE_BUILD_BUG_ON(NUM_PACKETS < MAX_EVENTS); + memset(seqn_list, 0, sizeof(seqn_list)); + seqn_list_index = 0; +} + +static inline int +seqn_list_update(int val) +{ + if (seqn_list_index >= NUM_PACKETS) + return -1; + + seqn_list[seqn_list_index++] = val; + rte_atomic_thread_fence(__ATOMIC_RELEASE); + return 0; +} + +static inline int +seqn_list_check(int limit) +{ + int i; + + for (i = 0; i < limit; i++) { + if (seqn_list[i] != i) { + plt_err("Seqn mismatch %d %d", seqn_list[i], i); + return -1; + } + } + return 0; +} + +struct test_core_param { + uint32_t *total_events; + uint64_t dequeue_tmo_ticks; + uint8_t port; + uint8_t sched_type; +}; + +static int +testsuite_setup(const char *eventdev_name) +{ + evdev = rte_event_dev_get_dev_id(eventdev_name); + if (evdev < 0) { + plt_err("%d: Eventdev %s not found", __LINE__, eventdev_name); + return -1; + } + return 0; +} + +static void +testsuite_teardown(void) +{ + rte_event_dev_close(evdev); + total = 0; + passed = 0; + failed = 0; + unsupported = 0; +} + +static inline void +devconf_set_default_sane_values(struct rte_event_dev_config *dev_conf, + struct rte_event_dev_info *info) +{ + memset(dev_conf, 0, sizeof(struct rte_event_dev_config)); + dev_conf->dequeue_timeout_ns = info->min_dequeue_timeout_ns; + dev_conf->nb_event_ports = info->max_event_ports; + dev_conf->nb_event_queues = info->max_event_queues; + dev_conf->nb_event_queue_flows = info->max_event_queue_flows; + dev_conf->nb_event_port_dequeue_depth = + info->max_event_port_dequeue_depth; + dev_conf->nb_event_port_enqueue_depth = + info->max_event_port_enqueue_depth; + dev_conf->nb_event_port_enqueue_depth = + info->max_event_port_enqueue_depth; + dev_conf->nb_events_limit = info->max_num_events; +} + +enum { + TEST_EVENTDEV_SETUP_DEFAULT, + TEST_EVENTDEV_SETUP_PRIORITY, + TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT, +}; + +static inline int +_eventdev_setup(int mode) +{ + const char *pool_name = "evdev_cnxk_test_pool"; + struct rte_event_dev_config dev_conf; + struct rte_event_dev_info info; + int i, ret; + + /* Create and destrory pool for each test case to make it standalone */ + eventdev_test_mempool = rte_pktmbuf_pool_create( + pool_name, MAX_EVENTS, 0, 0, 512, rte_socket_id()); + if (!eventdev_test_mempool) { + plt_err("ERROR creating mempool"); + return -1; + } + + ret = rte_event_dev_info_get(evdev, &info); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get event dev info"); + + devconf_set_default_sane_values(&dev_conf, &info); + if (mode == TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT) + dev_conf.event_dev_cfg |= RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT; + + ret = rte_event_dev_configure(evdev, &dev_conf); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to configure eventdev"); + + uint32_t queue_count; + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + + if (mode == TEST_EVENTDEV_SETUP_PRIORITY) { + if (queue_count > 8) + queue_count = 8; + + /* Configure event queues(0 to n) with + * RTE_EVENT_DEV_PRIORITY_HIGHEST to + * RTE_EVENT_DEV_PRIORITY_LOWEST + */ + uint8_t step = + (RTE_EVENT_DEV_PRIORITY_LOWEST + 1) / queue_count; + for (i = 0; i < (int)queue_count; i++) { + struct rte_event_queue_conf queue_conf; + + ret = rte_event_queue_default_conf_get(evdev, i, + &queue_conf); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get def_conf%d", + i); + queue_conf.priority = i * step; + ret = rte_event_queue_setup(evdev, i, &queue_conf); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup queue=%d", + i); + } + + } else { + /* Configure event queues with default priority */ + for (i = 0; i < (int)queue_count; i++) { + ret = rte_event_queue_setup(evdev, i, NULL); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup queue=%d", + i); + } + } + /* Configure event ports */ + uint32_t port_count; + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &port_count), + "Port count get failed"); + for (i = 0; i < (int)port_count; i++) { + ret = rte_event_port_setup(evdev, i, NULL); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup port=%d", i); + ret = rte_event_port_link(evdev, i, NULL, NULL, 0); + RTE_TEST_ASSERT(ret >= 0, "Failed to link all queues port=%d", + i); + } + + ret = rte_event_dev_start(evdev); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start device"); + + return 0; +} + +static inline int +eventdev_setup(void) +{ + return _eventdev_setup(TEST_EVENTDEV_SETUP_DEFAULT); +} + +static inline int +eventdev_setup_priority(void) +{ + return _eventdev_setup(TEST_EVENTDEV_SETUP_PRIORITY); +} + +static inline int +eventdev_setup_dequeue_timeout(void) +{ + return _eventdev_setup(TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT); +} + +static inline void +eventdev_teardown(void) +{ + rte_event_dev_stop(evdev); + rte_mempool_free(eventdev_test_mempool); +} + +static inline void +update_event_and_validation_attr(struct rte_mbuf *m, struct rte_event *ev, + uint32_t flow_id, uint8_t event_type, + uint8_t sub_event_type, uint8_t sched_type, + uint8_t queue, uint8_t port) +{ + struct event_attr *attr; + + /* Store the event attributes in mbuf for future reference */ + attr = rte_pktmbuf_mtod(m, struct event_attr *); + attr->flow_id = flow_id; + attr->event_type = event_type; + attr->sub_event_type = sub_event_type; + attr->sched_type = sched_type; + attr->queue = queue; + attr->port = port; + + ev->flow_id = flow_id; + ev->sub_event_type = sub_event_type; + ev->event_type = event_type; + /* Inject the new event */ + ev->op = RTE_EVENT_OP_NEW; + ev->sched_type = sched_type; + ev->queue_id = queue; + ev->mbuf = m; +} + +static inline int +inject_events(uint32_t flow_id, uint8_t event_type, uint8_t sub_event_type, + uint8_t sched_type, uint8_t queue, uint8_t port, + unsigned int events) +{ + struct rte_mbuf *m; + unsigned int i; + + for (i = 0; i < events; i++) { + struct rte_event ev = {.event = 0, .u64 = 0}; + + m = rte_pktmbuf_alloc(eventdev_test_mempool); + RTE_TEST_ASSERT_NOT_NULL(m, "mempool alloc failed"); + + *rte_event_pmd_selftest_seqn(m) = i; + update_event_and_validation_attr(m, &ev, flow_id, event_type, + sub_event_type, sched_type, + queue, port); + rte_event_enqueue_burst(evdev, port, &ev, 1); + } + return 0; +} + +static inline int +check_excess_events(uint8_t port) +{ + uint16_t valid_event; + struct rte_event ev; + int i; + + /* Check for excess events, try for a few times and exit */ + for (i = 0; i < 32; i++) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + + RTE_TEST_ASSERT_SUCCESS(valid_event, + "Unexpected valid event=%d", + *rte_event_pmd_selftest_seqn(ev.mbuf)); + } + return 0; +} + +static inline int +generate_random_events(const unsigned int total_events) +{ + struct rte_event_dev_info info; + uint32_t queue_count; + unsigned int i; + int ret; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + + ret = rte_event_dev_info_get(evdev, &info); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get event dev info"); + for (i = 0; i < total_events; i++) { + ret = inject_events( + rte_rand() % info.max_event_queue_flows /*flow_id */, + RTE_EVENT_TYPE_CPU /* event_type */, + rte_rand() % 256 /* sub_event_type */, + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1), + rte_rand() % queue_count /* queue */, 0 /* port */, + 1 /* events */); + if (ret) + return -1; + } + return ret; +} + +static inline int +validate_event(struct rte_event *ev) +{ + struct event_attr *attr; + + attr = rte_pktmbuf_mtod(ev->mbuf, struct event_attr *); + RTE_TEST_ASSERT_EQUAL(attr->flow_id, ev->flow_id, + "flow_id mismatch enq=%d deq =%d", attr->flow_id, + ev->flow_id); + RTE_TEST_ASSERT_EQUAL(attr->event_type, ev->event_type, + "event_type mismatch enq=%d deq =%d", + attr->event_type, ev->event_type); + RTE_TEST_ASSERT_EQUAL(attr->sub_event_type, ev->sub_event_type, + "sub_event_type mismatch enq=%d deq =%d", + attr->sub_event_type, ev->sub_event_type); + RTE_TEST_ASSERT_EQUAL(attr->sched_type, ev->sched_type, + "sched_type mismatch enq=%d deq =%d", + attr->sched_type, ev->sched_type); + RTE_TEST_ASSERT_EQUAL(attr->queue, ev->queue_id, + "queue mismatch enq=%d deq =%d", attr->queue, + ev->queue_id); + return 0; +} + +typedef int (*validate_event_cb)(uint32_t index, uint8_t port, + struct rte_event *ev); + +static inline int +consume_events(uint8_t port, const uint32_t total_events, validate_event_cb fn) +{ + uint32_t events = 0, forward_progress_cnt = 0, index = 0; + uint16_t valid_event; + struct rte_event ev; + int ret; + + while (1) { + if (++forward_progress_cnt > UINT16_MAX) { + plt_err("Detected deadlock"); + return -1; + } + + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + if (!valid_event) + continue; + + forward_progress_cnt = 0; + ret = validate_event(&ev); + if (ret) + return -1; + + if (fn != NULL) { + ret = fn(index, port, &ev); + RTE_TEST_ASSERT_SUCCESS( + ret, "Failed to validate test specific event"); + } + + ++index; + + rte_pktmbuf_free(ev.mbuf); + if (++events >= total_events) + break; + } + + return check_excess_events(port); +} + +static int +validate_simple_enqdeq(uint32_t index, uint8_t port, struct rte_event *ev) +{ + RTE_SET_USED(port); + RTE_TEST_ASSERT_EQUAL(index, *rte_event_pmd_selftest_seqn(ev->mbuf), + "index=%d != seqn=%d", index, + *rte_event_pmd_selftest_seqn(ev->mbuf)); + return 0; +} + +static inline int +test_simple_enqdeq(uint8_t sched_type) +{ + int ret; + + ret = inject_events(0 /*flow_id */, RTE_EVENT_TYPE_CPU /* event_type */, + 0 /* sub_event_type */, sched_type, 0 /* queue */, + 0 /* port */, MAX_EVENTS); + if (ret) + return -1; + + return consume_events(0 /* port */, MAX_EVENTS, validate_simple_enqdeq); +} + +static int +test_simple_enqdeq_ordered(void) +{ + return test_simple_enqdeq(RTE_SCHED_TYPE_ORDERED); +} + +static int +test_simple_enqdeq_atomic(void) +{ + return test_simple_enqdeq(RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_simple_enqdeq_parallel(void) +{ + return test_simple_enqdeq(RTE_SCHED_TYPE_PARALLEL); +} + +/* + * Generate a prescribed number of events and spread them across available + * queues. On dequeue, using single event port(port 0) verify the enqueued + * event attributes + */ +static int +test_multi_queue_enq_single_port_deq(void) +{ + int ret; + + ret = generate_random_events(MAX_EVENTS); + if (ret) + return -1; + + return consume_events(0 /* port */, MAX_EVENTS, NULL); +} + +/* + * Inject 0..MAX_EVENTS events over 0..queue_count with modulus + * operation + * + * For example, Inject 32 events over 0..7 queues + * enqueue events 0, 8, 16, 24 in queue 0 + * enqueue events 1, 9, 17, 25 in queue 1 + * .. + * .. + * enqueue events 7, 15, 23, 31 in queue 7 + * + * On dequeue, Validate the events comes in 0,8,16,24,1,9,17,25..,7,15,23,31 + * order from queue0(highest priority) to queue7(lowest_priority) + */ +static int +validate_queue_priority(uint32_t index, uint8_t port, struct rte_event *ev) +{ + uint32_t queue_count; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + if (queue_count > 8) + queue_count = 8; + uint32_t range = MAX_EVENTS / queue_count; + uint32_t expected_val = (index % range) * queue_count; + + expected_val += ev->queue_id; + RTE_SET_USED(port); + RTE_TEST_ASSERT_EQUAL( + *rte_event_pmd_selftest_seqn(ev->mbuf), expected_val, + "seqn=%d index=%d expected=%d range=%d nb_queues=%d max_event=%d", + *rte_event_pmd_selftest_seqn(ev->mbuf), index, expected_val, + range, queue_count, MAX_EVENTS); + return 0; +} + +static int +test_multi_queue_priority(void) +{ + int i, max_evts_roundoff; + /* See validate_queue_priority() comments for priority validate logic */ + uint32_t queue_count; + struct rte_mbuf *m; + uint8_t queue; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + if (queue_count > 8) + queue_count = 8; + max_evts_roundoff = MAX_EVENTS / queue_count; + max_evts_roundoff *= queue_count; + + for (i = 0; i < max_evts_roundoff; i++) { + struct rte_event ev = {.event = 0, .u64 = 0}; + + m = rte_pktmbuf_alloc(eventdev_test_mempool); + RTE_TEST_ASSERT_NOT_NULL(m, "mempool alloc failed"); + + *rte_event_pmd_selftest_seqn(m) = i; + queue = i % queue_count; + update_event_and_validation_attr(m, &ev, 0, RTE_EVENT_TYPE_CPU, + 0, RTE_SCHED_TYPE_PARALLEL, + queue, 0); + rte_event_enqueue_burst(evdev, 0, &ev, 1); + } + + return consume_events(0, max_evts_roundoff, validate_queue_priority); +} + +static int +worker_multi_port_fn(void *arg) +{ + struct test_core_param *param = arg; + uint32_t *total_events = param->total_events; + uint8_t port = param->port; + uint16_t valid_event; + struct rte_event ev; + int ret; + + while (__atomic_load_n(total_events, __ATOMIC_RELAXED) > 0) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + if (!valid_event) + continue; + + ret = validate_event(&ev); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to validate event"); + rte_pktmbuf_free(ev.mbuf); + __atomic_sub_fetch(total_events, 1, __ATOMIC_RELAXED); + } + + return 0; +} + +static inline int +wait_workers_to_join(const uint32_t *count) +{ + uint64_t cycles, print_cycles; + + cycles = rte_get_timer_cycles(); + print_cycles = cycles; + while (__atomic_load_n(count, __ATOMIC_RELAXED)) { + uint64_t new_cycles = rte_get_timer_cycles(); + + if (new_cycles - print_cycles > rte_get_timer_hz()) { + plt_info("Events %d", + __atomic_load_n(count, __ATOMIC_RELAXED)); + print_cycles = new_cycles; + } + if (new_cycles - cycles > rte_get_timer_hz() * 10000000000) { + plt_err("No schedules for seconds, deadlock (%d)", + __atomic_load_n(count, __ATOMIC_RELAXED)); + rte_event_dev_dump(evdev, stdout); + cycles = new_cycles; + return -1; + } + } + rte_eal_mp_wait_lcore(); + + return 0; +} + +static inline int +launch_workers_and_wait(int (*main_thread)(void *), + int (*worker_thread)(void *), uint32_t total_events, + uint8_t nb_workers, uint8_t sched_type) +{ + uint32_t atomic_total_events; + struct test_core_param *param; + uint64_t dequeue_tmo_ticks; + uint8_t port = 0; + int w_lcore; + int ret; + + if (!nb_workers) + return 0; + + __atomic_store_n(&atomic_total_events, total_events, __ATOMIC_RELAXED); + seqn_list_init(); + + param = malloc(sizeof(struct test_core_param) * nb_workers); + if (!param) + return -1; + + ret = rte_event_dequeue_timeout_ticks( + evdev, rte_rand() % 10000000 /* 10ms */, &dequeue_tmo_ticks); + if (ret) { + free(param); + return -1; + } + + param[0].total_events = &atomic_total_events; + param[0].sched_type = sched_type; + param[0].port = 0; + param[0].dequeue_tmo_ticks = dequeue_tmo_ticks; + rte_wmb(); + + w_lcore = rte_get_next_lcore( + /* start core */ -1, + /* skip main */ 1, + /* wrap */ 0); + rte_eal_remote_launch(main_thread, ¶m[0], w_lcore); + + for (port = 1; port < nb_workers; port++) { + param[port].total_events = &atomic_total_events; + param[port].sched_type = sched_type; + param[port].port = port; + param[port].dequeue_tmo_ticks = dequeue_tmo_ticks; + rte_atomic_thread_fence(__ATOMIC_RELEASE); + w_lcore = rte_get_next_lcore(w_lcore, 1, 0); + rte_eal_remote_launch(worker_thread, ¶m[port], w_lcore); + } + + rte_atomic_thread_fence(__ATOMIC_RELEASE); + ret = wait_workers_to_join(&atomic_total_events); + free(param); + + return ret; +} + +/* + * Generate a prescribed number of events and spread them across available + * queues. Dequeue the events through multiple ports and verify the enqueued + * event attributes + */ +static int +test_multi_queue_enq_multi_port_deq(void) +{ + const unsigned int total_events = MAX_EVENTS; + uint32_t nr_ports; + int ret; + + ret = generate_random_events(total_events); + if (ret) + return -1; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), + "Port count get failed"); + nr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1); + + if (!nr_ports) { + plt_err("Not enough ports=%d or workers=%d", nr_ports, + rte_lcore_count() - 1); + return 0; + } + + return launch_workers_and_wait(worker_multi_port_fn, + worker_multi_port_fn, total_events, + nr_ports, 0xff /* invalid */); +} + +static void +flush(uint8_t dev_id, struct rte_event event, void *arg) +{ + unsigned int *count = arg; + + RTE_SET_USED(dev_id); + if (event.event_type == RTE_EVENT_TYPE_CPU) + *count = *count + 1; +} + +static int +test_dev_stop_flush(void) +{ + unsigned int total_events = MAX_EVENTS, count = 0; + int ret; + + ret = generate_random_events(total_events); + if (ret) + return -1; + + ret = rte_event_dev_stop_flush_callback_register(evdev, flush, &count); + if (ret) + return -2; + rte_event_dev_stop(evdev); + ret = rte_event_dev_stop_flush_callback_register(evdev, NULL, NULL); + if (ret) + return -3; + RTE_TEST_ASSERT_EQUAL(total_events, count, + "count mismatch total_events=%d count=%d", + total_events, count); + + return 0; +} + +static int +validate_queue_to_port_single_link(uint32_t index, uint8_t port, + struct rte_event *ev) +{ + RTE_SET_USED(index); + RTE_TEST_ASSERT_EQUAL(port, ev->queue_id, + "queue mismatch enq=%d deq =%d", port, + ev->queue_id); + + return 0; +} + +/* + * Link queue x to port x and check correctness of link by checking + * queue_id == x on dequeue on the specific port x + */ +static int +test_queue_to_port_single_link(void) +{ + int i, nr_links, ret; + uint32_t queue_count; + uint32_t port_count; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &port_count), + "Port count get failed"); + + /* Unlink all connections that created in eventdev_setup */ + for (i = 0; i < (int)port_count; i++) { + ret = rte_event_port_unlink(evdev, i, NULL, 0); + RTE_TEST_ASSERT(ret >= 0, "Failed to unlink all queues port=%d", + i); + } + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + + nr_links = RTE_MIN(port_count, queue_count); + const unsigned int total_events = MAX_EVENTS / nr_links; + + /* Link queue x to port x and inject events to queue x through port x */ + for (i = 0; i < nr_links; i++) { + uint8_t queue = (uint8_t)i; + + ret = rte_event_port_link(evdev, i, &queue, NULL, 1); + RTE_TEST_ASSERT(ret == 1, "Failed to link queue to port %d", i); + + ret = inject_events(0x100 /*flow_id */, + RTE_EVENT_TYPE_CPU /* event_type */, + rte_rand() % 256 /* sub_event_type */, + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1), + queue /* queue */, i /* port */, + total_events /* events */); + if (ret) + return -1; + } + + /* Verify the events generated from correct queue */ + for (i = 0; i < nr_links; i++) { + ret = consume_events(i /* port */, total_events, + validate_queue_to_port_single_link); + if (ret) + return -1; + } + + return 0; +} + +static int +validate_queue_to_port_multi_link(uint32_t index, uint8_t port, + struct rte_event *ev) +{ + RTE_SET_USED(index); + RTE_TEST_ASSERT_EQUAL(port, (ev->queue_id & 0x1), + "queue mismatch enq=%d deq =%d", port, + ev->queue_id); + + return 0; +} + +/* + * Link all even number of queues to port 0 and all odd number of queues to + * port 1 and verify the link connection on dequeue + */ +static int +test_queue_to_port_multi_link(void) +{ + int ret, port0_events = 0, port1_events = 0; + uint32_t nr_queues = 0; + uint32_t nr_ports = 0; + uint8_t queue, port; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &nr_queues), + "Queue count get failed"); + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &nr_queues), + "Queue count get failed"); + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), + "Port count get failed"); + + if (nr_ports < 2) { + plt_err("Not enough ports to test ports=%d", nr_ports); + return 0; + } + + /* Unlink all connections that created in eventdev_setup */ + for (port = 0; port < nr_ports; port++) { + ret = rte_event_port_unlink(evdev, port, NULL, 0); + RTE_TEST_ASSERT(ret >= 0, "Failed to unlink all queues port=%d", + port); + } + + unsigned int total_events = MAX_EVENTS / nr_queues; + if (!total_events) { + nr_queues = MAX_EVENTS; + total_events = MAX_EVENTS / nr_queues; + } + + /* Link all even number of queues to port0 and odd numbers to port 1*/ + for (queue = 0; queue < nr_queues; queue++) { + port = queue & 0x1; + ret = rte_event_port_link(evdev, port, &queue, NULL, 1); + RTE_TEST_ASSERT(ret == 1, "Failed to link queue=%d to port=%d", + queue, port); + + ret = inject_events(0x100 /*flow_id */, + RTE_EVENT_TYPE_CPU /* event_type */, + rte_rand() % 256 /* sub_event_type */, + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1), + queue /* queue */, port /* port */, + total_events /* events */); + if (ret) + return -1; + + if (port == 0) + port0_events += total_events; + else + port1_events += total_events; + } + + ret = consume_events(0 /* port */, port0_events, + validate_queue_to_port_multi_link); + if (ret) + return -1; + ret = consume_events(1 /* port */, port1_events, + validate_queue_to_port_multi_link); + if (ret) + return -1; + + return 0; +} + +static int +worker_flow_based_pipeline(void *arg) +{ + struct test_core_param *param = arg; + uint64_t dequeue_tmo_ticks = param->dequeue_tmo_ticks; + uint32_t *total_events = param->total_events; + uint8_t new_sched_type = param->sched_type; + uint8_t port = param->port; + uint16_t valid_event; + struct rte_event ev; + + while (__atomic_load_n(total_events, __ATOMIC_RELAXED) > 0) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, + dequeue_tmo_ticks); + if (!valid_event) + continue; + + /* Events from stage 0 */ + if (ev.sub_event_type == 0) { + /* Move to atomic flow to maintain the ordering */ + ev.flow_id = 0x2; + ev.event_type = RTE_EVENT_TYPE_CPU; + ev.sub_event_type = 1; /* stage 1 */ + ev.sched_type = new_sched_type; + ev.op = RTE_EVENT_OP_FORWARD; + rte_event_enqueue_burst(evdev, port, &ev, 1); + } else if (ev.sub_event_type == 1) { /* Events from stage 1*/ + uint32_t seqn = *rte_event_pmd_selftest_seqn(ev.mbuf); + + if (seqn_list_update(seqn) == 0) { + rte_pktmbuf_free(ev.mbuf); + __atomic_sub_fetch(total_events, 1, + __ATOMIC_RELAXED); + } else { + plt_err("Failed to update seqn_list"); + return -1; + } + } else { + plt_err("Invalid ev.sub_event_type = %d", + ev.sub_event_type); + return -1; + } + } + return 0; +} + +static int +test_multiport_flow_sched_type_test(uint8_t in_sched_type, + uint8_t out_sched_type) +{ + const unsigned int total_events = MAX_EVENTS; + uint32_t nr_ports; + int ret; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), + "Port count get failed"); + nr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1); + + if (!nr_ports) { + plt_err("Not enough ports=%d or workers=%d", nr_ports, + rte_lcore_count() - 1); + return 0; + } + + /* Injects events with a 0 sequence number to total_events */ + ret = inject_events( + 0x1 /*flow_id */, RTE_EVENT_TYPE_CPU /* event_type */, + 0 /* sub_event_type (stage 0) */, in_sched_type, 0 /* queue */, + 0 /* port */, total_events /* events */); + if (ret) + return -1; + + rte_mb(); + ret = launch_workers_and_wait(worker_flow_based_pipeline, + worker_flow_based_pipeline, total_events, + nr_ports, out_sched_type); + if (ret) + return -1; + + if (in_sched_type != RTE_SCHED_TYPE_PARALLEL && + out_sched_type == RTE_SCHED_TYPE_ATOMIC) { + /* Check the events order maintained or not */ + return seqn_list_check(total_events); + } + + return 0; +} + +/* Multi port ordered to atomic transaction */ +static int +test_multi_port_flow_ordered_to_atomic(void) +{ + /* Ingress event order test */ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ORDERED, + RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_multi_port_flow_ordered_to_ordered(void) +{ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ORDERED, + RTE_SCHED_TYPE_ORDERED); +} + +static int +test_multi_port_flow_ordered_to_parallel(void) +{ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ORDERED, + RTE_SCHED_TYPE_PARALLEL); +} + +static int +test_multi_port_flow_atomic_to_atomic(void) +{ + /* Ingress event order test */ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ATOMIC, + RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_multi_port_flow_atomic_to_ordered(void) +{ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ATOMIC, + RTE_SCHED_TYPE_ORDERED); +} + +static int +test_multi_port_flow_atomic_to_parallel(void) +{ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ATOMIC, + RTE_SCHED_TYPE_PARALLEL); +} + +static int +test_multi_port_flow_parallel_to_atomic(void) +{ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_PARALLEL, + RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_multi_port_flow_parallel_to_ordered(void) +{ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_PARALLEL, + RTE_SCHED_TYPE_ORDERED); +} + +static int +test_multi_port_flow_parallel_to_parallel(void) +{ + return test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_PARALLEL, + RTE_SCHED_TYPE_PARALLEL); +} + +static int +worker_group_based_pipeline(void *arg) +{ + struct test_core_param *param = arg; + uint64_t dequeue_tmo_ticks = param->dequeue_tmo_ticks; + uint32_t *total_events = param->total_events; + uint8_t new_sched_type = param->sched_type; + uint8_t port = param->port; + uint16_t valid_event; + struct rte_event ev; + + while (__atomic_load_n(total_events, __ATOMIC_RELAXED) > 0) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, + dequeue_tmo_ticks); + if (!valid_event) + continue; + + /* Events from stage 0(group 0) */ + if (ev.queue_id == 0) { + /* Move to atomic flow to maintain the ordering */ + ev.flow_id = 0x2; + ev.event_type = RTE_EVENT_TYPE_CPU; + ev.sched_type = new_sched_type; + ev.queue_id = 1; /* Stage 1*/ + ev.op = RTE_EVENT_OP_FORWARD; + rte_event_enqueue_burst(evdev, port, &ev, 1); + } else if (ev.queue_id == 1) { /* Events from stage 1(group 1)*/ + uint32_t seqn = *rte_event_pmd_selftest_seqn(ev.mbuf); + + if (seqn_list_update(seqn) == 0) { + rte_pktmbuf_free(ev.mbuf); + __atomic_sub_fetch(total_events, 1, + __ATOMIC_RELAXED); + } else { + plt_err("Failed to update seqn_list"); + return -1; + } + } else { + plt_err("Invalid ev.queue_id = %d", ev.queue_id); + return -1; + } + } + + return 0; +} + +static int +test_multiport_queue_sched_type_test(uint8_t in_sched_type, + uint8_t out_sched_type) +{ + const unsigned int total_events = MAX_EVENTS; + uint32_t queue_count; + uint32_t nr_ports; + int ret; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), + "Port count get failed"); + + nr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1); + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + if (queue_count < 2 || !nr_ports) { + plt_err("Not enough queues=%d ports=%d or workers=%d", + queue_count, nr_ports, rte_lcore_count() - 1); + return 0; + } + + /* Injects events with a 0 sequence number to total_events */ + ret = inject_events( + 0x1 /*flow_id */, RTE_EVENT_TYPE_CPU /* event_type */, + 0 /* sub_event_type (stage 0) */, in_sched_type, 0 /* queue */, + 0 /* port */, total_events /* events */); + if (ret) + return -1; + + ret = launch_workers_and_wait(worker_group_based_pipeline, + worker_group_based_pipeline, total_events, + nr_ports, out_sched_type); + if (ret) + return -1; + + if (in_sched_type != RTE_SCHED_TYPE_PARALLEL && + out_sched_type == RTE_SCHED_TYPE_ATOMIC) { + /* Check the events order maintained or not */ + return seqn_list_check(total_events); + } + + return 0; +} + +static int +test_multi_port_queue_ordered_to_atomic(void) +{ + /* Ingress event order test */ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED, + RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_multi_port_queue_ordered_to_ordered(void) +{ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED, + RTE_SCHED_TYPE_ORDERED); +} + +static int +test_multi_port_queue_ordered_to_parallel(void) +{ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED, + RTE_SCHED_TYPE_PARALLEL); +} + +static int +test_multi_port_queue_atomic_to_atomic(void) +{ + /* Ingress event order test */ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC, + RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_multi_port_queue_atomic_to_ordered(void) +{ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC, + RTE_SCHED_TYPE_ORDERED); +} + +static int +test_multi_port_queue_atomic_to_parallel(void) +{ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC, + RTE_SCHED_TYPE_PARALLEL); +} + +static int +test_multi_port_queue_parallel_to_atomic(void) +{ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL, + RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_multi_port_queue_parallel_to_ordered(void) +{ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL, + RTE_SCHED_TYPE_ORDERED); +} + +static int +test_multi_port_queue_parallel_to_parallel(void) +{ + return test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL, + RTE_SCHED_TYPE_PARALLEL); +} + +static int +worker_flow_based_pipeline_max_stages_rand_sched_type(void *arg) +{ + struct test_core_param *param = arg; + uint32_t *total_events = param->total_events; + uint8_t port = param->port; + uint16_t valid_event; + struct rte_event ev; + + while (__atomic_load_n(total_events, __ATOMIC_RELAXED) > 0) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + if (!valid_event) + continue; + + if (ev.sub_event_type == MAX_STAGES) { /* last stage */ + rte_pktmbuf_free(ev.mbuf); + __atomic_sub_fetch(total_events, 1, __ATOMIC_RELAXED); + } else { + ev.event_type = RTE_EVENT_TYPE_CPU; + ev.sub_event_type++; + ev.sched_type = + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1); + ev.op = RTE_EVENT_OP_FORWARD; + rte_event_enqueue_burst(evdev, port, &ev, 1); + } + } + + return 0; +} + +static int +launch_multi_port_max_stages_random_sched_type(int (*fn)(void *)) +{ + uint32_t nr_ports; + int ret; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), + "Port count get failed"); + nr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1); + + if (!nr_ports) { + plt_err("Not enough ports=%d or workers=%d", nr_ports, + rte_lcore_count() - 1); + return 0; + } + + /* Injects events with a 0 sequence number to total_events */ + ret = inject_events( + 0x1 /*flow_id */, RTE_EVENT_TYPE_CPU /* event_type */, + 0 /* sub_event_type (stage 0) */, + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1) /* sched_type */, + 0 /* queue */, 0 /* port */, MAX_EVENTS /* events */); + if (ret) + return -1; + + return launch_workers_and_wait(fn, fn, MAX_EVENTS, nr_ports, + 0xff /* invalid */); +} + +/* Flow based pipeline with maximum stages with random sched type */ +static int +test_multi_port_flow_max_stages_random_sched_type(void) +{ + return launch_multi_port_max_stages_random_sched_type( + worker_flow_based_pipeline_max_stages_rand_sched_type); +} + +static int +worker_queue_based_pipeline_max_stages_rand_sched_type(void *arg) +{ + struct test_core_param *param = arg; + uint8_t port = param->port; + uint32_t queue_count; + uint16_t valid_event; + struct rte_event ev; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + uint8_t nr_queues = queue_count; + uint32_t *total_events = param->total_events; + + while (__atomic_load_n(total_events, __ATOMIC_RELAXED) > 0) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + if (!valid_event) + continue; + + if (ev.queue_id == nr_queues - 1) { /* last stage */ + rte_pktmbuf_free(ev.mbuf); + __atomic_sub_fetch(total_events, 1, __ATOMIC_RELAXED); + } else { + ev.event_type = RTE_EVENT_TYPE_CPU; + ev.queue_id++; + ev.sched_type = + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1); + ev.op = RTE_EVENT_OP_FORWARD; + rte_event_enqueue_burst(evdev, port, &ev, 1); + } + } + + return 0; +} + +/* Queue based pipeline with maximum stages with random sched type */ +static int +test_multi_port_queue_max_stages_random_sched_type(void) +{ + return launch_multi_port_max_stages_random_sched_type( + worker_queue_based_pipeline_max_stages_rand_sched_type); +} + +static int +worker_mixed_pipeline_max_stages_rand_sched_type(void *arg) +{ + struct test_core_param *param = arg; + uint8_t port = param->port; + uint32_t queue_count; + uint16_t valid_event; + struct rte_event ev; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), + "Queue count get failed"); + uint8_t nr_queues = queue_count; + uint32_t *total_events = param->total_events; + + while (__atomic_load_n(total_events, __ATOMIC_RELAXED) > 0) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + if (!valid_event) + continue; + + if (ev.queue_id == nr_queues - 1) { /* Last stage */ + rte_pktmbuf_free(ev.mbuf); + __atomic_sub_fetch(total_events, 1, __ATOMIC_RELAXED); + } else { + ev.event_type = RTE_EVENT_TYPE_CPU; + ev.queue_id++; + ev.sub_event_type = rte_rand() % 256; + ev.sched_type = + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1); + ev.op = RTE_EVENT_OP_FORWARD; + rte_event_enqueue_burst(evdev, port, &ev, 1); + } + } + + return 0; +} + +/* Queue and flow based pipeline with maximum stages with random sched type */ +static int +test_multi_port_mixed_max_stages_random_sched_type(void) +{ + return launch_multi_port_max_stages_random_sched_type( + worker_mixed_pipeline_max_stages_rand_sched_type); +} + +static int +worker_ordered_flow_producer(void *arg) +{ + struct test_core_param *param = arg; + uint8_t port = param->port; + struct rte_mbuf *m; + int counter = 0; + + while (counter < NUM_PACKETS) { + m = rte_pktmbuf_alloc(eventdev_test_mempool); + if (m == NULL) + continue; + + *rte_event_pmd_selftest_seqn(m) = counter++; + + struct rte_event ev = {.event = 0, .u64 = 0}; + + ev.flow_id = 0x1; /* Generate a fat flow */ + ev.sub_event_type = 0; + /* Inject the new event */ + ev.op = RTE_EVENT_OP_NEW; + ev.event_type = RTE_EVENT_TYPE_CPU; + ev.sched_type = RTE_SCHED_TYPE_ORDERED; + ev.queue_id = 0; + ev.mbuf = m; + rte_event_enqueue_burst(evdev, port, &ev, 1); + } + + return 0; +} + +static inline int +test_producer_consumer_ingress_order_test(int (*fn)(void *)) +{ + uint32_t nr_ports; + + RTE_TEST_ASSERT_SUCCESS( + rte_event_dev_attr_get(evdev, RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), + "Port count get failed"); + nr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1); + + if (rte_lcore_count() < 3 || nr_ports < 2) { + plt_err("### Not enough cores for test."); + return 0; + } + + launch_workers_and_wait(worker_ordered_flow_producer, fn, NUM_PACKETS, + nr_ports, RTE_SCHED_TYPE_ATOMIC); + /* Check the events order maintained or not */ + return seqn_list_check(NUM_PACKETS); +} + +/* Flow based producer consumer ingress order test */ +static int +test_flow_producer_consumer_ingress_order_test(void) +{ + return test_producer_consumer_ingress_order_test( + worker_flow_based_pipeline); +} + +/* Queue based producer consumer ingress order test */ +static int +test_queue_producer_consumer_ingress_order_test(void) +{ + return test_producer_consumer_ingress_order_test( + worker_group_based_pipeline); +} + +static void +cnxk_test_run(int (*setup)(void), void (*tdown)(void), int (*test)(void), + const char *name) +{ + if (setup() < 0) { + printf("Error setting up test %s", name); + unsupported++; + } else { + if (test() < 0) { + failed++; + printf("+ TestCase [%2d] : %s failed\n", total, name); + } else { + passed++; + printf("+ TestCase [%2d] : %s succeeded\n", total, + name); + } + } + + total++; + tdown(); +} + +static int +cnxk_sso_testsuite_run(const char *dev_name) +{ + int rc; + + testsuite_setup(dev_name); + + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_simple_enqdeq_ordered); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_simple_enqdeq_atomic); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_simple_enqdeq_parallel); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_queue_enq_single_port_deq); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, test_dev_stop_flush); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_queue_enq_multi_port_deq); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_queue_to_port_single_link); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_queue_to_port_multi_link); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_ordered_to_atomic); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_ordered_to_ordered); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_ordered_to_parallel); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_atomic_to_atomic); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_atomic_to_ordered); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_atomic_to_parallel); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_parallel_to_atomic); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_parallel_to_ordered); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_parallel_to_parallel); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_ordered_to_atomic); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_ordered_to_ordered); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_ordered_to_parallel); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_atomic_to_atomic); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_atomic_to_ordered); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_atomic_to_parallel); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_parallel_to_atomic); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_parallel_to_ordered); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_parallel_to_parallel); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_flow_max_stages_random_sched_type); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_queue_max_stages_random_sched_type); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_port_mixed_max_stages_random_sched_type); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_flow_producer_consumer_ingress_order_test); + CNXK_TEST_RUN(eventdev_setup, eventdev_teardown, + test_queue_producer_consumer_ingress_order_test); + CNXK_TEST_RUN(eventdev_setup_priority, eventdev_teardown, + test_multi_queue_priority); + CNXK_TEST_RUN(eventdev_setup_dequeue_timeout, eventdev_teardown, + test_multi_port_flow_ordered_to_atomic); + CNXK_TEST_RUN(eventdev_setup_dequeue_timeout, eventdev_teardown, + test_multi_port_queue_ordered_to_atomic); + printf("Total tests : %d\n", total); + printf("Passed : %d\n", passed); + printf("Failed : %d\n", failed); + printf("Not supported : %d\n", unsupported); + + rc = failed; + testsuite_teardown(); + + return rc; +} + +int +cnxk_sso_selftest(const char *dev_name) +{ + const struct rte_memzone *mz; + struct cnxk_sso_evdev *dev; + int rc = -1; + + mz = rte_memzone_lookup(CNXK_SSO_MZ_NAME); + if (mz == NULL) + return rc; + + dev = (void *)*((uint64_t *)mz->addr); + if (roc_model_runtime_is_cn9k()) { + /* Verify single ws mode. */ + printf("Verifying CN9K Single workslot mode\n"); + dev->dual_ws = 0; + cn9k_sso_set_rsrc(dev); + if (cnxk_sso_testsuite_run(dev_name)) + return rc; + /* Verift dual ws mode. */ + printf("Verifying CN9K Dual workslot mode\n"); + dev->dual_ws = 1; + cn9k_sso_set_rsrc(dev); + if (cnxk_sso_testsuite_run(dev_name)) + return rc; + } + + if (roc_model_runtime_is_cn10k()) { + printf("Verifying CN10K workslot getwork mode none\n"); + dev->gw_mode = CN10K_GW_MODE_NONE; + if (cnxk_sso_testsuite_run(dev_name)) + return rc; + printf("Verifying CN10K workslot getwork mode prefetch\n"); + dev->gw_mode = CN10K_GW_MODE_PREF; + if (cnxk_sso_testsuite_run(dev_name)) + return rc; + printf("Verifying CN10K workslot getwork mode smart prefetch\n"); + dev->gw_mode = CN10K_GW_MODE_PREF_WFE; + if (cnxk_sso_testsuite_run(dev_name)) + return rc; + } + + return 0; +} diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index 57b3f66ea..e37ea3478 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -13,6 +13,7 @@ sources = files('cn10k_worker.c', 'cn9k_worker.c', 'cn9k_eventdev.c', 'cnxk_eventdev.c', + 'cnxk_eventdev_selftest.c' ) deps += ['bus_pci', 'common_cnxk'] From patchwork Tue May 4 00:27:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92699 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 12B6BA0562; Tue, 4 May 2021 02:30:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 102354110A; Tue, 4 May 2021 02:29:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 25C9D41103 for ; Tue, 4 May 2021 02:29:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGNp002337; Mon, 3 May 2021 17:29:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=uBF+UsGDnFLx/5AhGznfAqHC6L6DMPhcy+82GzHqa84=; b=HJ4AF4mkdgqv97CL7k3Xj7JJ8eYfrUI/h0XaX8cTo4y7K/PS9c0OXVErQQu8SG6DVdRD XWrhwmYOkyivmjouO8db2NEt5ra5rBHOdfGHqTzr29clIBME2S8bmR0FsVpP9jR5beYK 3zzA1eEISLATACBs5A0M7L1XBzLM7EfAiYSGyGl0w3l2nCc5hCkTkpiPBbun4vnfpN33 u8txhVnoqyOlN86hgIXQTd/HjwD3vFOfqJPNumobW0SJ7e1HhGlUfgpygVsK4Au0AjAE 0wTh8SaGyn4EIiwXtqJhdVKr2GC0t6Qj2VKZcSm26MVjs6HiBelQ9u2/qsV3BKEE00fC cQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6mw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 03 May 2021 17:29:02 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:59 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id A193E3F703F; Mon, 3 May 2021 17:28:57 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:11 +0530 Message-ID: <20210504002726.525-22-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: hTpySH1SrnrWIcoiNytkREbW1L2zZSAg X-Proofpoint-ORIG-GUID: hTpySH1SrnrWIcoiNytkREbW1L2zZSAg X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 21/35] event/cnxk: add event port and queue xstats X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add support for retrieving statistics from SSO HWS and HWGRP. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_sso.c | 63 +++++ drivers/common/cnxk/roc_sso.h | 19 ++ drivers/common/cnxk/version.map | 2 + drivers/event/cnxk/cnxk_eventdev.h | 15 ++ drivers/event/cnxk/cnxk_eventdev_stats.c | 289 +++++++++++++++++++++++ drivers/event/cnxk/meson.build | 3 +- 6 files changed, 390 insertions(+), 1 deletion(-) create mode 100644 drivers/event/cnxk/cnxk_eventdev_stats.c diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 80d032039..1ccf2626b 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -279,6 +279,69 @@ roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], return nb_hwgrp; } +int +roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws, + struct roc_sso_hws_stats *stats) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso_hws_stats *req_rsp; + int rc; + + req_rsp = (struct sso_hws_stats *)mbox_alloc_msg_sso_hws_get_stats( + dev->mbox); + if (req_rsp == NULL) { + rc = mbox_process(dev->mbox); + if (rc < 0) + return rc; + req_rsp = (struct sso_hws_stats *) + mbox_alloc_msg_sso_hws_get_stats(dev->mbox); + if (req_rsp == NULL) + return -ENOSPC; + } + req_rsp->hws = hws; + rc = mbox_process_msg(dev->mbox, (void **)&req_rsp); + if (rc) + return rc; + + stats->arbitration = req_rsp->arbitration; + return 0; +} + +int +roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp, + struct roc_sso_hwgrp_stats *stats) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso_grp_stats *req_rsp; + int rc; + + req_rsp = (struct sso_grp_stats *)mbox_alloc_msg_sso_grp_get_stats( + dev->mbox); + if (req_rsp == NULL) { + rc = mbox_process(dev->mbox); + if (rc < 0) + return rc; + req_rsp = (struct sso_grp_stats *) + mbox_alloc_msg_sso_grp_get_stats(dev->mbox); + if (req_rsp == NULL) + return -ENOSPC; + } + req_rsp->grp = hwgrp; + rc = mbox_process_msg(dev->mbox, (void **)&req_rsp); + if (rc) + return rc; + + stats->aw_status = req_rsp->aw_status; + stats->dq_pc = req_rsp->dq_pc; + stats->ds_pc = req_rsp->ds_pc; + stats->ext_pc = req_rsp->ext_pc; + stats->page_cnt = req_rsp->page_cnt; + stats->ts_pc = req_rsp->ts_pc; + stats->wa_pc = req_rsp->wa_pc; + stats->ws_pc = req_rsp->ws_pc; + return 0; +} + int roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp) diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index f85799ba8..a6030e7d8 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -12,6 +12,21 @@ struct roc_sso_hwgrp_qos { uint8_t taq_prcnt; }; +struct roc_sso_hws_stats { + uint64_t arbitration; +}; + +struct roc_sso_hwgrp_stats { + uint64_t ws_pc; + uint64_t ext_pc; + uint64_t wa_pc; + uint64_t ts_pc; + uint64_t ds_pc; + uint64_t dq_pc; + uint64_t aw_status; + uint64_t page_cnt; +}; + struct roc_sso { struct plt_pci_device *pci_dev; /* Public data. */ @@ -61,5 +76,9 @@ uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, /* Debug */ void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t hwgrp, FILE *f); +int __roc_api roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp, + struct roc_sso_hwgrp_stats *stats); +int __roc_api roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws, + struct roc_sso_hws_stats *stats); #endif /* _ROC_SSOW_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 5f2264f23..8e67c83a6 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -183,8 +183,10 @@ INTERNAL { roc_sso_hwgrp_qos_config; roc_sso_hwgrp_release_xaq; roc_sso_hwgrp_set_priority; + roc_sso_hwgrp_stats_get; roc_sso_hws_base_get; roc_sso_hws_link; + roc_sso_hws_stats_get; roc_sso_hws_unlink; roc_sso_ns_to_gw; roc_sso_rsrc_fini; diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 9af04bc3d..abe36f21f 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -214,6 +214,21 @@ int cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn); int cnxk_sso_selftest(const char *dev_name); void cnxk_sso_dump(struct rte_eventdev *event_dev, FILE *f); +/* Stats API. */ +int cnxk_sso_xstats_get_names(const struct rte_eventdev *event_dev, + enum rte_event_dev_xstats_mode mode, + uint8_t queue_port_id, + struct rte_event_dev_xstats_name *xstats_names, + unsigned int *ids, unsigned int size); +int cnxk_sso_xstats_get(const struct rte_eventdev *event_dev, + enum rte_event_dev_xstats_mode mode, + uint8_t queue_port_id, const unsigned int ids[], + uint64_t values[], unsigned int n); +int cnxk_sso_xstats_reset(struct rte_eventdev *event_dev, + enum rte_event_dev_xstats_mode mode, + int16_t queue_port_id, const uint32_t ids[], + uint32_t n); + /* CN9K */ void cn9k_sso_set_rsrc(void *arg); diff --git a/drivers/event/cnxk/cnxk_eventdev_stats.c b/drivers/event/cnxk/cnxk_eventdev_stats.c new file mode 100644 index 000000000..a3b548f46 --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev_stats.c @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" + +struct cnxk_sso_xstats_name { + const char name[RTE_EVENT_DEV_XSTATS_NAME_SIZE]; + const size_t offset; + const uint64_t mask; + const uint8_t shift; + uint64_t reset_snap[CNXK_SSO_MAX_HWGRP]; +}; + +static struct cnxk_sso_xstats_name sso_hws_xstats[] = { + { + "last_grp_serviced", + offsetof(struct roc_sso_hws_stats, arbitration), + 0x3FF, + 0, + {0}, + }, + { + "affinity_arbitration_credits", + offsetof(struct roc_sso_hws_stats, arbitration), + 0xF, + 16, + {0}, + }, +}; + +static struct cnxk_sso_xstats_name sso_hwgrp_xstats[] = { + { + "wrk_sched", + offsetof(struct roc_sso_hwgrp_stats, ws_pc), + ~0x0, + 0, + {0}, + }, + { + "xaq_dram", + offsetof(struct roc_sso_hwgrp_stats, ext_pc), + ~0x0, + 0, + {0}, + }, + { + "add_wrk", + offsetof(struct roc_sso_hwgrp_stats, wa_pc), + ~0x0, + 0, + {0}, + }, + { + "tag_switch_req", + offsetof(struct roc_sso_hwgrp_stats, ts_pc), + ~0x0, + 0, + {0}, + }, + { + "desched_req", + offsetof(struct roc_sso_hwgrp_stats, ds_pc), + ~0x0, + 0, + {0}, + }, + { + "desched_wrk", + offsetof(struct roc_sso_hwgrp_stats, dq_pc), + ~0x0, + 0, + {0}, + }, + { + "xaq_cached", + offsetof(struct roc_sso_hwgrp_stats, aw_status), + 0x3, + 0, + {0}, + }, + { + "work_inflight", + offsetof(struct roc_sso_hwgrp_stats, aw_status), + 0x3F, + 16, + {0}, + }, + { + "inuse_pages", + offsetof(struct roc_sso_hwgrp_stats, page_cnt), + 0xFFFFFFFF, + 0, + {0}, + }, +}; + +#define CNXK_SSO_NUM_HWS_XSTATS RTE_DIM(sso_hws_xstats) +#define CNXK_SSO_NUM_GRP_XSTATS RTE_DIM(sso_hwgrp_xstats) + +#define CNXK_SSO_NUM_XSTATS (CNXK_SSO_NUM_HWS_XSTATS + CNXK_SSO_NUM_GRP_XSTATS) + +int +cnxk_sso_xstats_get(const struct rte_eventdev *event_dev, + enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id, + const unsigned int ids[], uint64_t values[], unsigned int n) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + struct roc_sso_hwgrp_stats hwgrp_stats; + struct cnxk_sso_xstats_name *xstats; + struct cnxk_sso_xstats_name *xstat; + struct roc_sso_hws_stats hws_stats; + uint32_t xstats_mode_count = 0; + uint32_t start_offset = 0; + unsigned int i; + uint64_t value; + void *rsp; + int rc; + + switch (mode) { + case RTE_EVENT_DEV_XSTATS_DEVICE: + return 0; + case RTE_EVENT_DEV_XSTATS_PORT: + if (queue_port_id >= (signed int)dev->nb_event_ports) + goto invalid_value; + + xstats_mode_count = CNXK_SSO_NUM_HWS_XSTATS; + xstats = sso_hws_xstats; + + rc = roc_sso_hws_stats_get(&dev->sso, queue_port_id, + &hws_stats); + if (rc < 0) + goto invalid_value; + rsp = &hws_stats; + break; + case RTE_EVENT_DEV_XSTATS_QUEUE: + if (queue_port_id >= (signed int)dev->nb_event_queues) + goto invalid_value; + + xstats_mode_count = CNXK_SSO_NUM_GRP_XSTATS; + start_offset = CNXK_SSO_NUM_HWS_XSTATS; + xstats = sso_hwgrp_xstats; + + rc = roc_sso_hwgrp_stats_get(&dev->sso, queue_port_id, + &hwgrp_stats); + if (rc < 0) + goto invalid_value; + rsp = &hwgrp_stats; + + break; + default: + plt_err("Invalid mode received"); + goto invalid_value; + }; + + for (i = 0; i < n && i < xstats_mode_count; i++) { + xstat = &xstats[ids[i] - start_offset]; + value = *(uint64_t *)((char *)rsp + xstat->offset); + value = (value >> xstat->shift) & xstat->mask; + + values[i] = value; + values[i] -= xstat->reset_snap[queue_port_id]; + } + + return i; +invalid_value: + return -EINVAL; +} + +int +cnxk_sso_xstats_reset(struct rte_eventdev *event_dev, + enum rte_event_dev_xstats_mode mode, + int16_t queue_port_id, const uint32_t ids[], uint32_t n) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + struct roc_sso_hwgrp_stats hwgrp_stats; + struct cnxk_sso_xstats_name *xstats; + struct cnxk_sso_xstats_name *xstat; + struct roc_sso_hws_stats hws_stats; + uint32_t xstats_mode_count = 0; + uint32_t start_offset = 0; + unsigned int i; + uint64_t value; + void *rsp; + int rc; + + switch (mode) { + case RTE_EVENT_DEV_XSTATS_DEVICE: + return 0; + case RTE_EVENT_DEV_XSTATS_PORT: + if (queue_port_id >= (signed int)dev->nb_event_ports) + goto invalid_value; + + xstats_mode_count = CNXK_SSO_NUM_HWS_XSTATS; + xstats = sso_hws_xstats; + rc = roc_sso_hws_stats_get(&dev->sso, queue_port_id, + &hws_stats); + if (rc < 0) + goto invalid_value; + rsp = &hws_stats; + break; + case RTE_EVENT_DEV_XSTATS_QUEUE: + if (queue_port_id >= (signed int)dev->nb_event_queues) + goto invalid_value; + + xstats_mode_count = CNXK_SSO_NUM_GRP_XSTATS; + start_offset = CNXK_SSO_NUM_HWS_XSTATS; + xstats = sso_hwgrp_xstats; + + rc = roc_sso_hwgrp_stats_get(&dev->sso, queue_port_id, + &hwgrp_stats); + if (rc < 0) + goto invalid_value; + rsp = &hwgrp_stats; + break; + default: + plt_err("Invalid mode received"); + goto invalid_value; + }; + + for (i = 0; i < n && i < xstats_mode_count; i++) { + xstat = &xstats[ids[i] - start_offset]; + value = *(uint64_t *)((char *)rsp + xstat->offset); + value = (value >> xstat->shift) & xstat->mask; + + xstat->reset_snap[queue_port_id] = value; + } + return i; +invalid_value: + return -EINVAL; +} + +int +cnxk_sso_xstats_get_names(const struct rte_eventdev *event_dev, + enum rte_event_dev_xstats_mode mode, + uint8_t queue_port_id, + struct rte_event_dev_xstats_name *xstats_names, + unsigned int *ids, unsigned int size) +{ + struct rte_event_dev_xstats_name xstats_names_copy[CNXK_SSO_NUM_XSTATS]; + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint32_t xstats_mode_count = 0; + uint32_t start_offset = 0; + unsigned int xidx = 0; + unsigned int i; + + for (i = 0; i < CNXK_SSO_NUM_HWS_XSTATS; i++) { + snprintf(xstats_names_copy[i].name, + sizeof(xstats_names_copy[i].name), "%s", + sso_hws_xstats[i].name); + } + + for (; i < CNXK_SSO_NUM_XSTATS; i++) { + snprintf(xstats_names_copy[i].name, + sizeof(xstats_names_copy[i].name), "%s", + sso_hwgrp_xstats[i - CNXK_SSO_NUM_HWS_XSTATS].name); + } + + switch (mode) { + case RTE_EVENT_DEV_XSTATS_DEVICE: + break; + case RTE_EVENT_DEV_XSTATS_PORT: + if (queue_port_id >= (signed int)dev->nb_event_ports) + break; + xstats_mode_count = CNXK_SSO_NUM_HWS_XSTATS; + break; + case RTE_EVENT_DEV_XSTATS_QUEUE: + if (queue_port_id >= (signed int)dev->nb_event_queues) + break; + xstats_mode_count = CNXK_SSO_NUM_GRP_XSTATS; + start_offset = CNXK_SSO_NUM_HWS_XSTATS; + break; + default: + plt_err("Invalid mode received"); + return -EINVAL; + }; + + if (xstats_mode_count > size || !ids || !xstats_names) + return xstats_mode_count; + + for (i = 0; i < xstats_mode_count; i++) { + xidx = i + start_offset; + strncpy(xstats_names[i].name, xstats_names_copy[xidx].name, + sizeof(xstats_names[i].name)); + ids[i] = xidx; + } + + return i; +} diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index e37ea3478..5b215b73f 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -13,7 +13,8 @@ sources = files('cn10k_worker.c', 'cn9k_worker.c', 'cn9k_eventdev.c', 'cnxk_eventdev.c', - 'cnxk_eventdev_selftest.c' + 'cnxk_eventdev_selftest.c', + 'cnxk_eventdev_stats.c', ) deps += ['bus_pci', 'common_cnxk'] From patchwork Tue May 4 00:27:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92700 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08E07A0562; Tue, 4 May 2021 02:30:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3507C4114A; Tue, 4 May 2021 02:29:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 68893410EE for ; Tue, 4 May 2021 02:29:06 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440Alh7002713; Mon, 3 May 2021 17:29:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=yEQuOodInjHetHE6+MkCKh9GK+K6E39TlXbX80HQARQ=; b=eYwYYIvxrgC/tFrxkah7cL0v/h2/gCIenfLNLZC4ZD6419JIFQO1jSpAI9juAx0SqRWx 4FYyoLLDNIkA4a4+6rHcF9YhHmAyS91wPeZ6Ppv1FTZDonQsiTVVaOfzYYiQ7R2afd2a rrfMBQ3ghiFw3jVQDf+mFJyo05slcpEE5PZkI6I6tTqoLvEHvKZv6xQx0s8us/BQmDfh fPiVgNgAn6zlZF83NnxNjJrAjjxn1kbOLMwOngA2FGpwKjWwcsxm/AslJJQ2QZcGYTCy gR743yixj8YQD4sTbAlj83MGO7UOUIuBH0VpEqMiM6hXy52eS+tKc+IPYrKkBXg6f+XK iA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6na-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 03 May 2021 17:29:05 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:03 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id D1C883F7044; Mon, 3 May 2021 17:29:01 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" , Anatoly Burakov CC: Date: Tue, 4 May 2021 05:57:12 +0530 Message-ID: <20210504002726.525-23-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: N9W4WT0c05qCDxLvk9U4g4zcOCpNxhCa X-Proofpoint-ORIG-GUID: N9W4WT0c05qCDxLvk9U4g4zcOCpNxhCa X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 22/35] event/cnxk: support event timer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add event timer adapter a.k.a TIM initialization on SSO probe. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 6 ++++ drivers/event/cnxk/cnxk_eventdev.c | 3 ++ drivers/event/cnxk/cnxk_eventdev.h | 2 ++ drivers/event/cnxk/cnxk_tim_evdev.c | 47 +++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_tim_evdev.h | 44 +++++++++++++++++++++++++++ drivers/event/cnxk/meson.build | 1 + 6 files changed, 103 insertions(+) create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.c create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.h diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index f48452982..e6f81f8b1 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -35,6 +35,10 @@ Features of the OCTEON cnxk SSO PMD are: - Open system with configurable amount of outstanding events limited only by DRAM - HW accelerated dequeue timeout support to enable power management +- HW managed event timers support through TIM, with high precision and + time granularity of 2.5us on CN9K and 1us on CN10K. +- Up to 256 TIM rings a.k.a event timer adapters. +- Up to 8 rings traversed in parallel. Prerequisites and Compilation procedure --------------------------------------- @@ -101,3 +105,5 @@ Debugging Options +===+============+=======================================================+ | 1 | SSO | --log-level='pmd\.event\.cnxk,8' | +---+------------+-------------------------------------------------------+ + | 2 | TIM | --log-level='pmd\.event\.cnxk\.timer,8' | + +---+------------+-------------------------------------------------------+ diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 0f084176c..85bb12e00 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -582,6 +582,8 @@ cnxk_sso_init(struct rte_eventdev *event_dev) dev->nb_event_queues = 0; dev->nb_event_ports = 0; + cnxk_tim_init(&dev->sso); + return 0; error: @@ -598,6 +600,7 @@ cnxk_sso_fini(struct rte_eventdev *event_dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + cnxk_tim_fini(); roc_sso_rsrc_fini(&dev->sso); roc_sso_dev_fini(&dev->sso); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index abe36f21f..1c61063c9 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -14,6 +14,8 @@ #include "roc_api.h" +#include "cnxk_tim_evdev.h" + #define CNXK_SSO_XAE_CNT "xae_cnt" #define CNXK_SSO_GGRP_QOS "qos" #define CN9K_SSO_SINGLE_WS "single_ws" diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c new file mode 100644 index 000000000..46461b885 --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" +#include "cnxk_tim_evdev.h" + +void +cnxk_tim_init(struct roc_sso *sso) +{ + const struct rte_memzone *mz; + struct cnxk_tim_evdev *dev; + int rc; + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return; + + mz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME), + sizeof(struct cnxk_tim_evdev), 0, 0); + if (mz == NULL) { + plt_tim_dbg("Unable to allocate memory for TIM Event device"); + return; + } + dev = mz->addr; + + dev->tim.roc_sso = sso; + rc = roc_tim_init(&dev->tim); + if (rc < 0) { + plt_err("Failed to initialize roc tim resources"); + rte_memzone_free(mz); + return; + } + dev->nb_rings = rc; + dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ; +} + +void +cnxk_tim_fini(void) +{ + struct cnxk_tim_evdev *dev = tim_priv_get(); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return; + + roc_tim_fini(&dev->tim); + rte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME))); +} diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h new file mode 100644 index 000000000..5ddc94ed4 --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CNXK_TIM_EVDEV_H__ +#define __CNXK_TIM_EVDEV_H__ + +#include +#include +#include +#include + +#include +#include +#include + +#include "roc_api.h" + +#define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev +#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096) + +struct cnxk_tim_evdev { + struct roc_tim tim; + struct rte_eventdev *event_dev; + uint16_t nb_rings; + uint32_t chunk_sz; +}; + +static inline struct cnxk_tim_evdev * +tim_priv_get(void) +{ + const struct rte_memzone *mz; + + mz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)); + if (mz == NULL) + return NULL; + + return mz->addr; +} + +void cnxk_tim_init(struct roc_sso *sso); +void cnxk_tim_fini(void); + +#endif /* __CNXK_TIM_EVDEV_H__ */ diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index 5b215b73f..ce8764eda 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -15,6 +15,7 @@ sources = files('cn10k_worker.c', 'cnxk_eventdev.c', 'cnxk_eventdev_selftest.c', 'cnxk_eventdev_stats.c', + 'cnxk_tim_evdev.c', ) deps += ['bus_pci', 'common_cnxk'] From patchwork Tue May 4 00:27:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92701 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0901CA0562; Tue, 4 May 2021 02:30:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7651D410F7; Tue, 4 May 2021 02:29:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7AD6F411AE for ; Tue, 4 May 2021 02:29:09 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440Ouk0025116 for ; Mon, 3 May 2021 17:29:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=FY6E2+vjKgzWOKVqU5VJqSugEMHYVkbSQ6veVgpuieI=; b=FQFt3P+C1XIDWWjFHlfAUvNGTPg07r+tIW3AYGV1tfvnw1N65Xx4YFSUywvNowhrE55D XtoxHMoKa1gqg9MhRLFVswfrljDBaJdX6wLCBf6WiRUlK2gerGvqBodmACVFLFF6rMC7 kgXKbyyNWUu+RXQNpziXFPRcsD+c5qeHD5dqf8AcjhiBZlY6FhxBhuvh+fVarKe3qC6s YVvRNpxj7g0IC5W1no3Kv4XUAlZLMU/vK13Qj5zVGvo7eSKQfNLuzSGJheNzON06Aq1X GMmA/SpeDjgXgGEP5qNXjygqII+hndNoP5lbziApqPFieXoxV71Q3QSY1xVH+1DqaHYw dg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnsh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:06 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id C6C653F7045; Mon, 3 May 2021 17:29:04 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:13 +0530 Message-ID: <20210504002726.525-24-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Xp5EG5oulQtfdOuVlP2BJMcZgX8lxTkz X-Proofpoint-ORIG-GUID: Xp5EG5oulQtfdOuVlP2BJMcZgX8lxTkz X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 23/35] event/cnxk: add timer adapter capabilities X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add function to retrieve event timer adapter capabilities. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cn10k_eventdev.c | 2 ++ drivers/event/cnxk/cn9k_eventdev.c | 2 ++ drivers/event/cnxk/cnxk_tim_evdev.c | 22 +++++++++++++++++++++- drivers/event/cnxk/cnxk_tim_evdev.h | 6 +++++- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index a0c6d32cc..0981085e8 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -420,6 +420,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .port_unlink = cn10k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + .timer_adapter_caps_get = cnxk_tim_caps_get, + .dump = cnxk_sso_dump, .dev_start = cn10k_sso_start, .dev_stop = cn10k_sso_stop, diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 48991e522..d9882ebb9 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -494,6 +494,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .port_unlink = cn9k_sso_port_unlink, .timeout_ticks = cnxk_sso_timeout_ticks, + .timer_adapter_caps_get = cnxk_tim_caps_get, + .dump = cnxk_sso_dump, .dev_start = cn9k_sso_start, .dev_stop = cn9k_sso_stop, diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 46461b885..265bee533 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -5,6 +5,26 @@ #include "cnxk_eventdev.h" #include "cnxk_tim_evdev.h" +int +cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, + uint32_t *caps, + const struct rte_event_timer_adapter_ops **ops) +{ + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + + RTE_SET_USED(flags); + RTE_SET_USED(ops); + + if (dev == NULL) + return -ENODEV; + + /* Store evdev pointer for later use. */ + dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + + return 0; +} + void cnxk_tim_init(struct roc_sso *sso) { @@ -37,7 +57,7 @@ cnxk_tim_init(struct roc_sso *sso) void cnxk_tim_fini(void) { - struct cnxk_tim_evdev *dev = tim_priv_get(); + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); if (rte_eal_process_type() != RTE_PROC_PRIMARY) return; diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 5ddc94ed4..ece66ab25 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -27,7 +27,7 @@ struct cnxk_tim_evdev { }; static inline struct cnxk_tim_evdev * -tim_priv_get(void) +cnxk_tim_priv_get(void) { const struct rte_memzone *mz; @@ -38,6 +38,10 @@ tim_priv_get(void) return mz->addr; } +int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags, + uint32_t *caps, + const struct rte_event_timer_adapter_ops **ops); + void cnxk_tim_init(struct roc_sso *sso); void cnxk_tim_fini(void); From patchwork Tue May 4 00:27:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92702 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4EE4A0562; Tue, 4 May 2021 02:30:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1382F411B0; Tue, 4 May 2021 02:29:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id DB89341151 for ; Tue, 4 May 2021 02:29:11 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AIFc002346 for ; Mon, 3 May 2021 17:29:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=wQkIuJLy8+HalecaToJLwbvjt0kqHHVHltKdikSmVI4=; b=RcgyKnqeqoC7oqicMe5nPI7/DvUevPSHvkjTB2Bb7PsbG/PIzbpTzAEL6i+U7QgCrl9a RKJZGrf8835ZcVLt1VEc42wfGBXIATuC4doi++V8R7E1PPIXLfLzaWjFLBolAreAt/9t ClOolcN/UnY+1nd5hOYWCdS3MFyd338CkHheQFfSFSW796f9H7XG4Jxd0vek4trk80rX Dlu28gZy1WRD2wZoNYu1pVgXOmnFUb7sDgnG6BpYyJk75svzvUMcHUGkw8wc25/vPDRH c8xpIFtoT5MIQGnd6vUPhoFyeNgAik/5SUcY5FwKm27JsOPdTC8SuuTnkGt26NbJngGg qQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6nn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:08 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 817833F703F; Mon, 3 May 2021 17:29:07 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:14 +0530 Message-ID: <20210504002726.525-25-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Eb-Z1YVcAQ094QcJFzILi8tFbt-e7qec X-Proofpoint-ORIG-GUID: Eb-Z1YVcAQ094QcJFzILi8tFbt-e7qec X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 24/35] event/cnxk: create and free timer adapter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton When the application calls timer adapter create the following is used: - Allocate a TIM LF based on number of LF's provisioned. - Verify the config parameters supplied. - Allocate memory required for * Buckets based on min and max timeout supplied. * Allocate the chunk pool based on the number of timers. On Free: - Free the allocated bucket and chunk memory. - Free the TIM lf allocated. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cnxk_tim_evdev.c | 174 ++++++++++++++++++++++++++++ drivers/event/cnxk/cnxk_tim_evdev.h | 128 +++++++++++++++++++- 2 files changed, 300 insertions(+), 2 deletions(-) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 265bee533..655540a72 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -5,6 +5,177 @@ #include "cnxk_eventdev.h" #include "cnxk_tim_evdev.h" +static struct rte_event_timer_adapter_ops cnxk_tim_ops; + +static int +cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, + struct rte_event_timer_adapter_conf *rcfg) +{ + unsigned int cache_sz = (tim_ring->nb_chunks / 1.5); + unsigned int mp_flags = 0; + char pool_name[25]; + int rc; + + cache_sz /= rte_lcore_count(); + /* Create chunk pool. */ + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) { + mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET; + plt_tim_dbg("Using single producer mode"); + tim_ring->prod_type_sp = true; + } + + snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d", + tim_ring->ring_id); + + if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE) + cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE; + cache_sz = cache_sz != 0 ? cache_sz : 2; + tim_ring->nb_chunks += (cache_sz * rte_lcore_count()); + tim_ring->chunk_pool = rte_mempool_create_empty( + pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, cache_sz, 0, + rte_socket_id(), mp_flags); + + if (tim_ring->chunk_pool == NULL) { + plt_err("Unable to create chunkpool."); + return -ENOMEM; + } + + rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool, + rte_mbuf_platform_mempool_ops(), NULL); + if (rc < 0) { + plt_err("Unable to set chunkpool ops"); + goto free; + } + + rc = rte_mempool_populate_default(tim_ring->chunk_pool); + if (rc < 0) { + plt_err("Unable to set populate chunkpool."); + goto free; + } + tim_ring->aura = + roc_npa_aura_handle_to_aura(tim_ring->chunk_pool->pool_id); + tim_ring->ena_dfb = 0; + + return 0; + +free: + rte_mempool_free(tim_ring->chunk_pool); + return rc; +} + +static int +cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) +{ + struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + struct cnxk_tim_ring *tim_ring; + int rc; + + if (dev == NULL) + return -ENODEV; + + if (adptr->data->id >= dev->nb_rings) + return -ENODEV; + + tim_ring = rte_zmalloc("cnxk_tim_prv", sizeof(struct cnxk_tim_ring), 0); + if (tim_ring == NULL) + return -ENOMEM; + + rc = roc_tim_lf_alloc(&dev->tim, adptr->data->id, NULL); + if (rc < 0) { + plt_err("Failed to create timer ring"); + goto tim_ring_free; + } + + if (NSEC2TICK(RTE_ALIGN_MUL_CEIL( + rcfg->timer_tick_ns, + cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())), + cnxk_tim_cntfrq()) < + cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) { + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES) + rcfg->timer_tick_ns = TICK2NSEC( + cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()), + cnxk_tim_cntfrq()); + else { + rc = -ERANGE; + goto tim_hw_free; + } + } + tim_ring->ring_id = adptr->data->id; + tim_ring->clk_src = (int)rcfg->clk_src; + tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL( + rcfg->timer_tick_ns, + cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())); + tim_ring->max_tout = rcfg->max_tmo_ns; + tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); + tim_ring->nb_timers = rcfg->nb_timers; + tim_ring->chunk_sz = dev->chunk_sz; + + tim_ring->nb_chunks = tim_ring->nb_timers; + tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); + /* Create buckets. */ + tim_ring->bkt = + rte_zmalloc("cnxk_tim_bucket", + (tim_ring->nb_bkts) * sizeof(struct cnxk_tim_bkt), + RTE_CACHE_LINE_SIZE); + if (tim_ring->bkt == NULL) + goto tim_hw_free; + + rc = cnxk_tim_chnk_pool_create(tim_ring, rcfg); + if (rc < 0) + goto tim_bkt_free; + + rc = roc_tim_lf_config( + &dev->tim, tim_ring->ring_id, + cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0, + tim_ring->nb_bkts, tim_ring->chunk_sz, + NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq())); + if (rc < 0) { + plt_err("Failed to configure timer ring"); + goto tim_chnk_free; + } + + tim_ring->base = roc_tim_lf_base_get(&dev->tim, tim_ring->ring_id); + plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE); + plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA); + + plt_tim_dbg( + "Total memory used %" PRIu64 "MB\n", + (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) + + (tim_ring->nb_bkts * sizeof(struct cnxk_tim_bkt))) / + BIT_ULL(20))); + + adptr->data->adapter_priv = tim_ring; + return rc; + +tim_chnk_free: + rte_mempool_free(tim_ring->chunk_pool); +tim_bkt_free: + rte_free(tim_ring->bkt); +tim_hw_free: + roc_tim_lf_free(&dev->tim, tim_ring->ring_id); +tim_ring_free: + rte_free(tim_ring); + return rc; +} + +static int +cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr) +{ + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + + if (dev == NULL) + return -ENODEV; + + roc_tim_lf_free(&dev->tim, tim_ring->ring_id); + rte_free(tim_ring->bkt); + rte_mempool_free(tim_ring->chunk_pool); + rte_free(tim_ring); + + return 0; +} + int cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, uint32_t *caps, @@ -18,6 +189,9 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, if (dev == NULL) return -ENODEV; + cnxk_tim_ops.init = cnxk_tim_ring_create; + cnxk_tim_ops.uninit = cnxk_tim_ring_free; + /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index ece66ab25..2335707cd 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -12,12 +12,26 @@ #include #include +#include #include #include "roc_api.h" -#define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev -#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096) +#define NSECPERSEC 1E9 +#define USECPERSEC 1E6 +#define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq)) + +#define CNXK_TIM_EVDEV_NAME cnxk_tim_eventdev +#define CNXK_TIM_MAX_BUCKETS (0xFFFFF) +#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096) +#define CNXK_TIM_CHUNK_ALIGNMENT (16) +#define CNXK_TIM_MAX_BURST \ + (RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT) +#define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1) +#define CNXK_TIM_MIN_CHUNK_SLOTS (0x1) +#define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE) + +#define CN9K_TIM_MIN_TMO_TKS (256) struct cnxk_tim_evdev { struct roc_tim tim; @@ -26,6 +40,57 @@ struct cnxk_tim_evdev { uint32_t chunk_sz; }; +enum cnxk_tim_clk_src { + CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK, + CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0, + CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1, + CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2, +}; + +struct cnxk_tim_bkt { + uint64_t first_chunk; + union { + uint64_t w1; + struct { + uint32_t nb_entry; + uint8_t sbt : 1; + uint8_t hbt : 1; + uint8_t bsk : 1; + uint8_t rsvd : 5; + uint8_t lock; + int16_t chunk_remainder; + }; + }; + uint64_t current_chunk; + uint64_t pad; +}; + +struct cnxk_tim_ring { + uintptr_t base; + uint16_t nb_chunk_slots; + uint32_t nb_bkts; + uint64_t tck_int; + uint64_t tot_int; + struct cnxk_tim_bkt *bkt; + struct rte_mempool *chunk_pool; + uint64_t arm_cnt; + uint8_t prod_type_sp; + uint8_t ena_dfb; + uint16_t ring_id; + uint32_t aura; + uint64_t nb_timers; + uint64_t tck_nsec; + uint64_t max_tout; + uint64_t nb_chunks; + uint64_t chunk_sz; + enum cnxk_tim_clk_src clk_src; +} __rte_cache_aligned; + +struct cnxk_tim_ent { + uint64_t w0; + uint64_t wqe; +}; + static inline struct cnxk_tim_evdev * cnxk_tim_priv_get(void) { @@ -38,6 +103,65 @@ cnxk_tim_priv_get(void) return mz->addr; } +static inline uint64_t +cnxk_tim_min_tmo_ticks(uint64_t freq) +{ + if (roc_model_runtime_is_cn9k()) + return CN9K_TIM_MIN_TMO_TKS; + else /* CN10K min tick is of 1us */ + return freq / USECPERSEC; +} + +static inline uint64_t +cnxk_tim_min_resolution_ns(uint64_t freq) +{ + return NSECPERSEC / freq; +} + +static inline enum roc_tim_clk_src +cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src) +{ + switch (clk_src) { + case RTE_EVENT_TIMER_ADAPTER_CPU_CLK: + return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS : + ROC_TIM_CLK_SRC_GTI; + default: + return ROC_TIM_CLK_SRC_INVALID; + } +} + +#ifdef RTE_ARCH_ARM64 +static inline uint64_t +cnxk_tim_cntvct(void) +{ + uint64_t tsc; + + asm volatile("mrs %0, cntvct_el0" : "=r"(tsc)); + return tsc; +} + +static inline uint64_t +cnxk_tim_cntfrq(void) +{ + uint64_t freq; + + asm volatile("mrs %0, cntfrq_el0" : "=r"(freq)); + return freq; +} +#else +static inline uint64_t +cnxk_tim_cntvct(void) +{ + return 0; +} + +static inline uint64_t +cnxk_tim_cntfrq(void) +{ + return 0; +} +#endif + int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags, uint32_t *caps, const struct rte_event_timer_adapter_ops **ops); From patchwork Tue May 4 00:27:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92703 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB193A0562; Tue, 4 May 2021 02:30:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5434C411A4; Tue, 4 May 2021 02:29:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A65A1411BA for ; Tue, 4 May 2021 02:29:14 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440Oui7025154 for ; Mon, 3 May 2021 17:29:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5re+N9i/eSpFPK3PcCnvmwyULUaV7SBo3xeCw4Ijakk=; b=Zy8N5TEzZQzVRsBbGeg8If2zu5MX596vQ+NytGLcjXXhXYAuRHttTn42DG0/+xIP9L6B aQTKa5NXUEFAa/7Z/ZmF5qZ7PNpKxafBltU6YLX4wMyUJ0UWxeVpDo53pI2TxuoCi72V MkKp0NcebblF8pQhYMLKDNyxtbXlGo2P0aPxvfO6XVaA6tKsoka3QzFBuFunWKJZk6uw s3xyDqCWNh+Prz/DrYo1e8okq7N/AOmvLhW7Wk5yOMqpJKkuCq+KBrblzRn3dMKRyt50 RZxxHwTpEv/hab/S0Bf4RjYY8XBMiL45lUcqO27Yz24BI8hDQcNtcWbKO84v2/nHR6v6 jw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnsv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:13 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:11 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 5FF2D3F703F; Mon, 3 May 2021 17:29:10 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:15 +0530 Message-ID: <20210504002726.525-26-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: KcXqFfcXXUjm9DN3fnKKh4EBT8UDiYEz X-Proofpoint-ORIG-GUID: KcXqFfcXXUjm9DN3fnKKh4EBT8UDiYEz X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 25/35] event/cnxk: add devargs to disable NPA X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh If the chunks are allocated from NPA then TIM can automatically free them when traversing the list of chunks. Add devargs to disable NPA and use software mempool to manage chunks. Example: --dev "0002:0e:00.0,tim_disable_npa=1" Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/cnxk.rst | 10 ++++ drivers/event/cnxk/cn10k_eventdev.c | 3 +- drivers/event/cnxk/cn9k_eventdev.c | 3 +- drivers/event/cnxk/cnxk_eventdev.h | 9 +++ drivers/event/cnxk/cnxk_tim_evdev.c | 86 +++++++++++++++++++++-------- drivers/event/cnxk/cnxk_tim_evdev.h | 5 ++ 6 files changed, 92 insertions(+), 24 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index e6f81f8b1..c2d6ed2fb 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -93,6 +93,16 @@ Runtime Config Options -a 0002:0e:00.0,qos=[1-50-50-50] +- ``TIM disable NPA`` + + By default chunks are allocated from NPA then TIM can automatically free + them when traversing the list of chunks. The ``tim_disable_npa`` devargs + parameter disables NPA and uses software mempool to manage chunks + + For example:: + + -a 0002:0e:00.0,tim_disable_npa=1 + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 0981085e8..a2ef1fa73 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -502,4 +502,5 @@ RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" - CN10K_SSO_GW_MODE "="); + CN10K_SSO_GW_MODE "=" + CNXK_TIM_DISABLE_NPA "=1"); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index d9882ebb9..3a0caa009 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -571,4 +571,5 @@ RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" - CN9K_SSO_SINGLE_WS "=1"); + CN9K_SSO_SINGLE_WS "=1" + CNXK_TIM_DISABLE_NPA "=1"); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 1c61063c9..77835e463 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -159,6 +159,15 @@ struct cnxk_sso_hws_cookie { bool configured; } __rte_cache_aligned; +static inline int +parse_kvargs_flag(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + *(uint8_t *)opaque = !!atoi(value); + return 0; +} + static inline int parse_kvargs_value(const char *key, const char *value, void *opaque) { diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 655540a72..d93b37e4f 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -31,30 +31,43 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE; cache_sz = cache_sz != 0 ? cache_sz : 2; tim_ring->nb_chunks += (cache_sz * rte_lcore_count()); - tim_ring->chunk_pool = rte_mempool_create_empty( - pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, cache_sz, 0, - rte_socket_id(), mp_flags); - - if (tim_ring->chunk_pool == NULL) { - plt_err("Unable to create chunkpool."); - return -ENOMEM; - } + if (!tim_ring->disable_npa) { + tim_ring->chunk_pool = rte_mempool_create_empty( + pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, + cache_sz, 0, rte_socket_id(), mp_flags); + + if (tim_ring->chunk_pool == NULL) { + plt_err("Unable to create chunkpool."); + return -ENOMEM; + } - rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool, - rte_mbuf_platform_mempool_ops(), NULL); - if (rc < 0) { - plt_err("Unable to set chunkpool ops"); - goto free; - } + rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool, + rte_mbuf_platform_mempool_ops(), + NULL); + if (rc < 0) { + plt_err("Unable to set chunkpool ops"); + goto free; + } - rc = rte_mempool_populate_default(tim_ring->chunk_pool); - if (rc < 0) { - plt_err("Unable to set populate chunkpool."); - goto free; + rc = rte_mempool_populate_default(tim_ring->chunk_pool); + if (rc < 0) { + plt_err("Unable to set populate chunkpool."); + goto free; + } + tim_ring->aura = roc_npa_aura_handle_to_aura( + tim_ring->chunk_pool->pool_id); + tim_ring->ena_dfb = 0; + } else { + tim_ring->chunk_pool = rte_mempool_create( + pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, + cache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(), + mp_flags); + if (tim_ring->chunk_pool == NULL) { + plt_err("Unable to create chunkpool."); + return -ENOMEM; + } + tim_ring->ena_dfb = 1; } - tim_ring->aura = - roc_npa_aura_handle_to_aura(tim_ring->chunk_pool->pool_id); - tim_ring->ena_dfb = 0; return 0; @@ -110,8 +123,17 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); tim_ring->nb_timers = rcfg->nb_timers; tim_ring->chunk_sz = dev->chunk_sz; + tim_ring->disable_npa = dev->disable_npa; + + if (tim_ring->disable_npa) { + tim_ring->nb_chunks = + tim_ring->nb_timers / + CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); + tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts; + } else { + tim_ring->nb_chunks = tim_ring->nb_timers; + } - tim_ring->nb_chunks = tim_ring->nb_timers; tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); /* Create buckets. */ tim_ring->bkt = @@ -199,6 +221,24 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, return 0; } +static void +cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) +{ + struct rte_kvargs *kvlist; + + if (devargs == NULL) + return; + + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + return; + + rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag, + &dev->disable_npa); + + rte_kvargs_free(kvlist); +} + void cnxk_tim_init(struct roc_sso *sso) { @@ -217,6 +257,8 @@ cnxk_tim_init(struct roc_sso *sso) } dev = mz->addr; + cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev); + dev->tim.roc_sso = sso; rc = roc_tim_init(&dev->tim); if (rc < 0) { diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 2335707cd..4896ed67a 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -33,11 +33,15 @@ #define CN9K_TIM_MIN_TMO_TKS (256) +#define CNXK_TIM_DISABLE_NPA "tim_disable_npa" + struct cnxk_tim_evdev { struct roc_tim tim; struct rte_eventdev *event_dev; uint16_t nb_rings; uint32_t chunk_sz; + /* Dev args */ + uint8_t disable_npa; }; enum cnxk_tim_clk_src { @@ -75,6 +79,7 @@ struct cnxk_tim_ring { struct rte_mempool *chunk_pool; uint64_t arm_cnt; uint8_t prod_type_sp; + uint8_t disable_npa; uint8_t ena_dfb; uint16_t ring_id; uint32_t aura; From patchwork Tue May 4 00:27:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92704 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6DB03A0562; Tue, 4 May 2021 02:30:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 83698411A8; Tue, 4 May 2021 02:29:18 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id ADC48411BA for ; Tue, 4 May 2021 02:29:16 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440P267025320 for ; Mon, 3 May 2021 17:29:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5aR5D11nqtg+Mt4Fs3mJc1qUmLVBAW/lzvrDkeaGj24=; b=N9RZPPxDCx136OuEypW71eHKuZTx9STyNTl8nkLtdLFENr09gdccyqPpmeR5V9Q1wx3S SaK/hTgaXdlUkDzlnGAznljgSMM0rOYYueaAvHinpY7wYnlrk7Ri0/InrW7gIrhUf6N6 GLmsL2sZ3nlRpGQrVf0bh6ggwbmmrwz5O94f0nLVxeuay/e2Qevaj421HU4FQGlRDw/9 G0Cxq4+LbFFKqRUzz8Yll/pvDAgftZC4DDyuHwmU5+0MLlYQA4IedDft8TZnCz4tJdXZ 9sswn5YKbqfjC7T66boCS9O7ksUOIHa+EDWxsH0zh5OplS7a62Ab0bZqwW0LO1IKcLk5 Fg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnt1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:14 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 24D5A3F7040; Mon, 3 May 2021 17:29:12 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:16 +0530 Message-ID: <20210504002726.525-27-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: fsIKKzDIcwPsSfJOFRqHKpN_PU58ie2d X-Proofpoint-ORIG-GUID: fsIKKzDIcwPsSfJOFRqHKpN_PU58ie2d X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 26/35] event/cnxk: allow adapters to resize inflights X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add internal SSO functions to allow event adapters to resize SSO buffers that are used to hold in-flight events in DRAM. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_eventdev.c | 33 ++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 7 +++ drivers/event/cnxk/cnxk_eventdev_adptr.c | 67 ++++++++++++++++++++++++ drivers/event/cnxk/cnxk_tim_evdev.c | 5 ++ drivers/event/cnxk/meson.build | 1 + 5 files changed, 113 insertions(+) create mode 100644 drivers/event/cnxk/cnxk_eventdev_adptr.c diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 85bb12e00..7189ee3a7 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -77,6 +77,9 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev) xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT; if (dev->xae_cnt) xaq_cnt += dev->xae_cnt / dev->sso.xae_waes; + else if (dev->adptr_xae_cnt) + xaq_cnt += (dev->adptr_xae_cnt / dev->sso.xae_waes) + + (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); else xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) + (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); @@ -125,6 +128,36 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev) return rc; } +int +cnxk_sso_xae_reconfigure(struct rte_eventdev *event_dev) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + int rc = 0; + + if (event_dev->data->dev_started) + event_dev->dev_ops->dev_stop(event_dev); + + rc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues); + if (rc < 0) { + plt_err("Failed to release XAQ %d", rc); + return rc; + } + + rte_mempool_free(dev->xaq_pool); + dev->xaq_pool = NULL; + rc = cnxk_sso_xaq_allocate(dev); + if (rc < 0) { + plt_err("Failed to alloc XAQ %d", rc); + return rc; + } + + rte_mb(); + if (event_dev->data->dev_started) + event_dev->dev_ops->dev_start(event_dev); + + return 0; +} + int cnxk_setup_event_ports(const struct rte_eventdev *event_dev, cnxk_sso_init_hws_mem_t init_hws_fn, diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 77835e463..668e51d62 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -81,6 +81,10 @@ struct cnxk_sso_evdev { uint64_t nb_xaq_cfg; rte_iova_t fc_iova; struct rte_mempool *xaq_pool; + uint64_t adptr_xae_cnt; + uint16_t tim_adptr_ring_cnt; + uint16_t *timer_adptr_rings; + uint64_t *timer_adptr_sz; /* Dev args */ uint32_t xae_cnt; uint8_t qos_queue_cnt; @@ -190,7 +194,10 @@ cnxk_sso_hws_get_cookie(void *ws) } /* Configuration functions */ +int cnxk_sso_xae_reconfigure(struct rte_eventdev *event_dev); int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev); +void cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data, + uint32_t event_type); /* Common ops API. */ int cnxk_sso_init(struct rte_eventdev *event_dev); diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c new file mode 100644 index 000000000..89a1d82c1 --- /dev/null +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_eventdev.h" + +void +cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data, + uint32_t event_type) +{ + int i; + + switch (event_type) { + case RTE_EVENT_TYPE_TIMER: { + struct cnxk_tim_ring *timr = data; + uint16_t *old_ring_ptr; + uint64_t *old_sz_ptr; + + for (i = 0; i < dev->tim_adptr_ring_cnt; i++) { + if (timr->ring_id != dev->timer_adptr_rings[i]) + continue; + if (timr->nb_timers == dev->timer_adptr_sz[i]) + return; + dev->adptr_xae_cnt -= dev->timer_adptr_sz[i]; + dev->adptr_xae_cnt += timr->nb_timers; + dev->timer_adptr_sz[i] = timr->nb_timers; + + return; + } + + dev->tim_adptr_ring_cnt++; + old_ring_ptr = dev->timer_adptr_rings; + old_sz_ptr = dev->timer_adptr_sz; + + dev->timer_adptr_rings = rte_realloc( + dev->timer_adptr_rings, + sizeof(uint16_t) * dev->tim_adptr_ring_cnt, 0); + if (dev->timer_adptr_rings == NULL) { + dev->adptr_xae_cnt += timr->nb_timers; + dev->timer_adptr_rings = old_ring_ptr; + dev->tim_adptr_ring_cnt--; + return; + } + + dev->timer_adptr_sz = rte_realloc( + dev->timer_adptr_sz, + sizeof(uint64_t) * dev->tim_adptr_ring_cnt, 0); + + if (dev->timer_adptr_sz == NULL) { + dev->adptr_xae_cnt += timr->nb_timers; + dev->timer_adptr_sz = old_sz_ptr; + dev->tim_adptr_ring_cnt--; + return; + } + + dev->timer_adptr_rings[dev->tim_adptr_ring_cnt - 1] = + timr->ring_id; + dev->timer_adptr_sz[dev->tim_adptr_ring_cnt - 1] = + timr->nb_timers; + + dev->adptr_xae_cnt += timr->nb_timers; + break; + } + default: + break; + } +} diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index d93b37e4f..1eb39a789 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -161,6 +161,11 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE); plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA); + /* Update SSO xae count. */ + cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring, + RTE_EVENT_TYPE_TIMER); + cnxk_sso_xae_reconfigure(dev->event_dev); + plt_tim_dbg( "Total memory used %" PRIu64 "MB\n", (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) + diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index ce8764eda..bd52cbc68 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -12,6 +12,7 @@ sources = files('cn10k_worker.c', 'cn10k_eventdev.c', 'cn9k_worker.c', 'cn9k_eventdev.c', + 'cnxk_eventdev_adptr.c', 'cnxk_eventdev.c', 'cnxk_eventdev_selftest.c', 'cnxk_eventdev_stats.c', From patchwork Tue May 4 00:27:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92705 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F33FA0562; Tue, 4 May 2021 02:30:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 444A841167; Tue, 4 May 2021 02:29:21 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 15F3E411CC for ; Tue, 4 May 2021 02:29:19 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AUKf002424 for ; Mon, 3 May 2021 17:29:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=xPQzcxYn+pqZvh/UVfryrwjewMW93g9ogKLpW2CnQLU=; b=EnNdAHRRtxx8DQ0kNt4y5WVCpR3KGXYN7wPtvhoPVaa2UpiQEapa4O59giMYvNVtV13J hHFr1F03gXjR3XJY8mcNpOxYDEtu0qwdVH56bopkhXFJ15nYWmZzaXnJKHpbj6Ulk2Ir ohEHXn+MnufJ07N77MazBHAz1hxPc4aoLFo/50Azrwowkn5TK5+3xzB1O8o91ffSpDtc CZ5y0HtsVjR2VPDisoIzTGzMexI1Y0YYc8lMDBYJrK/qbppjtDePkT+RIuFMhBKzG1Cn W0uaiicz6wPIj97R6FCX1rW41fzG1k9F6ttHmQuhSdSgeTmXygV28Ze1VP8OJjArmAyH Og== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6p4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:19 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:16 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id E0AA93F703F; Mon, 3 May 2021 17:29:15 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:17 +0530 Message-ID: <20210504002726.525-28-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: x7uYG9eRS2e4aGm-0C4HMeXscCCG54Xu X-Proofpoint-ORIG-GUID: x7uYG9eRS2e4aGm-0C4HMeXscCCG54Xu X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 27/35] event/cnxk: add timer adapter info function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add TIM event timer adapter info get function. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cnxk_tim_evdev.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 1eb39a789..2fefa56f5 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -76,6 +76,18 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, return rc; } +static void +cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer_adapter_info *adptr_info) +{ + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + + adptr_info->max_tmo_ns = tim_ring->max_tout; + adptr_info->min_resolution_ns = tim_ring->tck_nsec; + rte_memcpy(&adptr_info->conf, &adptr->data->conf, + sizeof(struct rte_event_timer_adapter_conf)); +} + static int cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) { @@ -218,6 +230,7 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, cnxk_tim_ops.init = cnxk_tim_ring_create; cnxk_tim_ops.uninit = cnxk_tim_ring_free; + cnxk_tim_ops.get_info = cnxk_tim_ring_info_get; /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; From patchwork Tue May 4 00:27:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92706 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 10D63A0562; Tue, 4 May 2021 02:30:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9096241139; Tue, 4 May 2021 02:29:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3F79B41148 for ; Tue, 4 May 2021 02:29:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OvGh025198 for ; Mon, 3 May 2021 17:29:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jiBhv/Dyeiw0L5bPn50MWjRhk6PBOF/XhtJhE4z30lA=; b=b4P6tzEFrepU8bru12hpa47sGEhn4MQH9yZeL7FmMHrJR6N6THLLLfErhdq3wVXoJDSY tThAUOM/yCzn8R0koLpToL3kcXlK2yvH6Dkxjn3yDBQCmSvvF1I0pCQXggzWTGxSc1Io Gw90oqGyIOkNSXWhk7YYEU6NiYvBhnadrjDIDQ5JOl+1/+GpSSNiQ+QBiI7yEP+qvXfy ZRGLl8ejUz0r5v7ZBJkU0MUeYcdV8HJBBJCr+JR1bZX+Jdd3CCf71K6tJitXNhP6hpIN GbhL0aQD3c6h1LxtBH/QoKWuNLL0aVIlPwuMM7jgMmlHdqfejMm95vlGcV5KC9jOGAtj ug== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnte-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:19 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id B06103F703F; Mon, 3 May 2021 17:29:18 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:18 +0530 Message-ID: <20210504002726.525-29-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 0tvSt4bPc_sjuV4zUD-grvWzC7IldnNk X-Proofpoint-ORIG-GUID: 0tvSt4bPc_sjuV4zUD-grvWzC7IldnNk X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 28/35] event/cnxk: add devargs for chunk size and rings X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add devargs to control default chunk size and max numbers of timer rings to attach to a given RVU PF. Example: --dev "0002:1e:00.0,tim_chnk_slots=1024" --dev "0002:1e:00.0,tim_rings_lmt=4" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 23 +++++++++++++++++++++++ drivers/event/cnxk/cn10k_eventdev.c | 4 +++- drivers/event/cnxk/cn9k_eventdev.c | 4 +++- drivers/event/cnxk/cnxk_tim_evdev.c | 14 +++++++++++++- drivers/event/cnxk/cnxk_tim_evdev.h | 4 ++++ 5 files changed, 46 insertions(+), 3 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index c2d6ed2fb..a8199aac7 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -103,6 +103,29 @@ Runtime Config Options -a 0002:0e:00.0,tim_disable_npa=1 +- ``TIM modify chunk slots`` + + The ``tim_chnk_slots`` devargs can be used to modify number of chunk slots. + Chunks are used to store event timers, a chunk can be visualised as an array + where the last element points to the next chunk and rest of them are used to + store events. TIM traverses the list of chunks and enqueues the event timers + to SSO. The default value is 255 and the max value is 4095. + + For example:: + + -a 0002:0e:00.0,tim_chnk_slots=1023 + +- ``TIM limit max rings reserved`` + + The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM + rings i.e. event timer adapter reserved on probe. Since, TIM rings are HW + resources we can avoid starving other applications by not grabbing all the + rings. + + For example:: + + -a 0002:0e:00.0,tim_rings_lmt=5 + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index a2ef1fa73..cadc792a7 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -503,4 +503,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CN10K_SSO_GW_MODE "=" - CNXK_TIM_DISABLE_NPA "=1"); + CNXK_TIM_DISABLE_NPA "=1" + CNXK_TIM_CHNK_SLOTS "=" + CNXK_TIM_RINGS_LMT "="); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 3a0caa009..e503f6b1c 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -572,4 +572,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CN9K_SSO_SINGLE_WS "=1" - CNXK_TIM_DISABLE_NPA "=1"); + CNXK_TIM_DISABLE_NPA "=1" + CNXK_TIM_CHNK_SLOTS "=" + CNXK_TIM_RINGS_LMT "="); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 2fefa56f5..e06fe2f52 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -253,6 +253,10 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag, &dev->disable_npa); + rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value, + &dev->chunk_slots); + rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value, + &dev->min_ring_cnt); rte_kvargs_free(kvlist); } @@ -278,6 +282,7 @@ cnxk_tim_init(struct roc_sso *sso) cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev); dev->tim.roc_sso = sso; + dev->tim.nb_lfs = dev->min_ring_cnt; rc = roc_tim_init(&dev->tim); if (rc < 0) { plt_err("Failed to initialize roc tim resources"); @@ -285,7 +290,14 @@ cnxk_tim_init(struct roc_sso *sso) return; } dev->nb_rings = rc; - dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ; + + if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS && + dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) { + dev->chunk_sz = + (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT; + } else { + dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ; + } } void diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 4896ed67a..9496634c8 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -34,6 +34,8 @@ #define CN9K_TIM_MIN_TMO_TKS (256) #define CNXK_TIM_DISABLE_NPA "tim_disable_npa" +#define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" +#define CNXK_TIM_RINGS_LMT "tim_rings_lmt" struct cnxk_tim_evdev { struct roc_tim tim; @@ -42,6 +44,8 @@ struct cnxk_tim_evdev { uint32_t chunk_sz; /* Dev args */ uint8_t disable_npa; + uint16_t chunk_slots; + uint16_t min_ring_cnt; }; enum cnxk_tim_clk_src { From patchwork Tue May 4 00:27:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92707 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1EBB6A0562; Tue, 4 May 2021 02:31:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E228C41129; Tue, 4 May 2021 02:29:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9469D41127 for ; Tue, 4 May 2021 02:29:25 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AG6B002335 for ; Mon, 3 May 2021 17:29:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=T0tMmSSidllLXetzWsSTFI0Qo20G67rAo7pX5HkHgcE=; b=a9l/Q/XVP6lJkcJLUvBAbl33X7cZJJDHelxT2xlaOfYOvL77Y11Evl8cFWKQNnGpER8z bTqbhgQwlYqP5mgqsUnWbomJHc1vqzU0nReTfTcAK4jzadG51GMPphFFjhqA7bXaar1u cMK9y3rN2/pFiqdNk3BDpEN4Xjp4hwmuBbpZUQG4piWNrZjfcPWVHvms4yBK0uzKrrBy pNkDLagZSUKNJqWyN56LQ1h6wNfJAb6SPr2dE1YJj8TMvkr4vydUzlTc/iJw7teMx7yb q5hHDRFWjEoKqMjMYoU3kMZxUb5pbvX2WVe5Z9kWT6kXQb8LwPIRKkKibQLr1agFBoLE cw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6pn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:24 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:23 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 7D40B3F703F; Mon, 3 May 2021 17:29:21 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:19 +0530 Message-ID: <20210504002726.525-30-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: PgjLDH6n6r0TswIC-pYGGQEOgslXnHjZ X-Proofpoint-ORIG-GUID: PgjLDH6n6r0TswIC-pYGGQEOgslXnHjZ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 29/35] event/cnxk: add TIM bucket operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add TIM bucket operations used for event timer arm and cancel. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.h | 30 +++++++ drivers/event/cnxk/cnxk_tim_worker.c | 6 ++ drivers/event/cnxk/cnxk_tim_worker.h | 123 +++++++++++++++++++++++++++ drivers/event/cnxk/meson.build | 1 + 4 files changed, 160 insertions(+) create mode 100644 drivers/event/cnxk/cnxk_tim_worker.c create mode 100644 drivers/event/cnxk/cnxk_tim_worker.h diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 9496634c8..f6895417a 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -37,6 +37,36 @@ #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" #define CNXK_TIM_RINGS_LMT "tim_rings_lmt" +#define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48) +#define TIM_BUCKET_W1_M_CHUNK_REMAINDER \ + ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1) +#define TIM_BUCKET_W1_S_LOCK (40) +#define TIM_BUCKET_W1_M_LOCK \ + ((1ULL << (TIM_BUCKET_W1_S_CHUNK_REMAINDER - TIM_BUCKET_W1_S_LOCK)) - 1) +#define TIM_BUCKET_W1_S_RSVD (35) +#define TIM_BUCKET_W1_S_BSK (34) +#define TIM_BUCKET_W1_M_BSK \ + ((1ULL << (TIM_BUCKET_W1_S_RSVD - TIM_BUCKET_W1_S_BSK)) - 1) +#define TIM_BUCKET_W1_S_HBT (33) +#define TIM_BUCKET_W1_M_HBT \ + ((1ULL << (TIM_BUCKET_W1_S_BSK - TIM_BUCKET_W1_S_HBT)) - 1) +#define TIM_BUCKET_W1_S_SBT (32) +#define TIM_BUCKET_W1_M_SBT \ + ((1ULL << (TIM_BUCKET_W1_S_HBT - TIM_BUCKET_W1_S_SBT)) - 1) +#define TIM_BUCKET_W1_S_NUM_ENTRIES (0) +#define TIM_BUCKET_W1_M_NUM_ENTRIES \ + ((1ULL << (TIM_BUCKET_W1_S_SBT - TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1) + +#define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN) + +#define TIM_BUCKET_CHUNK_REMAIN \ + (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER) + +#define TIM_BUCKET_LOCK (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK) + +#define TIM_BUCKET_SEMA_WLOCK \ + (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK)) + struct cnxk_tim_evdev { struct roc_tim tim; struct rte_eventdev *event_dev; diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c new file mode 100644 index 000000000..49ee85245 --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "cnxk_tim_evdev.h" +#include "cnxk_tim_worker.h" diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h new file mode 100644 index 000000000..d56e67360 --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_worker.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CNXK_TIM_WORKER_H__ +#define __CNXK_TIM_WORKER_H__ + +#include "cnxk_tim_evdev.h" + +static inline uint8_t +cnxk_tim_bkt_fetch_lock(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_LOCK) & TIM_BUCKET_W1_M_LOCK; +} + +static inline int16_t +cnxk_tim_bkt_fetch_rem(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_CHUNK_REMAINDER) & + TIM_BUCKET_W1_M_CHUNK_REMAINDER; +} + +static inline int16_t +cnxk_tim_bkt_get_rem(struct cnxk_tim_bkt *bktp) +{ + return __atomic_load_n(&bktp->chunk_remainder, __ATOMIC_ACQUIRE); +} + +static inline void +cnxk_tim_bkt_set_rem(struct cnxk_tim_bkt *bktp, uint16_t v) +{ + __atomic_store_n(&bktp->chunk_remainder, v, __ATOMIC_RELAXED); +} + +static inline void +cnxk_tim_bkt_sub_rem(struct cnxk_tim_bkt *bktp, uint16_t v) +{ + __atomic_fetch_sub(&bktp->chunk_remainder, v, __ATOMIC_RELAXED); +} + +static inline uint8_t +cnxk_tim_bkt_get_hbt(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_HBT) & TIM_BUCKET_W1_M_HBT; +} + +static inline uint8_t +cnxk_tim_bkt_get_bsk(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_BSK) & TIM_BUCKET_W1_M_BSK; +} + +static inline uint64_t +cnxk_tim_bkt_clr_bsk(struct cnxk_tim_bkt *bktp) +{ + /* Clear everything except lock. */ + const uint64_t v = TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK; + + return __atomic_fetch_and(&bktp->w1, v, __ATOMIC_ACQ_REL); +} + +static inline uint64_t +cnxk_tim_bkt_fetch_sema_lock(struct cnxk_tim_bkt *bktp) +{ + return __atomic_fetch_add(&bktp->w1, TIM_BUCKET_SEMA_WLOCK, + __ATOMIC_ACQUIRE); +} + +static inline uint64_t +cnxk_tim_bkt_fetch_sema(struct cnxk_tim_bkt *bktp) +{ + return __atomic_fetch_add(&bktp->w1, TIM_BUCKET_SEMA, __ATOMIC_RELAXED); +} + +static inline uint64_t +cnxk_tim_bkt_inc_lock(struct cnxk_tim_bkt *bktp) +{ + const uint64_t v = 1ull << TIM_BUCKET_W1_S_LOCK; + + return __atomic_fetch_add(&bktp->w1, v, __ATOMIC_ACQUIRE); +} + +static inline void +cnxk_tim_bkt_dec_lock(struct cnxk_tim_bkt *bktp) +{ + __atomic_fetch_sub(&bktp->lock, 1, __ATOMIC_RELEASE); +} + +static inline void +cnxk_tim_bkt_dec_lock_relaxed(struct cnxk_tim_bkt *bktp) +{ + __atomic_fetch_sub(&bktp->lock, 1, __ATOMIC_RELAXED); +} + +static inline uint32_t +cnxk_tim_bkt_get_nent(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_NUM_ENTRIES) & + TIM_BUCKET_W1_M_NUM_ENTRIES; +} + +static inline void +cnxk_tim_bkt_inc_nent(struct cnxk_tim_bkt *bktp) +{ + __atomic_add_fetch(&bktp->nb_entry, 1, __ATOMIC_RELAXED); +} + +static inline void +cnxk_tim_bkt_add_nent(struct cnxk_tim_bkt *bktp, uint32_t v) +{ + __atomic_add_fetch(&bktp->nb_entry, v, __ATOMIC_RELAXED); +} + +static inline uint64_t +cnxk_tim_bkt_clr_nent(struct cnxk_tim_bkt *bktp) +{ + const uint64_t v = + ~(TIM_BUCKET_W1_M_NUM_ENTRIES << TIM_BUCKET_W1_S_NUM_ENTRIES); + + return __atomic_and_fetch(&bktp->w1, v, __ATOMIC_ACQ_REL); +} + +#endif /* __CNXK_TIM_WORKER_H__ */ diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index bd52cbc68..e665dfc72 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -16,6 +16,7 @@ sources = files('cn10k_worker.c', 'cnxk_eventdev.c', 'cnxk_eventdev_selftest.c', 'cnxk_eventdev_stats.c', + 'cnxk_tim_worker.c', 'cnxk_tim_evdev.c', ) From patchwork Tue May 4 00:27:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92708 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08AA5A0562; Tue, 4 May 2021 02:31:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3F8FF4112F; Tue, 4 May 2021 02:29:30 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DFDAE4112F for ; Tue, 4 May 2021 02:29:27 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440Otxp025090 for ; Mon, 3 May 2021 17:29:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=pxkCf5F3AyDuNwv5E7VaVST6OcKY8OVlei0YXclRvhU=; b=Q0ac3Fg+BAY4KhgIHTLzq9yKm1osxm6Ni10hequQb0PIu04JxV61Zqqkc0BTJqF5+QoG X+3Z+06vczUUITdoSnrg2S5y9x9vmoAO6ZMlKXYI0v3vyf9LPoHww5lhrHVUOHC+Gd71 ps6bDkH3GVhVYJUD+CQjqxZzcTOIbYRW4RrZEkt//3ojrwhkY0N8hjUgjI9Xd1N2UjSA usa4zBZ5kOy5F5mOxnEj3LnzDFBK7j5/+ba8vhcX9d02JSTKvZhaak29WjluiHKqcehf cwm0WhiNNKWz6xE4+XgnGHvSO/zyWUKbzdaPdCzXoE140Ylei22Ecd0tQtaRHLcXBz4V VA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjntm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:27 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:25 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 419103F703F; Mon, 3 May 2021 17:29:24 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:20 +0530 Message-ID: <20210504002726.525-31-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: uldHbPFcK8_mLUdvkth1QBJulHhqDXjF X-Proofpoint-ORIG-GUID: uldHbPFcK8_mLUdvkth1QBJulHhqDXjF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 30/35] event/cnxk: add timer arm routine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add event timer arm routine. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.c | 18 ++ drivers/event/cnxk/cnxk_tim_evdev.h | 23 ++ drivers/event/cnxk/cnxk_tim_worker.c | 95 +++++++++ drivers/event/cnxk/cnxk_tim_worker.h | 300 +++++++++++++++++++++++++++ 4 files changed, 436 insertions(+) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index e06fe2f52..ecc952a6a 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -76,6 +76,21 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, return rc; } +static void +cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring) +{ + uint8_t prod_flag = !tim_ring->prod_type_sp; + + /* [DFB/FB] [SP][MP]*/ + const rte_event_timer_arm_burst_t arm_burst[2][2] = { +#define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name, + TIM_ARM_FASTPATH_MODES +#undef FP + }; + + cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag]; +} + static void cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr, struct rte_event_timer_adapter_info *adptr_info) @@ -173,6 +188,9 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE); plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA); + /* Set fastpath ops. */ + cnxk_tim_set_fp_ops(tim_ring); + /* Update SSO xae count. */ cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring, RTE_EVENT_TYPE_TIMER); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index f6895417a..1f2aad17a 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -14,6 +14,7 @@ #include #include #include +#include #include "roc_api.h" @@ -37,6 +38,11 @@ #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" #define CNXK_TIM_RINGS_LMT "tim_rings_lmt" +#define CNXK_TIM_SP 0x1 +#define CNXK_TIM_MP 0x2 +#define CNXK_TIM_ENA_FB 0x10 +#define CNXK_TIM_ENA_DFB 0x20 + #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48) #define TIM_BUCKET_W1_M_CHUNK_REMAINDER \ ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1) @@ -107,10 +113,14 @@ struct cnxk_tim_ring { uintptr_t base; uint16_t nb_chunk_slots; uint32_t nb_bkts; + uint64_t last_updt_cyc; + uint64_t ring_start_cyc; uint64_t tck_int; uint64_t tot_int; struct cnxk_tim_bkt *bkt; struct rte_mempool *chunk_pool; + struct rte_reciprocal_u64 fast_div; + struct rte_reciprocal_u64 fast_bkt; uint64_t arm_cnt; uint8_t prod_type_sp; uint8_t disable_npa; @@ -201,6 +211,19 @@ cnxk_tim_cntfrq(void) } #endif +#define TIM_ARM_FASTPATH_MODES \ + FP(sp, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ + FP(mp, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ + FP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ + FP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) + +#define FP(_name, _f2, _f1, flags) \ + uint16_t cnxk_tim_arm_burst_##_name( \ + const struct rte_event_timer_adapter *adptr, \ + struct rte_event_timer **tim, const uint16_t nb_timers); +TIM_ARM_FASTPATH_MODES +#undef FP + int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags, uint32_t *caps, const struct rte_event_timer_adapter_ops **ops); diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c index 49ee85245..268f845c8 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.c +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -4,3 +4,98 @@ #include "cnxk_tim_evdev.h" #include "cnxk_tim_worker.h" + +static inline int +cnxk_tim_arm_checks(const struct cnxk_tim_ring *const tim_ring, + struct rte_event_timer *const tim) +{ + if (unlikely(tim->state)) { + tim->state = RTE_EVENT_TIMER_ERROR; + rte_errno = EALREADY; + goto fail; + } + + if (unlikely(!tim->timeout_ticks || + tim->timeout_ticks > tim_ring->nb_bkts)) { + tim->state = tim->timeout_ticks ? + RTE_EVENT_TIMER_ERROR_TOOLATE : + RTE_EVENT_TIMER_ERROR_TOOEARLY; + rte_errno = EINVAL; + goto fail; + } + + return 0; + +fail: + return -EINVAL; +} + +static inline void +cnxk_tim_format_event(const struct rte_event_timer *const tim, + struct cnxk_tim_ent *const entry) +{ + entry->w0 = (tim->ev.event & 0xFFC000000000) >> 6 | + (tim->ev.event & 0xFFFFFFFFF); + entry->wqe = tim->ev.u64; +} + +static inline void +cnxk_tim_sync_start_cyc(struct cnxk_tim_ring *tim_ring) +{ + uint64_t cur_cyc = cnxk_tim_cntvct(); + uint32_t real_bkt; + + if (cur_cyc - tim_ring->last_updt_cyc > tim_ring->tot_int) { + real_bkt = plt_read64(tim_ring->base + TIM_LF_RING_REL) >> 44; + cur_cyc = cnxk_tim_cntvct(); + + tim_ring->ring_start_cyc = + cur_cyc - (real_bkt * tim_ring->tck_int); + tim_ring->last_updt_cyc = cur_cyc; + } +} + +static __rte_always_inline uint16_t +cnxk_tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer **tim, const uint16_t nb_timers, + const uint8_t flags) +{ + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + struct cnxk_tim_ent entry; + uint16_t index; + int ret; + + cnxk_tim_sync_start_cyc(tim_ring); + for (index = 0; index < nb_timers; index++) { + if (cnxk_tim_arm_checks(tim_ring, tim[index])) + break; + + cnxk_tim_format_event(tim[index], &entry); + if (flags & CNXK_TIM_SP) + ret = cnxk_tim_add_entry_sp(tim_ring, + tim[index]->timeout_ticks, + tim[index], &entry, flags); + if (flags & CNXK_TIM_MP) + ret = cnxk_tim_add_entry_mp(tim_ring, + tim[index]->timeout_ticks, + tim[index], &entry, flags); + + if (unlikely(ret)) { + rte_errno = -ret; + break; + } + } + + return index; +} + +#define FP(_name, _f2, _f1, _flags) \ + uint16_t __rte_noinline cnxk_tim_arm_burst_##_name( \ + const struct rte_event_timer_adapter *adptr, \ + struct rte_event_timer **tim, const uint16_t nb_timers) \ + { \ + return cnxk_tim_timer_arm_burst(adptr, tim, nb_timers, \ + _flags); \ + } +TIM_ARM_FASTPATH_MODES +#undef FP diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h index d56e67360..de8464e33 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.h +++ b/drivers/event/cnxk/cnxk_tim_worker.h @@ -120,4 +120,304 @@ cnxk_tim_bkt_clr_nent(struct cnxk_tim_bkt *bktp) return __atomic_and_fetch(&bktp->w1, v, __ATOMIC_ACQ_REL); } +static inline uint64_t +cnxk_tim_bkt_fast_mod(uint64_t n, uint64_t d, struct rte_reciprocal_u64 R) +{ + return (n - (d * rte_reciprocal_divide_u64(n, &R))); +} + +static __rte_always_inline void +cnxk_tim_get_target_bucket(struct cnxk_tim_ring *const tim_ring, + const uint32_t rel_bkt, struct cnxk_tim_bkt **bkt, + struct cnxk_tim_bkt **mirr_bkt) +{ + const uint64_t bkt_cyc = cnxk_tim_cntvct() - tim_ring->ring_start_cyc; + uint64_t bucket = + rte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div) + + rel_bkt; + uint64_t mirr_bucket = 0; + + bucket = cnxk_tim_bkt_fast_mod(bucket, tim_ring->nb_bkts, + tim_ring->fast_bkt); + mirr_bucket = + cnxk_tim_bkt_fast_mod(bucket + (tim_ring->nb_bkts >> 1), + tim_ring->nb_bkts, tim_ring->fast_bkt); + *bkt = &tim_ring->bkt[bucket]; + *mirr_bkt = &tim_ring->bkt[mirr_bucket]; +} + +static struct cnxk_tim_ent * +cnxk_tim_clr_bkt(struct cnxk_tim_ring *const tim_ring, + struct cnxk_tim_bkt *const bkt) +{ +#define TIM_MAX_OUTSTANDING_OBJ 64 + void *pend_chunks[TIM_MAX_OUTSTANDING_OBJ]; + struct cnxk_tim_ent *chunk; + struct cnxk_tim_ent *pnext; + uint8_t objs = 0; + + chunk = ((struct cnxk_tim_ent *)(uintptr_t)bkt->first_chunk); + chunk = (struct cnxk_tim_ent *)(uintptr_t)(chunk + + tim_ring->nb_chunk_slots) + ->w0; + while (chunk) { + pnext = (struct cnxk_tim_ent *)(uintptr_t)( + (chunk + tim_ring->nb_chunk_slots)->w0); + if (objs == TIM_MAX_OUTSTANDING_OBJ) { + rte_mempool_put_bulk(tim_ring->chunk_pool, pend_chunks, + objs); + objs = 0; + } + pend_chunks[objs++] = chunk; + chunk = pnext; + } + + if (objs) + rte_mempool_put_bulk(tim_ring->chunk_pool, pend_chunks, objs); + + return (struct cnxk_tim_ent *)(uintptr_t)bkt->first_chunk; +} + +static struct cnxk_tim_ent * +cnxk_tim_refill_chunk(struct cnxk_tim_bkt *const bkt, + struct cnxk_tim_bkt *const mirr_bkt, + struct cnxk_tim_ring *const tim_ring) +{ + struct cnxk_tim_ent *chunk; + + if (bkt->nb_entry || !bkt->first_chunk) { + if (unlikely(rte_mempool_get(tim_ring->chunk_pool, + (void **)&chunk))) + return NULL; + if (bkt->nb_entry) { + *(uint64_t *)(((struct cnxk_tim_ent *) + mirr_bkt->current_chunk) + + tim_ring->nb_chunk_slots) = + (uintptr_t)chunk; + } else { + bkt->first_chunk = (uintptr_t)chunk; + } + } else { + chunk = cnxk_tim_clr_bkt(tim_ring, bkt); + bkt->first_chunk = (uintptr_t)chunk; + } + *(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0; + + return chunk; +} + +static struct cnxk_tim_ent * +cnxk_tim_insert_chunk(struct cnxk_tim_bkt *const bkt, + struct cnxk_tim_bkt *const mirr_bkt, + struct cnxk_tim_ring *const tim_ring) +{ + struct cnxk_tim_ent *chunk; + + if (unlikely(rte_mempool_get(tim_ring->chunk_pool, (void **)&chunk))) + return NULL; + + *(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0; + if (bkt->nb_entry) { + *(uint64_t *)(((struct cnxk_tim_ent *)(uintptr_t) + mirr_bkt->current_chunk) + + tim_ring->nb_chunk_slots) = (uintptr_t)chunk; + } else { + bkt->first_chunk = (uintptr_t)chunk; + } + return chunk; +} + +static __rte_always_inline int +cnxk_tim_add_entry_sp(struct cnxk_tim_ring *const tim_ring, + const uint32_t rel_bkt, struct rte_event_timer *const tim, + const struct cnxk_tim_ent *const pent, + const uint8_t flags) +{ + struct cnxk_tim_bkt *mirr_bkt; + struct cnxk_tim_ent *chunk; + struct cnxk_tim_bkt *bkt; + uint64_t lock_sema; + int16_t rem; + +__retry: + cnxk_tim_get_target_bucket(tim_ring, rel_bkt, &bkt, &mirr_bkt); + + /* Get Bucket sema*/ + lock_sema = cnxk_tim_bkt_fetch_sema_lock(bkt); + + /* Bucket related checks. */ + if (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) { + if (cnxk_tim_bkt_get_nent(lock_sema) != 0) { + uint64_t hbt_state; +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldxr %[hbt], [%[w1]] \n" + " tbz %[hbt], 33, dne%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldxr %[hbt], [%[w1]] \n" + " tbnz %[hbt], 33, rty%= \n" + "dne%=: \n" + : [hbt] "=&r"(hbt_state) + : [w1] "r"((&bkt->w1)) + : "memory"); +#else + do { + hbt_state = __atomic_load_n(&bkt->w1, + __ATOMIC_RELAXED); + } while (hbt_state & BIT_ULL(33)); +#endif + + if (!(hbt_state & BIT_ULL(34))) { + cnxk_tim_bkt_dec_lock(bkt); + goto __retry; + } + } + } + /* Insert the work. */ + rem = cnxk_tim_bkt_fetch_rem(lock_sema); + + if (!rem) { + if (flags & CNXK_TIM_ENA_FB) + chunk = cnxk_tim_refill_chunk(bkt, mirr_bkt, tim_ring); + if (flags & CNXK_TIM_ENA_DFB) + chunk = cnxk_tim_insert_chunk(bkt, mirr_bkt, tim_ring); + + if (unlikely(chunk == NULL)) { + bkt->chunk_remainder = 0; + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + tim->state = RTE_EVENT_TIMER_ERROR; + cnxk_tim_bkt_dec_lock(bkt); + return -ENOMEM; + } + mirr_bkt->current_chunk = (uintptr_t)chunk; + bkt->chunk_remainder = tim_ring->nb_chunk_slots - 1; + } else { + chunk = (struct cnxk_tim_ent *)mirr_bkt->current_chunk; + chunk += tim_ring->nb_chunk_slots - rem; + } + + /* Copy work entry. */ + *chunk = *pent; + + tim->impl_opaque[0] = (uintptr_t)chunk; + tim->impl_opaque[1] = (uintptr_t)bkt; + __atomic_store_n(&tim->state, RTE_EVENT_TIMER_ARMED, __ATOMIC_RELEASE); + cnxk_tim_bkt_inc_nent(bkt); + cnxk_tim_bkt_dec_lock_relaxed(bkt); + + return 0; +} + +static __rte_always_inline int +cnxk_tim_add_entry_mp(struct cnxk_tim_ring *const tim_ring, + const uint32_t rel_bkt, struct rte_event_timer *const tim, + const struct cnxk_tim_ent *const pent, + const uint8_t flags) +{ + struct cnxk_tim_bkt *mirr_bkt; + struct cnxk_tim_ent *chunk; + struct cnxk_tim_bkt *bkt; + uint64_t lock_sema; + int16_t rem; + +__retry: + cnxk_tim_get_target_bucket(tim_ring, rel_bkt, &bkt, &mirr_bkt); + /* Get Bucket sema*/ + lock_sema = cnxk_tim_bkt_fetch_sema_lock(bkt); + + /* Bucket related checks. */ + if (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) { + if (cnxk_tim_bkt_get_nent(lock_sema) != 0) { + uint64_t hbt_state; +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldxr %[hbt], [%[w1]] \n" + " tbz %[hbt], 33, dne%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldxr %[hbt], [%[w1]] \n" + " tbnz %[hbt], 33, rty%= \n" + "dne%=: \n" + : [hbt] "=&r"(hbt_state) + : [w1] "r"((&bkt->w1)) + : "memory"); +#else + do { + hbt_state = __atomic_load_n(&bkt->w1, + __ATOMIC_RELAXED); + } while (hbt_state & BIT_ULL(33)); +#endif + + if (!(hbt_state & BIT_ULL(34))) { + cnxk_tim_bkt_dec_lock(bkt); + goto __retry; + } + } + } + + rem = cnxk_tim_bkt_fetch_rem(lock_sema); + if (rem < 0) { + cnxk_tim_bkt_dec_lock(bkt); +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldxr %[rem], [%[crem]] \n" + " tbz %[rem], 63, dne%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldxr %[rem], [%[crem]] \n" + " tbnz %[rem], 63, rty%= \n" + "dne%=: \n" + : [rem] "=&r"(rem) + : [crem] "r"(&bkt->w1) + : "memory"); +#else + while (__atomic_load_n((int64_t *)&bkt->w1, __ATOMIC_RELAXED) < + 0) + ; +#endif + goto __retry; + } else if (!rem) { + /* Only one thread can be here*/ + if (flags & CNXK_TIM_ENA_FB) + chunk = cnxk_tim_refill_chunk(bkt, mirr_bkt, tim_ring); + if (flags & CNXK_TIM_ENA_DFB) + chunk = cnxk_tim_insert_chunk(bkt, mirr_bkt, tim_ring); + + if (unlikely(chunk == NULL)) { + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + tim->state = RTE_EVENT_TIMER_ERROR; + cnxk_tim_bkt_set_rem(bkt, 0); + cnxk_tim_bkt_dec_lock(bkt); + return -ENOMEM; + } + *chunk = *pent; + if (cnxk_tim_bkt_fetch_lock(lock_sema)) { + do { + lock_sema = __atomic_load_n(&bkt->w1, + __ATOMIC_RELAXED); + } while (cnxk_tim_bkt_fetch_lock(lock_sema) - 1); + } + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); + mirr_bkt->current_chunk = (uintptr_t)chunk; + __atomic_store_n(&bkt->chunk_remainder, + tim_ring->nb_chunk_slots - 1, + __ATOMIC_RELEASE); + } else { + chunk = (struct cnxk_tim_ent *)mirr_bkt->current_chunk; + chunk += tim_ring->nb_chunk_slots - rem; + *chunk = *pent; + } + + tim->impl_opaque[0] = (uintptr_t)chunk; + tim->impl_opaque[1] = (uintptr_t)bkt; + __atomic_store_n(&tim->state, RTE_EVENT_TIMER_ARMED, __ATOMIC_RELEASE); + cnxk_tim_bkt_inc_nent(bkt); + cnxk_tim_bkt_dec_lock_relaxed(bkt); + + return 0; +} + #endif /* __CNXK_TIM_WORKER_H__ */ From patchwork Tue May 4 00:27:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92709 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B764A0562; Tue, 4 May 2021 02:31:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1190240150; Tue, 4 May 2021 02:29:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C447A410FD for ; Tue, 4 May 2021 02:29:30 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440P26L025320 for ; Mon, 3 May 2021 17:29:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=+1WaCOFp/l4jY9q1R+4GtwceMDR34A8ISQYQtPnlnnE=; b=LrBJ6M1A47oDnBDnMAxlkafrAOWHTnyTn87AU25ZrtmiFZANWf6CslFGNfH/6REfj7n2 +wVgG62TZT1WHb4FLA1XZGS3QhGOFgGWwOENO44dE78iEqyEusL1Bh3G4wLuFQ6tDk7j 3WM+wbaBj4+ygrUmJqOFJSt7ekU6UfLlVEW5LysfC6w7k4poYAgkf6Nrw6e7Sxt+R90B 8+ygQlA+Qq6jrtOFF2GdHSql7ys37b6tW7Bht0XlWP7rXj7QEWdJPpyTiPywadoBgkOT uPUkJfMiydFAY2isBt+7yzDASQYdv46wE4Yr7lkgiMh737lnlV2DbPb535YlGoqm4OQv 7A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjntw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:29 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:27 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 007773F703F; Mon, 3 May 2021 17:29:26 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:21 +0530 Message-ID: <20210504002726.525-32-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: hHjzbpySj_59wpQ4c3_Et_wlZ8buC0NR X-Proofpoint-ORIG-GUID: hHjzbpySj_59wpQ4c3_Et_wlZ8buC0NR X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 31/35] event/cnxk: add timer arm timeout burst X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add event timer arm timeout burst function. All the timers requested to be armed have the same timeout. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.c | 7 ++ drivers/event/cnxk/cnxk_tim_evdev.h | 12 +++ drivers/event/cnxk/cnxk_tim_worker.c | 53 ++++++++++ drivers/event/cnxk/cnxk_tim_worker.h | 141 +++++++++++++++++++++++++++ 4 files changed, 213 insertions(+) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index ecc952a6a..68c3b3049 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -88,7 +88,14 @@ cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring) #undef FP }; + const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2] = { +#define FP(_name, _f1, flags) [_f1] = cnxk_tim_arm_tmo_tick_burst_##_name, + TIM_ARM_TMO_FASTPATH_MODES +#undef FP + }; + cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag]; + cnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb]; } static void diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 1f2aad17a..b66aac17c 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -217,6 +217,10 @@ cnxk_tim_cntfrq(void) FP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ FP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) +#define TIM_ARM_TMO_FASTPATH_MODES \ + FP(dfb, 0, CNXK_TIM_ENA_DFB) \ + FP(fb, 1, CNXK_TIM_ENA_FB) + #define FP(_name, _f2, _f1, flags) \ uint16_t cnxk_tim_arm_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ @@ -224,6 +228,14 @@ cnxk_tim_cntfrq(void) TIM_ARM_FASTPATH_MODES #undef FP +#define FP(_name, _f1, flags) \ + uint16_t cnxk_tim_arm_tmo_tick_burst_##_name( \ + const struct rte_event_timer_adapter *adptr, \ + struct rte_event_timer **tim, const uint64_t timeout_tick, \ + const uint16_t nb_timers); +TIM_ARM_TMO_FASTPATH_MODES +#undef FP + int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags, uint32_t *caps, const struct rte_event_timer_adapter_ops **ops); diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c index 268f845c8..717c53fb7 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.c +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -99,3 +99,56 @@ cnxk_tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr, } TIM_ARM_FASTPATH_MODES #undef FP + +static __rte_always_inline uint16_t +cnxk_tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer **tim, + const uint64_t timeout_tick, + const uint16_t nb_timers, const uint8_t flags) +{ + struct cnxk_tim_ent entry[CNXK_TIM_MAX_BURST] __rte_cache_aligned; + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + uint16_t set_timers = 0; + uint16_t arr_idx = 0; + uint16_t idx; + int ret; + + if (unlikely(!timeout_tick || timeout_tick > tim_ring->nb_bkts)) { + const enum rte_event_timer_state state = + timeout_tick ? RTE_EVENT_TIMER_ERROR_TOOLATE : + RTE_EVENT_TIMER_ERROR_TOOEARLY; + for (idx = 0; idx < nb_timers; idx++) + tim[idx]->state = state; + + rte_errno = EINVAL; + return 0; + } + + cnxk_tim_sync_start_cyc(tim_ring); + while (arr_idx < nb_timers) { + for (idx = 0; idx < CNXK_TIM_MAX_BURST && (arr_idx < nb_timers); + idx++, arr_idx++) { + cnxk_tim_format_event(tim[arr_idx], &entry[idx]); + } + ret = cnxk_tim_add_entry_brst(tim_ring, timeout_tick, + &tim[set_timers], entry, idx, + flags); + set_timers += ret; + if (ret != idx) + break; + } + + return set_timers; +} + +#define FP(_name, _f1, _flags) \ + uint16_t __rte_noinline cnxk_tim_arm_tmo_tick_burst_##_name( \ + const struct rte_event_timer_adapter *adptr, \ + struct rte_event_timer **tim, const uint64_t timeout_tick, \ + const uint16_t nb_timers) \ + { \ + return cnxk_tim_timer_arm_tmo_brst(adptr, tim, timeout_tick, \ + nb_timers, _flags); \ + } +TIM_ARM_TMO_FASTPATH_MODES +#undef FP diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h index de8464e33..56cb4cdd9 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.h +++ b/drivers/event/cnxk/cnxk_tim_worker.h @@ -420,4 +420,145 @@ cnxk_tim_add_entry_mp(struct cnxk_tim_ring *const tim_ring, return 0; } +static inline uint16_t +cnxk_tim_cpy_wrk(uint16_t index, uint16_t cpy_lmt, struct cnxk_tim_ent *chunk, + struct rte_event_timer **const tim, + const struct cnxk_tim_ent *const ents, + const struct cnxk_tim_bkt *const bkt) +{ + for (; index < cpy_lmt; index++) { + *chunk = *(ents + index); + tim[index]->impl_opaque[0] = (uintptr_t)chunk++; + tim[index]->impl_opaque[1] = (uintptr_t)bkt; + tim[index]->state = RTE_EVENT_TIMER_ARMED; + } + + return index; +} + +/* Burst mode functions */ +static inline int +cnxk_tim_add_entry_brst(struct cnxk_tim_ring *const tim_ring, + const uint16_t rel_bkt, + struct rte_event_timer **const tim, + const struct cnxk_tim_ent *ents, + const uint16_t nb_timers, const uint8_t flags) +{ + struct cnxk_tim_ent *chunk = NULL; + struct cnxk_tim_bkt *mirr_bkt; + struct cnxk_tim_bkt *bkt; + uint16_t chunk_remainder; + uint16_t index = 0; + uint64_t lock_sema; + int16_t rem, crem; + uint8_t lock_cnt; + +__retry: + cnxk_tim_get_target_bucket(tim_ring, rel_bkt, &bkt, &mirr_bkt); + + /* Only one thread beyond this. */ + lock_sema = cnxk_tim_bkt_inc_lock(bkt); + lock_cnt = (uint8_t)((lock_sema >> TIM_BUCKET_W1_S_LOCK) & + TIM_BUCKET_W1_M_LOCK); + + if (lock_cnt) { + cnxk_tim_bkt_dec_lock(bkt); +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldxrb %w[lock_cnt], [%[lock]] \n" + " tst %w[lock_cnt], 255 \n" + " beq dne%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldxrb %w[lock_cnt], [%[lock]] \n" + " tst %w[lock_cnt], 255 \n" + " bne rty%= \n" + "dne%=: \n" + : [lock_cnt] "=&r"(lock_cnt) + : [lock] "r"(&bkt->lock) + : "memory"); +#else + while (__atomic_load_n(&bkt->lock, __ATOMIC_RELAXED)) + ; +#endif + goto __retry; + } + + /* Bucket related checks. */ + if (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) { + if (cnxk_tim_bkt_get_nent(lock_sema) != 0) { + uint64_t hbt_state; +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldxr %[hbt], [%[w1]] \n" + " tbz %[hbt], 33, dne%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldxr %[hbt], [%[w1]] \n" + " tbnz %[hbt], 33, rty%= \n" + "dne%=: \n" + : [hbt] "=&r"(hbt_state) + : [w1] "r"((&bkt->w1)) + : "memory"); +#else + do { + hbt_state = __atomic_load_n(&bkt->w1, + __ATOMIC_RELAXED); + } while (hbt_state & BIT_ULL(33)); +#endif + + if (!(hbt_state & BIT_ULL(34))) { + cnxk_tim_bkt_dec_lock(bkt); + goto __retry; + } + } + } + + chunk_remainder = cnxk_tim_bkt_fetch_rem(lock_sema); + rem = chunk_remainder - nb_timers; + if (rem < 0) { + crem = tim_ring->nb_chunk_slots - chunk_remainder; + if (chunk_remainder && crem) { + chunk = ((struct cnxk_tim_ent *) + mirr_bkt->current_chunk) + + crem; + + index = cnxk_tim_cpy_wrk(index, chunk_remainder, chunk, + tim, ents, bkt); + cnxk_tim_bkt_sub_rem(bkt, chunk_remainder); + cnxk_tim_bkt_add_nent(bkt, chunk_remainder); + } + + if (flags & CNXK_TIM_ENA_FB) + chunk = cnxk_tim_refill_chunk(bkt, mirr_bkt, tim_ring); + if (flags & CNXK_TIM_ENA_DFB) + chunk = cnxk_tim_insert_chunk(bkt, mirr_bkt, tim_ring); + + if (unlikely(chunk == NULL)) { + cnxk_tim_bkt_dec_lock(bkt); + rte_errno = ENOMEM; + tim[index]->state = RTE_EVENT_TIMER_ERROR; + return crem; + } + *(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0; + mirr_bkt->current_chunk = (uintptr_t)chunk; + cnxk_tim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt); + + rem = nb_timers - chunk_remainder; + cnxk_tim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - rem); + cnxk_tim_bkt_add_nent(bkt, rem); + } else { + chunk = (struct cnxk_tim_ent *)mirr_bkt->current_chunk; + chunk += (tim_ring->nb_chunk_slots - chunk_remainder); + + cnxk_tim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt); + cnxk_tim_bkt_sub_rem(bkt, nb_timers); + cnxk_tim_bkt_add_nent(bkt, nb_timers); + } + + cnxk_tim_bkt_dec_lock(bkt); + + return nb_timers; +} + #endif /* __CNXK_TIM_WORKER_H__ */ From patchwork Tue May 4 00:27:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92710 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3658A0562; Tue, 4 May 2021 02:31:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87318410F8; Tue, 4 May 2021 02:29:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AD55A4113A for ; Tue, 4 May 2021 02:29:34 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGTT002336 for ; Mon, 3 May 2021 17:29:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=46LXj6+OJw6WuFoSmB0QOL7ZMxoHYX/KJ0zTJo2e7bo=; b=MOve9pHwAgb6z0XYbPV5R35LdGGZGUjiYJhUkVWH+30gvvmYp6Ae590mAz3fJGjaIVOa 5kGueQa38xwmmSqtl2A+O19QUh+8rseEUrxars87XBNU9OCyzrPgD07DpNhE4SzIlSW3 5LRhCUdQ+PJYg7HICLlAwtlZVow71cHnnBJctLUKhzVHGlFp8qPPxNICeFWx+nuqI6xg OaDtGCdJ+7tAdpMxsZaPGhBbWVm1xbEi1+UXodqA44m2ARwqTIBTUClqZw0ElXTxuO9k LCKrLEWh1jCFCmFdyrtDiUCVlHH1To5sg7fCUQfGBis0ib30P5+1ymLZlK0PgGVouTOm xg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6q0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:33 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:30 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id B003A3F703F; Mon, 3 May 2021 17:29:29 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:22 +0530 Message-ID: <20210504002726.525-33-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: kjSMumwu_hLzqGP51c1v24r0X_Amzj20 X-Proofpoint-ORIG-GUID: kjSMumwu_hLzqGP51c1v24r0X_Amzj20 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 32/35] event/cnxk: add timer cancel function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add function to cancel event timer that has been armed. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.c | 1 + drivers/event/cnxk/cnxk_tim_evdev.h | 5 ++++ drivers/event/cnxk/cnxk_tim_worker.c | 30 ++++++++++++++++++++++ drivers/event/cnxk/cnxk_tim_worker.h | 37 ++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 68c3b3049..62a15a4a1 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -96,6 +96,7 @@ cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring) cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag]; cnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb]; + cnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst; } static void diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index b66aac17c..001f448d5 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -236,6 +236,11 @@ TIM_ARM_FASTPATH_MODES TIM_ARM_TMO_FASTPATH_MODES #undef FP +uint16_t +cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer **tim, + const uint16_t nb_timers); + int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags, uint32_t *caps, const struct rte_event_timer_adapter_ops **ops); diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c index 717c53fb7..98ff143c3 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.c +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -152,3 +152,33 @@ cnxk_tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, } TIM_ARM_TMO_FASTPATH_MODES #undef FP + +uint16_t +cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer **tim, + const uint16_t nb_timers) +{ + uint16_t index; + int ret; + + RTE_SET_USED(adptr); + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); + for (index = 0; index < nb_timers; index++) { + if (tim[index]->state == RTE_EVENT_TIMER_CANCELED) { + rte_errno = EALREADY; + break; + } + + if (tim[index]->state != RTE_EVENT_TIMER_ARMED) { + rte_errno = EINVAL; + break; + } + ret = cnxk_tim_rm_entry(tim[index]); + if (ret) { + rte_errno = -ret; + break; + } + } + + return index; +} diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h index 56cb4cdd9..7caeb1a8f 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.h +++ b/drivers/event/cnxk/cnxk_tim_worker.h @@ -561,4 +561,41 @@ cnxk_tim_add_entry_brst(struct cnxk_tim_ring *const tim_ring, return nb_timers; } +static int +cnxk_tim_rm_entry(struct rte_event_timer *tim) +{ + struct cnxk_tim_ent *entry; + struct cnxk_tim_bkt *bkt; + uint64_t lock_sema; + + if (tim->impl_opaque[1] == 0 || tim->impl_opaque[0] == 0) + return -ENOENT; + + entry = (struct cnxk_tim_ent *)(uintptr_t)tim->impl_opaque[0]; + if (entry->wqe != tim->ev.u64) { + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + return -ENOENT; + } + + bkt = (struct cnxk_tim_bkt *)(uintptr_t)tim->impl_opaque[1]; + lock_sema = cnxk_tim_bkt_inc_lock(bkt); + if (cnxk_tim_bkt_get_hbt(lock_sema) || + !cnxk_tim_bkt_get_nent(lock_sema)) { + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + cnxk_tim_bkt_dec_lock(bkt); + return -ENOENT; + } + + entry->w0 = 0; + entry->wqe = 0; + tim->state = RTE_EVENT_TIMER_CANCELED; + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + cnxk_tim_bkt_dec_lock(bkt); + + return 0; +} + #endif /* __CNXK_TIM_WORKER_H__ */ From patchwork Tue May 4 00:27:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92711 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 217FEA0562; Tue, 4 May 2021 02:31:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA7B54115A; Tue, 4 May 2021 02:29:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3763A4115A for ; Tue, 4 May 2021 02:29:36 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440P26P025320 for ; Mon, 3 May 2021 17:29:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=VLerbvCYDRMQyLw9SUPECMAGfCDV9Uh6w8+xs8tjtKs=; b=G/PxdE/SMOqSAxrtleyNYhCu6guxdWpGfRBEPap2Ex5Q01YcH62AOw7T/Pd9+TmQH3aj NWCLTdSnzyBVB74iIlp9OEAIFolKqvhhTlS7gF//mIyVVVdk/pVHQRYDy1dL4LXqvUJT rCFvcaO8Vvn+aGpZQ8YPqaYqimcPm63pnTGcpCcz8nXPEL3sg4mWYGuVqK6Ynzz92yaX 1VBFyztdMme/GwThx5DvSwCs0PqFgaqpb3txAnuadvNrC4a4QRjQyvi3GFuB8qsFYi6K +w1eQrhbMqBgiVhZ3gskKpMJixQcEdDNP9SF2kn2Bb3pdwsYHsO5pg2N6VYInUrB2DEk bA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnu8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:33 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 77A833F703F; Mon, 3 May 2021 17:29:32 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:23 +0530 Message-ID: <20210504002726.525-34-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: a5rt2uOiBDVzFTEbjydngCYkKmbV5jJS X-Proofpoint-ORIG-GUID: a5rt2uOiBDVzFTEbjydngCYkKmbV5jJS X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 33/35] event/cnxk: add timer stats get and reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add event timer adapter statistics get and reset functions. Stats are disabled by default and can be enabled through devargs. Example: --dev "0002:1e:00.0,tim_stats_ena=1" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 9 +++++ drivers/event/cnxk/cn10k_eventdev.c | 3 +- drivers/event/cnxk/cn9k_eventdev.c | 3 +- drivers/event/cnxk/cnxk_tim_evdev.c | 50 ++++++++++++++++++++++++---- drivers/event/cnxk/cnxk_tim_evdev.h | 38 ++++++++++++++------- drivers/event/cnxk/cnxk_tim_worker.c | 11 ++++-- 6 files changed, 91 insertions(+), 23 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index a8199aac7..11145dd7d 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -115,6 +115,15 @@ Runtime Config Options -a 0002:0e:00.0,tim_chnk_slots=1023 +- ``TIM enable arm/cancel statistics`` + + The ``tim_stats_ena`` devargs can be used to enable arm and cancel stats of + event timer adapter. + + For example:: + + -a 0002:0e:00.0,tim_stats_ena=1 + - ``TIM limit max rings reserved`` The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index cadc792a7..bf4052c76 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -505,4 +505,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CN10K_SSO_GW_MODE "=" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" - CNXK_TIM_RINGS_LMT "="); + CNXK_TIM_RINGS_LMT "=" + CNXK_TIM_STATS_ENA "=1"); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index e503f6b1c..0684417ea 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -574,4 +574,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" CN9K_SSO_SINGLE_WS "=1" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" - CNXK_TIM_RINGS_LMT "="); + CNXK_TIM_RINGS_LMT "=" + CNXK_TIM_STATS_ENA "=1"); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 62a15a4a1..a73ca33d8 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -81,21 +81,25 @@ cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring) { uint8_t prod_flag = !tim_ring->prod_type_sp; - /* [DFB/FB] [SP][MP]*/ - const rte_event_timer_arm_burst_t arm_burst[2][2] = { -#define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name, + /* [STATS] [DFB/FB] [SP][MP]*/ + const rte_event_timer_arm_burst_t arm_burst[2][2][2] = { +#define FP(_name, _f3, _f2, _f1, flags) \ + [_f3][_f2][_f1] = cnxk_tim_arm_burst_##_name, TIM_ARM_FASTPATH_MODES #undef FP }; - const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2] = { -#define FP(_name, _f1, flags) [_f1] = cnxk_tim_arm_tmo_tick_burst_##_name, + const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2] = { +#define FP(_name, _f2, _f1, flags) \ + [_f2][_f1] = cnxk_tim_arm_tmo_tick_burst_##_name, TIM_ARM_TMO_FASTPATH_MODES #undef FP }; - cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag]; - cnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb]; + cnxk_tim_ops.arm_burst = + arm_burst[tim_ring->enable_stats][tim_ring->ena_dfb][prod_flag]; + cnxk_tim_ops.arm_tmo_tick_burst = + arm_tmo_burst[tim_ring->enable_stats][tim_ring->ena_dfb]; cnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst; } @@ -159,6 +163,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->nb_timers = rcfg->nb_timers; tim_ring->chunk_sz = dev->chunk_sz; tim_ring->disable_npa = dev->disable_npa; + tim_ring->enable_stats = dev->enable_stats; if (tim_ring->disable_npa) { tim_ring->nb_chunks = @@ -241,6 +246,30 @@ cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr) return 0; } +static int +cnxk_tim_stats_get(const struct rte_event_timer_adapter *adapter, + struct rte_event_timer_adapter_stats *stats) +{ + struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv; + uint64_t bkt_cyc = cnxk_tim_cntvct() - tim_ring->ring_start_cyc; + + stats->evtim_exp_count = + __atomic_load_n(&tim_ring->arm_cnt, __ATOMIC_RELAXED); + stats->ev_enq_count = stats->evtim_exp_count; + stats->adapter_tick_count = + rte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div); + return 0; +} + +static int +cnxk_tim_stats_reset(const struct rte_event_timer_adapter *adapter) +{ + struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv; + + __atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED); + return 0; +} + int cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, uint32_t *caps, @@ -258,6 +287,11 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, cnxk_tim_ops.uninit = cnxk_tim_ring_free; cnxk_tim_ops.get_info = cnxk_tim_ring_info_get; + if (dev->enable_stats) { + cnxk_tim_ops.stats_get = cnxk_tim_stats_get; + cnxk_tim_ops.stats_reset = cnxk_tim_stats_reset; + } + /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; @@ -281,6 +315,8 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) &dev->disable_npa); rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value, &dev->chunk_slots); + rte_kvargs_process(kvlist, CNXK_TIM_STATS_ENA, &parse_kvargs_flag, + &dev->enable_stats); rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value, &dev->min_ring_cnt); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 001f448d5..b5e4cfc9e 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -36,12 +36,14 @@ #define CNXK_TIM_DISABLE_NPA "tim_disable_npa" #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" +#define CNXK_TIM_STATS_ENA "tim_stats_ena" #define CNXK_TIM_RINGS_LMT "tim_rings_lmt" -#define CNXK_TIM_SP 0x1 -#define CNXK_TIM_MP 0x2 -#define CNXK_TIM_ENA_FB 0x10 -#define CNXK_TIM_ENA_DFB 0x20 +#define CNXK_TIM_SP 0x1 +#define CNXK_TIM_MP 0x2 +#define CNXK_TIM_ENA_FB 0x10 +#define CNXK_TIM_ENA_DFB 0x20 +#define CNXK_TIM_ENA_STATS 0x40 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48) #define TIM_BUCKET_W1_M_CHUNK_REMAINDER \ @@ -82,6 +84,7 @@ struct cnxk_tim_evdev { uint8_t disable_npa; uint16_t chunk_slots; uint16_t min_ring_cnt; + uint8_t enable_stats; }; enum cnxk_tim_clk_src { @@ -123,6 +126,7 @@ struct cnxk_tim_ring { struct rte_reciprocal_u64 fast_bkt; uint64_t arm_cnt; uint8_t prod_type_sp; + uint8_t enable_stats; uint8_t disable_npa; uint8_t ena_dfb; uint16_t ring_id; @@ -212,23 +216,33 @@ cnxk_tim_cntfrq(void) #endif #define TIM_ARM_FASTPATH_MODES \ - FP(sp, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ - FP(mp, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ - FP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ - FP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) + FP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ + FP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ + FP(fb_sp, 0, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ + FP(fb_mp, 0, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) \ + FP(stats_sp, 1, 0, 0, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ + FP(stats_mp, 1, 0, 1, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ + FP(stats_fb_sp, 1, 1, 0, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ + FP(stats_fb_mp, 1, 1, 1, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_MP) #define TIM_ARM_TMO_FASTPATH_MODES \ - FP(dfb, 0, CNXK_TIM_ENA_DFB) \ - FP(fb, 1, CNXK_TIM_ENA_FB) + FP(dfb, 0, 0, CNXK_TIM_ENA_DFB) \ + FP(fb, 0, 1, CNXK_TIM_ENA_FB) \ + FP(stats_dfb, 1, 0, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB) \ + FP(stats_fb, 1, 1, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB) -#define FP(_name, _f2, _f1, flags) \ +#define FP(_name, _f3, _f2, _f1, flags) \ uint16_t cnxk_tim_arm_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint16_t nb_timers); TIM_ARM_FASTPATH_MODES #undef FP -#define FP(_name, _f1, flags) \ +#define FP(_name, _f2, _f1, flags) \ uint16_t cnxk_tim_arm_tmo_tick_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint64_t timeout_tick, \ diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c index 98ff143c3..3ce99864a 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.c +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -86,10 +86,13 @@ cnxk_tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr, } } + if (flags & CNXK_TIM_ENA_STATS) + __atomic_fetch_add(&tim_ring->arm_cnt, index, __ATOMIC_RELAXED); + return index; } -#define FP(_name, _f2, _f1, _flags) \ +#define FP(_name, _f3, _f2, _f1, _flags) \ uint16_t __rte_noinline cnxk_tim_arm_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint16_t nb_timers) \ @@ -138,10 +141,14 @@ cnxk_tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, break; } + if (flags & CNXK_TIM_ENA_STATS) + __atomic_fetch_add(&tim_ring->arm_cnt, set_timers, + __ATOMIC_RELAXED); + return set_timers; } -#define FP(_name, _f1, _flags) \ +#define FP(_name, _f2, _f1, _flags) \ uint16_t __rte_noinline cnxk_tim_arm_tmo_tick_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint64_t timeout_tick, \ From patchwork Tue May 4 00:27:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92712 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5AA21A0562; Tue, 4 May 2021 02:31:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8166C411AB; Tue, 4 May 2021 02:29:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B3EFD4111F for ; Tue, 4 May 2021 02:29:38 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440QWtI026649 for ; Mon, 3 May 2021 17:29:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Ux8UPAEKVRmN/cl7dCFWVf7Kaar1hHC1ysMQsyst6ko=; b=J6GNb/NUXEPFNA+SHMiZc5UO8rhAs/QgzHYtFwbJYiOysVXsoT0RQC+jiBjFGuYpp+RP 5BtZt36O/WDfOa9Ci51/77RXdkrsVd1bjDoNkIXMzjCQZk9fMQHgUwtEICn4xqYhlhee UoGNQi7Ydb5/u+NABTh9LX8kOOxlvu6gj03XsiKfXnLQfDLinn7ts7qfvTEFGUnujTfm y6TasGdxz9iFDJalOImWPu6ewJ7alcJDufIluG4aZBSThvbLASpdA5aaDFbPV0ZjKka3 Ev/RUyRg8UDAFoQtQkIU5wH/qutc8Mn7/xTUw8T6TkidWPdwz2Oi2G6SaPYakLs2E8mL FQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnud-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:36 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 2D71B3F703F; Mon, 3 May 2021 17:29:34 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:24 +0530 Message-ID: <20210504002726.525-35-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 1LMWxft54NHC5DHwhhou8Ttd3Bau17pF X-Proofpoint-ORIG-GUID: 1LMWxft54NHC5DHwhhou8Ttd3Bau17pF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 34/35] event/cnxk: add timer adapter start and stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add event timer adapter start and stop functions. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.c | 71 ++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index a73ca33d8..19b71b4f5 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -246,6 +246,73 @@ cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr) return 0; } +static void +cnxk_tim_calibrate_start_tsc(struct cnxk_tim_ring *tim_ring) +{ +#define CNXK_TIM_CALIB_ITER 1E6 + uint32_t real_bkt, bucket; + int icount, ecount = 0; + uint64_t bkt_cyc; + + for (icount = 0; icount < CNXK_TIM_CALIB_ITER; icount++) { + real_bkt = plt_read64(tim_ring->base + TIM_LF_RING_REL) >> 44; + bkt_cyc = cnxk_tim_cntvct(); + bucket = (bkt_cyc - tim_ring->ring_start_cyc) / + tim_ring->tck_int; + bucket = bucket % (tim_ring->nb_bkts); + tim_ring->ring_start_cyc = + bkt_cyc - (real_bkt * tim_ring->tck_int); + if (bucket != real_bkt) + ecount++; + } + tim_ring->last_updt_cyc = bkt_cyc; + plt_tim_dbg("Bucket mispredict %3.2f distance %d\n", + 100 - (((double)(icount - ecount) / (double)icount) * 100), + bucket - real_bkt); +} + +static int +cnxk_tim_ring_start(const struct rte_event_timer_adapter *adptr) +{ + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + int rc; + + if (dev == NULL) + return -ENODEV; + + rc = roc_tim_lf_enable(&dev->tim, tim_ring->ring_id, + &tim_ring->ring_start_cyc, NULL); + if (rc < 0) + return rc; + + tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()); + tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts; + tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int); + tim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts); + + cnxk_tim_calibrate_start_tsc(tim_ring); + + return rc; +} + +static int +cnxk_tim_ring_stop(const struct rte_event_timer_adapter *adptr) +{ + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + int rc; + + if (dev == NULL) + return -ENODEV; + + rc = roc_tim_lf_disable(&dev->tim, tim_ring->ring_id); + if (rc < 0) + plt_err("Failed to disable timer ring"); + + return rc; +} + static int cnxk_tim_stats_get(const struct rte_event_timer_adapter *adapter, struct rte_event_timer_adapter_stats *stats) @@ -278,13 +345,14 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); RTE_SET_USED(flags); - RTE_SET_USED(ops); if (dev == NULL) return -ENODEV; cnxk_tim_ops.init = cnxk_tim_ring_create; cnxk_tim_ops.uninit = cnxk_tim_ring_free; + cnxk_tim_ops.start = cnxk_tim_ring_start; + cnxk_tim_ops.stop = cnxk_tim_ring_stop; cnxk_tim_ops.get_info = cnxk_tim_ring_info_get; if (dev->enable_stats) { @@ -295,6 +363,7 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + *ops = &cnxk_tim_ops; return 0; } From patchwork Tue May 4 00:27:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92713 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56084A0562; Tue, 4 May 2021 02:31:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D6C9641145; Tue, 4 May 2021 02:29:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id EBF76411AD for ; Tue, 4 May 2021 02:29:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGOS002337 for ; Mon, 3 May 2021 17:29:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=661q1jEiZ9bRBapYxo/qzhse9SfGNSn9QprRrofjJUM=; b=edvJQnR0MINGVa3xFIHQD5xKAv6grWhm7/OQiGlrpJVFcLHehZAJn9E3XlzCDcortG/h vCNk0ZBjrKZ8ISszBx7AZT1u8T22g+K8cpD4tUqAqIXd8DWoNmM8JxvJPKj+9NtIV+e+ KCnSi7f4BtpD2FQyD7eHpt3nDCNnwzdj1+qGa5iX7Jmcn/5ybyT2B05Uv/s+NuE6R6YY KPqnt0/KciF7GG3v5LhsZ9hixCilB9ocWV+zDlKApxchpmY6YXhaCCcuBRomqPSBeuMe V3iHakwcedf7yp1i2v6K9yUdp3RP08bee8sLupTqHA9Anfeo80tWAbz+T3LNsxR9w6JH LQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6qg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:41 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:38 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id D7FE13F703F; Mon, 3 May 2021 17:29:37 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:25 +0530 Message-ID: <20210504002726.525-36-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Rw63jrtV1GMljexHHM9d_D1XAeEKOc1q X-Proofpoint-ORIG-GUID: Rw63jrtV1GMljexHHM9d_D1XAeEKOc1q X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 35/35] event/cnxk: add devargs to control timer adapters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add devargs to control each event timer adapter i.e. TIM rings internal parameters uniquely. The following dict format is expected [ring-chnk_slots-disable_npa-stats_ena]. 0 represents default values. Example: --dev "0002:1e:00.0,tim_ring_ctl=[2-1023-1-0]" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 11 ++++ drivers/event/cnxk/cnxk_tim_evdev.c | 96 ++++++++++++++++++++++++++++- drivers/event/cnxk/cnxk_tim_evdev.h | 10 +++ 3 files changed, 116 insertions(+), 1 deletion(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index 11145dd7d..1bd935abc 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -135,6 +135,17 @@ Runtime Config Options -a 0002:0e:00.0,tim_rings_lmt=5 +- ``TIM ring control internal parameters`` + + When using multiple TIM rings the ``tim_ring_ctl`` devargs can be used to + control each TIM rings internal parameters uniquely. The following dict + format is expected [ring-chnk_slots-disable_npa-stats_ena]. 0 represents + default values. + + For Example:: + + -a 0002:0e:00.0,tim_ring_ctl=[2-1023-1-0] + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 19b71b4f5..9d40e336d 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -121,7 +121,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); struct cnxk_tim_ring *tim_ring; - int rc; + int i, rc; if (dev == NULL) return -ENODEV; @@ -165,6 +165,20 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->disable_npa = dev->disable_npa; tim_ring->enable_stats = dev->enable_stats; + for (i = 0; i < dev->ring_ctl_cnt; i++) { + struct cnxk_tim_ctl *ring_ctl = &dev->ring_ctl_data[i]; + + if (ring_ctl->ring == tim_ring->ring_id) { + tim_ring->chunk_sz = + ring_ctl->chunk_slots ? + ((uint32_t)(ring_ctl->chunk_slots + 1) * + CNXK_TIM_CHUNK_ALIGNMENT) : + tim_ring->chunk_sz; + tim_ring->enable_stats = ring_ctl->enable_stats; + tim_ring->disable_npa = ring_ctl->disable_npa; + } + } + if (tim_ring->disable_npa) { tim_ring->nb_chunks = tim_ring->nb_timers / @@ -368,6 +382,84 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, return 0; } +static void +cnxk_tim_parse_ring_param(char *value, void *opaque) +{ + struct cnxk_tim_evdev *dev = opaque; + struct cnxk_tim_ctl ring_ctl = {0}; + char *tok = strtok(value, "-"); + struct cnxk_tim_ctl *old_ptr; + uint16_t *val; + + val = (uint16_t *)&ring_ctl; + + if (!strlen(value)) + return; + + while (tok != NULL) { + *val = atoi(tok); + tok = strtok(NULL, "-"); + val++; + } + + if (val != (&ring_ctl.enable_stats + 1)) { + plt_err("Invalid ring param expected [ring-chunk_sz-disable_npa-enable_stats]"); + return; + } + + dev->ring_ctl_cnt++; + old_ptr = dev->ring_ctl_data; + dev->ring_ctl_data = + rte_realloc(dev->ring_ctl_data, + sizeof(struct cnxk_tim_ctl) * dev->ring_ctl_cnt, 0); + if (dev->ring_ctl_data == NULL) { + dev->ring_ctl_data = old_ptr; + dev->ring_ctl_cnt--; + return; + } + + dev->ring_ctl_data[dev->ring_ctl_cnt - 1] = ring_ctl; +} + +static void +cnxk_tim_parse_ring_ctl_list(const char *value, void *opaque) +{ + char *s = strdup(value); + char *start = NULL; + char *end = NULL; + char *f = s; + + while (*s) { + if (*s == '[') + start = s; + else if (*s == ']') + end = s; + + if (start && start < end) { + *end = 0; + cnxk_tim_parse_ring_param(start + 1, opaque); + start = end; + s = end; + } + s++; + } + + free(f); +} + +static int +cnxk_tim_parse_kvargs_dict(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + /* Dict format [ring-chunk_sz-disable_npa-enable_stats] use '-' as ',' + * isn't allowed. 0 represents default. + */ + cnxk_tim_parse_ring_ctl_list(value, opaque); + + return 0; +} + static void cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) { @@ -388,6 +480,8 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) &dev->enable_stats); rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value, &dev->min_ring_cnt); + rte_kvargs_process(kvlist, CNXK_TIM_RING_CTL, + &cnxk_tim_parse_kvargs_dict, &dev); rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index b5e4cfc9e..c369f6f47 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -38,6 +38,7 @@ #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" #define CNXK_TIM_STATS_ENA "tim_stats_ena" #define CNXK_TIM_RINGS_LMT "tim_rings_lmt" +#define CNXK_TIM_RING_CTL "tim_ring_ctl" #define CNXK_TIM_SP 0x1 #define CNXK_TIM_MP 0x2 @@ -75,6 +76,13 @@ #define TIM_BUCKET_SEMA_WLOCK \ (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK)) +struct cnxk_tim_ctl { + uint16_t ring; + uint16_t chunk_slots; + uint16_t disable_npa; + uint16_t enable_stats; +}; + struct cnxk_tim_evdev { struct roc_tim tim; struct rte_eventdev *event_dev; @@ -85,6 +93,8 @@ struct cnxk_tim_evdev { uint16_t chunk_slots; uint16_t min_ring_cnt; uint8_t enable_stats; + uint16_t ring_ctl_cnt; + struct cnxk_tim_ctl *ring_ctl_data; }; enum cnxk_tim_clk_src {