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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT015.mail.protection.outlook.com (10.13.172.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.32 via Frontend Transport; Thu, 29 Apr 2021 15:44:20 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:43:57 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:20 +0300 Message-ID: <20210429154335.2820028-2-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0d459129-85b5-41f1-e5b0-08d90b25a78a X-MS-TrafficTypeDiagnostic: CH2PR12MB3702: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:20.1089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d459129-85b5-41f1-e5b0-08d90b25a78a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3702 Subject: [dpdk-dev] [PATCH v2 01/16] common/mlx5: remove redundant spaces in header file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled File drivers/common/mlx5/mlx5_prm.h includes structs representing data items as defined in PRM document. Some of these structs were copied as-is from kernel file mlx5_ifc.h. As result the structs are not all aligned with the same spacing. This patch removes redundant spaces and new lines from several structs, to align all structs in mlx5_prm.h to the same format. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 334 +++++++++++++++------------------ 1 file changed, 155 insertions(+), 179 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index efa5ae67bf..da1510ac1e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -953,163 +953,139 @@ enum { /* Flow counters. */ struct mlx5_ifc_alloc_flow_counter_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - u8 syndrome[0x20]; - u8 flow_counter_id[0x20]; - u8 reserved_at_60[0x20]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 flow_counter_id[0x20]; + u8 reserved_at_60[0x20]; }; struct mlx5_ifc_alloc_flow_counter_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - u8 flow_counter_id[0x20]; - u8 reserved_at_40[0x18]; - u8 flow_counter_bulk[0x8]; + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 flow_counter_id[0x20]; + u8 reserved_at_40[0x18]; + u8 flow_counter_bulk[0x8]; }; struct mlx5_ifc_dealloc_flow_counter_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - u8 syndrome[0x20]; - u8 reserved_at_40[0x40]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; }; struct mlx5_ifc_dealloc_flow_counter_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - u8 flow_counter_id[0x20]; - u8 reserved_at_60[0x20]; + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 flow_counter_id[0x20]; + u8 reserved_at_60[0x20]; }; struct mlx5_ifc_traffic_counter_bits { - u8 packets[0x40]; - u8 octets[0x40]; + u8 packets[0x40]; + u8 octets[0x40]; }; struct mlx5_ifc_query_flow_counter_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - u8 syndrome[0x20]; - u8 reserved_at_40[0x40]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; struct mlx5_ifc_traffic_counter_bits flow_statistics[]; }; struct mlx5_ifc_query_flow_counter_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - u8 reserved_at_40[0x20]; - u8 mkey[0x20]; - u8 address[0x40]; - u8 clear[0x1]; - u8 dump_to_memory[0x1]; - u8 num_of_counters[0x1e]; - u8 flow_counter_id[0x20]; + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x20]; + u8 mkey[0x20]; + u8 address[0x40]; + u8 clear[0x1]; + u8 dump_to_memory[0x1]; + u8 num_of_counters[0x1e]; + u8 flow_counter_id[0x20]; }; #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u - struct mlx5_ifc_klm_bits { - u8 byte_count[0x20]; - u8 mkey[0x20]; - u8 address[0x40]; + u8 byte_count[0x20]; + u8 mkey[0x20]; + u8 address[0x40]; }; struct mlx5_ifc_mkc_bits { - u8 reserved_at_0[0x1]; - u8 free[0x1]; - u8 reserved_at_2[0x1]; - u8 access_mode_4_2[0x3]; - u8 reserved_at_6[0x7]; - u8 relaxed_ordering_write[0x1]; - u8 reserved_at_e[0x1]; - u8 small_fence_on_rdma_read_response[0x1]; - u8 umr_en[0x1]; - u8 a[0x1]; - u8 rw[0x1]; - u8 rr[0x1]; - u8 lw[0x1]; - u8 lr[0x1]; - u8 access_mode_1_0[0x2]; - u8 reserved_at_18[0x8]; - - u8 qpn[0x18]; - u8 mkey_7_0[0x8]; - - u8 reserved_at_40[0x20]; - - u8 length64[0x1]; - u8 bsf_en[0x1]; - u8 sync_umr[0x1]; - u8 reserved_at_63[0x2]; - u8 expected_sigerr_count[0x1]; - u8 reserved_at_66[0x1]; - u8 en_rinval[0x1]; - u8 pd[0x18]; - - u8 start_addr[0x40]; - - u8 len[0x40]; - - u8 bsf_octword_size[0x20]; - - u8 reserved_at_120[0x80]; - - u8 translations_octword_size[0x20]; - - u8 reserved_at_1c0[0x19]; - u8 relaxed_ordering_read[0x1]; - u8 reserved_at_1da[0x1]; - u8 log_page_size[0x5]; - - u8 reserved_at_1e0[0x20]; + u8 reserved_at_0[0x1]; + u8 free[0x1]; + u8 reserved_at_2[0x1]; + u8 access_mode_4_2[0x3]; + u8 reserved_at_6[0x7]; + u8 relaxed_ordering_write[0x1]; + u8 reserved_at_e[0x1]; + u8 small_fence_on_rdma_read_response[0x1]; + u8 umr_en[0x1]; + u8 a[0x1]; + u8 rw[0x1]; + u8 rr[0x1]; + u8 lw[0x1]; + u8 lr[0x1]; + u8 access_mode_1_0[0x2]; + u8 reserved_at_18[0x8]; + u8 qpn[0x18]; + u8 mkey_7_0[0x8]; + u8 reserved_at_40[0x20]; + u8 length64[0x1]; + u8 bsf_en[0x1]; + u8 sync_umr[0x1]; + u8 reserved_at_63[0x2]; + u8 expected_sigerr_count[0x1]; + u8 reserved_at_66[0x1]; + u8 en_rinval[0x1]; + u8 pd[0x18]; + u8 start_addr[0x40]; + u8 len[0x40]; + u8 bsf_octword_size[0x20]; + u8 reserved_at_120[0x80]; + u8 translations_octword_size[0x20]; + u8 reserved_at_1c0[0x19]; + u8 relaxed_ordering_read[0x1]; + u8 reserved_at_1da[0x1]; + u8 log_page_size[0x5]; + u8 reserved_at_1e0[0x20]; }; struct mlx5_ifc_create_mkey_out_bits { - u8 status[0x8]; - u8 reserved_at_8[0x18]; - - u8 syndrome[0x20]; - - u8 reserved_at_40[0x8]; - u8 mkey_index[0x18]; - - u8 reserved_at_60[0x20]; + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x8]; + u8 mkey_index[0x18]; + u8 reserved_at_60[0x20]; }; struct mlx5_ifc_create_mkey_in_bits { - u8 opcode[0x10]; - u8 reserved_at_10[0x10]; - - u8 reserved_at_20[0x10]; - u8 op_mod[0x10]; - - u8 reserved_at_40[0x20]; - - u8 pg_access[0x1]; - u8 reserved_at_61[0x1f]; - + u8 opcode[0x10]; + u8 reserved_at_10[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x20]; + u8 pg_access[0x1]; + u8 reserved_at_61[0x1f]; struct mlx5_ifc_mkc_bits memory_key_mkey_entry; - - u8 reserved_at_280[0x80]; - - u8 translations_octword_actual_size[0x20]; - - u8 mkey_umem_id[0x20]; - - u8 mkey_umem_offset[0x40]; - - u8 reserved_at_380[0x500]; - - u8 klm_pas_mtt[][0x20]; + u8 reserved_at_280[0x80]; + u8 translations_octword_actual_size[0x20]; + u8 mkey_umem_id[0x20]; + u8 mkey_umem_offset[0x40]; + u8 reserved_at_380[0x500]; + u8 klm_pas_mtt[][0x20]; }; enum { @@ -2272,27 +2248,27 @@ enum { }; struct mlx5_ifc_flow_meter_parameters_bits { - u8 valid[0x1]; // 00h - u8 bucket_overflow[0x1]; - u8 start_color[0x2]; - u8 both_buckets_on_green[0x1]; - u8 meter_mode[0x2]; - u8 reserved_at_1[0x19]; - u8 reserved_at_2[0x20]; //04h - u8 reserved_at_3[0x3]; - u8 cbs_exponent[0x5]; // 08h - u8 cbs_mantissa[0x8]; - u8 reserved_at_4[0x3]; - u8 cir_exponent[0x5]; - u8 cir_mantissa[0x8]; - u8 reserved_at_5[0x20]; // 0Ch - u8 reserved_at_6[0x3]; - u8 ebs_exponent[0x5]; // 10h - u8 ebs_mantissa[0x8]; - u8 reserved_at_7[0x3]; - u8 eir_exponent[0x5]; - u8 eir_mantissa[0x8]; - u8 reserved_at_8[0x60]; // 14h-1Ch + u8 valid[0x1]; + u8 bucket_overflow[0x1]; + u8 start_color[0x2]; + u8 both_buckets_on_green[0x1]; + u8 meter_mode[0x2]; + u8 reserved_at_1[0x19]; + u8 reserved_at_2[0x20]; + u8 reserved_at_3[0x3]; + u8 cbs_exponent[0x5]; + u8 cbs_mantissa[0x8]; + u8 reserved_at_4[0x3]; + u8 cir_exponent[0x5]; + u8 cir_mantissa[0x8]; + u8 reserved_at_5[0x20]; + u8 reserved_at_6[0x3]; + u8 ebs_exponent[0x5]; + u8 ebs_mantissa[0x8]; + u8 reserved_at_7[0x3]; + u8 eir_exponent[0x5]; + u8 eir_mantissa[0x8]; + u8 reserved_at_8[0x60]; }; #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 @@ -2359,46 +2335,46 @@ struct mlx5_ifc_cqc_bits { }; struct mlx5_ifc_health_buffer_bits { - u8 reserved_0[0x100]; - u8 assert_existptr[0x20]; - u8 assert_callra[0x20]; - u8 reserved_1[0x40]; - u8 fw_version[0x20]; - u8 hw_id[0x20]; - u8 reserved_2[0x20]; - u8 irisc_index[0x8]; - u8 synd[0x8]; - u8 ext_synd[0x10]; + u8 reserved_0[0x100]; + u8 assert_existptr[0x20]; + u8 assert_callra[0x20]; + u8 reserved_1[0x40]; + u8 fw_version[0x20]; + u8 hw_id[0x20]; + u8 reserved_2[0x20]; + u8 irisc_index[0x8]; + u8 synd[0x8]; + u8 ext_synd[0x10]; }; struct mlx5_ifc_initial_seg_bits { - u8 fw_rev_minor[0x10]; - u8 fw_rev_major[0x10]; - u8 cmd_interface_rev[0x10]; - u8 fw_rev_subminor[0x10]; - u8 reserved_0[0x40]; - u8 cmdq_phy_addr_63_32[0x20]; - u8 cmdq_phy_addr_31_12[0x14]; - u8 reserved_1[0x2]; - u8 nic_interface[0x2]; - u8 log_cmdq_size[0x4]; - u8 log_cmdq_stride[0x4]; - u8 command_doorbell_vector[0x20]; - u8 reserved_2[0xf00]; - u8 initializing[0x1]; - u8 nic_interface_supported[0x7]; - u8 reserved_4[0x18]; + u8 fw_rev_minor[0x10]; + u8 fw_rev_major[0x10]; + u8 cmd_interface_rev[0x10]; + u8 fw_rev_subminor[0x10]; + u8 reserved_0[0x40]; + u8 cmdq_phy_addr_63_32[0x20]; + u8 cmdq_phy_addr_31_12[0x14]; + u8 reserved_1[0x2]; + u8 nic_interface[0x2]; + u8 log_cmdq_size[0x4]; + u8 log_cmdq_stride[0x4]; + u8 command_doorbell_vector[0x20]; + u8 reserved_2[0xf00]; + u8 initializing[0x1]; + u8 nic_interface_supported[0x7]; + u8 reserved_4[0x18]; struct mlx5_ifc_health_buffer_bits health_buffer; - u8 no_dram_nic_offset[0x20]; - u8 reserved_5[0x6de0]; - u8 internal_timer_h[0x20]; - u8 internal_timer_l[0x20]; - u8 reserved_6[0x20]; - u8 reserved_7[0x1f]; - u8 clear_int[0x1]; - u8 health_syndrome[0x8]; - u8 health_counter[0x18]; - u8 reserved_8[0x17fc0]; + u8 no_dram_nic_offset[0x20]; + u8 reserved_5[0x6de0]; + u8 internal_timer_h[0x20]; + u8 internal_timer_l[0x20]; + u8 reserved_6[0x20]; + u8 reserved_7[0x1f]; + u8 clear_int[0x1]; + u8 health_syndrome[0x8]; + u8 health_counter[0x18]; + u8 reserved_8[0x17fc0]; }; struct mlx5_ifc_create_cq_out_bits { From patchwork Thu Apr 29 15:43:21 2021 Content-Type: text/plain; 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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT015.mail.protection.outlook.com (10.13.172.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.32 via Frontend Transport; Thu, 29 Apr 2021 15:44:21 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:03 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:21 +0300 Message-ID: <20210429154335.2820028-3-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7cc54ce-5555-441d-e6af-08d90b25a838 X-MS-TrafficTypeDiagnostic: BY5PR12MB4919: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:21.2463 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7cc54ce-5555-441d-e6af-08d90b25a838 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4919 Subject: [dpdk-dev] [PATCH v2 02/16] common/mlx5: update GENEVE TLV OPT obj name X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled Rename MLX5_OBJ_TYPE_GENEVE_TLV_OPT as MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT, to align with other general objects names. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 2 +- drivers/common/mlx5/mlx5_prm.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 79fff6457c..831175efc5 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -2265,7 +2265,7 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT); MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, - MLX5_OBJ_TYPE_GENEVE_TLV_OPT); + MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); MLX5_SET(geneve_tlv_option, opt, option_class, rte_be_to_cpu_16(class)); MLX5_SET(geneve_tlv_option, opt, option_type, type); diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index da1510ac1e..2e5e42f6e9 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1108,7 +1108,7 @@ enum { #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ - (1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT) + (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -2402,7 +2402,7 @@ struct mlx5_ifc_create_cq_in_bits { }; enum { - MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, + MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, From patchwork Thu Apr 29 15:43:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92418 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79884A0547; Thu, 29 Apr 2021 17:44:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 21F8441328; Thu, 29 Apr 2021 17:44:29 +0200 (CEST) Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam08on2077.outbound.protection.outlook.com [40.107.101.77]) by mails.dpdk.org (Postfix) with ESMTP id 375CA411E5 for ; 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Thu, 29 Apr 2021 15:44:22 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:08 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:22 +0300 Message-ID: <20210429154335.2820028-4-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9ac87f71-d9db-4903-8482-08d90b25a91b X-MS-TrafficTypeDiagnostic: DM6PR12MB4729: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1775; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Fzuo5jGP8Amhzdgdb/CxqyCsYTQUjF882y/b7thG25pUGcls5At+f/DMvTmwBO9PFI6lXrZfNAdnJQQkWlyj3P4Hz/5YZe0NWmxgOZMdNBhk/Cc7F97fWsc3SXU8rGH+HAnxBNbbotvKK+V75D/Dc0IU75GLSxlLfqiWl8VMBZC+GrUelIg2ANzChi2xvF0L0R9ZN7qaYTXIorPgy23duSC+SgK/X2LlxJFYPxMaGuI7zwG3KX5xgXxuJ0jRB1oiebF4gB9w5+jLUu+qD490d+GZLN0P4BDPnGh01gR1EICTgNvKnTV78BmhliLMere6cr9Ob26jlYbrQhYWJeDgGfhu+2R54rYgC6bSztCR1IHQWXMU7etIQCC/oBqNMQBYH4rq32HTTjXzkC9s4WzQuO8dyngQWS6a7PM6cw+umRX2SZ/n6dmi5zElE/FRL+1k5etuctfNxFVHBUwaRVeve3TdupJZ0xF9A5dP1qeEDCEI/oW+edF9R1RV6uct3rLSTD3CEgN99TfXu7MFLItbGbwj3o1xxQjeOM9GNTbpKju/X6laHFohYEmnG5QF4Q+MJh8cpZTWu4xbNpLZEQuiVPSWsfdZBh5ztX0cD0ReD2qro5DMXWl/9ELMM3rOKxEH30poiWHC5XTJgQ1fQXr7bwV13mtmR6ZsRtED/qYroa0= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(346002)(136003)(376002)(396003)(46966006)(36840700001)(6666004)(336012)(107886003)(82310400003)(82740400003)(426003)(6916009)(2906002)(26005)(36756003)(316002)(86362001)(47076005)(55016002)(6286002)(7696005)(356005)(36860700001)(36906005)(8676002)(5660300002)(54906003)(70206006)(1076003)(4326008)(2616005)(16526019)(186003)(478600001)(7636003)(83380400001)(8936002)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:22.7444 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ac87f71-d9db-4903-8482-08d90b25a91b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4729 Subject: [dpdk-dev] [PATCH v2 03/16] common/mlx5: optimize read of general obj type caps X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled General object types support is indicated in bitmap general_obj_types, which is part of HCA capabilities list. Currently this bitmap is read multiple times, and each time a different bit is extracted. This patch optimizes the code, reading the bitmap once into a local variable, and then extracting the required bits. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 831175efc5..a0bf0d3009 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -647,6 +647,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; void *hcattr; int status, syndrome, rc, i; + uint64_t general_obj_types_supported = 0; MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); MLX5_SET(query_hca_cap_in, in, op_mod, @@ -725,12 +726,22 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, regexp_num_of_engines); - attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & + /* Read the general_obj_types bitmap and extract the relevant bits. */ + general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, + general_obj_types); + attr->vdpa.valid = !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); + attr->vdpa.queue_counters_valid = + !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); + attr->parse_graph_flex_node = + !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); + attr->flow_hit_aso = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); - attr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); + attr->geneve_tlv_opt = !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); + /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); From patchwork Thu Apr 29 15:43:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92419 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3DFDCA0547; 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Thu, 29 Apr 2021 15:44:23 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:15 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:23 +0300 Message-ID: <20210429154335.2820028-5-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 50b678f2-7dde-4574-f4c4-08d90b25a9a0 X-MS-TrafficTypeDiagnostic: BYAPR12MB4982: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W0c0B5nPlhSRyObx9F/SRbU3eQTTQXb0Q/AralID7TTp7kjA9iCpNaeg50f3hS7WdN0TgRhbkJmi34MvQzVtADn3omSRb/xyD07Ly7vw0OaORELvktLOlPIsOQyelgqpcHpdUKZhq529CaBo5PNB+AQgpJY18nW6wjvMePd2HFEwx+F1Yze5La333aGZqIbRQRKID4JZa0SV/xmnzn3zS1j1Cc+AJXTupp+qWLy5IpedrwHjDxu8E7GqFh5djpU2tfu6u0MGydXMCwkHTh82ZsnRYu/V/TBDbTRVLxtDktAbnhYjUy/yc37/QCaE2HhxXEc42V7/GPzBQ1RsJnS88X6UC+2nAm3MP8yOrBPHnvpW27GRauHMWC0eGGkszjdiyCQxB4G+HdCb8SoeM8oL9ZN3gMvePchrbFlfzNze/esIIKbAkhQnBAO6P8AhJ6yKIcLnWZLxT9qVb42uEbwOAZPW5Vuzlb+YZhmEztRea5rY29DCQCy/DizmyooB/QMCpgVQU/6YizlY/60BE0K1fA8Ubh9QEKoYhS1OwQTpMLI6F8InURDetFDmpM+zkvec4p1bgFSjDzaDh+1eeDbDTqhxk8SRgzkpj8rKzRvnE+NNqsIsPrbyd7ajaDhByaux8AvO+rpbG2EqP9LdZWPmwjLwgHmghywUVJGF+Wuc+KU= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(346002)(396003)(39860400002)(376002)(36840700001)(46966006)(426003)(1076003)(70586007)(4326008)(54906003)(16526019)(356005)(83380400001)(107886003)(2906002)(6916009)(36756003)(70206006)(7696005)(8676002)(86362001)(47076005)(7636003)(8936002)(36906005)(2616005)(82310400003)(316002)(186003)(478600001)(6286002)(36860700001)(5660300002)(336012)(55016002)(6666004)(82740400003)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:23.6179 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50b678f2-7dde-4574-f4c4-08d90b25a9a0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB4982 Subject: [dpdk-dev] [PATCH v2 04/16] common/mlx5: add HCA cap for AES-XTS crypto X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled Update the PRM structure and HCA capabilities reading, to include relevant capabilities for AES-XTS crypto. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 5 ++++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index a0bf0d3009..7ca767944e 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -771,6 +771,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); attr->umr_modify_entity_size_disabled = MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); + attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); + if (attr->crypto) + attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 870bdb6b30..28ade5bbc4 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -137,6 +137,8 @@ struct mlx5_hca_attr { uint32_t qp_ts_format:2; uint32_t regex:1; uint32_t reg_c_preserve:1; + uint32_t crypto:1; /* Crypto engine is supported. */ + uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; uint32_t geneve_tlv_opt; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2e5e42f6e9..a8fbfbb0f5 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1427,7 +1427,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 sq_ts_format[0x2]; u8 rq_ts_format[0x2]; u8 reserved_at_444[0x1C]; - u8 reserved_at_460[0x10]; + u8 reserved_at_460[0x8]; + u8 aes_xts[0x1]; + u8 crypto[0x1]; + u8 reserved_at_46a[0x6]; u8 max_num_eqs[0x10]; u8 reserved_at_480[0x3]; u8 log_max_l2_table[0x5]; From patchwork Thu Apr 29 15:43:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92421 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C66D0A0547; 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Thu, 29 Apr 2021 15:44:30 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:22 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:24 +0300 Message-ID: <20210429154335.2820028-6-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3a6122a1-9493-436b-cf35-08d90b25adfe X-MS-TrafficTypeDiagnostic: MWHPR12MB1214: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: afpZ7VB1O9mT9WWjdEPL+r4TOCuEG6ogPGPZkNh0uBWAVfafW2GrdPAgMcA33zg+slWM7Ax+D7w1mHpHvBeCzewUMzeXq065iCEQXhFkbz/wGpSo07iSes8nxsP9dIf1M/q0qTBq8q7Q9ac/szP9GM8qaAKixgscsmh6Q/2BTNeo3MAMJWAobse4DeLpUBqLy8DpFoR8KpQ1QHEvIX7vsm89vgdTkUX5h2Zoyd9CzhVlS+9OoFuuVn482K71fxoNJMEwUT2a7FRzXk+TDVyLhXzV5cw9jzkvCUPQPKPFRdya3fwltEFLSMK5XRA9ANFRg78uNLZqx96xVKyZG1jsA910jtocSoVsI6PWoR8JaaflGhQHCPz4TQUAlzZo8rC8NqSgKQsH/vHrkUYzXyiag6aRdshVXtO+fZ2WObYMibz3Q7tnhXU2o0yNXnKfF6f6pBjOMku/jSaAlJs5HpG+QlRlCmChEcA+g4bz7GSkEh/q2B7eTZx2eU7iiboYMvCLJrQ86YJaJgBafsRxJ4WudWxRFwIfSL0Cv/otExhTtOi16h0A/dDrp5pNRd+DRiBp8XGIaoOhQWX8K47GycYRBYqN34kb73YbDtGK0HItw1j+ud7uSKOn6xJligbB/Npa18bCiIhC60aCRxjqNIhwQg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(346002)(39860400002)(136003)(376002)(36840700001)(46966006)(6916009)(82740400003)(86362001)(8676002)(36860700001)(8936002)(54906003)(316002)(70586007)(5660300002)(2906002)(107886003)(70206006)(4326008)(426003)(336012)(1076003)(356005)(6286002)(36906005)(2616005)(186003)(16526019)(47076005)(82310400003)(478600001)(36756003)(55016002)(26005)(7636003)(7696005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:30.9379 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a6122a1-9493-436b-cf35-08d90b25adfe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1214 Subject: [dpdk-dev] [PATCH v2 05/16] common/mlx5: support general object DEK create op X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled Data Encryption Keys (DEKs) are the keys used for data encryption/decryption operations. Add reading of DEK support capability. Add function to create general object type DEK, using DevX API. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 53 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 17 +++++++++ drivers/common/mlx5/mlx5_prm.h | 39 ++++++++++++++++++++ drivers/common/mlx5/version.map | 1 + 4 files changed, 110 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 7ca767944e..742c82cca4 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -741,6 +741,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); attr->geneve_tlv_opt = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); + attr->dek = !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_DEK); /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); @@ -2397,3 +2399,54 @@ mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); return 0; } + +/** + * Create general object of type DEK using DevX API. + * + * @param[in] ctx + * Context returned from mlx5 open_device() glue function. + * @param [in] attr + * Pointer to DEK attributes structure. + * + * @return + * The DevX object created, NULL otherwise and rte_errno is set. + */ +struct mlx5_devx_obj * +mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) +{ + uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; + uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; + struct mlx5_devx_obj *dek_obj = NULL; + void *ptr = NULL, *key_addr = NULL; + + dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), + 0, SOCKET_ID_ANY); + if (dek_obj == NULL) { + DRV_LOG(ERR, "Failed to allocate DEK object data"); + rte_errno = ENOMEM; + return NULL; + } + ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); + MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, + MLX5_GENERAL_OBJ_TYPE_DEK); + ptr = MLX5_ADDR_OF(create_dek_in, in, dek); + MLX5_SET(dek, ptr, key_size, attr->key_size); + MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); + MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); + MLX5_SET(dek, ptr, pd, attr->pd); + MLX5_SET64(dek, ptr, opaque, attr->opaque); + key_addr = MLX5_ADDR_OF(dek, ptr, key); + memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); + dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), + out, sizeof(out)); + if (dek_obj->obj == NULL) { + rte_errno = errno; + DRV_LOG(ERR, "Failed to create DEK obj using DevX."); + mlx5_free(dek_obj); + return NULL; + } + dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + return dek_obj; +} diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 28ade5bbc4..b9ff7ab87d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -139,6 +139,7 @@ struct mlx5_hca_attr { uint32_t reg_c_preserve:1; uint32_t crypto:1; /* Crypto engine is supported. */ uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ + uint32_t dek:1; /* General obj type DEK is supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; uint32_t geneve_tlv_opt; @@ -435,6 +436,18 @@ struct mlx5_devx_graph_node_attr { struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; }; +/* Encryption key size is up to 1024 bit, 128 bytes. */ +#define MLX5_CRYPTO_KEY_MAX_SIZE 128 + +struct mlx5_devx_dek_attr { + uint32_t key_size:4; + uint32_t has_keytag:1; + uint32_t key_purpose:4; + uint32_t pd:24; + uint64_t opaque; + uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; +}; + /* mlx5_devx_cmds.c */ __rte_internal @@ -587,4 +600,8 @@ int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, __rte_internal struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, uint32_t log_obj_size); +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); + #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index a8fbfbb0f5..bc9f58ad03 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1109,6 +1109,8 @@ enum { (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) +#define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -2406,6 +2408,7 @@ struct mlx5_ifc_create_cq_in_bits { enum { MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, + MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, @@ -2469,6 +2472,42 @@ struct mlx5_ifc_create_geneve_tlv_option_in_bits { struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; }; +enum { + MLX5_CRYPTO_KEY_SIZE_128b = 0x0, + MLX5_CRYPTO_KEY_SIZE_256b = 0x1, +}; + +enum { + MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, + MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, + MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, + MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, + MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, + MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, +}; + +struct mlx5_ifc_dek_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0xc]; + u8 key_size[0x4]; + u8 has_keytag[0x1]; + u8 reserved_at_59[0x3]; + u8 key_purpose[0x4]; + u8 reserved_at_60[0x8]; + u8 pd[0x18]; + u8 reserved_at_80[0x100]; + u8 opaque[0x40]; + u8 reserved_at_1c0[0x40]; + u8 key[0x400]; + u8 reserved_at_600[0x200]; +}; + +struct mlx5_ifc_create_dek_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_dek_bits dek; +}; + enum { MLX5_VIRTQ_STATE_INIT = 0, MLX5_VIRTQ_STATE_RDY = 1, diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 18dc96276d..2976edce0b 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -27,6 +27,7 @@ INTERNAL { mlx5_devx_cmd_create_flow_hit_aso_obj; mlx5_devx_cmd_create_flow_meter_aso_obj; mlx5_devx_cmd_create_geneve_tlv_option; + mlx5_devx_cmd_create_dek_obj; mlx5_devx_cmd_destroy; mlx5_devx_cmd_flow_counter_alloc; mlx5_devx_cmd_flow_counter_query; From patchwork Thu Apr 29 15:43:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92420 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0D3AA0547; Thu, 29 Apr 2021 17:44:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CAB004123F; Thu, 29 Apr 2021 17:44:42 +0200 (CEST) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-eopbgr770052.outbound.protection.outlook.com [40.107.77.52]) by mails.dpdk.org (Postfix) with ESMTP id AD6CD411E5 for ; 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Thu, 29 Apr 2021 15:44:32 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:29 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:25 +0300 Message-ID: <20210429154335.2820028-7-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ae591d2a-7584-4c0b-d4cd-08d90b25af09 X-MS-TrafficTypeDiagnostic: MN2PR12MB4831: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mRoI8Fu3xy7hHBY3EiRyu47bkbuGGvqwMXEtnftmraKibAc1kpQR7WViti7QRCFiFR/gLR9KrZaVti2v7MpAIBYlZqfYiVFPjk/J5lCTmoe/YXlxcEL0QuAjF4xXe9EI6KEoHrfzDUDyNsS++/LtmvHlupqxYODp/njs7hP/sKjTV+kxygNf3LXD81bUm1VcCpsP41LdboYoTApACRS/WhBGqNHyUbq5TfPPhSA0neLf4ATBTPhOMTO7Zrdzgc4pmwrWZp2Ei4Zf/wtQRXEqugtgVlhvi33hpy55iKLJns3GIIwdbUCPwgDRWR3+ilBqpk+mqsCxqMJAoUrkw02kfr2LqE81llWaBLd628Ui1GYinrew/4xi9izi0Hs9AUImoTC/nVWzB6/t9HlFDxydgOTfdth034+yWJSIPa151awYIr2el2RILPyzLMyuoT2Kf6KPheue9btdE3J9RndvzD9qGpdy56Hp6jV4XxKCMkJpDGyDuHo+DdKq4mmHn8/bOYGzjOGVMbyoZ6k5vYLbBklx+ftDW4q0ZfC0SASmCWXpZ8Jm/O4AeiGnUM/2A2Uyfe/7ZWhocb5WHHKhkm/yoV8nB9+Q1UKg+jI1pDpDnr2Ji6hQHbevNkgYONqAk8nq1ntPCpttFdlxlEWgQZespAQUKCajZ8q+SCmQg6PJ+VE= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(396003)(376002)(39860400002)(346002)(36840700001)(46966006)(107886003)(83380400001)(478600001)(6666004)(47076005)(16526019)(36756003)(36860700001)(6286002)(4326008)(2906002)(426003)(82310400003)(5660300002)(86362001)(70586007)(70206006)(2616005)(186003)(7636003)(82740400003)(8936002)(8676002)(36906005)(54906003)(336012)(7696005)(356005)(316002)(55016002)(6916009)(1076003)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:32.7009 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae591d2a-7584-4c0b-d4cd-08d90b25af09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4831 Subject: [dpdk-dev] [PATCH v2 06/16] common/mlx5: adjust DevX MKEY fields for crypto X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled MKEY that will be used for crypto purposes must be created with crypto_en and remote access attributes. This patch adds support for them in the DevX MKEY context. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 10 +++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 742c82cca4..68a10b149a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -263,6 +263,10 @@ mlx5_devx_cmd_mkey_create(void *ctx, MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); MLX5_SET(mkc, mkc, lw, 0x1); MLX5_SET(mkc, mkc, lr, 0x1); + if (attr->set_remote_rw) { + MLX5_SET(mkc, mkc, rw, 0x1); + MLX5_SET(mkc, mkc, rr, 0x1); + } MLX5_SET(mkc, mkc, qpn, 0xffffff); MLX5_SET(mkc, mkc, pd, attr->pd); MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); @@ -273,6 +277,7 @@ mlx5_devx_cmd_mkey_create(void *ctx, MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); MLX5_SET64(mkc, mkc, start_addr, attr->addr); MLX5_SET64(mkc, mkc, len, attr->size); + MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, sizeof(out)); if (!mkey->obj) { diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index b9ff7ab87d..600577f18a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -32,6 +32,8 @@ struct mlx5_devx_mkey_attr { uint32_t relaxed_ordering_write:1; uint32_t relaxed_ordering_read:1; uint32_t umr_en:1; + uint32_t crypto_en:2; + uint32_t set_remote_rw:1; struct mlx5_klm *klm_array; int klm_num; }; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index bc9f58ad03..25f6f8ff00 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1059,7 +1059,15 @@ struct mlx5_ifc_mkc_bits { u8 relaxed_ordering_read[0x1]; u8 reserved_at_1da[0x1]; u8 log_page_size[0x5]; - u8 reserved_at_1e0[0x20]; + u8 reserved_at_1e0[0x3]; + u8 crypto_en[0x2]; + u8 reserved_at_1e5[0x1b]; +}; + +/* Range of values for MKEY context crypto_en field. */ +enum { + MLX5_MKEY_CRYPTO_DISABLED = 0x0, + MLX5_MKEY_CRYPTO_ENABLED = 0x1, }; struct mlx5_ifc_create_mkey_out_bits { From patchwork Thu Apr 29 15:43:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92422 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30E86A0547; Thu, 29 Apr 2021 17:45:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 791EC4132A; Thu, 29 Apr 2021 17:44:51 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2067.outbound.protection.outlook.com [40.107.94.67]) by mails.dpdk.org (Postfix) with ESMTP id A2718411E5 for ; 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Thu, 29 Apr 2021 15:44:41 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:39 +0000 From: Matan Azrad To: CC: , , Date: Thu, 29 Apr 2021 18:43:26 +0300 Message-ID: <20210429154335.2820028-8-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c219d753-4bd0-44f3-561d-08d90b25b475 X-MS-TrafficTypeDiagnostic: CY4PR12MB1703: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:216; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2cG3Rda0rz3v6bsoZaqZYJ81vavJbyAu0Oa1QVsPmkRwjyZXVowFeH7S56w6h8J364LpnPx/OjcaPe8bcQVhRUd9lKQ6SygNmO14WR7VjWy3rQ13e0XNfi2Hq2EyP4gUQ91hDpca9CQABll2VgOyuJ2/l/kj1uVAjsBC8xhaxPxdVperVjWhNbi3f808vw2vol+qsLzcVjWBJqcJVWH7Dor5+Ptnea65yXDqcB6BpESU30IK549H4lJN6paj2CjIVqMOzTfH765ZoCZ5ONhyEKxXFNRc8E62UYFRyIfGqkX2ulwgSOMM8Gp8qpJN0sOwEIBZaxCQjwdQf4RyQGCWdTdpZ5ZSO+dgGTOKwLHEXiBsTGX287mdlvJCg2p4TSwPHFH9Py5kLQ/rHe/rgXC/FU9OUEd8MX5BGb52pr4s9+pux/UusDm4McuQD6NZDCRsVBFwqnX9yYG6DBnPey0MK99S/ofLwU2LWo8VZra3xiY6xW6cmjEqOTC6ZFInCRJ8PWQ52wVnpOzQ//7GlDXrtIBuU3kUWu9undKoikOU7Ex18Mw+DCqH9yKAQubDAHjiECMkFkeUnsDffheczY9baL2QaEShIpv4eA9nxKr0HerYgfbYFM/z4A1JeaxMdLbQJRNhcZ49gAhKqPsCYF+6exzHM8cR64/RpuArMge9zbs= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(346002)(39860400002)(396003)(136003)(46966006)(36840700001)(82310400003)(55016002)(70586007)(426003)(316002)(6916009)(8936002)(82740400003)(4744005)(4326008)(356005)(107886003)(2616005)(36860700001)(16526019)(186003)(8676002)(6286002)(336012)(1076003)(26005)(478600001)(86362001)(6666004)(47076005)(5660300002)(54906003)(7696005)(36906005)(36756003)(2906002)(70206006)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:41.7750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c219d753-4bd0-44f3-561d-08d90b25b475 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1703 Subject: [dpdk-dev] [PATCH v2 07/16] common/mlx5: fix cypto bsf attr X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Suanming Mou This commit should be squash to crypto en commit. Signed-off-by: Suanming Mou --- drivers/common/mlx5/mlx5_devx_cmds.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 68a10b149a..7e3c8b55fa 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -278,6 +278,10 @@ mlx5_devx_cmd_mkey_create(void *ctx, MLX5_SET64(mkc, mkc, start_addr, attr->addr); MLX5_SET64(mkc, mkc, len, attr->size); MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); + if (attr->crypto_en) { + MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); + MLX5_SET(mkc, mkc, bsf_octword_size, 4); + } mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, sizeof(out)); if (!mkey->obj) { From patchwork Thu Apr 29 15:43:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92423 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C58CA0547; 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Thu, 29 Apr 2021 15:44:47 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:45 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:27 +0300 Message-ID: <20210429154335.2820028-9-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f5b248b6-2cb1-4b9d-783f-08d90b25b804 X-MS-TrafficTypeDiagnostic: BYAPR12MB2919: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PDuTkpsjEphsfWzpuaZfCXd/V2YPt0h0+oIF9ICLcWYu3c1xU83M2uoUlqjNQS8umfH+OYyHMP5SsoFljzsDDYQol/sOTCvR5CYO+XFbXQ10iZFzg7EtjGC17kPBt0meKur7K2ytoDcy0hKgNWGjK09VvDihLb5XcVWoNAhSp6eSdoRlaGV6g49LQN+1wN2HmQP421MmI6QoP1xK4MQ+Xa70L2Racn+VdoW40gBKgM7N9RL7NrVc9lYJdhCoPUt/4H4u+QSBSa8WN7Iw8z5VlgLmi025/Lo86ap1aDRRKaITKV8j4TkbkCvJl+9OLsIMamdHR2O3sSBbT04BET62cK5n13PRafdHtvJqvQyj6jhjE9lYbeR4D8zth5NrQXxr4us8Rz359wUoET7jfOE0Xou6LB6AbJb0x1JMZNKCojg9u34agxMFKCKJpv/ml+WN6noeJyL0ikv3TEQmikDUc2nMe0xgw31FgI3fbkwKPKQyw5gVIiscNFLSM8K3w5i+GtUmmYO80F2i7enMXd2eDvTMYLjh+7+Gor5lRWi60NlLO7KVVIzIjOx0GYRJGJi9qC06P3eeU62yctzuRR7sYohWspil2Ks5PGLaLW7p3MT8cVCpPbbgILjLFYDvBz+OV7VrBa3MdZWsSNyKOpvn5gFiLcCwC8DCX2QMZUeZj7g= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(396003)(346002)(376002)(136003)(36840700001)(46966006)(2906002)(8936002)(82310400003)(7696005)(4326008)(478600001)(6916009)(8676002)(7636003)(1076003)(54906003)(36906005)(82740400003)(356005)(36756003)(2616005)(6286002)(186003)(316002)(16526019)(70206006)(426003)(70586007)(26005)(336012)(107886003)(6666004)(47076005)(83380400001)(36860700001)(5660300002)(86362001)(55016002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:47.7432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5b248b6-2cb1-4b9d-783f-08d90b25b804 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2919 Subject: [dpdk-dev] [PATCH v2 08/16] common/mlx5: support general obj IMPORT KEK create X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled IMPORT_KEK object is used to wrap (encrypt) critical security parameters, such as other keys and credentials, when those need to be passed between the device and the software. This patch add support of IMPORT_KEK object create operation. Add reading of IMPORT_KEK support capability. Add function to create general object type IMPORT_KEK, using DevX API. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 50 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 13 ++++++++ drivers/common/mlx5/mlx5_prm.h | 18 ++++++++++ drivers/common/mlx5/version.map | 1 + 4 files changed, 82 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 7e3c8b55fa..afef7a5f63 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -752,6 +752,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); attr->dek = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_DEK); + attr->import_kek = !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); @@ -2459,3 +2461,51 @@ mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); return dek_obj; } + +/** + * Create general object of type IMPORT_KEK using DevX API. + * + * @param[in] ctx + * Context returned from mlx5 open_device() glue function. + * @param [in] attr + * Pointer to IMPORT_KEK attributes structure. + * + * @return + * The DevX object created, NULL otherwise and rte_errno is set. + */ +struct mlx5_devx_obj * +mlx5_devx_cmd_create_import_kek_obj(void *ctx, + struct mlx5_devx_import_kek_attr *attr) +{ + uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; + uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; + struct mlx5_devx_obj *import_kek_obj = NULL; + void *ptr = NULL, *key_addr = NULL; + + import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), + 0, SOCKET_ID_ANY); + if (import_kek_obj == NULL) { + DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); + rte_errno = ENOMEM; + return NULL; + } + ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); + MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, + MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); + ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); + MLX5_SET(import_kek, ptr, key_size, attr->key_size); + key_addr = MLX5_ADDR_OF(import_kek, ptr, key); + memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); + import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), + out, sizeof(out)); + if (import_kek_obj->obj == NULL) { + rte_errno = errno; + DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); + mlx5_free(import_kek_obj); + return NULL; + } + import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + return import_kek_obj; +} diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 600577f18a..6423610dae 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -142,6 +142,7 @@ struct mlx5_hca_attr { uint32_t crypto:1; /* Crypto engine is supported. */ uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ uint32_t dek:1; /* General obj type DEK is supported. */ + uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; uint32_t geneve_tlv_opt; @@ -450,6 +451,13 @@ struct mlx5_devx_dek_attr { uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; }; +struct mlx5_devx_import_kek_attr { + uint64_t modify_field_select; + uint32_t state:8; + uint32_t key_size:4; + uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; +}; + /* mlx5_devx_cmds.c */ __rte_internal @@ -606,4 +614,9 @@ __rte_internal struct mlx5_devx_obj * mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_import_kek_obj(void *ctx, + struct mlx5_devx_import_kek_attr *attr); + #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 25f6f8ff00..bc339566a6 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1119,6 +1119,8 @@ enum { (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) +#define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -2419,6 +2421,7 @@ enum { MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, + MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, @@ -2516,6 +2519,21 @@ struct mlx5_ifc_create_dek_in_bits { struct mlx5_ifc_dek_bits dek; }; +struct mlx5_ifc_import_kek_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0xc]; + u8 key_size[0x4]; + u8 reserved_at_58[0x1a8]; + u8 key[0x400]; + u8 reserved_at_600[0x200]; +}; + +struct mlx5_ifc_create_import_kek_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_import_kek_bits import_kek; +}; + enum { MLX5_VIRTQ_STATE_INIT = 0, MLX5_VIRTQ_STATE_RDY = 1, diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 2976edce0b..56a1b77b0a 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -28,6 +28,7 @@ INTERNAL { mlx5_devx_cmd_create_flow_meter_aso_obj; mlx5_devx_cmd_create_geneve_tlv_option; mlx5_devx_cmd_create_dek_obj; + mlx5_devx_cmd_create_import_kek_obj; mlx5_devx_cmd_destroy; mlx5_devx_cmd_flow_counter_alloc; mlx5_devx_cmd_flow_counter_query; From patchwork Thu Apr 29 15:43:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92424 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCEC4A0547; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(39860400002)(376002)(346002)(136003)(36840700001)(46966006)(107886003)(7696005)(6916009)(7636003)(82310400003)(5660300002)(55016002)(36906005)(1076003)(6286002)(47076005)(26005)(186003)(8936002)(70586007)(4326008)(426003)(16526019)(86362001)(36860700001)(70206006)(83380400001)(336012)(6666004)(2906002)(36756003)(478600001)(82740400003)(2616005)(8676002)(316002)(356005)(54906003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:51.7750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4d83c71-b3bc-4dff-029d-08d90b25ba68 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4100 Subject: [dpdk-dev] [PATCH v2 09/16] common/mlx5: support general obj CRYPTO LOGIN create X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled CRYPTO_LOGIN Object is used to login to the device as crypto user or crypto officer. Required in order to perform any crypto related control operations. This patch adds support of CRYPTO_LOGIN object create operation. Add reading of CRYPTO_LOGIN support capability. Add function to create general object type CRYPTO_LOGIN, using DevX API. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 54 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 15 ++++++++ drivers/common/mlx5/mlx5_prm.h | 19 ++++++++++ drivers/common/mlx5/version.map | 1 + 4 files changed, 89 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index afef7a5f63..5e082ebb78 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -754,6 +754,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GENERAL_OBJ_TYPES_CAP_DEK); attr->import_kek = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); + attr->crypto_login = !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); @@ -2509,3 +2511,55 @@ mlx5_devx_cmd_create_import_kek_obj(void *ctx, import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); return import_kek_obj; } + +/** + * Create general object of type CRYPTO_LOGIN using DevX API. + * + * @param[in] ctx + * Context returned from mlx5 open_device() glue function. + * @param [in] attr + * Pointer to CRYPTO_LOGIN attributes structure. + * + * @return + * The DevX object created, NULL otherwise and rte_errno is set. + */ +struct mlx5_devx_obj * +mlx5_devx_cmd_create_crypto_login_obj(void *ctx, + struct mlx5_devx_crypto_login_attr *attr) +{ + uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; + uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; + struct mlx5_devx_obj *crypto_login_obj = NULL; + void *ptr = NULL, *credential_addr = NULL; + + crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), + 0, SOCKET_ID_ANY); + if (crypto_login_obj == NULL) { + DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); + rte_errno = ENOMEM; + return NULL; + } + ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); + MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, + MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); + ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); + MLX5_SET(crypto_login, ptr, credential_pointer, + attr->credential_pointer); + MLX5_SET(crypto_login, ptr, session_import_kek_ptr, + attr->session_import_kek_ptr); + credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); + memcpy(credential_addr, (void *)(attr->credential), + MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE); + crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), + out, sizeof(out)); + if (crypto_login_obj->obj == NULL) { + rte_errno = errno; + DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); + mlx5_free(crypto_login_obj); + return NULL; + } + crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + return crypto_login_obj; +} diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 6423610dae..709e28bfba 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -143,6 +143,7 @@ struct mlx5_hca_attr { uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ uint32_t dek:1; /* General obj type DEK is supported. */ uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ + uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; uint32_t geneve_tlv_opt; @@ -458,6 +459,15 @@ struct mlx5_devx_import_kek_attr { uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; }; +#define MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE 48 + +struct mlx5_devx_crypto_login_attr { + uint64_t modify_field_select; + uint32_t credential_pointer:24; + uint32_t session_import_kek_ptr:24; + uint8_t credential[MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE]; +}; + /* mlx5_devx_cmds.c */ __rte_internal @@ -619,4 +629,9 @@ struct mlx5_devx_obj * mlx5_devx_cmd_create_import_kek_obj(void *ctx, struct mlx5_devx_import_kek_attr *attr); +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_crypto_login_obj(void *ctx, + struct mlx5_devx_crypto_login_attr *attr); + #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index bc339566a6..a2437faec0 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1121,6 +1121,8 @@ enum { (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -2422,6 +2424,7 @@ enum { MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, + MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, @@ -2534,6 +2537,22 @@ struct mlx5_ifc_create_import_kek_in_bits { struct mlx5_ifc_import_kek_bits import_kek; }; +struct mlx5_ifc_crypto_login_bits { + u8 modify_field_select[0x40]; + u8 reserved_at_40[0x48]; + u8 credential_pointer[0x18]; + u8 reserved_at_a0[0x8]; + u8 session_import_kek_ptr[0x18]; + u8 reserved_at_c0[0x140]; + u8 credential[0x180]; + u8 reserved_at_380[0x480]; +}; + +struct mlx5_ifc_create_crypto_login_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_crypto_login_bits crypto_login; +}; + enum { MLX5_VIRTQ_STATE_INIT = 0, MLX5_VIRTQ_STATE_RDY = 1, diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 56a1b77b0a..bbef436fde 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -29,6 +29,7 @@ INTERNAL { mlx5_devx_cmd_create_geneve_tlv_option; mlx5_devx_cmd_create_dek_obj; mlx5_devx_cmd_create_import_kek_obj; + mlx5_devx_cmd_create_crypto_login_obj; mlx5_devx_cmd_destroy; mlx5_devx_cmd_flow_counter_alloc; mlx5_devx_cmd_flow_counter_query; From patchwork Thu Apr 29 15:43:29 2021 Content-Type: text/plain; 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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT015.mail.protection.outlook.com (10.13.172.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.32 via Frontend Transport; Thu, 29 Apr 2021 15:44:54 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:52 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:29 +0300 Message-ID: <20210429154335.2820028-11-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 000d64c9-0a8c-49fc-6744-08d90b25bc22 X-MS-TrafficTypeDiagnostic: CH0PR12MB5388: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2043; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:54.6583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 000d64c9-0a8c-49fc-6744-08d90b25bc22 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5388 Subject: [dpdk-dev] [PATCH v2 10/16] common/mlx5: add crypto BSF struct and defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled This patch adds the struct defining crypto BSF segment of UMR WQE, and the related value definitions and offsets. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index a2437faec0..a9dcbfa63c 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1096,6 +1096,72 @@ struct mlx5_ifc_create_mkey_in_bits { u8 klm_pas_mtt[][0x20]; }; +enum { + MLX5_BSF_SIZE_16B = 0x0, + MLX5_BSF_SIZE_32B = 0x1, + MLX5_BSF_SIZE_64B = 0x2, + MLX5_BSF_SIZE_128B = 0x3, +}; + +enum { + MLX5_BSF_P_TYPE_SIGNATURE = 0x0, + MLX5_BSF_P_TYPE_CRYPTO = 0x1, +}; + +enum { + MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, +}; + +enum { + MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, +}; + +enum { + MLX5_BLOCK_SIZE_512B = 0x1, + MLX5_BLOCK_SIZE_520B = 0x2, + MLX5_BLOCK_SIZE_4096B = 0x3, + MLX5_BLOCK_SIZE_4160B = 0x4, + MLX5_BLOCK_SIZE_1MB = 0x5, + MLX5_BLOCK_SIZE_4048B = 0x6, +}; + +#define MLX5_BSF_SIZE_OFFSET 30 +#define MLX5_BSF_P_TYPE_OFFSET 24 +#define MLX5_ENCRYPTION_ORDER_OFFSET 16 +#define MLX5_BLOCK_SIZE_OFFSET 24 + +struct mlx5_wqe_umr_bsf_seg { + /* + * bs_bpt_eo_es contains: + * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET + * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET + * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET + * es encryption_standard 4 bits at offset 0 + */ + uint32_t bs_bpt_eo_es; + uint32_t raw_data_size; + /* + * bsp_res contains: + * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET + * res reserved 24 bits + */ + uint32_t bsp_res; + uint32_t reserved0; + uint8_t xts_initial_tweak[16]; + /* + * res_dp contains: + * res reserved 8 bits + * dp dek_pointer 24 bits at offset 0 + */ + uint32_t res_dp; + uint32_t reserved1; + uint64_t keytag; + uint32_t reserved2[4]; +} __rte_packed; + enum { MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, From patchwork Thu Apr 29 15:43:30 2021 Content-Type: text/plain; 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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT064.mail.protection.outlook.com (10.13.172.234) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 15:44:59 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:44:57 +0000 From: Matan Azrad To: CC: , , , "Shiri Kuzin" Date: Thu, 29 Apr 2021 18:43:30 +0300 Message-ID: <20210429154335.2820028-12-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 94465e1e-ca6d-4aca-0fee-08d90b25bef4 X-MS-TrafficTypeDiagnostic: CY4PR12MB1813: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:171; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:44:59.3488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94465e1e-ca6d-4aca-0fee-08d90b25bef4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1813 Subject: [dpdk-dev] [PATCH v2 11/16] common/mlx5: share hash list tool X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shiri Kuzin In order to use the hash list defined in net in other drivers, the hash list is moved to common utilities. In addition, the log definition was moved from the common utilities to a dedicated new log file in common in order to prevent a conflict. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- drivers/common/mlx5/linux/mlx5_common_os.c | 2 +- drivers/common/mlx5/linux/mlx5_nl.c | 2 +- drivers/common/mlx5/meson.build | 15 +- drivers/common/mlx5/mlx5_common.c | 2 +- drivers/common/mlx5/mlx5_common_devx.c | 2 +- drivers/common/mlx5/mlx5_common_log.h | 21 ++ drivers/common/mlx5/mlx5_common_mp.c | 2 +- drivers/common/mlx5/mlx5_common_mr.c | 2 +- drivers/common/mlx5/mlx5_common_pci.c | 4 +- drivers/common/mlx5/mlx5_common_utils.c | 221 +++++++++++++++++++ drivers/common/mlx5/mlx5_common_utils.h | 202 ++++++++++++++++- drivers/common/mlx5/mlx5_devx_cmds.c | 2 +- drivers/common/mlx5/mlx5_malloc.c | 2 +- drivers/common/mlx5/version.map | 6 + drivers/common/mlx5/windows/mlx5_common_os.c | 2 +- drivers/common/mlx5/windows/mlx5_glue.c | 2 +- drivers/net/mlx5/mlx5_utils.c | 209 ------------------ drivers/net/mlx5/mlx5_utils.h | 194 +--------------- 18 files changed, 465 insertions(+), 427 deletions(-) create mode 100644 drivers/common/mlx5/mlx5_common_log.h create mode 100644 drivers/common/mlx5/mlx5_common_utils.c diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index 5cf9576921..fba8245b8b 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -15,7 +15,7 @@ #include #include "mlx5_common.h" -#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" #include "mlx5_glue.h" #ifdef MLX5_GLUE diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index 752c57b33d..f0d04f9473 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -20,7 +20,7 @@ #include #include "mlx5_nl.h" -#include "mlx5_common_utils.h" +#include "../mlx5_common_log.h" #include "mlx5_malloc.h" #ifdef HAVE_DEVLINK #include diff --git a/drivers/common/mlx5/meson.build b/drivers/common/mlx5/meson.build index b5585d2cc3..cd371fe6e1 100644 --- a/drivers/common/mlx5/meson.build +++ b/drivers/common/mlx5/meson.build @@ -9,13 +9,14 @@ endif deps += ['hash', 'pci', 'bus_pci', 'net', 'eal', 'kvargs'] sources += files( - 'mlx5_devx_cmds.c', - 'mlx5_common.c', - 'mlx5_common_mp.c', - 'mlx5_common_mr.c', - 'mlx5_malloc.c', - 'mlx5_common_pci.c', - 'mlx5_common_devx.c', + 'mlx5_devx_cmds.c', + 'mlx5_common.c', + 'mlx5_common_mp.c', + 'mlx5_common_mr.c', + 'mlx5_malloc.c', + 'mlx5_common_pci.c', + 'mlx5_common_devx.c', + 'mlx5_common_utils.c', ) cflags_options = [ diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index f92f05bda5..d397459a3d 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -11,7 +11,7 @@ #include "mlx5_common.h" #include "mlx5_common_os.h" -#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" #include "mlx5_common_pci.h" uint8_t haswell_broadwell_cpu; diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c index d19be122bd..22c8d356c4 100644 --- a/drivers/common/mlx5/mlx5_common_devx.c +++ b/drivers/common/mlx5/mlx5_common_devx.c @@ -12,7 +12,7 @@ #include "mlx5_prm.h" #include "mlx5_devx_cmds.h" -#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" #include "mlx5_malloc.h" #include "mlx5_common.h" #include "mlx5_common_devx.h" diff --git a/drivers/common/mlx5/mlx5_common_log.h b/drivers/common/mlx5/mlx5_common_log.h new file mode 100644 index 0000000000..26b13fedaf --- /dev/null +++ b/drivers/common/mlx5/mlx5_common_log.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Mellanox Technologies, Ltd + */ + +#ifndef RTE_PMD_MLX5_COMMON_LOG_H_ +#define RTE_PMD_MLX5_COMMON_LOG_H_ + +#include "mlx5_common.h" + + +extern int mlx5_common_logtype; + +#define MLX5_COMMON_LOG_PREFIX "mlx5_common" +/* Generic printf()-like logging macro with automatic line feed. */ +#define DRV_LOG(level, ...) \ + PMD_DRV_LOG_(level, mlx5_common_logtype, MLX5_COMMON_LOG_PREFIX, \ + __VA_ARGS__ PMD_DRV_LOG_STRIP PMD_DRV_LOG_OPAREN, \ + PMD_DRV_LOG_CPAREN) + +#endif /* RTE_PMD_MLX5_COMMON_LOG_H_ */ + diff --git a/drivers/common/mlx5/mlx5_common_mp.c b/drivers/common/mlx5/mlx5_common_mp.c index 40e3956e45..673a7c31de 100644 --- a/drivers/common/mlx5/mlx5_common_mp.c +++ b/drivers/common/mlx5/mlx5_common_mp.c @@ -10,7 +10,7 @@ #include #include "mlx5_common_mp.h" -#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" #include "mlx5_malloc.h" /** diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c index e1ed0caf3a..afb5b3d0a7 100644 --- a/drivers/common/mlx5/mlx5_common_mr.c +++ b/drivers/common/mlx5/mlx5_common_mr.c @@ -11,7 +11,7 @@ #include "mlx5_glue.h" #include "mlx5_common_mp.h" #include "mlx5_common_mr.h" -#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" #include "mlx5_malloc.h" struct mr_find_contig_memsegs_data { diff --git a/drivers/common/mlx5/mlx5_common_pci.c b/drivers/common/mlx5/mlx5_common_pci.c index 5a73ffa60a..3f16cd21cf 100644 --- a/drivers/common/mlx5/mlx5_common_pci.c +++ b/drivers/common/mlx5/mlx5_common_pci.c @@ -4,7 +4,9 @@ #include #include -#include "mlx5_common_utils.h" +#include + +#include "mlx5_common_log.h" #include "mlx5_common_pci.h" struct mlx5_pci_device { diff --git a/drivers/common/mlx5/mlx5_common_utils.c b/drivers/common/mlx5/mlx5_common_utils.c new file mode 100644 index 0000000000..ad2011e858 --- /dev/null +++ b/drivers/common/mlx5/mlx5_common_utils.c @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Mellanox Technologies, Ltd + */ + +#include +#include +#include + +#include + +#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" + +/********************* Hash List **********************/ + +static struct mlx5_hlist_entry * +mlx5_hlist_default_create_cb(struct mlx5_hlist *h, uint64_t key __rte_unused, + void *ctx __rte_unused) +{ + return mlx5_malloc(MLX5_MEM_ZERO, h->entry_sz, 0, SOCKET_ID_ANY); +} + +static void +mlx5_hlist_default_remove_cb(struct mlx5_hlist *h __rte_unused, + struct mlx5_hlist_entry *entry) +{ + mlx5_free(entry); +} + +struct mlx5_hlist * +mlx5_hlist_create(const char *name, uint32_t size, uint32_t entry_size, + uint32_t flags, mlx5_hlist_create_cb cb_create, + mlx5_hlist_match_cb cb_match, mlx5_hlist_remove_cb cb_remove) +{ + struct mlx5_hlist *h; + uint32_t act_size; + uint32_t alloc_size; + uint32_t i; + + if (!size || !cb_match || (!cb_create ^ !cb_remove)) + return NULL; + /* Align to the next power of 2, 32bits integer is enough now. */ + if (!rte_is_power_of_2(size)) { + act_size = rte_align32pow2(size); + DRV_LOG(DEBUG, "Size 0x%" PRIX32 " is not power of 2, " + "will be aligned to 0x%" PRIX32 ".", size, act_size); + } else { + act_size = size; + } + alloc_size = sizeof(struct mlx5_hlist) + + sizeof(struct mlx5_hlist_bucket) * act_size; + /* Using zmalloc, then no need to initialize the heads. */ + h = mlx5_malloc(MLX5_MEM_ZERO, alloc_size, RTE_CACHE_LINE_SIZE, + SOCKET_ID_ANY); + if (!h) { + DRV_LOG(ERR, "No memory for hash list %s creation", + name ? name : "None"); + return NULL; + } + if (name) + snprintf(h->name, MLX5_HLIST_NAMESIZE, "%s", name); + h->table_sz = act_size; + h->mask = act_size - 1; + h->entry_sz = entry_size; + h->direct_key = !!(flags & MLX5_HLIST_DIRECT_KEY); + h->write_most = !!(flags & MLX5_HLIST_WRITE_MOST); + h->cb_create = cb_create ? cb_create : mlx5_hlist_default_create_cb; + h->cb_match = cb_match; + h->cb_remove = cb_remove ? cb_remove : mlx5_hlist_default_remove_cb; + for (i = 0; i < act_size; i++) + rte_rwlock_init(&h->buckets[i].lock); + DRV_LOG(DEBUG, "Hash list with %s size 0x%" PRIX32 " is created.", + h->name, act_size); + return h; +} + +static struct mlx5_hlist_entry * +__hlist_lookup(struct mlx5_hlist *h, uint64_t key, uint32_t idx, + void *ctx, bool reuse) +{ + struct mlx5_hlist_head *first; + struct mlx5_hlist_entry *node; + + MLX5_ASSERT(h); + first = &h->buckets[idx].head; + LIST_FOREACH(node, first, next) { + if (!h->cb_match(h, node, key, ctx)) { + if (reuse) { + __atomic_add_fetch(&node->ref_cnt, 1, + __ATOMIC_RELAXED); + DRV_LOG(DEBUG, "Hash list %s entry %p " + "reuse: %u.", + h->name, (void *)node, node->ref_cnt); + } + break; + } + } + return node; +} + +static struct mlx5_hlist_entry * +hlist_lookup(struct mlx5_hlist *h, uint64_t key, uint32_t idx, + void *ctx, bool reuse) +{ + struct mlx5_hlist_entry *node; + + MLX5_ASSERT(h); + rte_rwlock_read_lock(&h->buckets[idx].lock); + node = __hlist_lookup(h, key, idx, ctx, reuse); + rte_rwlock_read_unlock(&h->buckets[idx].lock); + return node; +} + +struct mlx5_hlist_entry * +mlx5_hlist_lookup(struct mlx5_hlist *h, uint64_t key, void *ctx) +{ + uint32_t idx; + + if (h->direct_key) + idx = (uint32_t)(key & h->mask); + else + idx = rte_hash_crc_8byte(key, 0) & h->mask; + return hlist_lookup(h, key, idx, ctx, false); +} + +struct mlx5_hlist_entry* +mlx5_hlist_register(struct mlx5_hlist *h, uint64_t key, void *ctx) +{ + uint32_t idx; + struct mlx5_hlist_head *first; + struct mlx5_hlist_bucket *b; + struct mlx5_hlist_entry *entry; + uint32_t prev_gen_cnt = 0; + + if (h->direct_key) + idx = (uint32_t)(key & h->mask); + else + idx = rte_hash_crc_8byte(key, 0) & h->mask; + MLX5_ASSERT(h); + b = &h->buckets[idx]; + /* Use write lock directly for write-most list. */ + if (!h->write_most) { + prev_gen_cnt = __atomic_load_n(&b->gen_cnt, __ATOMIC_ACQUIRE); + entry = hlist_lookup(h, key, idx, ctx, true); + if (entry) + return entry; + } + rte_rwlock_write_lock(&b->lock); + /* Check if the list changed by other threads. */ + if (h->write_most || + prev_gen_cnt != __atomic_load_n(&b->gen_cnt, __ATOMIC_ACQUIRE)) { + entry = __hlist_lookup(h, key, idx, ctx, true); + if (entry) + goto done; + } + first = &b->head; + entry = h->cb_create(h, key, ctx); + if (!entry) { + rte_errno = ENOMEM; + DRV_LOG(DEBUG, "Can't allocate hash list %s entry.", h->name); + goto done; + } + entry->idx = idx; + entry->ref_cnt = 1; + LIST_INSERT_HEAD(first, entry, next); + __atomic_add_fetch(&b->gen_cnt, 1, __ATOMIC_ACQ_REL); + DRV_LOG(DEBUG, "Hash list %s entry %p new: %u.", + h->name, (void *)entry, entry->ref_cnt); +done: + rte_rwlock_write_unlock(&b->lock); + return entry; +} + +int +mlx5_hlist_unregister(struct mlx5_hlist *h, struct mlx5_hlist_entry *entry) +{ + uint32_t idx = entry->idx; + + rte_rwlock_write_lock(&h->buckets[idx].lock); + MLX5_ASSERT(entry && entry->ref_cnt && entry->next.le_prev); + DRV_LOG(DEBUG, "Hash list %s entry %p deref: %u.", + h->name, (void *)entry, entry->ref_cnt); + if (--entry->ref_cnt) { + rte_rwlock_write_unlock(&h->buckets[idx].lock); + return 1; + } + LIST_REMOVE(entry, next); + /* Set to NULL to get rid of removing action for more than once. */ + entry->next.le_prev = NULL; + h->cb_remove(h, entry); + rte_rwlock_write_unlock(&h->buckets[idx].lock); + DRV_LOG(DEBUG, "Hash list %s entry %p removed.", + h->name, (void *)entry); + return 0; +} + +void +mlx5_hlist_destroy(struct mlx5_hlist *h) +{ + uint32_t idx; + struct mlx5_hlist_entry *entry; + + MLX5_ASSERT(h); + for (idx = 0; idx < h->table_sz; ++idx) { + /* No LIST_FOREACH_SAFE, using while instead. */ + while (!LIST_EMPTY(&h->buckets[idx].head)) { + entry = LIST_FIRST(&h->buckets[idx].head); + LIST_REMOVE(entry, next); + /* + * The owner of whole element which contains data entry + * is the user, so it's the user's duty to do the clean + * up and the free work because someone may not put the + * hlist entry at the beginning(suggested to locate at + * the beginning). Or else the default free function + * will be used. + */ + h->cb_remove(h, entry); + } + } + mlx5_free(h); +} diff --git a/drivers/common/mlx5/mlx5_common_utils.h b/drivers/common/mlx5/mlx5_common_utils.h index 6cba39c8cc..ed378ce9bd 100644 --- a/drivers/common/mlx5/mlx5_common_utils.h +++ b/drivers/common/mlx5/mlx5_common_utils.h @@ -7,14 +7,202 @@ #include "mlx5_common.h" +#define MLX5_HLIST_DIRECT_KEY 0x0001 /* Use the key directly as hash index. */ +#define MLX5_HLIST_WRITE_MOST 0x0002 /* List mostly used for append new. */ -extern int mlx5_common_logtype; +/** Maximum size of string for naming the hlist table. */ +#define MLX5_HLIST_NAMESIZE 32 -#define MLX5_COMMON_LOG_PREFIX "mlx5_common" -/* Generic printf()-like logging macro with automatic line feed. */ -#define DRV_LOG(level, ...) \ - PMD_DRV_LOG_(level, mlx5_common_logtype, MLX5_COMMON_LOG_PREFIX, \ - __VA_ARGS__ PMD_DRV_LOG_STRIP PMD_DRV_LOG_OPAREN, \ - PMD_DRV_LOG_CPAREN) +struct mlx5_hlist; + +/** + * Structure of the entry in the hash list, user should define its own struct + * that contains this in order to store the data. The 'key' is 64-bits right + * now and its user's responsibility to guarantee there is no collision. + */ +struct mlx5_hlist_entry { + LIST_ENTRY(mlx5_hlist_entry) next; /* entry pointers in the list. */ + uint32_t idx; /* Bucket index the entry belongs to. */ + uint32_t ref_cnt; /* Reference count. */ +}; + +/** Structure for hash head. */ +LIST_HEAD(mlx5_hlist_head, mlx5_hlist_entry); + +/** + * Type of callback function for entry removal. + * + * @param list + * The hash list. + * @param entry + * The entry in the list. + */ +typedef void (*mlx5_hlist_remove_cb)(struct mlx5_hlist *list, + struct mlx5_hlist_entry *entry); + +/** + * Type of function for user defined matching. + * + * @param list + * The hash list. + * @param entry + * The entry in the list. + * @param key + * The new entry key. + * @param ctx + * The pointer to new entry context. + * + * @return + * 0 if matching, non-zero number otherwise. + */ +typedef int (*mlx5_hlist_match_cb)(struct mlx5_hlist *list, + struct mlx5_hlist_entry *entry, + uint64_t key, void *ctx); + +/** + * Type of function for user defined hash list entry creation. + * + * @param list + * The hash list. + * @param key + * The key of the new entry. + * @param ctx + * The pointer to new entry context. + * + * @return + * Pointer to allocated entry on success, NULL otherwise. + */ +typedef struct mlx5_hlist_entry *(*mlx5_hlist_create_cb) + (struct mlx5_hlist *list, + uint64_t key, void *ctx); + +/* Hash list bucket head. */ +struct mlx5_hlist_bucket { + struct mlx5_hlist_head head; /* List head. */ + rte_rwlock_t lock; /* Bucket lock. */ + uint32_t gen_cnt; /* List modification will update generation count. */ +} __rte_cache_aligned; + +/** + * Hash list table structure + * + * Entry in hash list could be reused if entry already exists, reference + * count will increase and the existing entry returns. + * + * When destroy an entry from list, decrease reference count and only + * destroy when no further reference. + */ +struct mlx5_hlist { + char name[MLX5_HLIST_NAMESIZE]; /**< Name of the hash list. */ + /**< number of heads, need to be power of 2. */ + uint32_t table_sz; + uint32_t entry_sz; /**< Size of entry, used to allocate entry. */ + /**< mask to get the index of the list heads. */ + uint32_t mask; + bool direct_key; /* Use the new entry key directly as hash index. */ + bool write_most; /* List mostly used for append new or destroy. */ + void *ctx; + mlx5_hlist_create_cb cb_create; /**< entry create callback. */ + mlx5_hlist_match_cb cb_match; /**< entry match callback. */ + mlx5_hlist_remove_cb cb_remove; /**< entry remove callback. */ + struct mlx5_hlist_bucket buckets[] __rte_cache_aligned; + /**< list bucket arrays. */ +}; + +/** + * Create a hash list table, the user can specify the list heads array size + * of the table, now the size should be a power of 2 in order to get better + * distribution for the entries. Each entry is a part of the whole data element + * and the caller should be responsible for the data element's allocation and + * cleanup / free. Key of each entry will be calculated with CRC in order to + * generate a little fairer distribution. + * + * @param name + * Name of the hash list(optional). + * @param size + * Heads array size of the hash list. + * @param entry_size + * Entry size to allocate if cb_create not specified. + * @param flags + * The hash list attribute flags. + * @param cb_create + * Callback function for entry create. + * @param cb_match + * Callback function for entry match. + * @param cb_destroy + * Callback function for entry destroy. + * @return + * Pointer of the hash list table created, NULL on failure. + */ +__rte_internal +struct mlx5_hlist *mlx5_hlist_create(const char *name, uint32_t size, + uint32_t entry_size, uint32_t flags, + mlx5_hlist_create_cb cb_create, + mlx5_hlist_match_cb cb_match, + mlx5_hlist_remove_cb cb_destroy); + +/** + * Search an entry matching the key. + * + * Result returned might be destroyed by other thread, must use + * this function only in main thread. + * + * @param h + * Pointer to the hast list table. + * @param key + * Key for the searching entry. + * @param ctx + * Common context parameter used by entry callback function. + * + * @return + * Pointer of the hlist entry if found, NULL otherwise. + */ +__rte_internal +struct mlx5_hlist_entry *mlx5_hlist_lookup(struct mlx5_hlist *h, uint64_t key, + void *ctx); + +/** + * Insert an entry to the hash list table, the entry is only part of whole data + * element and a 64B key is used for matching. User should construct the key or + * give a calculated hash signature and guarantee there is no collision. + * + * @param h + * Pointer to the hast list table. + * @param entry + * Entry to be inserted into the hash list table. + * @param ctx + * Common context parameter used by callback function. + * + * @return + * registered entry on success, NULL otherwise + */ +__rte_internal +struct mlx5_hlist_entry *mlx5_hlist_register(struct mlx5_hlist *h, uint64_t key, + void *ctx); + +/** + * Remove an entry from the hash list table. User should guarantee the validity + * of the entry. + * + * @param h + * Pointer to the hast list table. (not used) + * @param entry + * Entry to be removed from the hash list table. + * @return + * 0 on entry removed, 1 on entry still referenced. + */ +__rte_internal +int mlx5_hlist_unregister(struct mlx5_hlist *h, struct mlx5_hlist_entry *entry); + +/** + * Destroy the hash list table, all the entries already inserted into the lists + * will be handled by the callback function provided by the user (including + * free if needed) before the table is freed. + * + * @param h + * Pointer to the hast list table. + */ +__rte_internal +void mlx5_hlist_destroy(struct mlx5_hlist *h); #endif /* RTE_PMD_MLX5_COMMON_UTILS_H_ */ diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 5e082ebb78..c0061741e8 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -9,7 +9,7 @@ #include "mlx5_prm.h" #include "mlx5_devx_cmds.h" -#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" #include "mlx5_malloc.h" diff --git a/drivers/common/mlx5/mlx5_malloc.c b/drivers/common/mlx5/mlx5_malloc.c index 9d30cedbaa..b19501e1bc 100644 --- a/drivers/common/mlx5/mlx5_malloc.c +++ b/drivers/common/mlx5/mlx5_malloc.c @@ -8,7 +8,7 @@ #include #include -#include "mlx5_common_utils.h" +#include "mlx5_common_log.h" #include "mlx5_common_os.h" #include "mlx5_malloc.h" diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index bbef436fde..d16e484ffa 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -121,4 +121,10 @@ INTERNAL { mlx5_free; mlx5_pci_driver_register; + + mlx5_hlist_create; + mlx5_hlist_lookup; + mlx5_hlist_register; + mlx5_hlist_unregister; + mlx5_hlist_destroy; }; diff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c index f2d781a965..2e6e172a96 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.c +++ b/drivers/common/mlx5/windows/mlx5_common_os.c @@ -11,7 +11,7 @@ #include #include "mlx5_devx_cmds.h" -#include "mlx5_common_utils.h" +#include "../mlx5_common_log.h" #include "mlx5_common.h" #include "mlx5_common_os.h" #include "mlx5_malloc.h" diff --git a/drivers/common/mlx5/windows/mlx5_glue.c b/drivers/common/mlx5/windows/mlx5_glue.c index aef6d3b5f4..535487a8d4 100644 --- a/drivers/common/mlx5/windows/mlx5_glue.c +++ b/drivers/common/mlx5/windows/mlx5_glue.c @@ -12,7 +12,7 @@ #include #include "mlx5_glue.h" -#include "mlx5_common_utils.h" +#include "../mlx5_common_log.h" #include "mlx5_win_ext.h" /* diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c index a39b5edddc..18fe23e4fb 100644 --- a/drivers/net/mlx5/mlx5_utils.c +++ b/drivers/net/mlx5/mlx5_utils.c @@ -3,220 +3,11 @@ */ #include -#include #include #include "mlx5_utils.h" -/********************* Hash List **********************/ - -static struct mlx5_hlist_entry * -mlx5_hlist_default_create_cb(struct mlx5_hlist *h, uint64_t key __rte_unused, - void *ctx __rte_unused) -{ - return mlx5_malloc(MLX5_MEM_ZERO, h->entry_sz, 0, SOCKET_ID_ANY); -} - -static void -mlx5_hlist_default_remove_cb(struct mlx5_hlist *h __rte_unused, - struct mlx5_hlist_entry *entry) -{ - mlx5_free(entry); -} - -struct mlx5_hlist * -mlx5_hlist_create(const char *name, uint32_t size, uint32_t entry_size, - uint32_t flags, mlx5_hlist_create_cb cb_create, - mlx5_hlist_match_cb cb_match, mlx5_hlist_remove_cb cb_remove) -{ - struct mlx5_hlist *h; - uint32_t act_size; - uint32_t alloc_size; - uint32_t i; - - if (!size || !cb_match || (!cb_create ^ !cb_remove)) - return NULL; - /* Align to the next power of 2, 32bits integer is enough now. */ - if (!rte_is_power_of_2(size)) { - act_size = rte_align32pow2(size); - DRV_LOG(DEBUG, "Size 0x%" PRIX32 " is not power of 2, " - "will be aligned to 0x%" PRIX32 ".", size, act_size); - } else { - act_size = size; - } - alloc_size = sizeof(struct mlx5_hlist) + - sizeof(struct mlx5_hlist_bucket) * act_size; - /* Using zmalloc, then no need to initialize the heads. */ - h = mlx5_malloc(MLX5_MEM_ZERO, alloc_size, RTE_CACHE_LINE_SIZE, - SOCKET_ID_ANY); - if (!h) { - DRV_LOG(ERR, "No memory for hash list %s creation", - name ? name : "None"); - return NULL; - } - if (name) - snprintf(h->name, MLX5_HLIST_NAMESIZE, "%s", name); - h->table_sz = act_size; - h->mask = act_size - 1; - h->entry_sz = entry_size; - h->direct_key = !!(flags & MLX5_HLIST_DIRECT_KEY); - h->write_most = !!(flags & MLX5_HLIST_WRITE_MOST); - h->cb_create = cb_create ? cb_create : mlx5_hlist_default_create_cb; - h->cb_match = cb_match; - h->cb_remove = cb_remove ? cb_remove : mlx5_hlist_default_remove_cb; - for (i = 0; i < act_size; i++) - rte_rwlock_init(&h->buckets[i].lock); - DRV_LOG(DEBUG, "Hash list with %s size 0x%" PRIX32 " is created.", - h->name, act_size); - return h; -} - -static struct mlx5_hlist_entry * -__hlist_lookup(struct mlx5_hlist *h, uint64_t key, uint32_t idx, - void *ctx, bool reuse) -{ - struct mlx5_hlist_head *first; - struct mlx5_hlist_entry *node; - - MLX5_ASSERT(h); - first = &h->buckets[idx].head; - LIST_FOREACH(node, first, next) { - if (!h->cb_match(h, node, key, ctx)) { - if (reuse) { - __atomic_add_fetch(&node->ref_cnt, 1, - __ATOMIC_RELAXED); - DRV_LOG(DEBUG, "Hash list %s entry %p " - "reuse: %u.", - h->name, (void *)node, node->ref_cnt); - } - break; - } - } - return node; -} - -static struct mlx5_hlist_entry * -hlist_lookup(struct mlx5_hlist *h, uint64_t key, uint32_t idx, - void *ctx, bool reuse) -{ - struct mlx5_hlist_entry *node; - - MLX5_ASSERT(h); - rte_rwlock_read_lock(&h->buckets[idx].lock); - node = __hlist_lookup(h, key, idx, ctx, reuse); - rte_rwlock_read_unlock(&h->buckets[idx].lock); - return node; -} - -struct mlx5_hlist_entry * -mlx5_hlist_lookup(struct mlx5_hlist *h, uint64_t key, void *ctx) -{ - uint32_t idx; - - if (h->direct_key) - idx = (uint32_t)(key & h->mask); - else - idx = rte_hash_crc_8byte(key, 0) & h->mask; - return hlist_lookup(h, key, idx, ctx, false); -} - -struct mlx5_hlist_entry* -mlx5_hlist_register(struct mlx5_hlist *h, uint64_t key, void *ctx) -{ - uint32_t idx; - struct mlx5_hlist_head *first; - struct mlx5_hlist_bucket *b; - struct mlx5_hlist_entry *entry; - uint32_t prev_gen_cnt = 0; - - if (h->direct_key) - idx = (uint32_t)(key & h->mask); - else - idx = rte_hash_crc_8byte(key, 0) & h->mask; - MLX5_ASSERT(h); - b = &h->buckets[idx]; - /* Use write lock directly for write-most list. */ - if (!h->write_most) { - prev_gen_cnt = __atomic_load_n(&b->gen_cnt, __ATOMIC_ACQUIRE); - entry = hlist_lookup(h, key, idx, ctx, true); - if (entry) - return entry; - } - rte_rwlock_write_lock(&b->lock); - /* Check if the list changed by other threads. */ - if (h->write_most || - prev_gen_cnt != __atomic_load_n(&b->gen_cnt, __ATOMIC_ACQUIRE)) { - entry = __hlist_lookup(h, key, idx, ctx, true); - if (entry) - goto done; - } - first = &b->head; - entry = h->cb_create(h, key, ctx); - if (!entry) { - rte_errno = ENOMEM; - DRV_LOG(DEBUG, "Can't allocate hash list %s entry.", h->name); - goto done; - } - entry->idx = idx; - entry->ref_cnt = 1; - LIST_INSERT_HEAD(first, entry, next); - __atomic_add_fetch(&b->gen_cnt, 1, __ATOMIC_ACQ_REL); - DRV_LOG(DEBUG, "Hash list %s entry %p new: %u.", - h->name, (void *)entry, entry->ref_cnt); -done: - rte_rwlock_write_unlock(&b->lock); - return entry; -} - -int -mlx5_hlist_unregister(struct mlx5_hlist *h, struct mlx5_hlist_entry *entry) -{ - uint32_t idx = entry->idx; - - rte_rwlock_write_lock(&h->buckets[idx].lock); - MLX5_ASSERT(entry && entry->ref_cnt && entry->next.le_prev); - DRV_LOG(DEBUG, "Hash list %s entry %p deref: %u.", - h->name, (void *)entry, entry->ref_cnt); - if (--entry->ref_cnt) { - rte_rwlock_write_unlock(&h->buckets[idx].lock); - return 1; - } - LIST_REMOVE(entry, next); - /* Set to NULL to get rid of removing action for more than once. */ - entry->next.le_prev = NULL; - h->cb_remove(h, entry); - rte_rwlock_write_unlock(&h->buckets[idx].lock); - DRV_LOG(DEBUG, "Hash list %s entry %p removed.", - h->name, (void *)entry); - return 0; -} - -void -mlx5_hlist_destroy(struct mlx5_hlist *h) -{ - uint32_t idx; - struct mlx5_hlist_entry *entry; - - MLX5_ASSERT(h); - for (idx = 0; idx < h->table_sz; ++idx) { - /* No LIST_FOREACH_SAFE, using while instead. */ - while (!LIST_EMPTY(&h->buckets[idx].head)) { - entry = LIST_FIRST(&h->buckets[idx].head); - LIST_REMOVE(entry, next); - /* - * The owner of whole element which contains data entry - * is the user, so it's the user's duty to do the clean - * up and the free work because someone may not put the - * hlist entry at the beginning(suggested to locate at - * the beginning). Or else the default free function - * will be used. - */ - h->cb_remove(h, entry); - } - } - mlx5_free(h); -} /********************* Cache list ************************/ diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h index 289941cebc..b54517c6df 100644 --- a/drivers/net/mlx5/mlx5_utils.h +++ b/drivers/net/mlx5/mlx5_utils.h @@ -18,6 +18,7 @@ #include #include +#include #include "mlx5_defs.h" @@ -261,199 +262,6 @@ log2above(unsigned int v) return l + r; } -#define MLX5_HLIST_DIRECT_KEY 0x0001 /* Use the key directly as hash index. */ -#define MLX5_HLIST_WRITE_MOST 0x0002 /* List mostly used for append new. */ - -/** Maximum size of string for naming the hlist table. */ -#define MLX5_HLIST_NAMESIZE 32 - -struct mlx5_hlist; - -/** - * Structure of the entry in the hash list, user should define its own struct - * that contains this in order to store the data. The 'key' is 64-bits right - * now and its user's responsibility to guarantee there is no collision. - */ -struct mlx5_hlist_entry { - LIST_ENTRY(mlx5_hlist_entry) next; /* entry pointers in the list. */ - uint32_t idx; /* Bucket index the entry belongs to. */ - uint32_t ref_cnt; /* Reference count. */ -}; - -/** Structure for hash head. */ -LIST_HEAD(mlx5_hlist_head, mlx5_hlist_entry); - -/** - * Type of callback function for entry removal. - * - * @param list - * The hash list. - * @param entry - * The entry in the list. - */ -typedef void (*mlx5_hlist_remove_cb)(struct mlx5_hlist *list, - struct mlx5_hlist_entry *entry); - -/** - * Type of function for user defined matching. - * - * @param list - * The hash list. - * @param entry - * The entry in the list. - * @param key - * The new entry key. - * @param ctx - * The pointer to new entry context. - * - * @return - * 0 if matching, non-zero number otherwise. - */ -typedef int (*mlx5_hlist_match_cb)(struct mlx5_hlist *list, - struct mlx5_hlist_entry *entry, - uint64_t key, void *ctx); - -/** - * Type of function for user defined hash list entry creation. - * - * @param list - * The hash list. - * @param key - * The key of the new entry. - * @param ctx - * The pointer to new entry context. - * - * @return - * Pointer to allocated entry on success, NULL otherwise. - */ -typedef struct mlx5_hlist_entry *(*mlx5_hlist_create_cb) - (struct mlx5_hlist *list, - uint64_t key, void *ctx); - -/* Hash list bucket head. */ -struct mlx5_hlist_bucket { - struct mlx5_hlist_head head; /* List head. */ - rte_rwlock_t lock; /* Bucket lock. */ - uint32_t gen_cnt; /* List modification will update generation count. */ -} __rte_cache_aligned; - -/** - * Hash list table structure - * - * Entry in hash list could be reused if entry already exists, reference - * count will increase and the existing entry returns. - * - * When destroy an entry from list, decrease reference count and only - * destroy when no further reference. - */ -struct mlx5_hlist { - char name[MLX5_HLIST_NAMESIZE]; /**< Name of the hash list. */ - /**< number of heads, need to be power of 2. */ - uint32_t table_sz; - uint32_t entry_sz; /**< Size of entry, used to allocate entry. */ - /**< mask to get the index of the list heads. */ - uint32_t mask; - bool direct_key; /* Use the new entry key directly as hash index. */ - bool write_most; /* List mostly used for append new or destroy. */ - void *ctx; - mlx5_hlist_create_cb cb_create; /**< entry create callback. */ - mlx5_hlist_match_cb cb_match; /**< entry match callback. */ - mlx5_hlist_remove_cb cb_remove; /**< entry remove callback. */ - struct mlx5_hlist_bucket buckets[] __rte_cache_aligned; - /**< list bucket arrays. */ -}; - -/** - * Create a hash list table, the user can specify the list heads array size - * of the table, now the size should be a power of 2 in order to get better - * distribution for the entries. Each entry is a part of the whole data element - * and the caller should be responsible for the data element's allocation and - * cleanup / free. Key of each entry will be calculated with CRC in order to - * generate a little fairer distribution. - * - * @param name - * Name of the hash list(optional). - * @param size - * Heads array size of the hash list. - * @param entry_size - * Entry size to allocate if cb_create not specified. - * @param flags - * The hash list attribute flags. - * @param cb_create - * Callback function for entry create. - * @param cb_match - * Callback function for entry match. - * @param cb_destroy - * Callback function for entry destroy. - * @return - * Pointer of the hash list table created, NULL on failure. - */ -struct mlx5_hlist *mlx5_hlist_create(const char *name, uint32_t size, - uint32_t entry_size, uint32_t flags, - mlx5_hlist_create_cb cb_create, - mlx5_hlist_match_cb cb_match, - mlx5_hlist_remove_cb cb_destroy); - -/** - * Search an entry matching the key. - * - * Result returned might be destroyed by other thread, must use - * this function only in main thread. - * - * @param h - * Pointer to the hast list table. - * @param key - * Key for the searching entry. - * @param ctx - * Common context parameter used by entry callback function. - * - * @return - * Pointer of the hlist entry if found, NULL otherwise. - */ -struct mlx5_hlist_entry *mlx5_hlist_lookup(struct mlx5_hlist *h, uint64_t key, - void *ctx); - -/** - * Insert an entry to the hash list table, the entry is only part of whole data - * element and a 64B key is used for matching. User should construct the key or - * give a calculated hash signature and guarantee there is no collision. - * - * @param h - * Pointer to the hast list table. - * @param entry - * Entry to be inserted into the hash list table. - * @param ctx - * Common context parameter used by callback function. - * - * @return - * registered entry on success, NULL otherwise - */ -struct mlx5_hlist_entry *mlx5_hlist_register(struct mlx5_hlist *h, uint64_t key, - void *ctx); - -/** - * Remove an entry from the hash list table. User should guarantee the validity - * of the entry. - * - * @param h - * Pointer to the hast list table. (not used) - * @param entry - * Entry to be removed from the hash list table. - * @return - * 0 on entry removed, 1 on entry still referenced. - */ -int mlx5_hlist_unregister(struct mlx5_hlist *h, struct mlx5_hlist_entry *entry); - -/** - * Destroy the hash list table, all the entries already inserted into the lists - * will be handled by the callback function provided by the user (including - * free if needed) before the table is freed. - * - * @param h - * Pointer to the hast list table. - */ -void mlx5_hlist_destroy(struct mlx5_hlist *h); - /************************ cache list *****************************/ /** Maximum size of string for naming. */ From patchwork Thu Apr 29 15:43:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92427 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1078A0547; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(39860400002)(376002)(346002)(396003)(46966006)(36840700001)(82310400003)(356005)(47076005)(82740400003)(36860700001)(186003)(7696005)(86362001)(7636003)(70586007)(8676002)(8936002)(6666004)(83380400001)(426003)(2906002)(6916009)(107886003)(4326008)(36906005)(2616005)(36756003)(5660300002)(55016002)(54906003)(16526019)(478600001)(316002)(336012)(6286002)(1076003)(70206006)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:02.7684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aded14f2-ad42-4847-c75c-08d90b25c0f5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB4711 Subject: [dpdk-dev] [PATCH v2 12/16] common/mlx5: share get ib device match function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shiri Kuzin The get_ib_device_match function iterates over the list of ib devices returned by the get_device_list glue function and returns the ib device matching the provided address. Since this function is in use by several drivers, in this patch we share the function in common part. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- drivers/common/mlx5/linux/mlx5_common_os.c | 28 +++++++++++++++++++ drivers/common/mlx5/linux/mlx5_common_os.h | 5 ++++ drivers/common/mlx5/mlx5_common.h | 2 ++ drivers/common/mlx5/version.map | 1 + drivers/compress/mlx5/mlx5_compress.c | 30 +------------------- drivers/regex/mlx5/mlx5_regex.c | 30 ++------------------ drivers/vdpa/mlx5/mlx5_vdpa.c | 32 ++-------------------- 7 files changed, 41 insertions(+), 87 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index fba8245b8b..037147fe31 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -16,6 +16,7 @@ #include "mlx5_common.h" #include "mlx5_common_log.h" +#include "mlx5_common_os.h" #include "mlx5_glue.h" #ifdef MLX5_GLUE @@ -423,3 +424,30 @@ mlx5_glue_constructor(void) mlx5_glue = NULL; } +struct ibv_device * +mlx5_os_get_ib_device_match(struct rte_pci_addr *addr) +{ + int n; + struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n); + struct ibv_device *ibv_match = NULL; + + if (ibv_list == NULL) { + rte_errno = ENOSYS; + return NULL; + } + while (n-- > 0) { + struct rte_pci_addr paddr; + + DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name); + if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0) + continue; + if (rte_pci_addr_cmp(addr, &paddr) != 0) + continue; + ibv_match = ibv_list[n]; + break; + } + if (ibv_match == NULL) + rte_errno = ENOENT; + mlx5_glue->free_device_list(ibv_list); + return ibv_match; +} diff --git a/drivers/common/mlx5/linux/mlx5_common_os.h b/drivers/common/mlx5/linux/mlx5_common_os.h index d1c7e3dce0..9fff9cdb83 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.h +++ b/drivers/common/mlx5/linux/mlx5_common_os.h @@ -288,4 +288,9 @@ mlx5_os_free(void *addr) { free(addr); } + +__rte_internal +struct ibv_device * +mlx5_os_get_ib_device_match(struct rte_pci_addr *addr); + #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */ diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index f3c6beb23b..89aca32305 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -18,6 +18,7 @@ #include "mlx5_prm.h" #include "mlx5_devx_cmds.h" +#include "mlx5_common_os.h" /* Reported driver name. */ #define MLX5_PCI_DRIVER_NAME "mlx5_pci" @@ -215,6 +216,7 @@ enum mlx5_class { MLX5_CLASS_VDPA = RTE_BIT64(1), MLX5_CLASS_REGEX = RTE_BIT64(2), MLX5_CLASS_COMPRESS = RTE_BIT64(3), + MLX5_CLASS_CRYPTO = RTE_BIT64(4), }; #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index d16e484ffa..00df37e81a 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -111,6 +111,7 @@ INTERNAL { mlx5_os_reg_mr; mlx5_os_umem_reg; mlx5_os_umem_dereg; + mlx5_os_get_ib_device_match; # WINDOWS_NO_EXPORT mlx5_translate_port_name; # WINDOWS_NO_EXPORT diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index ec3c237512..ff988d26ef 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -647,34 +647,6 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, return i; } -static struct ibv_device * -mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr) -{ - int n; - struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n); - struct ibv_device *ibv_match = NULL; - - if (ibv_list == NULL) { - rte_errno = ENOSYS; - return NULL; - } - while (n-- > 0) { - struct rte_pci_addr paddr; - - DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name); - if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0) - continue; - if (rte_pci_addr_cmp(addr, &paddr) != 0) - continue; - ibv_match = ibv_list[n]; - break; - } - if (ibv_match == NULL) - rte_errno = ENOENT; - mlx5_glue->free_device_list(ibv_list); - return ibv_match; -} - static void mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv) { @@ -774,7 +746,7 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, rte_errno = ENOTSUP; return -rte_errno; } - ibv = mlx5_compress_get_ib_device_match(&pci_dev->addr); + ibv = mlx5_os_get_ib_device_match(&pci_dev->addr); if (ibv == NULL) { DRV_LOG(ERR, "No matching IB device for PCI slot " PCI_PRI_FMT ".", pci_dev->addr.domain, diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index 82c485e50c..5b81666d21 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -52,33 +53,6 @@ mlx5_regex_close(struct rte_regexdev *dev __rte_unused) return 0; } -static struct ibv_device * -mlx5_regex_get_ib_device_match(struct rte_pci_addr *addr) -{ - int n; - struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n); - struct ibv_device *ibv_match = NULL; - - if (!ibv_list) { - rte_errno = ENOSYS; - return NULL; - } - while (n-- > 0) { - struct rte_pci_addr pci_addr; - - DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name); - if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &pci_addr)) - continue; - if (rte_pci_addr_cmp(addr, &pci_addr)) - continue; - ibv_match = ibv_list[n]; - break; - } - if (!ibv_match) - rte_errno = ENOENT; - mlx5_glue->free_device_list(ibv_list); - return ibv_match; -} static int mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines) { @@ -121,7 +95,7 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, int ret; uint32_t val; - ibv = mlx5_regex_get_ib_device_match(&pci_dev->addr); + ibv = mlx5_os_get_ib_device_match(&pci_dev->addr); if (!ibv) { DRV_LOG(ERR, "No matching IB device for PCI slot " PCI_PRI_FMT ".", pci_dev->addr.domain, diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index 898e50f807..9a946ac8a7 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -472,34 +472,6 @@ static struct rte_vdpa_dev_ops mlx5_vdpa_ops = { .reset_stats = mlx5_vdpa_reset_stats, }; -static struct ibv_device * -mlx5_vdpa_get_ib_device_match(struct rte_pci_addr *addr) -{ - int n; - struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n); - struct ibv_device *ibv_match = NULL; - - if (!ibv_list) { - rte_errno = ENOSYS; - return NULL; - } - while (n-- > 0) { - struct rte_pci_addr pci_addr; - - DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name); - if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &pci_addr)) - continue; - if (rte_pci_addr_cmp(addr, &pci_addr)) - continue; - ibv_match = ibv_list[n]; - break; - } - if (!ibv_match) - rte_errno = ENOENT; - mlx5_glue->free_device_list(ibv_list); - return ibv_match; -} - /* Try to disable ROCE by Netlink\Devlink. */ static int mlx5_vdpa_nl_roce_disable(const char *addr) @@ -595,7 +567,7 @@ mlx5_vdpa_roce_disable(struct rte_pci_addr *addr, struct ibv_device **ibv) struct ibv_device *ibv_new; for (r = MLX5_VDPA_MAX_RETRIES; r; r--) { - ibv_new = mlx5_vdpa_get_ib_device_match(addr); + ibv_new = mlx5_os_get_ib_device_match(addr); if (ibv_new) { *ibv = ibv_new; return 0; @@ -698,7 +670,7 @@ mlx5_vdpa_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct mlx5_hca_attr attr; int ret; - ibv = mlx5_vdpa_get_ib_device_match(&pci_dev->addr); + ibv = mlx5_os_get_ib_device_match(&pci_dev->addr); if (!ibv) { DRV_LOG(ERR, "No matching IB device for PCI slot " PCI_PRI_FMT ".", pci_dev->addr.domain, From patchwork Thu Apr 29 15:43:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92428 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 94495A0547; Thu, 29 Apr 2021 17:45:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AF40941356; Thu, 29 Apr 2021 17:45:11 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2086.outbound.protection.outlook.com [40.107.220.86]) by mails.dpdk.org (Postfix) with ESMTP id 69710410DD for ; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(376002)(396003)(39860400002)(136003)(46966006)(36840700001)(55016002)(16526019)(82310400003)(1076003)(36906005)(7636003)(478600001)(356005)(70206006)(8676002)(70586007)(82740400003)(8936002)(26005)(336012)(426003)(5660300002)(36756003)(83380400001)(2906002)(86362001)(2616005)(7696005)(4326008)(54906003)(6286002)(47076005)(186003)(316002)(36860700001)(107886003)(6666004)(6916009); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:05.3939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd09b9f3-ea13-4078-8677-08d90b25c291 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5424 Subject: [dpdk-dev] [PATCH v2 13/16] common/mlx5: support general obj CREDENTIAL create X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled CREDENTIAL object is used for any crypto operation in wrapped mode. This patch add support of CREDENTIAL object create operation. Add reading of CREDENTIAL support capability. Add function to create general object type CREDENTIAL, using DevX API. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 53 +++++++++++++++++++++++++++- drivers/common/mlx5/mlx5_devx_cmds.h | 17 +++++++-- drivers/common/mlx5/mlx5_prm.h | 23 ++++++++++++ drivers/common/mlx5/version.map | 1 + 4 files changed, 91 insertions(+), 3 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index c0061741e8..c0a0853c3a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -754,6 +754,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GENERAL_OBJ_TYPES_CAP_DEK); attr->import_kek = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); + attr->credential = !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); attr->crypto_login = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ @@ -2512,6 +2514,55 @@ mlx5_devx_cmd_create_import_kek_obj(void *ctx, return import_kek_obj; } +/** + * Create general object of type CREDENTIAL using DevX API. + * + * @param[in] ctx + * Context returned from mlx5 open_device() glue function. + * @param [in] attr + * Pointer to CREDENTIAL attributes structure. + * + * @return + * The DevX object created, NULL otherwise and rte_errno is set. + */ +struct mlx5_devx_obj * +mlx5_devx_cmd_create_credential_obj(void *ctx, + struct mlx5_devx_credential_attr *attr) +{ + uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; + uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; + struct mlx5_devx_obj *credential_obj = NULL; + void *ptr = NULL, *credential_addr = NULL; + + credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), + 0, SOCKET_ID_ANY); + if (credential_obj == NULL) { + DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); + rte_errno = ENOMEM; + return NULL; + } + ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); + MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, + MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); + ptr = MLX5_ADDR_OF(create_credential_in, in, credential); + MLX5_SET(credential, ptr, credential_role, attr->credential_role); + credential_addr = MLX5_ADDR_OF(credential, ptr, credential); + memcpy(credential_addr, (void *)(attr->credential), + MLX5_CRYPTO_CREDENTIAL_SIZE); + credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), + out, sizeof(out)); + if (credential_obj->obj == NULL) { + rte_errno = errno; + DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); + mlx5_free(credential_obj); + return NULL; + } + credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + return credential_obj; +} + /** * Create general object of type CRYPTO_LOGIN using DevX API. * @@ -2551,7 +2602,7 @@ mlx5_devx_cmd_create_crypto_login_obj(void *ctx, attr->session_import_kek_ptr); credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); memcpy(credential_addr, (void *)(attr->credential), - MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE); + MLX5_CRYPTO_CREDENTIAL_SIZE); crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out)); if (crypto_login_obj->obj == NULL) { diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 709e28bfba..811e7a1462 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -143,6 +143,7 @@ struct mlx5_hca_attr { uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ uint32_t dek:1; /* General obj type DEK is supported. */ uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ + uint32_t credential:1; /* General obj type CREDENTIAL supported. */ uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; @@ -459,13 +460,20 @@ struct mlx5_devx_import_kek_attr { uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; }; -#define MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE 48 +#define MLX5_CRYPTO_CREDENTIAL_SIZE 48 + +struct mlx5_devx_credential_attr { + uint64_t modify_field_select; + uint32_t state:8; + uint32_t credential_role:8; + uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; +}; struct mlx5_devx_crypto_login_attr { uint64_t modify_field_select; uint32_t credential_pointer:24; uint32_t session_import_kek_ptr:24; - uint8_t credential[MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE]; + uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; }; /* mlx5_devx_cmds.c */ @@ -629,6 +637,11 @@ struct mlx5_devx_obj * mlx5_devx_cmd_create_import_kek_obj(void *ctx, struct mlx5_devx_import_kek_attr *attr); +__rte_internal +struct mlx5_devx_obj * +mlx5_devx_cmd_create_credential_obj(void *ctx, + struct mlx5_devx_credential_attr *attr); + __rte_internal struct mlx5_devx_obj * mlx5_devx_cmd_create_crypto_login_obj(void *ctx, diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index a9dcbfa63c..432c8fdb63 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1187,6 +1187,8 @@ enum { (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) @@ -2490,6 +2492,7 @@ enum { MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, + MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, @@ -2603,6 +2606,26 @@ struct mlx5_ifc_create_import_kek_in_bits { struct mlx5_ifc_import_kek_bits import_kek; }; +enum { + MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, + MLX5_CREDENTIAL_ROLE_USER = 0x1, +}; + +struct mlx5_ifc_credential_bits { + u8 modify_field_select[0x40]; + u8 state[0x8]; + u8 reserved_at_48[0x10]; + u8 credential_role[0x8]; + u8 reserved_at_60[0x1a0]; + u8 credential[0x180]; + u8 reserved_at_380[0x480]; +}; + +struct mlx5_ifc_create_credential_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_credential_bits credential; +}; + struct mlx5_ifc_crypto_login_bits { u8 modify_field_select[0x40]; u8 reserved_at_40[0x48]; diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 00df37e81a..1885cb8f6a 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -29,6 +29,7 @@ INTERNAL { mlx5_devx_cmd_create_geneve_tlv_option; mlx5_devx_cmd_create_dek_obj; mlx5_devx_cmd_create_import_kek_obj; + mlx5_devx_cmd_create_credential_obj; mlx5_devx_cmd_create_crypto_login_obj; mlx5_devx_cmd_destroy; mlx5_devx_cmd_flow_counter_alloc; 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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT041.mail.protection.outlook.com (10.13.172.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4087.27 via Frontend Transport; Thu, 29 Apr 2021 15:45:07 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:45:05 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:33 +0300 Message-ID: <20210429154335.2820028-15-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a14cef10-cf10-4860-aba9-08d90b25c40c X-MS-TrafficTypeDiagnostic: BN8PR12MB3586: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1751; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:07.9276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a14cef10-cf10-4860-aba9-08d90b25c40c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3586 Subject: [dpdk-dev] [PATCH v2 14/16] common/mlx5: add crypto register structs and defs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled Encryption key management requires use of several related registers. This patch adds the relevant structs and values, according to PRM definitions. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 432c8fdb63..c2cd2d9f70 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3307,6 +3307,10 @@ enum { enum { MLX5_REGISTER_ID_MTUTC = 0x9055, + MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, + MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, + MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, + MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, }; struct mlx5_ifc_register_mtutc_bits { @@ -3324,6 +3328,43 @@ struct mlx5_ifc_register_mtutc_bits { #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 +struct mlx5_ifc_crypto_operational_register_bits { + u8 wrapped_crypto_operational[0x1]; + u8 reserved_at_1[0x1b]; + u8 kek_size[0x4]; + u8 reserved_at_20[0x20]; + u8 credential[0x140]; + u8 kek[0x100]; + u8 reserved_at_280[0x180]; +}; + +struct mlx5_ifc_crypto_commissioning_register_bits { + u8 token[0x1]; /* TODO: add size after PRM update */ +}; + +struct mlx5_ifc_import_kek_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_import_kek_bits import_kek_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 import_kek_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +struct mlx5_ifc_credential_handle_register_bits { + struct mlx5_ifc_crypto_login_bits crypto_login_object; + struct mlx5_ifc_credential_bits credential_object; + u8 reserved_at_200[0x4]; + u8 write_operation[0x4]; + u8 credential_id[0x18]; + u8 reserved_at_220[0xe0]; +}; + +enum { + MLX5_REGISTER_ADD_OPERATION = 0x1, + MLX5_REGISTER_DELETE_OPERATION = 0x2, +}; + struct mlx5_ifc_parse_graph_arc_bits { u8 start_inner_tunnel[0x1]; u8 reserved_at_1[0x7]; From patchwork Thu Apr 29 15:43:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92430 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 21346A0547; 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Thu, 29 Apr 2021 15:45:12 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:45:09 +0000 From: Matan Azrad To: CC: , , , "Dekel Peled" Date: Thu, 29 Apr 2021 18:43:34 +0300 Message-ID: <20210429154335.2820028-16-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b795937b-4648-4847-fac0-08d90b25c6a9 X-MS-TrafficTypeDiagnostic: SN6PR12MB2702: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1303; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6jjFx9bDgPAODWLG7iny5yzdfnhWJeBV6VrELhta4xDNGmbpV4mfk291W2mfSbmOFyYUlLqojHMPpmc1f1nIxufhoEjXt4UmelUQPCo/d/pzD3dAPhcyv+0+tpcvsZWOX94eam2fywkICa1qCp1XOSL60EdPkvbmrAMeeoE0U5abZv4CJ8v04t1RiiZ//nhghJhSrKgj1hOumAyXZOspJaQ86YybT4d7AfivMDWyvkuW/4Q1TgF91ewxlzaWejAnTCcLtOv8petC4C5wVNOGD9x7SG6ATqQ2lGY1uo8pFfSWf2HX/HjS+ZBGPr6536Zm4VWaNQxxr6uzq0/aNUwGDujXpCmuXBfTmbbYUYvB3827fnTtR5wmRlVikzxrlmfIDtvQaF7BxUOPwn10q07x4sQE1oZhbdmqhGtYVJhi54fDcwuVnJhG4i4zZZK4WuGYwF7l2NhcVpZ2zZWyUdWk+zC8YMchcaFdYeLBLv8xIcCvCDT6seob01omP2pqWhvD4F5Yn+Cpkwr44YC/nAPGUbHpwZJtZ8k2lIWgTxucH+UO2rpJSRfhfwgd+rug13Oqt32Kge9NRgzSuoFtcg9tlvftX5RZPifWFKhuvj+5kMo6fX5BK7D5uZAGRbPl0dZShh6pImE0ZyTi/6eaQyIGVujAKXNxILFBkB3HdOTZG5U= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(396003)(136003)(39860400002)(346002)(36840700001)(46966006)(36906005)(336012)(186003)(83380400001)(55016002)(356005)(7636003)(478600001)(1076003)(6666004)(2906002)(107886003)(316002)(86362001)(82310400003)(82740400003)(16526019)(7696005)(426003)(54906003)(26005)(5660300002)(70586007)(8676002)(36860700001)(36756003)(70206006)(4326008)(8936002)(6916009)(2616005)(6286002)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:12.3290 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b795937b-4648-4847-fac0-08d90b25c6a9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2702 Subject: [dpdk-dev] [PATCH v2 15/16] common/mlx5: support register write access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dekel Peled This patch adds support of write operation to NIC registers. Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 67 +++++++++++++++++++++++++++- drivers/common/mlx5/mlx5_devx_cmds.h | 4 ++ drivers/common/mlx5/version.map | 21 ++++++--- 3 files changed, 83 insertions(+), 9 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index c0a0853c3a..0b421933ce 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -12,7 +12,6 @@ #include "mlx5_common_log.h" #include "mlx5_malloc.h" - /** * Perform read access to the registers. Reads data from register * and writes ones to the specified buffer. @@ -61,7 +60,7 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, if (status) { int syndrome = MLX5_GET(access_register_out, out, syndrome); - DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " + DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " "status %x, syndrome = %x", reg_id, status, syndrome); return -1; @@ -74,6 +73,70 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, return rc; } +/** + * Perform write access to the registers. + * + * @param[in] ctx + * Context returned from mlx5 open_device() glue function. + * @param[in] reg_id + * Register identifier according to the PRM. + * @param[in] arg + * Register access auxiliary parameter according to the PRM. + * @param[out] data + * Pointer to the buffer containing data to write. + * @param[in] dw_cnt + * Buffer size in double words (32bit units). + * + * @return + * 0 on success, a negative value otherwise. + */ +int +mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, + uint32_t *data, uint32_t dw_cnt) +{ + uint32_t in[MLX5_ST_SZ_DW(access_register_in) + + MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; + uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; + int status, rc; + void *ptr; + + MLX5_ASSERT(data && dw_cnt); + MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); + if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { + DRV_LOG(ERR, "Data to write exceeds max size"); + return -1; + } + MLX5_SET(access_register_in, in, opcode, + MLX5_CMD_OP_ACCESS_REGISTER_USER); + MLX5_SET(access_register_in, in, op_mod, + MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); + MLX5_SET(access_register_in, in, register_id, reg_id); + MLX5_SET(access_register_in, in, argument, arg); + ptr = MLX5_ADDR_OF(access_register_in, in, register_data); + memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); + rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); + + rc = mlx5_glue->devx_general_cmd(ctx, in, + MLX5_ST_SZ_BYTES(access_register_in) + + dw_cnt * sizeof(uint32_t), + out, sizeof(out)); + if (rc) + goto error; + status = MLX5_GET(access_register_out, out, status); + if (status) { + int syndrome = MLX5_GET(access_register_out, out, syndrome); + + DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " + "status %x, syndrome = %x", + reg_id, status, syndrome); + return -1; + } + return 0; +error: + rc = (rc > 0) ? -rc : rc; + return rc; +} + /** * Allocate flow counters via devx interface. * diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 811e7a1462..ce570ad28a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -566,6 +566,10 @@ __rte_internal int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, uint32_t *data, uint32_t dw_cnt); +__rte_internal +int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, + uint32_t arg, uint32_t *data, uint32_t dw_cnt); + __rte_internal struct mlx5_devx_obj * mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 1885cb8f6a..1dc2d063ff 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -13,8 +13,17 @@ INTERNAL { mlx5_dev_to_pci_addr; # WINDOWS_NO_EXPORT mlx5_devx_cmd_alloc_pd; + mlx5_devx_alloc_uar; + mlx5_devx_cmd_create_cq; + mlx5_devx_cmd_create_credential_obj; + mlx5_devx_cmd_create_crypto_login_obj; + mlx5_devx_cmd_create_dek_obj; mlx5_devx_cmd_create_flex_parser; + mlx5_devx_cmd_create_flow_hit_aso_obj; + mlx5_devx_cmd_create_flow_meter_aso_obj; + mlx5_devx_cmd_create_geneve_tlv_option; + mlx5_devx_cmd_create_import_kek_obj; mlx5_devx_cmd_create_qp; mlx5_devx_cmd_create_rq; mlx5_devx_cmd_create_rqt; @@ -24,13 +33,6 @@ INTERNAL { mlx5_devx_cmd_create_tis; mlx5_devx_cmd_create_virtio_q_counters; # WINDOWS_NO_EXPORT mlx5_devx_cmd_create_virtq; - mlx5_devx_cmd_create_flow_hit_aso_obj; - mlx5_devx_cmd_create_flow_meter_aso_obj; - mlx5_devx_cmd_create_geneve_tlv_option; - mlx5_devx_cmd_create_dek_obj; - mlx5_devx_cmd_create_import_kek_obj; - mlx5_devx_cmd_create_credential_obj; - mlx5_devx_cmd_create_crypto_login_obj; mlx5_devx_cmd_destroy; mlx5_devx_cmd_flow_counter_alloc; mlx5_devx_cmd_flow_counter_query; @@ -51,12 +53,17 @@ INTERNAL { mlx5_devx_cmd_queue_counter_alloc; # WINDOWS_NO_EXPORT mlx5_devx_cmd_queue_counter_query; # WINDOWS_NO_EXPORT mlx5_devx_cmd_register_read; + mlx5_devx_cmd_register_write; mlx5_devx_cmd_wq_query; # WINDOWS_NO_EXPORT mlx5_devx_get_out_command_status; mlx5_devx_alloc_uar; # WINDOWS_NO_EXPORT + mlx5_devx_cq_create; mlx5_devx_cq_destroy; + + mlx5_devx_get_out_command_status; + mlx5_devx_rq_create; mlx5_devx_rq_destroy; mlx5_devx_sq_create; From patchwork Thu Apr 29 15:43:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matan Azrad X-Patchwork-Id: 92431 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B74A0A0547; Thu, 29 Apr 2021 17:46:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C2A1341360; Thu, 29 Apr 2021 17:45:28 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2064.outbound.protection.outlook.com [40.107.236.64]) by mails.dpdk.org (Postfix) with ESMTP id 3920B41352 for ; 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Thu, 29 Apr 2021 15:45:13 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Apr 2021 15:45:10 +0000 From: Matan Azrad To: CC: , , Date: Thu, 29 Apr 2021 18:43:35 +0300 Message-ID: <20210429154335.2820028-17-matan@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210429154335.2820028-1-matan@nvidia.com> References: <20210408204849.9543-1-shirik@nvidia.com> <20210429154335.2820028-1-matan@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 54457a1e-2292-402c-fcdc-08d90b25c782 X-MS-TrafficTypeDiagnostic: BY5PR12MB4870: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Tl9r84fStyXAoBYMGjHZB+ZpZkTcveSQ/UbHz+bG3v5lHF0bIJxl6Z6pJZJ0qjOhq8ZUYbd6K2009kKc13vScS0eUaWATWFONx9Ex8HabcqDivuiXGJUngQ6k65j5wrS+HK4RJZ/0Bm2aXldZj450U11K0M6KhKzVs88Qyi2nvVBZAq6OrzkES8perYaEh7viG40nYGloXHaeT2M4pYNRTwibKEz1bn1TOd34dPmhUOUi/EmGj56+Fck1nO/5hoe+nAmCNWk4Ga9ZNIGhSabYrlNUqneOP/jfE+tJR7st/gTbMHvZonEzWcfZ+m5TeG3vOBh1MdZwWjFWjdXaIip0NDJFhyneN3DaLeK/FQwwlRE0332PH5Yer2cPCUP1VZy7kxTB3G+YBlkhBB1df7y4UuBZUwQeXj0wPrK/kufZXeclUb6JU9CzYg7WbAa/hdjMs6257Pf1q4z84ktYKeG14wToax++H1KPDiKO8MKiJ3A7VHgV7kMMnPzFQzH+ePT+ryeDB/9dyplTe1Tr0v9Yc8tp25rqfQP8GWfO5rmA6bYZtyQ/+965HBECxvYwNTX/aBQ8N9L6VE8vep3RhIsU2ROAWRhR/dQSa10ZfgP9ExiEuDASUdyk3nyK28FPj6Cr6VMbKpOeGHvpXH8vRZbTDxqlXSih5nwpgh/x9JwpF0= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(396003)(346002)(39860400002)(136003)(46966006)(36840700001)(186003)(70206006)(426003)(356005)(16526019)(4326008)(107886003)(6286002)(336012)(70586007)(55016002)(47076005)(2906002)(54906003)(478600001)(36756003)(316002)(6916009)(36906005)(2616005)(86362001)(8936002)(82740400003)(6666004)(7636003)(82310400003)(5660300002)(36860700001)(8676002)(26005)(1076003)(7696005)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2021 15:45:13.7462 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54457a1e-2292-402c-fcdc-08d90b25c782 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4870 Subject: [dpdk-dev] [PATCH v2 16/16] common/mlx5: add UMR and RDMA write WQE defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Suanming Mou This patch adds the struct defining UMR and RDMA write WQEs. Signed-off-by: Suanming Mou Signed-off-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 187 +++++++++++++++++++++------------ 1 file changed, 121 insertions(+), 66 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index c2cd2d9f70..1ffee5fd56 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -412,6 +412,127 @@ struct mlx5_cqe_ts { uint8_t op_own; }; +struct mlx5_wqe_rseg { + uint64_t raddr; + uint32_t rkey; + uint32_t reserved; +} __rte_packed; + +#define MLX5_UMRC_IF_OFFSET 31u +#define MLX5_UMRC_KO_OFFSET 16u +#define MLX5_UMRC_TO_BS_OFFSET 0u + +struct mlx5_wqe_umr_cseg { + uint32_t if_cf_toe_cq_res; + uint32_t ko_to_bs; + uint64_t mkey_mask; + uint32_t rsvd1[8]; +} __rte_packed; + +struct mlx5_wqe_mkey_cseg { + uint32_t fr_res_af_sf; + uint32_t qpn_mkey; + uint32_t reserved2; + uint32_t flags_pd; + uint64_t start_addr; + uint64_t len; + uint32_t bsf_octword_size; + uint32_t reserved3[4]; + uint32_t translations_octword_size; + uint32_t res4_lps; + uint32_t reserved; +} __rte_packed; + +enum { + MLX5_BSF_SIZE_16B = 0x0, + MLX5_BSF_SIZE_32B = 0x1, + MLX5_BSF_SIZE_64B = 0x2, + MLX5_BSF_SIZE_128B = 0x3, +}; + +enum { + MLX5_BSF_P_TYPE_SIGNATURE = 0x0, + MLX5_BSF_P_TYPE_CRYPTO = 0x1, +}; + +enum { + MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, + MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, +}; + +enum { + MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, +}; + +enum { + MLX5_BLOCK_SIZE_512B = 0x1, + MLX5_BLOCK_SIZE_520B = 0x2, + MLX5_BLOCK_SIZE_4096B = 0x3, + MLX5_BLOCK_SIZE_4160B = 0x4, + MLX5_BLOCK_SIZE_1MB = 0x5, + MLX5_BLOCK_SIZE_4048B = 0x6, +}; + +#define MLX5_BSF_SIZE_OFFSET 30 +#define MLX5_BSF_P_TYPE_OFFSET 24 +#define MLX5_ENCRYPTION_ORDER_OFFSET 16 +#define MLX5_BLOCK_SIZE_OFFSET 24 + +struct mlx5_wqe_umr_bsf_seg { + /* + * bs_bpt_eo_es contains: + * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET + * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET + * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET + * es encryption_standard 4 bits at offset 0 + */ + uint32_t bs_bpt_eo_es; + uint32_t raw_data_size; + /* + * bsp_res contains: + * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET + * res reserved 24 bits + */ + uint32_t bsp_res; + uint32_t reserved0; + uint8_t xts_initial_tweak[16]; + /* + * res_dp contains: + * res reserved 8 bits + * dp dek_pointer 24 bits at offset 0 + */ + uint32_t res_dp; + uint32_t reserved1; + uint64_t keytag; + uint32_t reserved2[4]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +struct mlx5_umr_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_umr_cseg ucseg; + struct mlx5_wqe_mkey_cseg mkc; + union { + struct mlx5_wqe_dseg kseg[0]; + struct mlx5_wqe_umr_bsf_seg bsf[0]; + }; +} __rte_packed; + +struct mlx5_rdma_write_wqe { + struct mlx5_wqe_cseg ctr; + struct mlx5_wqe_rseg rseg; + struct mlx5_wqe_dseg dseg[0]; +} __rte_packed; + +#ifdef PEDANTIC +#pragma GCC diagnostic error "-Wpedantic" +#endif + /* GGA */ /* MMO metadata segment */ @@ -1096,72 +1217,6 @@ struct mlx5_ifc_create_mkey_in_bits { u8 klm_pas_mtt[][0x20]; }; -enum { - MLX5_BSF_SIZE_16B = 0x0, - MLX5_BSF_SIZE_32B = 0x1, - MLX5_BSF_SIZE_64B = 0x2, - MLX5_BSF_SIZE_128B = 0x3, -}; - -enum { - MLX5_BSF_P_TYPE_SIGNATURE = 0x0, - MLX5_BSF_P_TYPE_CRYPTO = 0x1, -}; - -enum { - MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, - MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, - MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, - MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, -}; - -enum { - MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, -}; - -enum { - MLX5_BLOCK_SIZE_512B = 0x1, - MLX5_BLOCK_SIZE_520B = 0x2, - MLX5_BLOCK_SIZE_4096B = 0x3, - MLX5_BLOCK_SIZE_4160B = 0x4, - MLX5_BLOCK_SIZE_1MB = 0x5, - MLX5_BLOCK_SIZE_4048B = 0x6, -}; - -#define MLX5_BSF_SIZE_OFFSET 30 -#define MLX5_BSF_P_TYPE_OFFSET 24 -#define MLX5_ENCRYPTION_ORDER_OFFSET 16 -#define MLX5_BLOCK_SIZE_OFFSET 24 - -struct mlx5_wqe_umr_bsf_seg { - /* - * bs_bpt_eo_es contains: - * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET - * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET - * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET - * es encryption_standard 4 bits at offset 0 - */ - uint32_t bs_bpt_eo_es; - uint32_t raw_data_size; - /* - * bsp_res contains: - * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET - * res reserved 24 bits - */ - uint32_t bsp_res; - uint32_t reserved0; - uint8_t xts_initial_tweak[16]; - /* - * res_dp contains: - * res reserved 8 bits - * dp dek_pointer 24 bits at offset 0 - */ - uint32_t res_dp; - uint32_t reserved1; - uint64_t keytag; - uint32_t reserved2[4]; -} __rte_packed; - enum { MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,