From patchwork Thu Apr 29 18:23:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Lingyu" X-Patchwork-Id: 92411 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 39A87A0547; Thu, 29 Apr 2021 13:49:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1FE10410DD; Thu, 29 Apr 2021 13:49:13 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id D69CB406FF for ; Thu, 29 Apr 2021 13:49:11 +0200 (CEST) IronPort-SDR: 2dXaaJmYLgitsCkM/9t5VzZslAz3VGlrwHaTbmADTLYqEpD6zECnEqQuHeHQ33g61+LOHCEIp4 MVdIcrdIP4qA== X-IronPort-AV: E=McAfee;i="6200,9189,9968"; a="177096772" X-IronPort-AV: E=Sophos;i="5.82,259,1613462400"; d="scan'208";a="177096772" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 04:49:10 -0700 IronPort-SDR: GysFv4JImGYac4yKWfIdp8zqA0UmIv+BANCg+uUYLd/HrAd9yH3zPB8Eyy98Z/ye50dYo/3/DH RQFl4XQmLRCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,259,1613462400"; d="scan'208";a="526914717" Received: from dpdk-liulingy-1.sh.intel.com ([10.67.118.243]) by fmsmga001.fm.intel.com with ESMTP; 29 Apr 2021 04:49:10 -0700 From: Lingyu Liu To: dev@dpdk.org Cc: Lingyu Liu Date: Thu, 29 Apr 2021 18:23:43 +0000 Message-Id: <20210429182343.52628-1-lingyu.liu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v1] net/ixgbe: configure EXVET_T register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" According to X550 datasheet (section 8.2.1.2), when setting vlan tpid, the register EXVET_T on X550 NICs also need to be configured. Signed-off-by: Lingyu Liu --- drivers/net/ixgbe/base/ixgbe_type.h | 1 + drivers/net/ixgbe/ixgbe_ethdev.c | 33 +++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index bc927a3..8e22be7 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -151,6 +151,7 @@ #define IXGBE_TCPTIMER 0x0004C #define IXGBE_CORESPARE 0x00600 #define IXGBE_EXVET 0x05078 +#define IXGBE_EXVET_T 0x08224 /* NVM Registers */ #define IXGBE_EEC 0x10010 diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index dcd7291..b9c89e8 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -1925,6 +1925,39 @@ ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, /* Only the high 16-bits is valid */ IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << IXGBE_EXVET_VET_EXT_SHIFT); + /* For X550, additional register need be set*/ + switch (hw->device_id) { + case IXGBE_DEV_ID_X550T: + case IXGBE_DEV_ID_X550T1: + case IXGBE_DEV_ID_X550EM_A_KR: + case IXGBE_DEV_ID_X550EM_A_KR_L: + case IXGBE_DEV_ID_X550EM_A_SFP_N: + case IXGBE_DEV_ID_X550EM_A_SGMII: + case IXGBE_DEV_ID_X550EM_A_SGMII_L: + case IXGBE_DEV_ID_X550EM_A_10G_T: + case IXGBE_DEV_ID_X550EM_A_QSFP: + case IXGBE_DEV_ID_X550EM_A_QSFP_N: + case IXGBE_DEV_ID_X550EM_A_SFP: + case IXGBE_DEV_ID_X550EM_A_1G_T: + case IXGBE_DEV_ID_X550EM_A_1G_T_L: + case IXGBE_DEV_ID_X550EM_X_KX4: + case IXGBE_DEV_ID_X550EM_X_KR: + case IXGBE_DEV_ID_X550EM_X_SFP: + case IXGBE_DEV_ID_X550EM_X_10G_T: + case IXGBE_DEV_ID_X550EM_X_1G_T: + case IXGBE_DEV_ID_X550EM_X_XFI: + case IXGBE_DEV_ID_X550_VF_HV: + case IXGBE_DEV_ID_X550_VF: + case IXGBE_DEV_ID_X550EM_A_VF: + case IXGBE_DEV_ID_X550EM_A_VF_HV: + case IXGBE_DEV_ID_X550EM_X_VF: + case IXGBE_DEV_ID_X550EM_X_VF_HV: + IXGBE_WRITE_REG(hw, IXGBE_EXVET_T, (uint32_t)tpid << + IXGBE_EXVET_VET_EXT_SHIFT); + break; + default: + break; + } } else { reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;