From patchwork Wed Apr 28 17:59:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 92341 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F07F9A0A0A; Wed, 28 Apr 2021 19:59:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EF7E341172; Wed, 28 Apr 2021 19:59:33 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2080.outbound.protection.outlook.com [40.107.237.80]) by mails.dpdk.org (Postfix) with ESMTP id D5E50410FE for ; Wed, 28 Apr 2021 19:59:31 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UwddsrjrwEkZITx8nHc+PeUKLiEJCyIw9Rgw5guhMd2+gbvshI2NuJOuaLbZU2xlajcLXZsyzSKjixGW30/1Qi8xuPhEdMSD7Y5lhKZyxXU3zQIljAqpe13VRNKsJeDjQ1BZ7CEUEQN1bbPjPjCOGmjbaVzASF4urKZe4IXvfyBfXN0ybH0XFqnhbeiR4zhOGCG8+mpCqtoBYgTVR5HWRqSuREMAngfWVqL7V0tEk/zt5HYpmJVJ5mZmOf3Yr1Tmv0VmEuGvS8ox8dWNTdTEmoAveeJZj92ogVlEKQyWvIkXQohTJxHcdNrPQa1E7WnzJOlHjgZUvX3Z/WVXR3ROAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IkM9DYmaztXvLkqz3wk9EjfqDRNeoLyml3k1n7eNCQA=; b=n+CjPpY/cZ1AAusQCDsUltvjSSFKlhW08U3BAnKlCyctCR6tKHjEKVGJA9jgk9+2Q94RtPZnYLylhRVGZTZLX7mnyu6YijhlXn2wpvWfktvUqQcwhiZnSAocq2ah6dz9P4q5ldqoGDYcQE/lGcJEWit8Vk9DTlxH6W3q0a+BYQbyYaZV2fT/x8iZM1ZKEteSj0s2WIdkluun15iWHFkv6ySNEVG5ddDxIC9mpHDr3aVgkjHL6ePuu3+XsZ8EhzvS1goXSLpRMBKG4Z+O7UC3/RvFqwcTemweK4CilY2iFErJTM/+EshInFCvPJ63EYh+b0K3M0WqFoV3f0M3HtZkTA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=oktetlabs.ru smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IkM9DYmaztXvLkqz3wk9EjfqDRNeoLyml3k1n7eNCQA=; b=VPokkytFVJiKwy9apgZ1pH2mUKOqu5SWZwRev//beehNM5z6ENUGMYS1tEzPBR7vv7xMd639UD8nY2VYKx1GYzAhYiqQjcY/4AMu6s7xBE8VxSmNHBG2WfBZrOjI+STo76U6unrPzkPcZOm6h1xqaewCWZPxMP6WFGsDbBb8jZOi8BtmrD9VHYqEJfXC8CSt9o8MFU2tbxjI/u8YagVl8pTv+g4rqs9EMbMmtJIAqpv6VATY0zEXPixCSTAScGhB5Jpzx/wUaOQNAXwuexzyWnD96riiG4jeyMmco5pNCnRRZ3bDmE4IyOzYd2lBlmdcqNfcrRRa0Afqsq3xHgeDvw== Received: from DM5PR05CA0018.namprd05.prod.outlook.com (2603:10b6:3:d4::28) by DM5PR12MB2584.namprd12.prod.outlook.com (2603:10b6:4:b0::37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.21; Wed, 28 Apr 2021 17:59:30 +0000 Received: from DM6NAM11FT034.eop-nam11.prod.protection.outlook.com (2603:10b6:3:d4:cafe::3f) by DM5PR05CA0018.outlook.office365.com (2603:10b6:3:d4::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; Wed, 28 Apr 2021 17:59:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; oktetlabs.ru; dkim=none (message not signed) header.d=none;oktetlabs.ru; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT034.mail.protection.outlook.com (10.13.173.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4065.21 via Frontend Transport; Wed, 28 Apr 2021 17:59:29 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 28 Apr 2021 17:59:26 +0000 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko , "Thomas Monjalon" , Ferruh Yigit , "Andrew Rybchenko" , Ajit Khaparde Date: Wed, 28 Apr 2021 20:59:03 +0300 Message-ID: <20210428175906.21387-2-getelson@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210428175906.21387-1-getelson@nvidia.com> References: <20210428175906.21387-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3c7c48f3-8f17-41ca-b9e9-08d90a6f5e77 X-MS-TrafficTypeDiagnostic: DM5PR12MB2584: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GJCtXv8DOSDtnEf9UPypTPgxyfqInrvQa0dkr3LHg9NgZN8lO49gyPfYrazylQg+XJPEJPF7y5L1RQDn72VJnTI+/2Q2BatQFfLTMDGwDWqfRzxSTDoJwdzggq73jyvELtP2VMqwSCfc9ZnHqLUMKlsjOQoc1PFvLlFXk7bNYfUAiIYaVNccGBOPlzh8xWwFwEljoPzK7H0iB5FiBK1h73V3NyRFXwJuYBugxVdvZMq3tgpM8iAiKmp6q/Xna1BdTTE1X7+XIaHFlS/HFZQ0/U2AwpLYhdTNG2C1RWugCcIuASNktOx3lcT31n302tx8gLdHVdwNmnQSLOWTHKNLHYL79NF0nONkLj+7m78u0o2u/tK0kQ/nobL9kCKGAfbhwQ7DI8knLJk0jcPZkNcthzE7oxvTDifbz1NI99jiHDgKE6PTfo6tJLgG8ednhYVxFFHUTqd6Dp32bnBfLBtcmR+YiBXQ0dFUR1HRoGrLpj8kio6kqaQepewv+mbVQ3UQGzU9yanSZwLZB63h0B06zOxv9nc3VktGbTPLQ+JagJb/9tGoK3PMWy5pdFP4zwMpAH7lgDJBFIzYwUNzrpozRYkGPWWaOrjH9zHX2whGtmTTNLZM0RVkXwkaQviyRXMJIw65eSR6U7mVqJ/lsuhy9NX0duVuETBb85KjIh7NZy0= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(346002)(376002)(136003)(39860400002)(46966006)(36840700001)(7636003)(6286002)(36860700001)(2616005)(82740400003)(2906002)(6666004)(55016002)(336012)(86362001)(478600001)(356005)(6916009)(1076003)(5660300002)(70586007)(36906005)(316002)(8676002)(70206006)(186003)(426003)(16526019)(47076005)(36756003)(82310400003)(4326008)(7696005)(26005)(8936002)(54906003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2021 17:59:29.1178 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c7c48f3-8f17-41ca-b9e9-08d90a6f5e77 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2584 Subject: [dpdk-dev] [PATCH 1/4] ethdev: fix integrity flow item X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add integrity item definition to the rte_flow_desc_item array. The new entry allows RTE conv API to work with the new flow item. Add bitmasks to the integrity item value. The masks allow to query multiple integrity filters in a single compare operation. Fixes: b10a421a1f3b ("ethdev: add packet integrity check flow rules") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- lib/ethdev/rte_flow.c | 1 + lib/ethdev/rte_flow.h | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c index c7c7108933..8cb7a069c8 100644 --- a/lib/ethdev/rte_flow.c +++ b/lib/ethdev/rte_flow.c @@ -98,6 +98,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = { MK_FLOW_ITEM(PFCP, sizeof(struct rte_flow_item_pfcp)), MK_FLOW_ITEM(ECPRI, sizeof(struct rte_flow_item_ecpri)), MK_FLOW_ITEM(GENEVE_OPT, sizeof(struct rte_flow_item_geneve_opt)), + MK_FLOW_ITEM(INTEGRITY, sizeof(struct rte_flow_item_integrity)), MK_FLOW_ITEM(CONNTRACK, sizeof(uint32_t)), }; diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index 94c8c1ccc8..cf72999cd9 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -1738,6 +1738,15 @@ struct rte_flow_item_integrity { }; }; +#define RTE_FLOW_ITEM_INTEGRITY_PKT_OK (1ULL << 0) +#define RTE_FLOW_ITEM_INTEGRITY_L2_OK (1ULL << 1) +#define RTE_FLOW_ITEM_INTEGRITY_L3_OK (1ULL << 2) +#define RTE_FLOW_ITEM_INTEGRITY_L4_OK (1ULL << 3) +#define RTE_FLOW_ITEM_INTEGRITY_L2_CRC_OK (1ULL << 4) +#define RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK (1ULL << 5) +#define RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK (1ULL << 6) +#define RTE_FLOW_ITEM_INTEGRITY_L3_LEN_OK (1ULL << 7) + #ifndef __cplusplus static const struct rte_flow_item_integrity rte_flow_item_integrity_mask = { From patchwork Wed Apr 28 17:59:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 92342 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D1BACA0A0A; Wed, 28 Apr 2021 19:59:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3EA51412C1; Wed, 28 Apr 2021 19:59:36 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2060.outbound.protection.outlook.com [40.107.92.60]) by mails.dpdk.org (Postfix) with ESMTP id 01C7241101 for ; Wed, 28 Apr 2021 19:59:32 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l6T0c2T5zporchh9EC5Y/m30nNcmF7uSTOwXT9OmScFsWIwFr+lR6JC8K/nKFjfeIgodVpkItcaYPDSFNR98rWZjNdHmaGQfhIHXFHawrBYW+rAM6VlhgutD1FysDZl7k7nwRGkqWO5uJXG5L5U4wTuamEuQZIlTuKEAHpYN2x84YhXCh9/f/0tv7hMa2CMh4zp0WG6UkQbf/sr4Ga09YSvNF7GxlZlI0KyOE8D+JTPh31JnzDC2CP/NUtzZndifHRdoBa4RPC7l6Aij5WUcmyjQUFA3MT370sF196a85A8oO9OwHZzvZ7UlP7xcUtThIsllPb9oUZxyAp20iZZFrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+Bm1nDhAv2hov74gtoCFTzH72BaLb2NIbahinLVYfgM=; b=XSyJnkv9zp2JRhgYyWqkDC8/QcnvF3oXpl3wSDbsFMkjA3j223F/leG2HGMFRkWzjwzeqhp0zfYXwQzaIkqIqqkwD0BcYLi3Hd/Nd60nNmXRnq/rj1Kd9UhCXYhnH15m9d+i5eTGHaa/STHeHCRSllVBPzPw8TBU3l/t76Qz9G6qM0AI57X9gGB3tGcKB+8omlhL90qRU5trZP4ta4zqh0pImAQRSiXoKPtCEurzV3SeLn9qIKG2bBXR+AqhnSPOakgc8x9MSQEFmCQDOvTwJsZtpS3IaZH6xcXVgVhYASHmDS/oQkRoQUIfSaKYaph18XKfQYJumPigxKPEUgACqg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+Bm1nDhAv2hov74gtoCFTzH72BaLb2NIbahinLVYfgM=; b=cYs4VuW3yN4KO4koojb6HhEB0kAHG5BLwgGu8J5QU6VTnFWuYffUp4k6Ozg4DH7kVtZO9jvbgB+GIrl7uYDqEahRtYE48RPVR/pFTeTwJRdlF1e+4ECVg2EVloV8wGVLoT/UGR92c6Lf7cWMZ/sXZsgAR/l1FjoOS+3wObxfhDQP5aw4N1kSHNSseYqi9NttIMoWPUmw788IrHn7o3WusB3+Lo3bG0DENzSufy8X2BqF98BL82UCI+btdxuI8cv7jM7FtcefBZ4+0mN2SXgjMAe72z3FVC2HUKD+026C06bS/YsUBWqzAhobagpe3Pi3t0fEfufmopRoNQBojfmLNA== Received: from DM5PR16CA0030.namprd16.prod.outlook.com (2603:10b6:4:15::16) by DM8PR12MB5477.namprd12.prod.outlook.com (2603:10b6:8:35::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.21; Wed, 28 Apr 2021 17:59:31 +0000 Received: from DM6NAM11FT014.eop-nam11.prod.protection.outlook.com (2603:10b6:4:15:cafe::a9) by DM5PR16CA0030.outlook.office365.com (2603:10b6:4:15::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.21 via Frontend Transport; Wed, 28 Apr 2021 17:59:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT014.mail.protection.outlook.com (10.13.173.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4065.21 via Frontend Transport; Wed, 28 Apr 2021 17:59:31 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 28 Apr 2021 17:59:29 +0000 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko , "Shahaf Shuler" Date: Wed, 28 Apr 2021 20:59:04 +0300 Message-ID: <20210428175906.21387-3-getelson@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210428175906.21387-1-getelson@nvidia.com> References: <20210428175906.21387-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7a280359-8d86-49a1-cda9-08d90a6f5fed X-MS-TrafficTypeDiagnostic: DM8PR12MB5477: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: va6nEWCKLhBlDEMxak4ppl19sjp2FYdVRL3XluK7D/5I0RZ5EC6h0dHE337yX/dxoPV3nhozvm1N3JQ0Ot0FnfSDbpR+Tteaec2PtQX2eHd90IHwK1j7IlZsayCNXDVhgeww0e+7lyfEZwRc8wuvfcU6/sofBkdPS/nHcgYSmPeNCXsfDfRJa3u0oytqtmouK+WP9X74Gm4Nk9lphSzPHUsxCjBjgjDYNbtZndxcxOoE5t4rdfxziLOOtFIQyoQ/syQlxGTioFUEjaU+ZomNhTohnw+LzbKBpf+u+Rx8PIWhxTruvdjGmskSaWqsNTU01zB6LRi1NqdnsW+GUkBlu2ZHjuJJiZlOorK45poC7wqfmSaBCwLrzDNXVyFV9g69+bur1Yw641RhPa831eOoNeaxLCy9A5XrypqO9FZk128xXsWu8FngUrFdlAznHi416iAXgJJ7rtqw4Q9MxxGPD+hS92rXY+gNrx9tB8EL5fOnLRMXTLp/fuB2LWRpmT5M0Y2171ua+ldkcF6+rufaREHKNFuUnNBtx88CersiPfaOmRIs7LRAQCZVUc/Jpkp4uOw2eSMdd6pRvi8T5V11smy9QKEg92kzZToTlHlsgebmxfTocpKtLGKg/drj9vGyr8yCyzYvyrbUG4QF13kU4QIPnSrbl8LHutRoGdA3j/Y= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(396003)(376002)(136003)(346002)(36840700001)(46966006)(54906003)(36906005)(16526019)(36756003)(82310400003)(70206006)(6286002)(356005)(86362001)(107886003)(336012)(1076003)(7636003)(70586007)(316002)(55016002)(186003)(83380400001)(82740400003)(7696005)(2616005)(47076005)(2906002)(6666004)(4326008)(5660300002)(426003)(36860700001)(26005)(6916009)(8936002)(8676002)(478600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2021 17:59:31.5674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a280359-8d86-49a1-cda9-08d90a6f5fed X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5477 Subject: [dpdk-dev] [PATCH 2/4] net/mlx5: update PRM definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add integrity and IPv4 IHL bits to PRM file. Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 31 ++++++++++++++++++++---- drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 35 ++++++++++++++++++++++++++-- 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 6c6f4391a1..3d3994e575 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -626,6 +626,29 @@ mlx5_devx_cmd_create_flex_parser(void *ctx, return parse_flex_obj; } +static int +mlx5_devx_query_pkt_integrity_match(void *hcattr) +{ + return MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.inner_l3_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.inner_l4_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.outer_l3_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.outer_l4_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive + .inner_ipv4_checksum_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.inner_l4_checksum_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive + .outer_ipv4_checksum_ok) && + MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.outer_l4_checksum_ok); +} + /** * Query HCA attributes. * Using those attributes we can check on run time if the device @@ -823,10 +846,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, return -1; } hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); - attr->log_max_ft_sampler_num = - MLX5_GET(flow_table_nic_cap, - hcattr, flow_table_properties.log_max_ft_sampler_num); - + attr->log_max_ft_sampler_num = MLX5_GET + (flow_table_nic_cap, hcattr, + flow_table_properties_nic_receive.log_max_ft_sampler_num); + attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); /* Query HCA offloads for Ethernet protocol. */ memset(in, 0, sizeof(in)); memset(out, 0, sizeof(out)); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index eee8fee107..b31a828383 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -142,6 +142,7 @@ struct mlx5_hca_attr { uint32_t cqe_compression:1; uint32_t mini_cqe_resp_flow_tag:1; uint32_t mini_cqe_resp_l3_l4_tag:1; + uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; int log_max_qp_sz; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index c6d8060bb9..903faccd56 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -778,7 +778,12 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits { u8 tcp_flags[0x9]; u8 tcp_sport[0x10]; u8 tcp_dport[0x10]; - u8 reserved_at_c0[0x18]; + u8 reserved_at_c0[0x10]; + u8 ipv4_ihl[0x4]; + u8 l3_ok[0x1]; + u8 l4_ok[0x1]; + u8 ipv4_checksum_ok[0x1]; + u8 l4_checksum_ok[0x1]; u8 ip_ttl_hoplimit[0x8]; u8 udp_sport[0x10]; u8 udp_dport[0x10]; @@ -1656,9 +1661,35 @@ struct mlx5_ifc_roce_caps_bits { u8 reserved_at_20[0x7e0]; }; +/* + * Table 1872 - Flow Table Fields Supported 2 Format + */ +struct mlx5_ifc_ft_fields_support_2_bits { + u8 reserved_at_0[0x14]; + u8 inner_ipv4_ihl[0x1]; + u8 outer_ipv4_ihl[0x1]; + u8 psp_syndrome[0x1]; + u8 inner_l3_ok[0x1]; + u8 inner_l4_ok[0x1]; + u8 outer_l3_ok[0x1]; + u8 outer_l4_ok[0x1]; + u8 psp_header[0x1]; + u8 inner_ipv4_checksum_ok[0x1]; + u8 inner_l4_checksum_ok[0x1]; + u8 outer_ipv4_checksum_ok[0x1]; + u8 outer_l4_checksum_ok[0x1]; +}; + struct mlx5_ifc_flow_table_nic_cap_bits { u8 reserved_at_0[0x200]; - struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_nic_receive; + struct mlx5_ifc_flow_table_prop_layout_bits + flow_table_properties_unused[5]; + u8 reserved_at_1C0[0x200]; + u8 header_modify_nic_receive[0x400]; + struct mlx5_ifc_ft_fields_support_2_bits + ft_field_support_2_nic_receive; }; union mlx5_ifc_hca_cap_union_bits { From patchwork Wed Apr 28 17:59:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 92343 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B46A9A0A0A; Wed, 28 Apr 2021 19:59:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E05C412C6; Wed, 28 Apr 2021 19:59:38 +0200 (CEST) Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-eopbgr750049.outbound.protection.outlook.com [40.107.75.49]) by mails.dpdk.org (Postfix) with ESMTP id D2E1540147 for ; Wed, 28 Apr 2021 19:59:35 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MjyyLQsVBcdcfolCpOHtMdHrc4B4DM1w0gaLncTw7JJo5Z2uD1WKWGSdWnxPP3qrDe/ONB+UoztSwGfjbmZc5LdBe0fmVEiaebvjz4y1al7OCw6nKx5duhXtq1LZ0BcldhckgWCGaBcTBeyDftQ8VOvZFhCRrewHDKtUDhA0ItL/H2awWSgF4cOFt06Rj+AoUD1NprOSGK9MgPTkHRytecnMFFFxWeiZkxigLtcoi9JPytfeQkdEsB48Av4wWtXUkGEP7MMYJDCXgx46A1yhPCpR+fAQaQrny+240QtJXiJY6FdDL17kNykeQu+RhRCNSF69jEJSPZYIzIfG9re1NA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2IIIKMkkAnigtUlpsxOxUmDvoeyTiA1my+gvWIjB5B8=; b=Y+bxmpF3mzJxD7Lxo3ij2YXz9CkyOZX5QQT0vXTvOXobR8aZh9o2dGcMNSvCktCmpkSghtOdzbfrK5IXBpWQLC8NYatFaOJaq8YHHnvEOdFG+vTHYpXYAugez8UZogA+XRakSY5B3oBy5UTgY8uNAseRaEuqYhAXbiVyN6ey9nx4dvBnWrFb4ukVb/qgmeO1B3CM8IsUGaWPpkUCZ4PtvFJkffYi+Q0/ZXDiVaE8fEPdRNsTXNDSbEs6WW5eyhQoGjhOeR3JVi6BACzcJY+PD8VIq/wC4LzSOhHAEeGS03W1efY6Tnm1kbHseAIAoahEo8+iYmCqF1uQrM8EQNcpQQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2IIIKMkkAnigtUlpsxOxUmDvoeyTiA1my+gvWIjB5B8=; b=l8XMwVKNGV+VXVM/xtbJzhpyvjvubamWzcWaAQvHfC/DF3mbGhq69iz2/eqMWJ6eJpJSLU02/jDb9hBSCk+LZmSXSWMIaMSDkIyXwATrOOx1gB08BW25v6gcCjlvX8UQOUJDfo0LWmv7s86NK3+xgppahcWN8RDfZ8Gdg6IQCGlAm2yjeYrRaYMMl042Afkp0QccmiHW2iuYPtoUU2yubgSZhHBSq3zRKL7uK5GIdHV/uOJRjkdKD47cAijOZigxfwoIvmYUaBoPP9DNlIVQ0G1qAzepcPG5TT79+MlIbkVuUKCuv8u0boH8kEmffxMl7a7/ixc8lKxifJgTa2zAww== Received: from DM6PR07CA0071.namprd07.prod.outlook.com (2603:10b6:5:74::48) by MWHPR12MB1262.namprd12.prod.outlook.com (2603:10b6:300:12::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.26; Wed, 28 Apr 2021 17:59:34 +0000 Received: from DM6NAM11FT056.eop-nam11.prod.protection.outlook.com (2603:10b6:5:74:cafe::1) by DM6PR07CA0071.outlook.office365.com (2603:10b6:5:74::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.27 via Frontend Transport; Wed, 28 Apr 2021 17:59:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT056.mail.protection.outlook.com (10.13.173.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4065.21 via Frontend Transport; Wed, 28 Apr 2021 17:59:33 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 28 Apr 2021 17:59:31 +0000 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko , "Shahaf Shuler" Date: Wed, 28 Apr 2021 20:59:05 +0300 Message-ID: <20210428175906.21387-4-getelson@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210428175906.21387-1-getelson@nvidia.com> References: <20210428175906.21387-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 21466011-daf6-47df-b005-08d90a6f615a X-MS-TrafficTypeDiagnostic: MWHPR12MB1262: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:240; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yDwn8/D7K87uIhkav6VuLWLlRbvzA/ZiolZB7u5m/vweozSSVNwyXcqHS+bFh5ZqTSDNYFsxVJpcmD/5XhG144P5yB/FPZQj3xbKWGT/mlt0yBv7VHqDYo4whcPzymH00am0TjQzv4qfpX4Pe1XEOlCfiE1sabI0jJNtKm/ghxS7ErDdJaj4eP1JeEsQ+ZqZfHVweOh2EiGaPjzJL8BCS7Hm37x4FdZRdzGc/Xl7i3Ubpba0hN774eTaNh8Rp1A50YpV+52tjsgbGj/JrFVjgxljv95HO0An9bAlEHKIQkWZaBFbUkf+wOFftRd43Gx5UpFHI/bYIL1S+FpvI9/sNnHjIrQEDa+Hf5H6GvRzYbzReB2+n9sDknLWeV6yNY0qjH/JNmAuGBt86ZwyiJ6oaS7fvF4JncSw0Zo1zlvhLDLwCxnIfxzdnp6y+ailyzuMZEgXJ7oNi9z9VoIwgsXT/lBHmxNbyAY9GOGgPbNMGEVazBsSgbo4+c5Pn8pl3ylBbN/hV3ejCQOWDGtPDlFbCedilT4GrTXDxV2GHHQP7UrO9BgHTPocC53oPss2AO2Ot6p9RvWTDC2lO4eOUi+r/o1Zm4XAqsXJGwIo1X0IS/UrNvcsXXjV6jiKcmpki+Jtewc7MOUMxyYK9s+J24LrVj000brSY1v0rDiM4GzO1Bo3D/12jV8QpxjHUU7sxFVB X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(39860400002)(346002)(376002)(136003)(36840700001)(46966006)(30864003)(55016002)(54906003)(70206006)(82310400003)(7636003)(82740400003)(8936002)(36756003)(83380400001)(5660300002)(70586007)(2616005)(4326008)(36860700001)(2906002)(316002)(6286002)(36906005)(1076003)(186003)(426003)(7696005)(8676002)(86362001)(26005)(16526019)(107886003)(47076005)(356005)(6666004)(6916009)(478600001)(336012)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2021 17:59:33.9137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21466011-daf6-47df-b005-08d90a6f615a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1262 Subject: [dpdk-dev] [PATCH 3/4] net/mlx5: support integrity flow item X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" MLX5 PMD supports the following integrity filters for outer and inner network headers: - l3_ok - l4_ok - ipv4_csum_ok - l4_csum_ok `level` values 0 and 1 reference outer headers. `level` > 1 reference inner headers. Flow rule items supplied by application must explicitly specify network headers referred by integrity item. For example: flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end … or flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end … Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.c | 25 ++++ drivers/net/mlx5/mlx5_flow.h | 26 ++++ drivers/net/mlx5/mlx5_flow_dv.c | 258 ++++++++++++++++++++++++++++++++ 3 files changed, 309 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 15ed5ec7a2..db9a251c68 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -8083,6 +8083,31 @@ mlx5_action_handle_flush(struct rte_eth_dev *dev) return ret; } +const struct rte_flow_item * +mlx5_flow_find_tunnel_item(const struct rte_flow_item *item) +{ + for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { + switch (item->type) { + default: + break; + case RTE_FLOW_ITEM_TYPE_VXLAN: + case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: + case RTE_FLOW_ITEM_TYPE_GRE: + case RTE_FLOW_ITEM_TYPE_MPLS: + case RTE_FLOW_ITEM_TYPE_NVGRE: + case RTE_FLOW_ITEM_TYPE_GENEVE: + return item; + case RTE_FLOW_ITEM_TYPE_IPV4: + case RTE_FLOW_ITEM_TYPE_IPV6: + if (item[1].type == RTE_FLOW_ITEM_TYPE_IPV4 || + item[1].type == RTE_FLOW_ITEM_TYPE_IPV6) + return item; + break; + } + } + return NULL; +} + #ifndef HAVE_MLX5DV_DR #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) #else diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 56908ae08b..eb7035d259 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -145,6 +145,9 @@ enum mlx5_feature_name { #define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32) #define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33) +/* INTEGRITY item bit */ +#define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -1010,6 +1013,20 @@ struct rte_flow { (MLX5_RSS_HASH_IPV6 | IBV_RX_HASH_DST_PORT_TCP) #define MLX5_RSS_HASH_NONE 0ULL +/* + * Define integrity bits supported by the PMD + */ +#define MLX5_DV_PKT_INTEGRITY_MASK \ + (RTE_FLOW_ITEM_INTEGRITY_L3_OK | RTE_FLOW_ITEM_INTEGRITY_L4_OK | \ + RTE_FLOW_ITEM_INTEGRITY_IPV4_CSUM_OK | \ + RTE_FLOW_ITEM_INTEGRITY_L4_CSUM_OK) + +#define MLX5_ETHER_TYPE_FROM_HEADER(_s, _m, _itm, _prt) do { \ + (_prt) = ((const struct _s *)(_itm)->mask)->_m; \ + (_prt) &= ((const struct _s *)(_itm)->spec)->_m; \ + (_prt) = rte_be_to_cpu_16((_prt)); \ +} while (0) + /* array of valid combinations of RX Hash fields for RSS */ static const uint64_t mlx5_rss_hash_fields[] = { MLX5_RSS_HASH_IPV4, @@ -1282,6 +1299,13 @@ mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx) return &pool->mtrs[idx % MLX5_ASO_MTRS_PER_POOL]; } +static __rte_always_inline const struct rte_flow_item * +mlx5_find_end_item(const struct rte_flow_item *item) +{ + for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++); + return item; +} + int mlx5_flow_group_to_table(struct rte_eth_dev *dev, const struct mlx5_flow_tunnel *tunnel, uint32_t group, uint32_t *table, @@ -1433,6 +1457,8 @@ struct mlx5_flow_meter_sub_policy *mlx5_flow_meter_sub_policy_rss_prepare struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]); int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev); int mlx5_action_handle_flush(struct rte_eth_dev *dev); +const struct rte_flow_item * +mlx5_flow_find_tunnel_item(const struct rte_flow_item *item); void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id); int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh); diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index d810466242..2d4042e458 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6230,6 +6230,163 @@ flow_dv_validate_attributes(struct rte_eth_dev *dev, return ret; } +static uint16_t +mlx5_flow_locate_proto_l3(const struct rte_flow_item **head, + const struct rte_flow_item *end) +{ + const struct rte_flow_item *item = *head; + uint16_t l3_protocol; + + for (; item != end; item++) { + switch (item->type) { + default: + break; + case RTE_FLOW_ITEM_TYPE_IPV4: + l3_protocol = RTE_ETHER_TYPE_IPV4; + goto l3_ok; + case RTE_FLOW_ITEM_TYPE_IPV6: + l3_protocol = RTE_ETHER_TYPE_IPV6; + goto l3_ok; + case RTE_FLOW_ITEM_TYPE_ETH: + if (item->mask && item->spec) { + MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_eth, + type, item, + l3_protocol); + if (l3_protocol == RTE_ETHER_TYPE_IPV4 || + l3_protocol == RTE_ETHER_TYPE_IPV6) + goto l3_ok; + } + break; + case RTE_FLOW_ITEM_TYPE_VLAN: + if (item->mask && item->spec) { + MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_vlan, + inner_type, item, + l3_protocol); + if (l3_protocol == RTE_ETHER_TYPE_IPV4 || + l3_protocol == RTE_ETHER_TYPE_IPV6) + goto l3_ok; + } + break; + } + } + + return 0; + +l3_ok: + *head = item; + return l3_protocol; +} + +static uint8_t +mlx5_flow_locate_proto_l4(const struct rte_flow_item **head, + const struct rte_flow_item *end) +{ + const struct rte_flow_item *item = *head; + uint8_t l4_protocol; + + for (; item != end; item++) { + switch (item->type) { + default: + break; + case RTE_FLOW_ITEM_TYPE_TCP: + l4_protocol = IPPROTO_TCP; + goto l4_ok; + case RTE_FLOW_ITEM_TYPE_UDP: + l4_protocol = IPPROTO_UDP; + goto l4_ok; + case RTE_FLOW_ITEM_TYPE_IPV4: + if (item->mask && item->spec) { + const struct rte_flow_item_ipv4 *mask, *spec; + + mask = (typeof(mask))item->mask; + spec = (typeof(spec))item->spec; + l4_protocol = mask->hdr.next_proto_id & + spec->hdr.next_proto_id; + if (l4_protocol == IPPROTO_TCP || + l4_protocol == IPPROTO_UDP) + goto l4_ok; + } + break; + case RTE_FLOW_ITEM_TYPE_IPV6: + if (item->mask && item->spec) { + const struct rte_flow_item_ipv6 *mask, *spec; + mask = (typeof(mask))item->mask; + spec = (typeof(spec))item->spec; + l4_protocol = mask->hdr.proto & spec->hdr.proto; + if (l4_protocol == IPPROTO_TCP || + l4_protocol == IPPROTO_UDP) + goto l4_ok; + } + break; + } + } + + return 0; + +l4_ok: + *head = item; + return l4_protocol; +} + +static int +flow_dv_validate_item_integrity(struct rte_eth_dev *dev, + const struct rte_flow_item *rule_items, + const struct rte_flow_item *integrity_item, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + const struct rte_flow_item *tunnel_item, *end_item, *item = rule_items; + const struct rte_flow_item_integrity *mask = (typeof(mask)) + integrity_item->mask; + const struct rte_flow_item_integrity *spec = (typeof(spec)) + integrity_item->spec; + uint32_t protocol; + + if (!priv->config.hca_attr.pkt_integrity_match) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + integrity_item, + "packet integrity integrity_item not supported"); + if (!mask) + mask = &rte_flow_item_integrity_mask; + if (mask->value && ((mask->value & ~MLX5_DV_PKT_INTEGRITY_MASK) != 0)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + integrity_item, + "unsupported integrity filter"); + tunnel_item = mlx5_flow_find_tunnel_item(rule_items); + if (spec->level > 1) { + if (!tunnel_item) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + integrity_item, + "missing tunnel item"); + item = tunnel_item; + end_item = mlx5_find_end_item(tunnel_item); + } else { + end_item = tunnel_item ? tunnel_item : + mlx5_find_end_item(integrity_item); + } + if (mask->l3_ok || mask->ipv4_csum_ok) { + protocol = mlx5_flow_locate_proto_l3(&item, end_item); + if (!protocol) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + integrity_item, + "missing L3 protocol"); + } + if (mask->l4_ok || mask->l4_csum_ok) { + protocol = mlx5_flow_locate_proto_l4(&item, end_item); + if (!protocol) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + integrity_item, + "missing L4 protocol"); + } + + return 0; +} + /** * Internal validation function. For validating both actions and items. * @@ -6321,6 +6478,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, .fdb_def_rule = !!priv->fdb_def_rule, }; const struct rte_eth_hairpin_conf *conf; + const struct rte_flow_item *rule_items = items; bool def_policy = false; if (items == NULL) @@ -6644,6 +6802,18 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return ret; last_item = MLX5_FLOW_LAYER_ECPRI; break; + case RTE_FLOW_ITEM_TYPE_INTEGRITY: + if (item_flags & RTE_FLOW_ITEM_TYPE_INTEGRITY) + return rte_flow_error_set + (error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "multiple integrity items not supported"); + ret = flow_dv_validate_item_integrity(dev, rule_items, + items, error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_ITEM_INTEGRITY; + break; default: return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, @@ -11119,6 +11289,90 @@ flow_dv_translate_create_aso_age(struct rte_eth_dev *dev, return age_idx; } +static void +flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask, + const struct rte_flow_item_integrity *value, + void *headers_m, void *headers_v) +{ + if (mask->l4_ok) { + /* application l4_ok filter aggregates all hardware l4 filters + * therefore hw l4_checksum_ok must be implicitly added here. + */ + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1); + if (value->l4_ok) { + /* application l4_ok = 1 matches sets both hw flags + * l4_ok and l4_checksum_ok flags to 1. + */ + MLX5_SET(fte_match_set_lyr_2_4, headers_v, + l4_checksum_ok, 1); + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1); + } else { + /* application l4_ok = 0 matches on hw flag + * l4_checksum_ok = 0 only. + */ + MLX5_SET(fte_match_set_lyr_2_4, headers_v, + l4_checksum_ok, 0); + } + } else if (mask->l4_csum_ok) { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, + mask->l4_csum_ok); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok, + mask->ipv4_csum_ok & value->ipv4_csum_ok); + } +} + +static void +flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask, + const struct rte_flow_item_integrity *value, + void *headers_m, void *headers_v) +{ + if (mask->l3_ok) { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, + mask->ipv4_csum_ok); + if (value->l3_ok) { + MLX5_SET(fte_match_set_lyr_2_4, headers_v, + ipv4_checksum_ok, 1); + MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok, 1); + } else { + MLX5_SET(fte_match_set_lyr_2_4, headers_v, + ipv4_checksum_ok, 0); + } + } else if (mask->ipv4_csum_ok) { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, + mask->ipv4_csum_ok); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok, + value->ipv4_csum_ok); + } +} + +static void +flow_dv_translate_item_integrity(void *matcher, void *key, + const struct rte_flow_item *item) +{ + const struct rte_flow_item_integrity *mask = item->mask; + const struct rte_flow_item_integrity *value = item->spec; + void *headers_m; + void *headers_v; + + if (!value) + return; + if (!mask) + mask = &rte_flow_item_integrity_mask; + if (value->level > 1) { + headers_m = MLX5_ADDR_OF(fte_match_param, matcher, + inner_headers); + headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers); + } else { + headers_m = MLX5_ADDR_OF(fte_match_param, matcher, + outer_headers); + headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers); + } + flow_dv_translate_integrity_l3(mask, value, headers_m, headers_v); + flow_dv_translate_integrity_l4(mask, value, headers_m, headers_v); +} + /** * Fill the flow with DV spec, lock free * (mutex should be acquired by caller). @@ -12027,6 +12281,10 @@ flow_dv_translate(struct rte_eth_dev *dev, /* No other protocol should follow eCPRI layer. */ last_item = MLX5_FLOW_LAYER_ECPRI; break; + case RTE_FLOW_ITEM_TYPE_INTEGRITY: + flow_dv_translate_item_integrity(match_mask, + match_value, items); + break; default: break; } From patchwork Wed Apr 28 17:59:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 92344 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 75011A0A0A; Wed, 28 Apr 2021 19:59:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E0ADD412CB; Wed, 28 Apr 2021 19:59:39 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2066.outbound.protection.outlook.com [40.107.237.66]) by mails.dpdk.org (Postfix) with ESMTP id 74EB7412C6 for ; Wed, 28 Apr 2021 19:59:37 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=T6xhc4CQe66dZQtjzO9bqL/Cvmot9XxapPBOwDOy+N4rSqZ/o9SbTjLeDziyYtl1z+xK5x7K3Pp09kjNlrbs5xPyUQhvr22TLw2q/GPiTiFYyqgXkjO5eL/UXUHs7IFsl5hE5LTA3E1OlVS8JVdRkLgrpEKIMFgwgh5SHRffX/UO1Numzh0tlz09sDANbhdjf68Ax7qod6cPCSJ2pjJY1pxqw/sUJkoi+HIeFcV+7wIqKzdhAsmoPDvdp+m5YATARdoNJXnZCxyklbhHgh3cknQMtrrribtNccYQyQMQKwRtOH+M9dNKHkeGWEX0CFXHGYqrIlLtQ2YHC/YXGf2W9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jrj7f2LeTYv42CeHKfWoD3uFXS5tG/t67CVGBCnPHRQ=; b=i9Ulmj09rFEZRI5/4ylWQwQ1Qbi15vQR1jeyUNvINFxDKQa2ORm1auutuO6uCXHz6Xr0CNAaaekmSNqT7HkcVzkMUY4eocJ+/5kijzRH9iWR7FpLYRNWJk6NlokiOCRU5uO9+RPS0dBbaE1AdYDedNNySeAuM72CIG/IncEJRKdtfjvw9yobB92HsYOVRqfuij70WOBw00G94Wugt5WOWKm/4A3qDOs5ZYcZEKxnaqu2PQVgkTqctDF2fBtZPFeendraNPl6dzPvhwLfpdEDR+2VReJJksLRbDADwaxqpybav7qPolx1VFtyO45EXW/Dpt625H5iv1qWbxFNY6kJyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jrj7f2LeTYv42CeHKfWoD3uFXS5tG/t67CVGBCnPHRQ=; b=royDsnLGXE/wpZUMidWybSqAxaGHa13ZcQzx7g9rz6cOzSdT0LmedUjtXGeGY+09YhRVOIvKdeOfzCM+Jm8+3oz79Khiz9g7cU5S8OH9T0K1dsJf/o1nHxMVcod9aKL6Qg3YAD1I030LyDGXErSVthwwbJIWShfPWHNYvSCiy7whkw0v+zBBm0VfAKQOJwnRQu5Dckdjo5yYlDIXY5FBLVGlUYfaig+PmMTqf+URlb8DoPZaHHQ5RguG2pno7gN0kmEeHm99K2xc0fRQLDZzJo+s//k014DSX+INt918s8W1jPfoJC7/OEYtvSOI+Bqmyb+KNR5hHxV2zz50Ni3oAw== Received: from DM5PR2201CA0021.namprd22.prod.outlook.com (2603:10b6:4:14::31) by DM6PR12MB4074.namprd12.prod.outlook.com (2603:10b6:5:218::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.23; Wed, 28 Apr 2021 17:59:36 +0000 Received: from DM6NAM11FT022.eop-nam11.prod.protection.outlook.com (2603:10b6:4:14:cafe::13) by DM5PR2201CA0021.outlook.office365.com (2603:10b6:4:14::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.21 via Frontend Transport; Wed, 28 Apr 2021 17:59:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4065.21 via Frontend Transport; Wed, 28 Apr 2021 17:59:36 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 28 Apr 2021 17:59:34 +0000 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko , "Shahaf Shuler" Date: Wed, 28 Apr 2021 20:59:06 +0300 Message-ID: <20210428175906.21387-5-getelson@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210428175906.21387-1-getelson@nvidia.com> References: <20210428175906.21387-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1a497b06-6529-4452-8373-08d90a6f62c6 X-MS-TrafficTypeDiagnostic: DM6PR12MB4074: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GVor3XJNt4K+YkzljReAhTbRRARFRZ7VvQ9tCWIa29QfhtvJpQS3wV5eq0/XAExKWeksiWV2PUuGSONzMFNYelmIGTfM3V+THPpaYihmJV6QV9/Ijltk6APK84Ryf1bhfd7oeukJy3KWtABlkSYGSfRAUjx3NmlI3c73ekEBcky7piroB0QWw/cgG6QvKTBppNh1BPo+AIJ88Lh5dF4lV3wunF07UsP3ZoJy0EbwYvDDBpI6ZhSlUtFHVpKu2uOWOHq8dbapR4eC6VWeIY+jU/UTdVSC9xjwMj7HrKSUGaGp6sOj04N3LB6UhK9Elu62gMdMaxbSwl6XP0tybe5dMJQHAWhC0XokNWC5ttly9ffQCGMILvRFrQBJX4wMe+kkXSgk/ge1mJffw/gef93AcmLqXWH+VxvfdjI+IzHxCMn0iL2QlcAKOS5YU12kxVy4U1dlLIyTN6niR5PFGXfJ0VdFVF9crxT5GEY7dwK0dfJhmWFyMBTZP20aH3rUrh92xhI+nW8BO8oWW3NCbgPVfJe0w8Mda2R03PfKtyJAW7wGshXdj63aoaayZI4AAu/6ROICiRA6x/1O1vSg8zeucLyjBXvkO/fMJA12Hy0XNkkB4o0cIhaFV11FsLrJbAE1eQH6lcxN4wN12R9uD6rDI7AB4FXtHnOA8FVKLBSO0DE= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(346002)(396003)(376002)(136003)(36840700001)(46966006)(55016002)(7696005)(336012)(7636003)(36906005)(70206006)(36756003)(2906002)(4326008)(16526019)(426003)(6286002)(83380400001)(8676002)(2616005)(186003)(82740400003)(5660300002)(82310400003)(86362001)(47076005)(70586007)(54906003)(6916009)(36860700001)(316002)(356005)(26005)(1076003)(478600001)(6666004)(107886003)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2021 17:59:36.2631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a497b06-6529-4452-8373-08d90a6f62c6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4074 Subject: [dpdk-dev] [PATCH 4/4] doc: add MLX5 PMD integrity item limitations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add MLX5 PMD integrity item limitations. Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index b27a9a69f6..12b45a69b5 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -107,6 +107,7 @@ Features - 21844 flow priorities for ingress or egress flow groups greater than 0 and for any transfer flow group. - Flow metering, including meter policy API. +- Flow integrity offload API. Limitations ----------- @@ -417,6 +418,20 @@ Limitations - yellow: must be empty. - RED: must be DROP. +- Integrity: + + - Integrity offload is enabled for **ConnectX-6** family. + - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``. + - ``level`` value 0 references outer headers. + - Multiple integrity items not supported in a single flow rule. + - Flow rule items supplied by application must explicitly specify network headers referred by integrity item. + For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header, + TCP or UDP, must be in the rule pattern as well:: + + flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end … + or + flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec 0 / eth / ipv4 proto is udp / end … + Statistics ----------