From patchwork Wed Apr 28 07:20:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 92307 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60068A0A0E; Wed, 28 Apr 2021 09:20:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E500B41289; Wed, 28 Apr 2021 09:20:54 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id B6E1641147 for ; Wed, 28 Apr 2021 09:20:52 +0200 (CEST) Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FVVNG06WMz16Mgj for ; Wed, 28 Apr 2021 15:18:22 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Wed, 28 Apr 2021 15:20:47 +0800 From: "Min Hu (Connor)" To: CC: Date: Wed, 28 Apr 2021 15:20:51 +0800 Message-ID: <1619594455-56787-2-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619594455-56787-1-git-send-email-humin29@huawei.com> References: <1619594455-56787-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 1/5] net/hns3: support preferred burst size and queues in VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng This patch supports get preferred burst size and queues when call rte_eth_dev_info_get() API with VF. Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 3 --- drivers/net/hns3/hns3_ethdev.h | 3 +++ drivers/net/hns3/hns3_ethdev_vf.c | 5 +++++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index e3f1b7c..95d701c 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -16,9 +16,6 @@ #include "hns3_dcb.h" #include "hns3_mp.h" -#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 -#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 - #define HNS3_SERVICE_INTERVAL 1000000 /* us */ #define HNS3_SERVICE_QUICK_INTERVAL 10 #define HNS3_INVALID_PVID 0xFFFF diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index d27c725..ba50e70 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -42,6 +42,9 @@ #define HNS3_PF_FUNC_ID 0 #define HNS3_1ST_VF_FUNC_ID 1 +#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 +#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 + #define HNS3_SW_SHIFT_AND_DISCARD_MODE 0 #define HNS3_HW_SHIFT_AND_DISCARD_MODE 1 diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 06a26fb..74b90e2 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1027,6 +1027,11 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) info->reta_size = hw->rss_ind_tbl_size; info->hash_key_size = HNS3_RSS_KEY_SIZE; info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; + + info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; + info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; + info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; + info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; From patchwork Wed Apr 28 07:20:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 92306 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FAE7A0A0E; Wed, 28 Apr 2021 09:20:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D3A5441220; Wed, 28 Apr 2021 09:20:53 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id B2886410EB for ; Wed, 28 Apr 2021 09:20:52 +0200 (CEST) Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FVVNG0H0Dz16Mhj for ; Wed, 28 Apr 2021 15:18:22 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Wed, 28 Apr 2021 15:20:47 +0800 From: "Min Hu (Connor)" To: CC: Date: Wed, 28 Apr 2021 15:20:52 +0800 Message-ID: <1619594455-56787-3-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619594455-56787-1-git-send-email-humin29@huawei.com> References: <1619594455-56787-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 2/5] net/hns3: log time delta in decimal format X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng If the reset process cost too much time, driver will log one error message which formats the time delta, but the formatting is using hexadecimal which was not readable. This patch fixes it by formatting in decimal format. Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 2 +- drivers/net/hns3/hns3_ethdev_vf.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 95d701c..ad000a1 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6698,7 +6698,7 @@ hns3_reset_service(void *param) msec = tv_delta.tv_sec * MSEC_PER_SEC + tv_delta.tv_usec / USEC_PER_MSEC; if (msec > HNS3_RESET_PROCESS_MS) - hns3_err(hw, "%d handle long time delta %" PRIx64 + hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", hw->reset.level, msec, tv.tv_sec, tv.tv_usec); diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 74b90e2..fcdf0e3 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2782,7 +2782,7 @@ hns3vf_reset_service(void *param) msec = tv_delta.tv_sec * MSEC_PER_SEC + tv_delta.tv_usec / USEC_PER_MSEC; if (msec > HNS3_RESET_PROCESS_MS) - hns3_err(hw, "%d handle long time delta %" PRIx64 + hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", hw->reset.level, msec, tv.tv_sec, tv.tv_usec); } From patchwork Wed Apr 28 07:20:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 92310 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F661A0A0E; Wed, 28 Apr 2021 09:21:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C76B2412A0; Wed, 28 Apr 2021 09:20:59 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id DD40741277 for ; Wed, 28 Apr 2021 09:20:52 +0200 (CEST) Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FVVNF70Pwz16MgX for ; Wed, 28 Apr 2021 15:18:21 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Wed, 28 Apr 2021 15:20:47 +0800 From: "Min Hu (Connor)" To: CC: Date: Wed, 28 Apr 2021 15:20:53 +0800 Message-ID: <1619594455-56787-4-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619594455-56787-1-git-send-email-humin29@huawei.com> References: <1619594455-56787-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 3/5] net/hns3: fix use wrong time API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng Currently, driver uses gettimeofday() API to get the time, and then calculate the time delta, the delta will be used mainly in judging timeout process. But the time which gets from gettimeofday() API isn't monotonically increasing. The process may fail if the system time is changed. We use the following scheme to fix it: 1. Add hns3_clock_gettime() API which will get the monotonically increasing time. 2. Add hns3_clock_calctime_ms() API which will get the milliseconds of the monotonically increasing time. 3. Add hns3_clock_calctime_ms() API which will calc the milliseconds of a given time. Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 46 +++++++++++++++++++++++++++++++++------ drivers/net/hns3/hns3_ethdev.h | 12 +++------- drivers/net/hns3/hns3_ethdev_vf.c | 11 +++++----- drivers/net/hns3/hns3_intr.c | 34 ++++++++++++++--------------- 4 files changed, 63 insertions(+), 40 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index ad000a1..021e33c 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6334,7 +6334,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) if (wait_data->result == HNS3_WAIT_SUCCESS) return 0; else if (wait_data->result == HNS3_WAIT_TIMEOUT) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); return -ETIME; @@ -6344,7 +6344,7 @@ hns3_wait_hardware_ready(struct hns3_adapter *hns) wait_data->hns = hns; wait_data->check_completion = is_pf_reset_done; wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * - HNS3_RESET_WAIT_MS + get_timeofday_ms(); + HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms(); wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; wait_data->count = HNS3_RESET_WAIT_CNT; wait_data->result = HNS3_WAIT_REQUEST; @@ -6383,7 +6383,7 @@ hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) struct timeval tv; uint32_t val; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || hns3_read_dev(hw, HNS3_FUN_RST_ING)) { hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", @@ -6691,12 +6691,11 @@ hns3_reset_service(void *param) */ reset_level = hns3_get_reset_level(hns, &hw->reset.pending); if (reset_level != HNS3_NONE_RESET) { - gettimeofday(&tv_start, NULL); + hns3_clock_gettime(&tv_start); ret = hns3_reset_process(hns, reset_level); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &tv_start, &tv_delta); - msec = tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC; + msec = hns3_clock_calctime_ms(&tv_delta); if (msec > HNS3_RESET_PROCESS_MS) hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", @@ -7196,6 +7195,39 @@ hns3_get_module_info(struct rte_eth_dev *dev, return 0; } +void +hns3_clock_gettime(struct timeval *tv) +{ +#ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ +#define CLOCK_TYPE CLOCK_MONOTONIC_RAW +#else +#define CLOCK_TYPE CLOCK_MONOTONIC +#endif +#define NSEC_TO_USEC_DIV 1000 + + struct timespec spec; + (void)clock_gettime(CLOCK_TYPE, &spec); + + tv->tv_sec = spec.tv_sec; + tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV; +} + +uint64_t +hns3_clock_calctime_ms(struct timeval *tv) +{ + return (uint64_t)tv->tv_sec * MSEC_PER_SEC + + tv->tv_usec / USEC_PER_MSEC; +} + +uint64_t +hns3_clock_gettime_ms(void) +{ + struct timeval tv; + + hns3_clock_gettime(&tv); + return hns3_clock_calctime_ms(&tv); +} + static int hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) { diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index ba50e70..b2dacb9 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -1022,15 +1022,9 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg) #define MSEC_PER_SEC 1000L #define USEC_PER_MSEC 1000L -static inline uint64_t -get_timeofday_ms(void) -{ - struct timeval tv; - - (void)gettimeofday(&tv, NULL); - - return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC; -} +void hns3_clock_gettime(struct timeval *tv); +uint64_t hns3_clock_calctime_ms(struct timeval *tv); +uint64_t hns3_clock_gettime_ms(void); static inline uint64_t hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index fcdf0e3..9a85e97 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2510,7 +2510,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); return -EAGAIN; } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); return -ETIME; @@ -2520,7 +2520,7 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) wait_data->hns = hns; wait_data->check_completion = is_vf_reset_done; wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT * - HNS3VF_RESET_WAIT_MS + get_timeofday_ms(); + HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms(); wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC; wait_data->count = HNS3VF_RESET_WAIT_CNT; wait_data->result = HNS3_WAIT_REQUEST; @@ -2775,12 +2775,11 @@ hns3vf_reset_service(void *param) */ reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); if (reset_level != HNS3_NONE_RESET) { - gettimeofday(&tv_start, NULL); + hns3_clock_gettime(&tv_start); hns3_reset_process(hns, reset_level); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &tv_start, &tv_delta); - msec = tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC; + msec = hns3_clock_calctime_ms(&tv_delta); if (msec > HNS3_RESET_PROCESS_MS) hns3_err(hw, "%d handle long time delta %" PRIu64 " ms time=%ld.%.6ld", diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index cc7d7c6..ba6a044 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -2465,7 +2465,7 @@ hns3_wait_callback(void *param) * Check if the current time exceeds the deadline * or a pending reset coming, or reset during close. */ - msec = get_timeofday_ms(); + msec = hns3_clock_gettime_ms(); if (msec > data->end_ms || is_reset_pending(hns) || hw->adapter_state == HNS3_NIC_CLOSING) { done = false; @@ -2650,7 +2650,7 @@ hns3_reset_pre(struct hns3_adapter *hns) __atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED); hw->reset.stage = RESET_STAGE_DOWN; ret = hw->reset.ops->stop_service(hns); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld", ret, tv.tv_sec, tv.tv_usec); @@ -2662,7 +2662,7 @@ hns3_reset_pre(struct hns3_adapter *hns) } if (hw->reset.stage == RESET_STAGE_PREWAIT) { ret = hw->reset.ops->prepare_reset(hns); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step2 prepare wait fail=%d time=%ld.%.6ld", @@ -2700,7 +2700,7 @@ hns3_reset_post(struct hns3_adapter *hns) } ret = hw->reset.ops->reinit_dev(hns); rte_spinlock_unlock(&hw->lock); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d", ret, hw->reset.retries); @@ -2718,7 +2718,7 @@ hns3_reset_post(struct hns3_adapter *hns) rte_spinlock_lock(&hw->lock); ret = hw->reset.ops->restore_conf(hns); rte_spinlock_unlock(&hw->lock); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); if (ret) { hns3_warn(hw, "Reset step6 restore fail=%d retries=%d", @@ -2741,7 +2741,7 @@ hns3_reset_post(struct hns3_adapter *hns) rte_spinlock_lock(&hw->lock); hw->reset.ops->start_service(hns); rte_spinlock_unlock(&hw->lock); - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &hw->reset.start_time, &tv_delta); hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64 @@ -2753,10 +2753,9 @@ hns3_reset_post(struct hns3_adapter *hns) hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt); hns3_warn(hw, - "%s reset done delta %ld ms time=%ld.%.6ld", + "%s reset done delta %" PRIu64 " ms time=%ld.%.6ld", reset_string[hw->reset.level], - tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC, + hns3_clock_calctime_ms(&tv_delta), tv.tv_sec, tv.tv_usec); hw->reset.level = HNS3_NONE_RESET; } @@ -2796,7 +2795,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) if (hw->reset.level == HNS3_NONE_RESET) { hw->reset.level = new_level; hw->reset.stats.exec_cnt++; - gettimeofday(&hw->reset.start_time, NULL); + hns3_clock_gettime(&hw->reset.start_time); hns3_warn(hw, "Start %s reset time=%ld.%.6ld", reset_string[hw->reset.level], hw->reset.start_time.tv_sec, @@ -2804,7 +2803,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) } if (is_reset_pending(hns)) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "%s reset is aborted by high level time=%ld.%.6ld", reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); @@ -2822,7 +2821,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) ret = hns3_reset_req_hw_reset(hns); if (ret == -EAGAIN) return ret; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step3 request IMP reset success time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); @@ -2833,7 +2832,7 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) ret = hw->reset.ops->wait_hardware_ready(hns); if (ret) goto retry; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); hw->reset.stage = RESET_STAGE_DEV_INIT; @@ -2861,12 +2860,11 @@ hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) rte_spinlock_unlock(&hw->lock); __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); hw->reset.stage = RESET_STAGE_NONE; - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); timersub(&tv, &hw->reset.start_time, &tv_delta); - hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld", + hns3_warn(hw, "%s reset fail delta %" PRIu64 " ms time=%ld.%.6ld", reset_string[hw->reset.level], - tv_delta.tv_sec * MSEC_PER_SEC + - tv_delta.tv_usec / USEC_PER_MSEC, + hns3_clock_calctime_ms(&tv_delta), tv.tv_sec, tv.tv_usec); hw->reset.level = HNS3_NONE_RESET; } @@ -2898,7 +2896,7 @@ hns3_reset_abort(struct hns3_adapter *hns) rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data); if (hw->reset.level != HNS3_NONE_RESET) { - gettimeofday(&tv, NULL); + hns3_clock_gettime(&tv); hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld", reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); } From patchwork Wed Apr 28 07:20:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 92309 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F9BBA0A0E; Wed, 28 Apr 2021 09:21:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7975241299; Wed, 28 Apr 2021 09:20:57 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id BF27041221 for ; Wed, 28 Apr 2021 09:20:52 +0200 (CEST) Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FVVNF6ZNQz16Mg8 for ; Wed, 28 Apr 2021 15:18:21 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Wed, 28 Apr 2021 15:20:47 +0800 From: "Min Hu (Connor)" To: CC: Date: Wed, 28 Apr 2021 15:20:54 +0800 Message-ID: <1619594455-56787-5-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619594455-56787-1-git-send-email-humin29@huawei.com> References: <1619594455-56787-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 4/5] net/hns3: delete unused macro of cmd module X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng The hns3_is_csq() and cmq_ring_to_dev() macro were defined in previous version but never used. Fixes: 737f30e1c3ab ("net/hns3: support command interface with firmware") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_cmd.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 62dfc19..5beb3d9 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -10,10 +10,6 @@ #include "hns3_intr.h" #include "hns3_logs.h" -#define hns3_is_csq(ring) ((ring)->flag & HNS3_TYPE_CSQ) - -#define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev) - static int hns3_ring_space(struct hns3_cmq_ring *ring) { From patchwork Wed Apr 28 07:20:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 92311 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97EB7A0A0E; Wed, 28 Apr 2021 09:21:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 06668412A7; Wed, 28 Apr 2021 09:21:01 +0200 (CEST) Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mails.dpdk.org (Postfix) with ESMTP id BE1B0410EB for ; Wed, 28 Apr 2021 09:20:53 +0200 (CEST) Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FVVNG0b74z16Mhk for ; Wed, 28 Apr 2021 15:18:22 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Wed, 28 Apr 2021 15:20:48 +0800 From: "Min Hu (Connor)" To: CC: Date: Wed, 28 Apr 2021 15:20:55 +0800 Message-ID: <1619594455-56787-6-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619594455-56787-1-git-send-email-humin29@huawei.com> References: <1619594455-56787-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 5/5] net/hns3: select Tx prepare based on Tx offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang Tx prepare should be called only when necessary to reduce the impact on performance. For partial TX offload, users need to call rte_eth_tx_prepare() to invoke the tx_prepare callback of PMDs. In this callback, the PMDs adjust the packet based on the offloading used by the user. (e.g. For some PMDs, pseudo-headers need to be calculated when the TX cksum is offloaded.) However, for the users, they cannot grasp all the hardware and PMDs characteristics. As a result, users cannot decide when they need to actually call tx_prepare. Therefore, we should assume that the user calls rte_eth_tx_prepare() when using any Tx offloading to ensure that related functions work properly. Whether packets need to be adjusted should be determined by PMDs. They can make judgments in the dev_configure or queue_setup phase. When the related function is not used, the pointer of tx_prepare should be set to NULL to reduce the performance loss caused by invoking rte_eth_tx_repare(). In this patch, if tx_prepare is not required for the offloading used by the users, the tx_prepare pointer will be set to NULL. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 3881a72..7ac3a48 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4203,17 +4203,45 @@ hns3_tx_check_simple_support(struct rte_eth_dev *dev) return (offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)); } +static bool +hns3_get_tx_prep_needed(struct rte_eth_dev *dev) +{ +#ifdef RTE_LIBRTE_ETHDEV_DEBUG + /* always perform tx_prepare when debug */ + return true; +#else +#define HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK (\ + DEV_TX_OFFLOAD_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_TCP_CKSUM | \ + DEV_TX_OFFLOAD_UDP_CKSUM | \ + DEV_TX_OFFLOAD_SCTP_CKSUM | \ + DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \ + DEV_TX_OFFLOAD_TCP_TSO | \ + DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ + DEV_TX_OFFLOAD_GRE_TNL_TSO | \ + DEV_TX_OFFLOAD_GENEVE_TNL_TSO) + + uint64_t tx_offload = dev->data->dev_conf.txmode.offloads; + if (tx_offload & HNS3_DEV_TX_CSKUM_TSO_OFFLOAD_MASK) + return true; + + return false; +#endif +} + static eth_tx_burst_t hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) { struct hns3_adapter *hns = dev->data->dev_private; bool vec_allowed, sve_allowed, simple_allowed; - bool vec_support; + bool vec_support, tx_prepare_needed; vec_support = hns3_tx_check_vec_support(dev) == 0; vec_allowed = vec_support && hns3_get_default_vec_support(); sve_allowed = vec_support && hns3_get_sve_support(); simple_allowed = hns3_tx_check_simple_support(dev); + tx_prepare_needed = hns3_get_tx_prep_needed(dev); *prep = NULL; @@ -4224,7 +4252,8 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) return hns3_xmit_pkts_simple; if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) { - *prep = hns3_prep_pkts; + if (tx_prepare_needed) + *prep = hns3_prep_pkts; return hns3_xmit_pkts; } @@ -4233,7 +4262,8 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) if (simple_allowed) return hns3_xmit_pkts_simple; - *prep = hns3_prep_pkts; + if (tx_prepare_needed) + *prep = hns3_prep_pkts; return hns3_xmit_pkts; }