From patchwork Sat Apr 24 06:03:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92096 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7965CA0547; Sat, 24 Apr 2021 08:00:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AF60D41115; Sat, 24 Apr 2021 08:00:00 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id A73DC4110F; Sat, 24 Apr 2021 07:59:58 +0200 (CEST) IronPort-SDR: LEXcCcSgTem6ofOx3ErXE+gGuSqS3vBiOXzIiqrsX93zIod2PoIZ62jYImDnf8J4eotWksT5O2 gdoTocsaop6A== X-IronPort-AV: E=McAfee;i="6200,9189,9963"; a="257470323" X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="257470323" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 22:59:58 -0700 IronPort-SDR: yZbae2NKjuj+OmdJHu3FObPa8bSgwhfpfYuSA8InZZQC+xUceFYVJZ3tggoxXd9WT7uIh7MwcS iO3HDC5hUJoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="421999413" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 23 Apr 2021 22:59:55 -0700 From: Qi Zhang To: beilei.xing@intel.com Cc: haiyue.wang@intel.com, dev@dpdk.org, Qi Zhang , stable@dpdk.org, Brett Creeley Date: Sat, 24 Apr 2021 14:03:34 +0800 Message-Id: <20210424060337.2824837-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210424060337.2824837-1-qi.z.zhang@intel.com> References: <20210424060337.2824837-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/4] common/iavf: fix duplicate defined offload bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The value of offload VIRTCHNL_VF_OFFLOAD_CRC bit already existed as VIRTCHNL_VF_CAP_ADV_LINK_SPEED. Fix this now by changing the value of VIRTCHNL_VF_OFFLOAD_CRC to a currently unused value. Also, move the define for VIRTCHNL_VF_CAP_ADV_LINK_SPEED in the correct place to line up with the other bit values and add a comment for its purpose. Hopefully this will prevent from defining duplicate bits moving forward. Fixes: e244eeafcecb ("net/iavf/base: update virtual channel") Cc: stable@dpdk.org Signed-off-by: Brett Creeley Signed-off-by: Qi Zhang --- drivers/common/iavf/virtchnl.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index 139569787f..c68128f773 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -372,9 +372,11 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource); #define VIRTCHNL_VF_OFFLOAD_RSS_REG 0x00000010 #define VIRTCHNL_VF_OFFLOAD_WB_ON_ITR 0x00000020 #define VIRTCHNL_VF_OFFLOAD_REQ_QUEUES 0x00000040 -#define VIRTCHNL_VF_OFFLOAD_CRC 0x00000080 +/* used to negotiate communicating link speeds in Mbps */ +#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED 0x00000080 /* 0X00000100 is reserved */ #define VIRTCHNL_VF_LARGE_NUM_QPAIRS 0x00000200 +#define VIRTCHNL_VF_OFFLOAD_CRC 0x00000400 #define VIRTCHNL_VF_OFFLOAD_VLAN_V2 0x00008000 #define VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000 #define VIRTCHNL_VF_OFFLOAD_RX_POLLING 0x00020000 @@ -393,8 +395,6 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource); #define VIRTCHNL_VF_CAP_DCF 0X40000000 /* 0X80000000 is reserved */ -/* Define below the capability flags that are not offloads */ -#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED 0x00000080 #define VF_BASE_MODE_OFFLOADS (VIRTCHNL_VF_OFFLOAD_L2 | \ VIRTCHNL_VF_OFFLOAD_VLAN | \ VIRTCHNL_VF_OFFLOAD_RSS_PF) From patchwork Sat Apr 24 06:03:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92097 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7974A0547; Sat, 24 Apr 2021 08:00:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E5C2A4111E; Sat, 24 Apr 2021 08:00:01 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 4C62A41112 for ; Sat, 24 Apr 2021 08:00:00 +0200 (CEST) IronPort-SDR: rqEr+Z1T+vjdRuY73iZk89AOjZGlDsR3UOZ+CX2sGpahQ8ChwPsVV4JXZN08jTJCa/AZBFEPdU zaSYgtsZ9LxA== X-IronPort-AV: E=McAfee;i="6200,9189,9963"; a="257470324" X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="257470324" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 22:59:59 -0700 IronPort-SDR: J+eEhKr5B3TzimJI5K8G+6X3U5yLDzyxAlhul41a/t2HjYnTK2DFXI4hEhMk9UQhORQJD/XPZF E/YnucT29bdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="421999419" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 23 Apr 2021 22:59:58 -0700 From: Qi Zhang To: beilei.xing@intel.com Cc: haiyue.wang@intel.com, dev@dpdk.org, Qi Zhang , Jacob Keller Date: Sat, 24 Apr 2021 14:03:35 +0800 Message-Id: <20210424060337.2824837-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210424060337.2824837-1-qi.z.zhang@intel.com> References: <20210424060337.2824837-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/4] common/iavf: add enumeration for the rxdid format X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support for allowing VFs to negotiate the descriptor format was added previously. This support requires that the VF specify which descriptor format to use when requesting Rx queues. The VF is supposed to request the set of supported formats via the new VIRTCHNL_OP_GET_SUPPORTED_RXDIDS, and then set one of the supported formats in the rxdid field of the virtchnl_rxq_info structure. The virtchnl.h header does not provide an enumeration of the format values. The existing implementations in the PF directly use the values from the DDP package. Make the formats explicit by defining an enumeration of the RXDIDs. Provide an enumeration for the values as well as the bit positions as returned by the supported_rxdids data from the VIRTCHNL_OP_GET_SUPPORTED_RXDIDS. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/common/iavf/virtchnl.h | 55 +++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index c68128f773..d794f11c01 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -432,6 +432,54 @@ struct virtchnl_txq_info { VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_txq_info); +/* RX descriptor IDs (range from 0 to 63) */ +enum virtchnl_rx_desc_ids { + VIRTCHNL_RXDID_0_16B_BASE = 0, + /* 32B_BASE and FLEX_SPLITQ share desc ids as default descriptors + * because they can be differentiated based on queue model; e.g. single + * queue model can only use 32B_BASE and split queue model can only use + * FLEX_SPLITQ. Having these as 1 allows them to be used as default + * descriptors without negotiation. + */ + VIRTCHNL_RXDID_1_32B_BASE = 1, + VIRTCHNL_RXDID_1_FLEX_SPLITQ = 1, + VIRTCHNL_RXDID_2_FLEX_SQ_NIC = 2, + VIRTCHNL_RXDID_3_FLEX_SQ_SW = 3, + VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB = 4, + VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL = 5, + VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2 = 6, + VIRTCHNL_RXDID_7_HW_RSVD = 7, + /* 9 through 15 are reserved */ + VIRTCHNL_RXDID_16_COMMS_GENERIC = 16, + VIRTCHNL_RXDID_17_COMMS_AUX_VLAN = 17, + VIRTCHNL_RXDID_18_COMMS_AUX_IPV4 = 18, + VIRTCHNL_RXDID_19_COMMS_AUX_IPV6 = 19, + VIRTCHNL_RXDID_20_COMMS_AUX_FLOW = 20, + VIRTCHNL_RXDID_21_COMMS_AUX_TCP = 21, + /* 22 through 63 are reserved */ +}; + +/* RX descriptor ID bitmasks */ +enum virtchnl_rx_desc_id_bitmasks { + VIRTCHNL_RXDID_0_16B_BASE_M = BIT(VIRTCHNL_RXDID_0_16B_BASE), + VIRTCHNL_RXDID_1_32B_BASE_M = BIT(VIRTCHNL_RXDID_1_32B_BASE), + VIRTCHNL_RXDID_1_FLEX_SPLITQ_M = BIT(VIRTCHNL_RXDID_1_FLEX_SPLITQ), + VIRTCHNL_RXDID_2_FLEX_SQ_NIC_M = BIT(VIRTCHNL_RXDID_2_FLEX_SQ_NIC), + VIRTCHNL_RXDID_3_FLEX_SQ_SW_M = BIT(VIRTCHNL_RXDID_3_FLEX_SQ_SW), + VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB_M = BIT(VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB), + VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL_M = BIT(VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL), + VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2_M = BIT(VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2), + VIRTCHNL_RXDID_7_HW_RSVD_M = BIT(VIRTCHNL_RXDID_7_HW_RSVD), + /* 9 through 15 are reserved */ + VIRTCHNL_RXDID_16_COMMS_GENERIC_M = BIT(VIRTCHNL_RXDID_16_COMMS_GENERIC), + VIRTCHNL_RXDID_17_COMMS_AUX_VLAN_M = BIT(VIRTCHNL_RXDID_17_COMMS_AUX_VLAN), + VIRTCHNL_RXDID_18_COMMS_AUX_IPV4_M = BIT(VIRTCHNL_RXDID_18_COMMS_AUX_IPV4), + VIRTCHNL_RXDID_19_COMMS_AUX_IPV6_M = BIT(VIRTCHNL_RXDID_19_COMMS_AUX_IPV6), + VIRTCHNL_RXDID_20_COMMS_AUX_FLOW_M = BIT(VIRTCHNL_RXDID_20_COMMS_AUX_FLOW), + VIRTCHNL_RXDID_21_COMMS_AUX_TCP_M = BIT(VIRTCHNL_RXDID_21_COMMS_AUX_TCP), + /* 22 through 63 are reserved */ +}; + /* VIRTCHNL_OP_CONFIG_RX_QUEUE * VF sends this message to set up parameters for one RX queue. * External data buffer contains one instance of virtchnl_rxq_info. @@ -454,7 +502,11 @@ struct virtchnl_rxq_info { u32 databuffer_size; u32 max_pkt_size; u8 crc_disable; - /* only used when VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC is supported */ + /* see enum virtchnl_rx_desc_ids; + * only used when VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC is supported. Note + * that when the offload is not supported, the descriptor format aligns + * with VIRTCHNL_RXDID_1_32B_BASE. + */ u8 rxdid; u8 pad1[2]; u64 dma_ring_addr; @@ -1294,6 +1346,7 @@ struct virtchnl_dcf_vlan_offload { VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_dcf_vlan_offload); struct virtchnl_supported_rxdids { + /* see enum virtchnl_rx_desc_id_bitmasks */ u64 supported_rxdids; }; From patchwork Sat Apr 24 06:03:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92098 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 757A6A0547; Sat, 24 Apr 2021 08:00:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ED5074111C; Sat, 24 Apr 2021 08:00:03 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 3B7F341121 for ; Sat, 24 Apr 2021 08:00:02 +0200 (CEST) IronPort-SDR: rWzINVtCEXYkZPwAOIuJYVUd4eEdgBX2vgrJL3B/oVz04EQVBlkxxmBHiu9l6NiILGeNBYdA1F IwK/xkUeG+LQ== X-IronPort-AV: E=McAfee;i="6200,9189,9963"; a="257470326" X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="257470326" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 23:00:01 -0700 IronPort-SDR: oN62jVKOvIDNcdveKG0sYJrHB/ddmOveydKv+X2QpYAX/dxb9PMssG4yFl5ieQRpv8RRVSjMn6 2vi7SthMXilQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="421999442" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 23 Apr 2021 23:00:00 -0700 From: Qi Zhang To: beilei.xing@intel.com Cc: haiyue.wang@intel.com, dev@dpdk.org, Qi Zhang , Sridhar Samudrala , Joshua Hay Date: Sat, 24 Apr 2021 14:03:36 +0800 Message-Id: <20210424060337.2824837-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210424060337.2824837-1-qi.z.zhang@intel.com> References: <20210424060337.2824837-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/4] common/iavf: refine comment in virtchnl X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" General clean up for comment in virtchnl. Signed-off-by: Sridhar Samudrala Signed-off-by: Joshua Hay Signed-off-by: Qi Zhang --- drivers/common/iavf/virtchnl.h | 69 ++++++++++++++++++++++++---------- 1 file changed, 49 insertions(+), 20 deletions(-) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index d794f11c01..0772c28527 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -6,8 +6,9 @@ #define _VIRTCHNL_H_ /* Description: - * This header file describes the VF-PF communication protocol used - * by the drivers for all devices starting from our 40G product line + * This header file describes the Virtual Function (VF) - Physical Function + * (PF) communication protocol used by the drivers for all devices starting + * from our 40G product line * * Admin queue buffer usage: * desc->opcode is always aqc_opc_send_msg_to_pf @@ -21,8 +22,8 @@ * have a maximum of sixteen queues for all of its VSIs. * * The PF is required to return a status code in v_retval for all messages - * except RESET_VF, which does not require any response. The return value - * is of status_code type, defined in the shared type.h. + * except RESET_VF, which does not require any response. The returned value + * is of virtchnl_status_code type, defined in the shared type.h. * * In general, VF driver initialization should roughly follow the order of * these opcodes. The VF driver must first validate the API version of the @@ -287,8 +288,12 @@ static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode) struct virtchnl_msg { u8 pad[8]; /* AQ flags/opcode/len/retval fields */ - enum virtchnl_ops v_opcode; /* avoid confusion with desc->opcode */ - enum virtchnl_status_code v_retval; /* ditto for desc->retval */ + + /* avoid confusion with desc->opcode */ + enum virtchnl_ops v_opcode; + + /* ditto for desc->retval */ + enum virtchnl_status_code v_retval; u32 vfid; /* used by PF when sending to VF */ }; @@ -354,7 +359,9 @@ enum virtchnl_vsi_type { struct virtchnl_vsi_resource { u16 vsi_id; u16 num_queue_pairs; - enum virtchnl_vsi_type vsi_type; + + /* see enum virtchnl_vsi_type */ + s32 vsi_type; u16 qset_handle; u8 default_mac_addr[VIRTCHNL_ETH_LENGTH_OF_ADDRESS]; }; @@ -510,7 +517,9 @@ struct virtchnl_rxq_info { u8 rxdid; u8 pad1[2]; u64 dma_ring_addr; - enum virtchnl_rx_hsplit rx_split_pos; /* deprecated with AVF 1.0 */ + + /* see enum virtchnl_rx_hsplit; deprecated with AVF 1.0 */ + s32 rx_split_pos; u32 pad2; }; @@ -1265,8 +1274,12 @@ enum virtchnl_flow_type { struct virtchnl_filter { union virtchnl_flow_spec data; union virtchnl_flow_spec mask; - enum virtchnl_flow_type flow_type; - enum virtchnl_action action; + + /* see enum virtchnl_flow_type */ + s32 flow_type; + + /* see enum virtchnl_action */ + s32 action; u32 action_meta; u8 field_flags; }; @@ -1371,7 +1384,8 @@ enum virtchnl_event_codes { #define PF_EVENT_SEVERITY_CERTAIN_DOOM 255 struct virtchnl_pf_event { - enum virtchnl_event_codes event; + /* see enum virtchnl_event_codes */ + s32 event; union { /* If the PF driver does not support the new speed reporting * capabilities then use link_event else use link_event_adv to @@ -1579,7 +1593,8 @@ enum virtchnl_proto_hdr_field { }; struct virtchnl_proto_hdr { - enum virtchnl_proto_hdr_type type; + /* see enum virtchnl_proto_hdr_type */ + s32 type; u32 field_selector; /* a bit mask to select field for header type */ u8 buffer[64]; /** @@ -1608,7 +1623,9 @@ VIRTCHNL_CHECK_STRUCT_LEN(2312, virtchnl_proto_hdrs); struct virtchnl_rss_cfg { struct virtchnl_proto_hdrs proto_hdrs; /* protocol headers */ - enum virtchnl_rss_algorithm rss_algorithm; /* rss algorithm type */ + + /* see enum virtchnl_rss_algorithm; rss algorithm type */ + s32 rss_algorithm; u8 reserved[128]; /* reserve for future */ }; @@ -1616,7 +1633,8 @@ VIRTCHNL_CHECK_STRUCT_LEN(2444, virtchnl_rss_cfg); /* action configuration for FDIR */ struct virtchnl_filter_action { - enum virtchnl_action type; + /* see enum virtchnl_action type */ + s32 type; union { /* used for queue and qgroup action */ struct { @@ -1723,7 +1741,9 @@ struct virtchnl_fdir_add { u16 validate_only; /* INPUT */ u32 flow_id; /* OUTPUT */ struct virtchnl_fdir_rule rule_cfg; /* INPUT */ - enum virtchnl_fdir_prgm_status status; /* OUTPUT */ + + /* see enum virtchnl_fdir_prgm_status; OUTPUT */ + s32 status; }; VIRTCHNL_CHECK_STRUCT_LEN(2616, virtchnl_fdir_add); @@ -1736,7 +1756,9 @@ struct virtchnl_fdir_del { u16 vsi_id; /* INPUT */ u16 pad; u32 flow_id; /* INPUT */ - enum virtchnl_fdir_prgm_status status; /* OUTPUT */ + + /* see enum virtchnl_fdir_prgm_status; OUTPUT */ + s32 status; }; VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_fdir_del); @@ -1752,7 +1774,9 @@ struct virtchnl_fdir_query { u32 flow_id; /* INPUT */ u32 reset_counter:1; /* INPUT */ struct virtchnl_fdir_query_info query_info; /* OUTPUT */ - enum virtchnl_fdir_prgm_status status; /* OUTPUT */ + + /* see enum virtchnl_fdir_prgm_status; OUTPUT */ + s32 status; u32 pad2; }; @@ -1775,7 +1799,8 @@ enum virtchnl_queue_type { /* structure to specify a chunk of contiguous queues */ struct virtchnl_queue_chunk { - enum virtchnl_queue_type type; + /* see enum virtchnl_queue_type */ + s32 type; u16 start_queue_id; u16 num_queues; }; @@ -1828,8 +1853,12 @@ struct virtchnl_queue_vector { u16 queue_id; u16 vector_id; u8 pad[4]; - enum virtchnl_itr_idx itr_idx; - enum virtchnl_queue_type queue_type; + + /* see enum virtchnl_itr_idx */ + s32 itr_idx; + + /* see enum virtchnl_queue_type */ + s32 queue_type; }; VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_queue_vector); From patchwork Sat Apr 24 06:03:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 92099 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6EDD3A0547; Sat, 24 Apr 2021 08:00:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 587F741118; Sat, 24 Apr 2021 08:00:06 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 24FC44112D for ; Sat, 24 Apr 2021 08:00:04 +0200 (CEST) IronPort-SDR: Toy9yyUESOvvaNvwDPqdV0NZFEMDidGVs9uC6Rs7hgaM4PLO5V5oGdFoeWcEHWud5Dy3UpS0vk doDKCLftYOcQ== X-IronPort-AV: E=McAfee;i="6200,9189,9963"; a="257470331" X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="257470331" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 23:00:04 -0700 IronPort-SDR: /dcrJjVV2ZxMPh+NX9bvq/Fc5Y6Wd/ZWUjOS+9kyhIyAcprjnQR5e3fZ2sHmIVVga21mNl3F2I tneaiYtdb2CQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,247,1613462400"; d="scan'208";a="421999491" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 23 Apr 2021 23:00:01 -0700 From: Qi Zhang To: beilei.xing@intel.com Cc: haiyue.wang@intel.com, dev@dpdk.org, Qi Zhang , Brett Creeley Date: Sat, 24 Apr 2021 14:03:37 +0800 Message-Id: <20210424060337.2824837-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210424060337.2824837-1-qi.z.zhang@intel.com> References: <20210424060337.2824837-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/4] common/iavf: use BIT() macro for offload/cap bits X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently raw hex values are used to define specific bits for each offload/capability in virtchnl.h. The can and has led to duplicate defined bits. Fix this by using the BIT() macro so it's immediately obvious which bits are used/available. Signed-off-by: Brett Creeley Signed-off-by: Qi Zhang --- drivers/common/iavf/virtchnl.h | 55 +++++++++++++++++----------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index 0772c28527..09d4c86550 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -372,35 +372,34 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource); * VIRTCHNL_VF_OFFLOAD_L2 flag is inclusive of base mode L2 offloads including * TX/RX Checksum offloading and TSO for non-tunnelled packets. */ -#define VIRTCHNL_VF_OFFLOAD_L2 0x00000001 -#define VIRTCHNL_VF_OFFLOAD_IWARP 0x00000002 -#define VIRTCHNL_VF_OFFLOAD_RSVD 0x00000004 -#define VIRTCHNL_VF_OFFLOAD_RSS_AQ 0x00000008 -#define VIRTCHNL_VF_OFFLOAD_RSS_REG 0x00000010 -#define VIRTCHNL_VF_OFFLOAD_WB_ON_ITR 0x00000020 -#define VIRTCHNL_VF_OFFLOAD_REQ_QUEUES 0x00000040 +#define VIRTCHNL_VF_OFFLOAD_L2 BIT(0) +#define VIRTCHNL_VF_OFFLOAD_IWARP BIT(1) +#define VIRTCHNL_VF_OFFLOAD_RSVD BIT(2) +#define VIRTCHNL_VF_OFFLOAD_RSS_AQ BIT(3) +#define VIRTCHNL_VF_OFFLOAD_RSS_REG BIT(4) +#define VIRTCHNL_VF_OFFLOAD_WB_ON_ITR BIT(5) +#define VIRTCHNL_VF_OFFLOAD_REQ_QUEUES BIT(6) /* used to negotiate communicating link speeds in Mbps */ -#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED 0x00000080 - /* 0X00000100 is reserved */ -#define VIRTCHNL_VF_LARGE_NUM_QPAIRS 0x00000200 -#define VIRTCHNL_VF_OFFLOAD_CRC 0x00000400 -#define VIRTCHNL_VF_OFFLOAD_VLAN_V2 0x00008000 -#define VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000 -#define VIRTCHNL_VF_OFFLOAD_RX_POLLING 0x00020000 -#define VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2 0x00040000 -#define VIRTCHNL_VF_OFFLOAD_RSS_PF 0X00080000 -#define VIRTCHNL_VF_OFFLOAD_ENCAP 0X00100000 -#define VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM 0X00200000 -#define VIRTCHNL_VF_OFFLOAD_RX_ENCAP_CSUM 0X00400000 -#define VIRTCHNL_VF_OFFLOAD_ADQ 0X00800000 -#define VIRTCHNL_VF_OFFLOAD_ADQ_V2 0X01000000 -#define VIRTCHNL_VF_OFFLOAD_USO 0X02000000 -#define VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC 0X04000000 -#define VIRTCHNL_VF_OFFLOAD_ADV_RSS_PF 0X08000000 -#define VIRTCHNL_VF_OFFLOAD_FDIR_PF 0X10000000 - /* 0X20000000 is reserved */ -#define VIRTCHNL_VF_CAP_DCF 0X40000000 - /* 0X80000000 is reserved */ +#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED BIT(7) + /* BIT(8) is reserved */ +#define VIRTCHNL_VF_LARGE_NUM_QPAIRS BIT(9) +#define VIRTCHNL_VF_OFFLOAD_CRC BIT(10) +#define VIRTCHNL_VF_OFFLOAD_VLAN_V2 BIT(15) +#define VIRTCHNL_VF_OFFLOAD_VLAN BIT(16) +#define VIRTCHNL_VF_OFFLOAD_RX_POLLING BIT(17) +#define VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2 BIT(18) +#define VIRTCHNL_VF_OFFLOAD_RSS_PF BIT(19) +#define VIRTCHNL_VF_OFFLOAD_ENCAP BIT(20) +#define VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM BIT(21) +#define VIRTCHNL_VF_OFFLOAD_RX_ENCAP_CSUM BIT(22) +#define VIRTCHNL_VF_OFFLOAD_ADQ BIT(23) +#define VIRTCHNL_VF_OFFLOAD_ADQ_V2 BIT(24) +#define VIRTCHNL_VF_OFFLOAD_USO BIT(25) +#define VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC BIT(26) +#define VIRTCHNL_VF_OFFLOAD_ADV_RSS_PF BIT(27) +#define VIRTCHNL_VF_OFFLOAD_FDIR_PF BIT(28) +#define VIRTCHNL_VF_CAP_DCF BIT(30) + /* BIT(31) is reserved */ #define VF_BASE_MODE_OFFLOADS (VIRTCHNL_VF_OFFLOAD_L2 | \ VIRTCHNL_VF_OFFLOAD_VLAN | \