From patchwork Wed Apr 21 16:34:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 91960 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1FFC7A0547; Wed, 21 Apr 2021 18:35:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E1CE7410F9; Wed, 21 Apr 2021 18:35:13 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 0504041B82 for ; Wed, 21 Apr 2021 18:35:12 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 21 Apr 2021 19:35:11 +0300 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13LGZBMd005314; Wed, 21 Apr 2021 19:35:11 +0300 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, asafp@nvidia.com, odia@nvidia.com, stable@dpdk.org Date: Wed, 21 Apr 2021 19:34:39 +0300 Message-Id: <20210421163441.17240-2-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210421163441.17240-1-talshn@nvidia.com> References: <20210421163441.17240-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads disablement X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" mlx5 offloads which are unsupported on Windows are currently disabled by checks with IBV/DV flags which are irrelevant to Windows. The checks are removed until they are fully available. Fixes: 93f4ece91a1f ("net/mlx5: spawn ethdev ports on Windows") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad Tested-by: Odi Assli --- drivers/net/mlx5/windows/mlx5_os.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 814063b5ce..5e53042b85 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -359,11 +359,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->swp = 0; config->ind_table_max_size = sh->device_attr.max_rwq_indirection_table_size; - if (RTE_CACHE_LINE_SIZE == 128 && - !(device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) - cqe_comp = 0; - else - cqe_comp = 1; + cqe_comp = 0; config->cqe_comp = cqe_comp; DRV_LOG(DEBUG, "tunnel offloading is not supported"); config->tunnel_en = 0; @@ -424,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, err = mlx5_dev_check_sibling_config(priv, config); if (err) goto error; - config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & - IBV_DEVICE_RAW_IP_CSUM); DRV_LOG(DEBUG, "checksum offloading is %ssupported", (config->hw_csum ? "" : "not ")); DRV_LOG(DEBUG, "counters are not supported"); @@ -439,19 +433,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", config->ind_table_max_size); - config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & - IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); DRV_LOG(DEBUG, "VLAN stripping is %ssupported", (config->hw_vlan_strip ? "" : "not ")); - config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & - IBV_RAW_PACKET_CAP_SCATTER_FCS); if (config->hw_padding) { DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); config->hw_padding = 0; } - config->tso = (sh->device_attr.max_tso > 0 && - (sh->device_attr.tso_supported_qpts & - (1 << IBV_QPT_RAW_PACKET))); if (config->tso) config->tso_max_payload_sz = sh->device_attr.max_tso; DRV_LOG(DEBUG, "%sMPS is %s.", From patchwork Wed Apr 21 16:34:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 91962 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60D72A0547; Wed, 21 Apr 2021 18:35:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 80D8641B93; Wed, 21 Apr 2021 18:35:16 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id F05B94068A for ; Wed, 21 Apr 2021 18:35:12 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 21 Apr 2021 19:35:11 +0300 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13LGZBMe005314; Wed, 21 Apr 2021 19:35:11 +0300 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, asafp@nvidia.com, odia@nvidia.com Date: Wed, 21 Apr 2021 19:34:40 +0300 Message-Id: <20210421163441.17240-3-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210421163441.17240-1-talshn@nvidia.com> References: <20210421163441.17240-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 2/3] common/mlx5: read checksum capability from DevX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" mlx5 in Windows needs the hca capability csum_cap to query the NIC for checksum offloading support Added the capability as part of the capabilities queried by the PMD using DevX. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad Tested-by: Odi Assli --- drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 268bcd0d99..d2e4ab33a2 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -837,6 +837,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, hcattr, wqe_vlan_insert); + attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, + hcattr, csum_cap); attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, lro_cap); attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 67b5f771c6..1fb9130e51 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -92,6 +92,7 @@ struct mlx5_hca_attr { uint32_t eth_net_offloads:1; uint32_t eth_virt:1; uint32_t wqe_vlan_insert:1; + uint32_t csum_cap:1; uint32_t wqe_inline_mode:2; uint32_t vport_inline_mode:3; uint32_t tunnel_stateless_geneve_rx:1; From patchwork Wed Apr 21 16:34:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 91963 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9EB0A0547; Wed, 21 Apr 2021 18:35:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C09F241B98; Wed, 21 Apr 2021 18:35:17 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 0DC8041B84 for ; Wed, 21 Apr 2021 18:35:12 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 21 Apr 2021 19:35:11 +0300 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13LGZBMf005314; Wed, 21 Apr 2021 19:35:11 +0300 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, asafp@nvidia.com, odia@nvidia.com Date: Wed, 21 Apr 2021 19:34:41 +0300 Message-Id: <20210421163441.17240-4-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210421163441.17240-1-talshn@nvidia.com> References: <20210421163441.17240-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 3/3] net/mlx5: support checksum offload on Windows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support of the checksum offloading by checking the relevant FW capability (csum_cap) for NIC support. RX supported offloads: DEV_RX_OFFLOAD_IPV4_CKSUM DEV_RX_OFFLOAD_UDP_CKSUM DEV_RX_OFFLOAD_TCP_CKSUM TX supported offloads: DEV_TX_OFFLOAD_IPV4_CKSUM DEV_TX_OFFLOAD_UDP_CKSUM DEV_TX_OFFLOAD_TCP_CKSUM Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad Tested-by: Odi Assli --- drivers/net/mlx5/windows/mlx5_os.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 5e53042b85..3fe3f55f49 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -420,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, err = mlx5_dev_check_sibling_config(priv, config); if (err) goto error; - DRV_LOG(DEBUG, "checksum offloading is %ssupported", - (config->hw_csum ? "" : "not ")); DRV_LOG(DEBUG, "counters are not supported"); config->ind_table_max_size = sh->device_attr.max_rwq_indirection_table_size; @@ -464,6 +462,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, sh->cmng.relaxed_ordering_read = config->hca_attr.relaxed_ordering_read; } + config->hw_csum = config->hca_attr.csum_cap; + DRV_LOG(DEBUG, "checksum offloading is %ssupported", + (config->hw_csum ? "" : "not ")); } if (config->devx) { uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];