From patchwork Sat Apr 10 01:11:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 90995 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE7CFA0547; Sat, 10 Apr 2021 03:11:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 78FD9141163; Sat, 10 Apr 2021 03:11:16 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 1504140688 for ; Sat, 10 Apr 2021 03:11:10 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FHH1X1gv2zNvVt for ; Sat, 10 Apr 2021 09:08:16 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Sat, 10 Apr 2021 09:10:59 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 10 Apr 2021 09:11:14 +0800 Message-ID: <1618017080-50053-2-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618017080-50053-1-git-send-email-humin29@huawei.com> References: <1617963365-41299-1-git-send-email-humin29@huawei.com> <1618017080-50053-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 1/7] net/hns3: remove variables of selecting Rx/Tx function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng Currently, there are four control variables (rx_simple_allowed, rx_vec_allowed, tx_simple_allowed and tx_vec_allowed) which are used to impact the selection of Rx/Tx burst function. The purpose of the design is to provide a way to control the selection of Rx/Tx burst function by modifying it's values, but these variables have no entry to modify unless make intrusive modifications. Now we already support runtime config to select Rx/Tx function, these variables could be removed. Fixes: a124f9e9591b ("net/hns3: add runtime config to select IO burst function") Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 5 ----- drivers/net/hns3/hns3_ethdev.h | 5 ----- drivers/net/hns3/hns3_ethdev_vf.c | 5 ----- drivers/net/hns3/hns3_rxtx.c | 11 ++++------- 4 files changed, 4 insertions(+), 22 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 6192705..19e2eca 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2512,11 +2512,6 @@ hns3_dev_configure(struct rte_eth_dev *dev) if (ret) goto cfg_err; - hns->rx_simple_allowed = true; - hns->rx_vec_allowed = true; - hns->tx_simple_allowed = true; - hns->tx_vec_allowed = true; - hns3_init_rx_ptype_tble(dev); hw->adapter_state = HNS3_NIC_CONFIGURED; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 4efa403..225a173 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -777,11 +777,6 @@ struct hns3_adapter { struct hns3_vf vf; }; - bool rx_simple_allowed; - bool rx_vec_allowed; - bool tx_simple_allowed; - bool tx_vec_allowed; - uint32_t rx_func_hint; uint32_t tx_func_hint; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 5f8a460..2043b54 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -854,11 +854,6 @@ hns3vf_dev_configure(struct rte_eth_dev *dev) if (ret) goto cfg_err; - hns->rx_simple_allowed = true; - hns->rx_vec_allowed = true; - hns->tx_simple_allowed = true; - hns->tx_vec_allowed = true; - hns3_init_rx_ptype_tble(dev); hw->adapter_state = HNS3_NIC_CONFIGURED; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index ebf7c82..7300f67 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2805,10 +2805,9 @@ hns3_get_rx_function(struct rte_eth_dev *dev) uint64_t offloads = dev->data->dev_conf.rxmode.offloads; bool vec_allowed, sve_allowed, simple_allowed; - vec_allowed = hns->rx_vec_allowed && - hns3_rx_check_vec_support(dev) == 0; + vec_allowed = hns3_rx_check_vec_support(dev) == 0; sve_allowed = vec_allowed && hns3_check_sve_support(); - simple_allowed = hns->rx_simple_allowed && !dev->data->scattered_rx && + simple_allowed = !dev->data->scattered_rx && (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0; if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) @@ -4195,11 +4194,9 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) struct hns3_adapter *hns = dev->data->dev_private; bool vec_allowed, sve_allowed, simple_allowed; - vec_allowed = hns->tx_vec_allowed && - hns3_tx_check_vec_support(dev) == 0; + vec_allowed = hns3_tx_check_vec_support(dev) == 0; sve_allowed = vec_allowed && hns3_check_sve_support(); - simple_allowed = hns->tx_simple_allowed && - hns3_tx_check_simple_support(dev); + simple_allowed = hns3_tx_check_simple_support(dev); *prep = NULL; From patchwork Sat Apr 10 01:11:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 90991 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50BDEA0547; Sat, 10 Apr 2021 03:11:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5109E14113A; Sat, 10 Apr 2021 03:11:11 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 0C6B8141137 for ; Sat, 10 Apr 2021 03:11:08 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FHH1X0j00zNvTQ for ; Sat, 10 Apr 2021 09:08:16 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Sat, 10 Apr 2021 09:10:59 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 10 Apr 2021 09:11:15 +0800 Message-ID: <1618017080-50053-3-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618017080-50053-1-git-send-email-humin29@huawei.com> References: <1617963365-41299-1-git-send-email-humin29@huawei.com> <1618017080-50053-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 2/7] net/hns3: fix missing rollback in PF init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds rollback processing when updating imissed stats failed in PF init. Fixes: 3e9f3042d7c8 ("net/hns3: add imissed packet stats") Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 19e2eca..edace55 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -4991,7 +4991,7 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) ret = hns3_update_imissed_stats(hw, true); if (ret) { hns3_err(hw, "clear imissed stats failed, ret = %d", ret); - return ret; + goto err_cmd_init; } hns3_config_all_msix_error(hw, true); From patchwork Sat Apr 10 01:11:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 90997 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E9AEA0547; Sat, 10 Apr 2021 03:11:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D4FAC14116C; Sat, 10 Apr 2021 03:11:18 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 625FA141139 for ; Sat, 10 Apr 2021 03:11:10 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FHH1X19D7zNvTX for ; Sat, 10 Apr 2021 09:08:16 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Sat, 10 Apr 2021 09:11:00 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 10 Apr 2021 09:11:16 +0800 Message-ID: <1618017080-50053-4-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618017080-50053-1-git-send-email-humin29@huawei.com> References: <1617963365-41299-1-git-send-email-humin29@huawei.com> <1618017080-50053-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 3/7] net/hns3: fix FLR failure when RAS concurrent with FLR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng Currently, if RAS interrupt and FLR occurred at the same time, FLR will be detected and corresponding schedule state will be set during RAS interrupt processing. However, the schedule state value will be overridden in subsequent RAS processing, resulting in FLR processing failure. This patch solves this problem. Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Hongbo Zheng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_intr.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 39a16a0..f3217c6 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -2133,10 +2133,11 @@ hns3_schedule_reset(struct hns3_adapter *hns) SCHEDULE_REQUESTED) return; if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == - SCHEDULE_DEFERRED) + SCHEDULE_DEFERRED) rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns); - __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, - __ATOMIC_RELAXED); + else + __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, + __ATOMIC_RELAXED); rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns); } From patchwork Sat Apr 10 01:11:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 90994 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E658CA0547; Sat, 10 Apr 2021 03:11:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E0BA2141155; Sat, 10 Apr 2021 03:11:14 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 038B0141132 for ; Sat, 10 Apr 2021 03:11:08 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FHH1X09XBzNvTD for ; Sat, 10 Apr 2021 09:08:16 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Sat, 10 Apr 2021 09:11:00 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 10 Apr 2021 09:11:17 +0800 Message-ID: <1618017080-50053-5-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618017080-50053-1-git-send-email-humin29@huawei.com> References: <1617963365-41299-1-git-send-email-humin29@huawei.com> <1618017080-50053-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 4/7] net/hns3: fix some packet type calc error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng Currently, the packet type calculated by vlan/ovlan/l3id/l4id/ol3id/ol4id fields have the following problems: 1) Identify error when exist vlan strip which will lead to the data buffer has non vlan header but mbuf's ptype have L2_ETHER_VLAN flag. 2) Some packet identifies error, eg: hardware report it's RARP or unknown packet, but ptype will marked with L2_ETHER . So driver will calculate packet type only by l3id/l4id/ol3id/ol4id fields. Fixes: 0e98d5e6d9c3 ("net/hns3: fix packet type report in Rx") Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.h | 4 +-- drivers/net/hns3/hns3_rxtx.c | 60 +++++++++++++----------------------------- drivers/net/hns3/hns3_rxtx.h | 14 ++++------ 3 files changed, 24 insertions(+), 54 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 225a173..c3d2078 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -682,12 +682,10 @@ struct hns3_ptype_table { * The next fields used to calc packet-type by the * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor. */ - uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM]; + uint32_t l3table[HNS3_L3TBL_NUM]; uint32_t l4table[HNS3_L4TBL_NUM]; - uint32_t inner_l2table[HNS3_L2TBL_NUM]; uint32_t inner_l3table[HNS3_L3TBL_NUM]; uint32_t inner_l4table[HNS3_L4TBL_NUM]; - uint32_t ol2table[HNS3_OL2TBL_NUM]; uint32_t ol3table[HNS3_OL3TBL_NUM]; uint32_t ol4table[HNS3_OL4TBL_NUM]; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 7300f67..8c5da44 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2003,32 +2003,12 @@ hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev) static void hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) { - tbl->l2l3table[0][0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; - tbl->l2l3table[0][1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; - tbl->l2l3table[0][2] = RTE_PTYPE_L2_ETHER_ARP; - tbl->l2l3table[0][3] = RTE_PTYPE_L2_ETHER; - tbl->l2l3table[0][4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT; - tbl->l2l3table[0][5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT; - tbl->l2l3table[0][6] = RTE_PTYPE_L2_ETHER_LLDP; - tbl->l2l3table[0][15] = RTE_PTYPE_L2_ETHER; - - tbl->l2l3table[1][0] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4; - tbl->l2l3table[1][1] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6; - tbl->l2l3table[1][2] = RTE_PTYPE_L2_ETHER_ARP; - tbl->l2l3table[1][3] = RTE_PTYPE_L2_ETHER_VLAN; - tbl->l2l3table[1][4] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV4_EXT; - tbl->l2l3table[1][5] = RTE_PTYPE_L2_ETHER_VLAN | RTE_PTYPE_L3_IPV6_EXT; - tbl->l2l3table[1][6] = RTE_PTYPE_L2_ETHER_LLDP; - tbl->l2l3table[1][15] = RTE_PTYPE_L2_ETHER_VLAN; - - tbl->l2l3table[2][0] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4; - tbl->l2l3table[2][1] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6; - tbl->l2l3table[2][2] = RTE_PTYPE_L2_ETHER_ARP; - tbl->l2l3table[2][3] = RTE_PTYPE_L2_ETHER_QINQ; - tbl->l2l3table[2][4] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV4_EXT; - tbl->l2l3table[2][5] = RTE_PTYPE_L2_ETHER_QINQ | RTE_PTYPE_L3_IPV6_EXT; - tbl->l2l3table[2][6] = RTE_PTYPE_L2_ETHER_LLDP; - tbl->l2l3table[2][15] = RTE_PTYPE_L2_ETHER_QINQ; + tbl->l3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; + tbl->l3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; + tbl->l3table[2] = RTE_PTYPE_L2_ETHER_ARP; + tbl->l3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT; + tbl->l3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT; + tbl->l3table[6] = RTE_PTYPE_L2_ETHER_LLDP; tbl->l4table[0] = RTE_PTYPE_L4_UDP; tbl->l4table[1] = RTE_PTYPE_L4_TCP; @@ -2041,17 +2021,17 @@ hns3_init_non_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) static void hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) { - tbl->inner_l2table[0] = RTE_PTYPE_INNER_L2_ETHER; - tbl->inner_l2table[1] = RTE_PTYPE_INNER_L2_ETHER_VLAN; - tbl->inner_l2table[2] = RTE_PTYPE_INNER_L2_ETHER_QINQ; - - tbl->inner_l3table[0] = RTE_PTYPE_INNER_L3_IPV4; - tbl->inner_l3table[1] = RTE_PTYPE_INNER_L3_IPV6; + tbl->inner_l3table[0] = RTE_PTYPE_INNER_L2_ETHER | + RTE_PTYPE_INNER_L3_IPV4; + tbl->inner_l3table[1] = RTE_PTYPE_INNER_L2_ETHER | + RTE_PTYPE_INNER_L3_IPV6; /* There is not a ptype for inner ARP/RARP */ tbl->inner_l3table[2] = RTE_PTYPE_UNKNOWN; tbl->inner_l3table[3] = RTE_PTYPE_UNKNOWN; - tbl->inner_l3table[4] = RTE_PTYPE_INNER_L3_IPV4_EXT; - tbl->inner_l3table[5] = RTE_PTYPE_INNER_L3_IPV6_EXT; + tbl->inner_l3table[4] = RTE_PTYPE_INNER_L2_ETHER | + RTE_PTYPE_INNER_L3_IPV4_EXT; + tbl->inner_l3table[5] = RTE_PTYPE_INNER_L2_ETHER | + RTE_PTYPE_INNER_L3_IPV6_EXT; tbl->inner_l4table[0] = RTE_PTYPE_INNER_L4_UDP; tbl->inner_l4table[1] = RTE_PTYPE_INNER_L4_TCP; @@ -2062,16 +2042,12 @@ hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl) tbl->inner_l4table[4] = RTE_PTYPE_UNKNOWN; tbl->inner_l4table[5] = RTE_PTYPE_INNER_L4_ICMP; - tbl->ol2table[0] = RTE_PTYPE_L2_ETHER; - tbl->ol2table[1] = RTE_PTYPE_L2_ETHER_VLAN; - tbl->ol2table[2] = RTE_PTYPE_L2_ETHER_QINQ; - - tbl->ol3table[0] = RTE_PTYPE_L3_IPV4; - tbl->ol3table[1] = RTE_PTYPE_L3_IPV6; + tbl->ol3table[0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; + tbl->ol3table[1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; tbl->ol3table[2] = RTE_PTYPE_UNKNOWN; tbl->ol3table[3] = RTE_PTYPE_UNKNOWN; - tbl->ol3table[4] = RTE_PTYPE_L3_IPV4_EXT; - tbl->ol3table[5] = RTE_PTYPE_L3_IPV6_EXT; + tbl->ol3table[4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT; + tbl->ol3table[5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT; tbl->ol4table[0] = RTE_PTYPE_UNKNOWN; tbl->ol4table[1] = RTE_PTYPE_TUNNEL_VXLAN; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index e39d18d..10a6c64 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -635,8 +635,8 @@ hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info, const uint32_t ol_info) { const struct hns3_ptype_table * const ptype_tbl = rxq->ptype_tbl; - uint32_t l2id, l3id, l4id; - uint32_t ol3id, ol4id, ol2id; + uint32_t ol3id, ol4id; + uint32_t l3id, l4id; uint32_t ptype; if (rxq->ptype_en) { @@ -647,20 +647,16 @@ hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info, ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S); ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S); - ol2id = hns3_get_field(ol_info, HNS3_RXD_OVLAN_M, HNS3_RXD_OVLAN_S); - l2id = hns3_get_field(l234_info, HNS3_RXD_VLAN_M, HNS3_RXD_VLAN_S); l3id = hns3_get_field(l234_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); l4id = hns3_get_field(l234_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S); if (unlikely(ptype_tbl->ol4table[ol4id])) - return ptype_tbl->inner_l2table[l2id] | - ptype_tbl->inner_l3table[l3id] | + return ptype_tbl->inner_l3table[l3id] | ptype_tbl->inner_l4table[l4id] | ptype_tbl->ol3table[ol3id] | - ptype_tbl->ol4table[ol4id] | ptype_tbl->ol2table[ol2id]; + ptype_tbl->ol4table[ol4id]; else - return ptype_tbl->l2l3table[l2id][l3id] | - ptype_tbl->l4table[l4id]; + return ptype_tbl->l3table[l3id] | ptype_tbl->l4table[l4id]; } void hns3_dev_rx_queue_release(void *queue); From patchwork Sat Apr 10 01:11:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 90992 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 47B14A0547; Sat, 10 Apr 2021 03:11:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 83C41141145; Sat, 10 Apr 2021 03:11:12 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 105F1141138 for ; Sat, 10 Apr 2021 03:11:08 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FHH1X10xZzNvTV for ; Sat, 10 Apr 2021 09:08:16 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Sat, 10 Apr 2021 09:11:00 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 10 Apr 2021 09:11:18 +0800 Message-ID: <1618017080-50053-6-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618017080-50053-1-git-send-email-humin29@huawei.com> References: <1617963365-41299-1-git-send-email-humin29@huawei.com> <1618017080-50053-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 5/7] net/hns3: fix incorrect timing in resetting queues X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang During the task queue pairs reset, the getimeofday is used to obtain the timestamp to determine whether the command execution times out. But gettimeofday is not monotonous, it can be modified by system administrators, so the timing may not be accurate or even cause the loop to wait consistently. And actually, in this scenario, it is not necessary to obain the timestamp. This patch removes the operation of obtaining the timestamp from the task queue pairs reset function. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 8c5da44..be93618 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -625,8 +625,8 @@ static int hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) { #define HNS3_TQP_RESET_TRY_MS 200 + uint16_t wait_time = 0; uint8_t reset_status; - uint64_t end; int ret; /* @@ -639,17 +639,18 @@ hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret); return ret; } - end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS; + do { /* Wait for tqp hw reset */ rte_delay_ms(HNS3_POLL_RESPONE_MS); + wait_time += HNS3_POLL_RESPONE_MS; ret = hns3_get_tqp_reset_status(hw, queue_id, &reset_status); if (ret) goto tqp_reset_fail; if (reset_status) break; - } while (get_timeofday_ms() < end); + } while (wait_time < HNS3_TQP_RESET_TRY_MS); if (!reset_status) { ret = -ETIMEDOUT; From patchwork Sat Apr 10 01:11:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 90993 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E44DDA0547; Sat, 10 Apr 2021 03:11:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AFC3014114D; Sat, 10 Apr 2021 03:11:13 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 0110540688 for ; Sat, 10 Apr 2021 03:11:08 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FHH1X1K4LzNvVR for ; Sat, 10 Apr 2021 09:08:16 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Sat, 10 Apr 2021 09:11:00 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 10 Apr 2021 09:11:19 +0800 Message-ID: <1618017080-50053-7-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618017080-50053-1-git-send-email-humin29@huawei.com> References: <1617963365-41299-1-git-send-email-humin29@huawei.com> <1618017080-50053-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 6/7] net/hns3: fix queue state when concurrent with reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang At the end of the reset, the state of queues need to be restored according to the states saved in the driver. If the start and stop operations of the queues are concurrent at this time, it may cause the final status to be uncertain. This patch requires queues to acquire the hw lock before starting and stopping. If the device is being restored due to reset at this time, it will block until the reset is completed. Fixes: fa29fe45a7b4 ("net/hns3: support queue start and stop") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_rxtx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index be93618..b45afcd 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4270,10 +4270,12 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); ret = hns3_reset_queue(hw, rx_queue_id, HNS3_RING_TYPE_RX); if (ret) { hns3_err(hw, "fail to reset Rx queue %u, ret = %d.", rx_queue_id, ret); + rte_spinlock_unlock(&hw->lock); return ret; } @@ -4281,11 +4283,13 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (ret) { hns3_err(hw, "fail to init Rx queue %u, ret = %d.", rx_queue_id, ret); + rte_spinlock_unlock(&hw->lock); return ret; } hns3_enable_rxq(rxq, true); dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; + rte_spinlock_unlock(&hw->lock); return ret; } @@ -4312,12 +4316,14 @@ hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); hns3_enable_rxq(rxq, false); hns3_rx_queue_release_mbufs(rxq); hns3_reset_sw_rxq(rxq); dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + rte_spinlock_unlock(&hw->lock); return 0; } @@ -4332,16 +4338,19 @@ hns3_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); ret = hns3_reset_queue(hw, tx_queue_id, HNS3_RING_TYPE_TX); if (ret) { hns3_err(hw, "fail to reset Tx queue %u, ret = %d.", tx_queue_id, ret); + rte_spinlock_unlock(&hw->lock); return ret; } hns3_init_txq(txq); hns3_enable_txq(txq, true); dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; + rte_spinlock_unlock(&hw->lock); return ret; } @@ -4355,6 +4364,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) if (!hns3_dev_indep_txrx_supported(hw)) return -ENOTSUP; + rte_spinlock_lock(&hw->lock); hns3_enable_txq(txq, false); hns3_tx_queue_release_mbufs(txq); /* @@ -4366,6 +4376,7 @@ hns3_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) */ hns3_init_txq(txq); dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + rte_spinlock_unlock(&hw->lock); return 0; } From patchwork Sat Apr 10 01:11:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 90996 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 15187A0547; Sat, 10 Apr 2021 03:11:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AAB6D141169; Sat, 10 Apr 2021 03:11:17 +0200 (CEST) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 6391C14113A for ; Sat, 10 Apr 2021 03:11:10 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FHH1X0WndzNvTN for ; Sat, 10 Apr 2021 09:08:16 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Sat, 10 Apr 2021 09:11:01 +0800 From: "Min Hu (Connor)" To: CC: Date: Sat, 10 Apr 2021 09:11:20 +0800 Message-ID: <1618017080-50053-8-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618017080-50053-1-git-send-email-humin29@huawei.com> References: <1617963365-41299-1-git-send-email-humin29@huawei.com> <1618017080-50053-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 7/7] net/hns3: fix configure FEC when concurrent with reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang Currently, after the reset is complete, the PMD restores the FEC according to the FEC configuration reserved in the driver. If there is a concurrency between the FEC setup operation and the restore operation after a reset, the FEC status of the last hardware may be unknown. This patch adds the step of obtaining the lock when setting the FEC to avoid concurrency between restore operation and setting operation. Fixes: 9bf2ea8dbc65 ("net/hns3: support FEC") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index edace55..c359efc 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6411,11 +6411,16 @@ hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) return -EINVAL; } + rte_spinlock_lock(&hw->lock); ret = hns3_set_fec_hw(hw, mode); - if (ret) + if (ret) { + rte_spinlock_unlock(&hw->lock); return ret; + } pf->fec_mode = mode; + rte_spinlock_unlock(&hw->lock); + return 0; }