From patchwork Fri Apr 9 10:09:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radu Nicolau X-Patchwork-Id: 90956 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D90FCA0579; Fri, 9 Apr 2021 12:10:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A421F407FF; Fri, 9 Apr 2021 12:10:39 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 11D514014D for ; Fri, 9 Apr 2021 12:10:37 +0200 (CEST) IronPort-SDR: /sNkptQmDYide83S9EGEbNuq56d/8ESPHL4A4R2M04oOrCASC1exide49GaIaPKZhMgpcVooD7 f6ET7mwa8npw== X-IronPort-AV: E=McAfee;i="6000,8403,9948"; a="173815684" X-IronPort-AV: E=Sophos;i="5.82,209,1613462400"; d="scan'208";a="173815684" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2021 03:10:36 -0700 IronPort-SDR: h0z8+WhlwceBuUjVkp8S31OA5T++EphUSx7zezOVpurVywidZU1jl2IiF9Tm4djZajuyPt+qi5 NZvXnREz9epA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,209,1613462400"; d="scan'208";a="530940428" Received: from silpixa00399477.ir.intel.com ([10.237.214.232]) by orsmga004.jf.intel.com with ESMTP; 09 Apr 2021 03:10:34 -0700 From: Radu Nicolau To: dev@dpdk.org Cc: bruce.richardson@intel.com, leyi.rong@intel.com, qi.z.zhang@intel.com, wenzhuo.lu@intel.com, Radu Nicolau Date: Fri, 9 Apr 2021 10:09:03 +0000 Message-Id: <20210409100903.8619-1-radu.nicolau@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-dev] [PATCH] net/ice: use write combining store for tail updates on AVX512 path. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Performance improvement: use a write combining store instead of a regular mmio write to update queue tail registers. Signed-off-by: Radu Nicolau Acked-by: Qi Zhang --- drivers/net/ice/ice_rxtx_vec_avx512.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c index 0e5a676e6..9f3501238 100644 --- a/drivers/net/ice/ice_rxtx_vec_avx512.c +++ b/drivers/net/ice/ice_rxtx_vec_avx512.c @@ -125,7 +125,7 @@ ice_rxq_rearm(struct ice_rx_queue *rxq) (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1)); /* Update the tail pointer on the NIC */ - ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id); + ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id); } static inline __m256i @@ -1111,7 +1111,7 @@ ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts, txq->tx_tail = tx_id; - ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail); + ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail); return nb_pkts; }