From patchwork Wed Mar 24 08:25:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yan, Zhirun" X-Patchwork-Id: 89739 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 01A42A0A02; Wed, 24 Mar 2021 09:33:41 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7DE8040683; Wed, 24 Mar 2021 09:33:41 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id D02CA4067B for ; Wed, 24 Mar 2021 09:33:39 +0100 (CET) IronPort-SDR: 8V7YOCQLdgyegTPQB1OrMlv+v++ea7Dsx3xtRHMzu6Xs4jNreoNmKK25u/m1q9ebPFsQUFcIzR 7l9Nk953C91A== X-IronPort-AV: E=McAfee;i="6000,8403,9932"; a="254653631" X-IronPort-AV: E=Sophos;i="5.81,274,1610438400"; d="scan'208";a="254653631" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2021 01:33:37 -0700 IronPort-SDR: 47UHaNxMJUa9AV/OHBebSNWVNL+NFQs1ondAiIJNwycqYONoGM9xEI7D1TcoNh+F97TdHgpsgE zRZLfg/G9PRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,274,1610438400"; d="scan'208";a="442115789" Received: from dpdk-zhirun-dev.sh.intel.com ([10.67.118.176]) by fmsmga002.fm.intel.com with ESMTP; 24 Mar 2021 01:33:35 -0700 From: Zhirun Yan To: dev@dpdk.org, qi.z.zhang@intel.com, xiao.w.wang@intel.com Cc: yahui.cao@intel.com, junfeng.guo@intel.com, ting.xu@intel.com, Zhirun Yan Date: Wed, 24 Mar 2021 16:25:21 +0800 Message-Id: <20210324082521.3862163-1-zhirun.yan@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v1] net/ice: support VXLAN VNI field in FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for VNI field in FDIR. Treat VXLAN flow type as ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN to align with shared code. It allows to match outer L2/L3, VNI and inner L2/L3 fields with VXLAN pattern. VNI takes 24 bits in VXLAN header, but uses 32 bits for matching in shared code. The 8 bits reserved field adjacent should always be 0. Signed-off-by: Zhirun Yan --- drivers/net/ice/ice_fdir_filter.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir_filter.c index 3af5812660..91638909c4 100644 --- a/drivers/net/ice/ice_fdir_filter.c +++ b/drivers/net/ice/ice_fdir_filter.c @@ -71,8 +71,8 @@ ICE_INSET_SCTP_SRC_PORT | ICE_INSET_SCTP_DST_PORT) #define ICE_FDIR_INSET_ETH_IPV4_VXLAN (\ - ICE_FDIR_INSET_ETH | \ - ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST) + ICE_FDIR_INSET_ETH | ICE_FDIR_INSET_ETH_IPV4 | \ + ICE_INSET_TUN_VXLAN_VNI) #define ICE_FDIR_INSET_IPV4_GTPU (\ ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | ICE_INSET_GTPU_TEID) @@ -903,6 +903,7 @@ ice_fdir_input_set_parse(uint64_t inset, enum ice_flow_field *field) {ICE_INSET_TUN_SCTP_DST_PORT, ICE_FLOW_FIELD_IDX_SCTP_DST_PORT}, {ICE_INSET_GTPU_TEID, ICE_FLOW_FIELD_IDX_GTPU_IP_TEID}, {ICE_INSET_GTPU_QFI, ICE_FLOW_FIELD_IDX_GTPU_EH_QFI}, + {ICE_INSET_TUN_VXLAN_VNI, ICE_FLOW_FIELD_IDX_VXLAN_VNI}, }; for (i = 0, j = 0; i < RTE_DIM(ice_inset_map); i++) { @@ -954,6 +955,12 @@ ice_fdir_input_set_hdrs(enum ice_fltr_ptype flow, struct ice_flow_seg_info *seg) ICE_FLOW_SET_HDRS(seg, ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER); break; + case ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN: + ICE_FLOW_SET_HDRS(seg, ICE_FLOW_SEG_HDR_UDP | + ICE_FLOW_SEG_HDR_IPV4 | + ICE_FLOW_SEG_HDR_VXLAN | + ICE_FLOW_SEG_HDR_IPV_OTHER); + break; case ICE_FLTR_PTYPE_NONF_IPV4_GTPU: ICE_FLOW_SET_HDRS(seg, ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 | @@ -1897,13 +1904,14 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad, vxlan_mask = item->mask; is_outer = false; - if (vxlan_spec || vxlan_mask) { - rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ITEM, - item, - "Invalid vxlan field"); - return -rte_errno; - } + if (!(vxlan_spec && vxlan_mask)) + break; + + if (vxlan_mask->vni) + *input_set |= ICE_INSET_TUN_VXLAN_VNI; + + filter->input.vxlan_data.vni = vxlan_spec->vni[2] << 24 | + vxlan_spec->vni[1] << 16 | vxlan_spec->vni[0] << 8; break; case RTE_FLOW_ITEM_TYPE_GTPU: @@ -1965,6 +1973,8 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad, else if (tunnel_type == ICE_FDIR_TUNNEL_TYPE_GTPU_EH && flow_type == ICE_FLTR_PTYPE_NONF_IPV6_UDP) flow_type = ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH; + else if (tunnel_type == ICE_FDIR_TUNNEL_TYPE_VXLAN) + flow_type = ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN; filter->tunnel_type = tunnel_type; filter->input.flow_type = flow_type;