From patchwork Tue Mar 23 18:52:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kozyrev X-Patchwork-Id: 89712 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 88144A0A0A; Tue, 23 Mar 2021 19:52:25 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F09F2140D22; Tue, 23 Mar 2021 19:52:20 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id CA16C4069E for ; Tue, 23 Mar 2021 19:52:17 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from akozyrev@nvidia.com) with SMTP; 23 Mar 2021 20:52:16 +0200 Received: from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12NIqFHn028719; Tue, 23 Mar 2021 20:52:16 +0200 From: Alexander Kozyrev To: dev@dpdk.org Cc: rasland@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com, stable@dpdk.org Date: Tue, 23 Mar 2021 18:52:08 +0000 Message-Id: <20210323185212.3878-2-akozyrev@nvidia.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210323185212.3878-1-akozyrev@nvidia.com> References: <20210323185212.3878-1-akozyrev@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/5] net/mlx5: check for a field size in modify field action X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a validation check to make sure that the specified width for MODIFY_FIELD RTE action is not bigger than a field size. Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/mlx5_flow_dv.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 23e5849783..4e78f54567 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -4610,7 +4610,8 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags, if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE && action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) { - if (action_modify_field->dst.offset >= dst_width || + if ((action_modify_field->dst.offset + + action_modify_field->width > dst_width) || (action_modify_field->dst.offset % 32)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, @@ -4626,7 +4627,8 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags, } if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE && action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) { - if (action_modify_field->src.offset >= src_width || + if ((action_modify_field->src.offset + + action_modify_field->width > src_width) || (action_modify_field->src.offset % 32)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, @@ -4642,9 +4644,16 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags, } if (action_modify_field->width == 0) return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION, - NULL, - "width is required for modify action"); + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, + "cannot modify 0 bits"); + else if (action_modify_field->width > dst_width || + action_modify_field->width > src_width) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, + "cannot modify more bits than" + " the width of a field"); if (action_modify_field->dst.field == action_modify_field->src.field) return rte_flow_error_set(error, EINVAL, From patchwork Tue Mar 23 18:52:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kozyrev X-Patchwork-Id: 89715 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7448A0A0A; Tue, 23 Mar 2021 19:52:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 98D25140D5B; Tue, 23 Mar 2021 19:52:24 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id D71F3140D0D for ; Tue, 23 Mar 2021 19:52:17 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from akozyrev@nvidia.com) with SMTP; 23 Mar 2021 20:52:16 +0200 Received: from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12NIqFHo028719; Tue, 23 Mar 2021 20:52:16 +0200 From: Alexander Kozyrev To: dev@dpdk.org Cc: rasland@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com, stable@dpdk.org Date: Tue, 23 Mar 2021 18:52:09 +0000 Message-Id: <20210323185212.3878-3-akozyrev@nvidia.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210323185212.3878-1-akozyrev@nvidia.com> References: <20210323185212.3878-1-akozyrev@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/5] net/mlx5: adjust modify field action endianess X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Masks that used to modify a packet field must be in a big endian format. Convert then to BE to ensure proper modification. Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/mlx5_flow_dv.c | 241 ++++++++++++++------------------ 1 file changed, 103 insertions(+), 138 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 4e78f54567..aba66b2cfb 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1345,11 +1345,13 @@ mlx5_flow_field_id_to_modify_info if (data->offset < 32) { info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_DMAC_47_16}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1358,10 +1360,8 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){2, 4 * idx, MLX5_MODI_OUT_DMAC_15_0}; - mask[idx] = (width) ? 0x0000ffff : 0x0; - if (width < 16) - mask[idx] = (mask[idx] << (16 - width)) & - 0x0000ffff; + mask[idx] = rte_cpu_to_be_32(0x0000ffff >> + (16 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, @@ -1375,11 +1375,13 @@ mlx5_flow_field_id_to_modify_info if (data->offset < 32) { info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_SMAC_47_16}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1388,10 +1390,8 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){2, 4 * idx, MLX5_MODI_OUT_SMAC_15_0}; - mask[idx] = (width) ? 0x0000ffff : 0x0; - if (width < 16) - mask[idx] = (mask[idx] << (16 - width)) & - 0x0000ffff; + mask[idx] = rte_cpu_to_be_32(0x0000ffff >> + (16 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, @@ -1406,91 +1406,71 @@ mlx5_flow_field_id_to_modify_info case RTE_FLOW_FIELD_VLAN_ID: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_FIRST_VID}; - if (mask) { - mask[idx] = 0x00000fff; - if (width < 12) - mask[idx] = (mask[idx] << (12 - width)) & - 0x00000fff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x00000fff >> + (12 - width)); break; case RTE_FLOW_FIELD_MAC_TYPE: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_ETHERTYPE}; - if (mask) { - mask[idx] = 0x0000ffff; - if (width < 16) - mask[idx] = (mask[idx] << (16 - width)) & - 0x0000ffff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000ffff >> + (16 - width)); break; case RTE_FLOW_FIELD_IPV4_DSCP: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IP_DSCP}; - if (mask) { - mask[idx] = 0x0000003f; - if (width < 6) - mask[idx] = (mask[idx] << (6 - width)) & - 0x0000003f; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000003f >> + (6 - width)); break; case RTE_FLOW_FIELD_IPV4_TTL: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPV4_TTL}; - if (mask) { - mask[idx] = 0x000000ff; - if (width < 8) - mask[idx] = (mask[idx] << (8 - width)) & - 0x000000ff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x000000ff >> + (8 - width)); break; case RTE_FLOW_FIELD_IPV4_SRC: info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_SIPV4}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0xffffffff >> + (32 - width)); break; case RTE_FLOW_FIELD_IPV4_DST: info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_DIPV4}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0xffffffff >> + (32 - width)); break; case RTE_FLOW_FIELD_IPV6_DSCP: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IP_DSCP}; - if (mask) { - mask[idx] = 0x0000003f; - if (width < 6) - mask[idx] = (mask[idx] << (6 - width)) & - 0x0000003f; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000003f >> + (6 - width)); break; case RTE_FLOW_FIELD_IPV6_HOPLIMIT: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPV6_HOPLIMIT}; - if (mask) { - mask[idx] = 0x000000ff; - if (width < 8) - mask[idx] = (mask[idx] << (8 - width)) & - 0x000000ff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x000000ff >> + (8 - width)); break; case RTE_FLOW_FIELD_IPV6_SRC: if (mask) { if (data->offset < 32) { info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_SIPV6_127_96}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1501,11 +1481,13 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 4 * idx, MLX5_MODI_OUT_SIPV6_95_64}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1516,11 +1498,13 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 8 * idx, MLX5_MODI_OUT_SIPV6_63_32}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1529,9 +1513,8 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){4, 12 * idx, MLX5_MODI_OUT_SIPV6_31_0}; - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); + mask[idx] = rte_cpu_to_be_32(0xffffffff >> + (32 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, @@ -1552,11 +1535,13 @@ mlx5_flow_field_id_to_modify_info if (data->offset < 32) { info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_DIPV6_127_96}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1567,11 +1552,13 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 4 * idx, MLX5_MODI_OUT_DIPV6_95_64}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1582,11 +1569,13 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 8 * idx, MLX5_MODI_OUT_DIPV6_63_32}; - mask[idx] = 0xffffffff; if (width < 32) { - mask[idx] = mask[idx] << (32 - width); + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); width = 0; } else { + mask[idx] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1595,9 +1584,8 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){4, 12 * idx, MLX5_MODI_OUT_DIPV6_31_0}; - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); + mask[idx] = rte_cpu_to_be_32(0xffffffff >> + (32 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, @@ -1616,70 +1604,51 @@ mlx5_flow_field_id_to_modify_info case RTE_FLOW_FIELD_TCP_PORT_SRC: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_TCP_SPORT}; - if (mask) { - mask[idx] = 0x0000ffff; - if (width < 16) - mask[idx] = (mask[idx] << (16 - width)) & - 0x0000ffff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000ffff >> + (16 - width)); break; case RTE_FLOW_FIELD_TCP_PORT_DST: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_TCP_DPORT}; - if (mask) { - mask[idx] = 0x0000ffff; - if (width < 16) - mask[idx] = (mask[idx] << (16 - width)) & - 0x0000ffff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000ffff >> + (16 - width)); break; case RTE_FLOW_FIELD_TCP_SEQ_NUM: info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_TCP_SEQ_NUM}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = (mask[idx] << (32 - width)); - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0xffffffff >> + (32 - width)); break; case RTE_FLOW_FIELD_TCP_ACK_NUM: info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_TCP_ACK_NUM}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = (mask[idx] << (32 - width)); - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0xffffffff >> + (32 - width)); break; case RTE_FLOW_FIELD_TCP_FLAGS: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_TCP_FLAGS}; - if (mask) { - mask[idx] = 0x0000003f; - if (width < 6) - mask[idx] = (mask[idx] << (6 - width)) & - 0x0000003f; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000003f >> + (6 - width)); break; case RTE_FLOW_FIELD_UDP_PORT_SRC: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_UDP_SPORT}; - if (mask) { - mask[idx] = 0x0000ffff; - if (width < 16) - mask[idx] = (mask[idx] << (16 - width)) & - 0x0000ffff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000ffff >> + (16 - width)); break; case RTE_FLOW_FIELD_UDP_PORT_DST: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_UDP_DPORT}; - if (mask) { - mask[idx] = 0x0000ffff; - if (width < 16) - mask[idx] = (mask[idx] << (16 - width)) & - 0x0000ffff; - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0x0000ffff >> + (16 - width)); break; case RTE_FLOW_FIELD_VXLAN_VNI: /* not supported yet */ @@ -1690,11 +1659,9 @@ mlx5_flow_field_id_to_modify_info case RTE_FLOW_FIELD_GTP_TEID: info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_GTP_TEID}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); - } + if (mask) + mask[idx] = rte_cpu_to_be_32(0xffffffff >> + (32 - width)); break; case RTE_FLOW_FIELD_TAG: { @@ -1706,11 +1673,10 @@ mlx5_flow_field_id_to_modify_info MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field)); info[idx] = (struct field_modify_info){4, 0, reg_to_field[reg]}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); - } + if (mask) + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); } break; case RTE_FLOW_FIELD_MARK: @@ -1723,11 +1689,10 @@ mlx5_flow_field_id_to_modify_info MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field)); info[idx] = (struct field_modify_info){4, 0, reg_to_field[reg]}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); - } + if (mask) + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); } break; case RTE_FLOW_FIELD_META: @@ -1739,11 +1704,10 @@ mlx5_flow_field_id_to_modify_info MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field)); info[idx] = (struct field_modify_info){4, 0, reg_to_field[reg]}; - if (mask) { - mask[idx] = 0xffffffff; - if (width < 32) - mask[idx] = mask[idx] << (32 - width); - } + if (mask) + mask[idx] = + rte_cpu_to_be_32(0xffffffff >> + (32 - width)); } break; case RTE_FLOW_FIELD_POINTER: @@ -1751,7 +1715,7 @@ mlx5_flow_field_id_to_modify_info if (mask[idx]) { memcpy(&value[idx], (void *)(uintptr_t)data->value, 32); - value[idx] = RTE_BE32(value[idx]); + value[idx] = rte_cpu_to_be_32(value[idx]); break; } } @@ -1759,7 +1723,8 @@ mlx5_flow_field_id_to_modify_info case RTE_FLOW_FIELD_VALUE: for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) { if (mask[idx]) { - value[idx] = RTE_BE32((uint32_t)data->value); + value[idx] = + rte_cpu_to_be_32((uint32_t)data->value); break; } } From patchwork Tue Mar 23 18:52:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kozyrev X-Patchwork-Id: 89713 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83562A0A0A; Tue, 23 Mar 2021 19:52:31 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 26850140D3A; Tue, 23 Mar 2021 19:52:22 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id D3125140D06 for ; Tue, 23 Mar 2021 19:52:17 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from akozyrev@nvidia.com) with SMTP; 23 Mar 2021 20:52:16 +0200 Received: from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12NIqFHp028719; Tue, 23 Mar 2021 20:52:16 +0200 From: Alexander Kozyrev To: dev@dpdk.org Cc: rasland@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com, stable@dpdk.org Date: Tue, 23 Mar 2021 18:52:10 +0000 Message-Id: <20210323185212.3878-4-akozyrev@nvidia.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210323185212.3878-1-akozyrev@nvidia.com> References: <20210323185212.3878-1-akozyrev@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/5] net/mlx5: check extended metadata for mark modififcation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The MODIFY_FIELD RTE action requires the extended metadata support in order to manipulate on MARK register. Check if it is supported and reject the MODIFY_FIELD action if it is not. Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/mlx5_flow_dv.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index aba66b2cfb..71165cdfdd 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -4542,7 +4542,8 @@ mlx5_flow_item_field_width(enum rte_flow_field_id field) /** * Validate the generic modify field actions. - * + * @param[in] dev + * Pointer to the rte_eth_dev structure. * @param[in] action_flags * Holds the actions detected until now. * @param[in] action @@ -4557,11 +4558,14 @@ mlx5_flow_item_field_width(enum rte_flow_field_id field) * a negative errno value otherwise and rte_errno is set. */ static int -flow_dv_validate_action_modify_field(const uint64_t action_flags, +flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, + const uint64_t action_flags, const struct rte_flow_action *action, struct rte_flow_error *error) { int ret = 0; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_config *config = &priv->config; const struct rte_flow_action_modify_field *action_modify_field = action->conf; uint32_t dst_width = @@ -4640,6 +4644,15 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags, NULL, "modifications of an arbitrary" " place in a packet is not supported"); + if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK || + action_modify_field->src.field == RTE_FLOW_FIELD_MARK) { + if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || + !mlx5_flow_ext_mreg_supported(dev)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "cannot modify mark without extended" + " metadata register support"); + } if (action_modify_field->operation != RTE_FLOW_MODIFY_SET) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, @@ -6914,9 +6927,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "modify field action " "is not supported for group 0"); - ret = flow_dv_validate_action_modify_field(action_flags, - actions, - error); + ret = flow_dv_validate_action_modify_field(dev, + action_flags, + actions, + error); if (ret < 0) return ret; /* Count all modify-header actions as one action. */ From patchwork Tue Mar 23 18:52:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kozyrev X-Patchwork-Id: 89716 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 12064A0A0A; Tue, 23 Mar 2021 19:52:50 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D81B8140D6F; Tue, 23 Mar 2021 19:52:25 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id DE772140D19 for ; Tue, 23 Mar 2021 19:52:17 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from akozyrev@nvidia.com) with SMTP; 23 Mar 2021 20:52:16 +0200 Received: from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12NIqFHq028719; Tue, 23 Mar 2021 20:52:16 +0200 From: Alexander Kozyrev To: dev@dpdk.org Cc: rasland@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com Date: Tue, 23 Mar 2021 18:52:11 +0000 Message-Id: <20210323185212.3878-5-akozyrev@nvidia.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210323185212.3878-1-akozyrev@nvidia.com> References: <20210323185212.3878-1-akozyrev@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/5] net/mlx5: allow group 0 modify field action X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There is a limitation about copying one header field to another for the Flow group 0. Such copy action is not allowed there. But setting a header field with an immediate value is perfrectly fine. Allow the MODIFY_FIELD RTE action on group 0 in case the source field is an immediate value or a pointer to it. Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/mlx5_flow_dv.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 71165cdfdd..ac781f45eb 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -4548,8 +4548,8 @@ mlx5_flow_item_field_width(enum rte_flow_field_id field) * Holds the actions detected until now. * @param[in] action * Pointer to the modify action. - * @param[in] item_flags - * Holds the items detected. + * @param[in] attr + * Pointer to the flow attributes. * @param[out] error * Pointer to error structure. * @@ -4561,6 +4561,7 @@ static int flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, const uint64_t action_flags, const struct rte_flow_action *action, + const struct rte_flow_attr *attr, struct rte_flow_error *error) { int ret = 0; @@ -4596,6 +4597,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, } if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE && action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) { + if (!attr->transfer && !attr->group) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, "modify field action " + "is not supported for group 0"); if ((action_modify_field->src.offset + action_modify_field->width > src_width) || (action_modify_field->src.offset % 32)) @@ -6922,14 +6928,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET; break; case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: - if (!attr->transfer && !attr->group) - return rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ACTION, - NULL, "modify field action " - "is not supported for group 0"); ret = flow_dv_validate_action_modify_field(dev, action_flags, actions, + attr, error); if (ret < 0) return ret; From patchwork Tue Mar 23 18:52:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kozyrev X-Patchwork-Id: 89711 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CFCA2A0A0A; Tue, 23 Mar 2021 19:52:19 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF255140D17; Tue, 23 Mar 2021 19:52:19 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id C66B040683 for ; Tue, 23 Mar 2021 19:52:17 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from akozyrev@nvidia.com) with SMTP; 23 Mar 2021 20:52:16 +0200 Received: from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12NIqFHr028719; Tue, 23 Mar 2021 20:52:16 +0200 From: Alexander Kozyrev To: dev@dpdk.org Cc: rasland@nvidia.com, viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com Date: Tue, 23 Mar 2021 18:52:12 +0000 Message-Id: <20210323185212.3878-6-akozyrev@nvidia.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210323185212.3878-1-akozyrev@nvidia.com> References: <20210323185212.3878-1-akozyrev@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 5/5] doc: add list of supported Field IDs to modify X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Include the rte_flow_field_id enumeration into the documentation to provide the full list of all supported Field IDs availabe for the MODIFY_FIELD RTE action. Signed-off-by: Alexander Kozyrev --- doc/guides/prog_guide/rte_flow.rst | 45 ++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst index 62a57919eb..4265b7bfb8 100644 --- a/doc/guides/prog_guide/rte_flow.rst +++ b/doc/guides/prog_guide/rte_flow.rst @@ -2784,6 +2784,41 @@ can be used as both source and destination fields as set by ``field``. The immediate value ``RTE_FLOW_FIELD_VALUE`` (or a pointer to it ``RTE_FLOW_FIELD_POINTER``) is allowed as a source only. ``RTE_FLOW_FIELD_START`` is used to point to the beginning of a packet. +See ``enum rte_flow_field_id`` for the list of supported fields: + +.. code-block:: c + + enum rte_flow_field_id { + RTE_FLOW_FIELD_START = 0, /**< Start of a packet. */ + RTE_FLOW_FIELD_MAC_DST, /**< Destination MAC Address. */ + RTE_FLOW_FIELD_MAC_SRC, /**< Source MAC Address. */ + RTE_FLOW_FIELD_VLAN_TYPE, /**< 802.1Q Tag Identifier. */ + RTE_FLOW_FIELD_VLAN_ID, /**< 802.1Q VLAN Identifier. */ + RTE_FLOW_FIELD_MAC_TYPE, /**< EtherType. */ + RTE_FLOW_FIELD_IPV4_DSCP, /**< IPv4 DSCP. */ + RTE_FLOW_FIELD_IPV4_TTL, /**< IPv4 Time To Live. */ + RTE_FLOW_FIELD_IPV4_SRC, /**< IPv4 Source Address. */ + RTE_FLOW_FIELD_IPV4_DST, /**< IPv4 Destination Address. */ + RTE_FLOW_FIELD_IPV6_DSCP, /**< IPv6 DSCP. */ + RTE_FLOW_FIELD_IPV6_HOPLIMIT, /**< IPv6 Hop Limit. */ + RTE_FLOW_FIELD_IPV6_SRC, /**< IPv6 Source Address. */ + RTE_FLOW_FIELD_IPV6_DST, /**< IPv6 Destination Address. */ + RTE_FLOW_FIELD_TCP_PORT_SRC, /**< TCP Source Port Number. */ + RTE_FLOW_FIELD_TCP_PORT_DST, /**< TCP Destination Port Number. */ + RTE_FLOW_FIELD_TCP_SEQ_NUM, /**< TCP Sequence Number. */ + RTE_FLOW_FIELD_TCP_ACK_NUM, /**< TCP Acknowledgment Number. */ + RTE_FLOW_FIELD_TCP_FLAGS, /**< TCP Flags. */ + RTE_FLOW_FIELD_UDP_PORT_SRC, /**< UDP Source Port Number. */ + RTE_FLOW_FIELD_UDP_PORT_DST, /**< UDP Destination Port Number. */ + RTE_FLOW_FIELD_VXLAN_VNI, /**< VXLAN Network Identifier. */ + RTE_FLOW_FIELD_GENEVE_VNI, /**< GENEVE Network Identifier. */ + RTE_FLOW_FIELD_GTP_TEID, /**< GTP Tunnel Endpoint Identifier. */ + RTE_FLOW_FIELD_TAG, /**< Tag value. */ + RTE_FLOW_FIELD_MARK, /**< Mark value. */ + RTE_FLOW_FIELD_META, /**< Metadata value. */ + RTE_FLOW_FIELD_POINTER, /**< Memory pointer. */ + RTE_FLOW_FIELD_VALUE, /**< Immediate value. */ + }; ``op`` selects the operation to perform on a destination field. - ``set`` copies the data from ``src`` field to ``dst`` field. @@ -2817,12 +2852,15 @@ for ``RTE_FLOW_FIELD_VALUE`` and ``RTE_FLOW_FIELD_POINTER`` respectively. .. table:: MODIFY_FIELD - +-----------------------------------------+ + +---------------+-------------------------+ | Field | Value | +===============+=========================+ | ``op`` | operation to perform | + +---------------+-------------------------+ | ``dst`` | destination field | + +---------------+-------------------------+ | ``src`` | source field | + +---------------+-------------------------+ | ``width`` | number of bits to use | +---------------+-------------------------+ @@ -2830,12 +2868,15 @@ for ``RTE_FLOW_FIELD_VALUE`` and ``RTE_FLOW_FIELD_POINTER`` respectively. .. table:: destination/source field definition - +--------------------------------------------------------------------------+ + +---------------+----------------------------------------------------------+ | Field | Value | +===============+==========================================================+ | ``field`` | ID: packet field, mark, meta, tag, immediate, pointer | + +---------------+----------------------------------------------------------+ | ``level`` | encapsulation level of a packet field or tag array index | + +---------------+----------------------------------------------------------+ | ``offset`` | number of bits to skip at the beginning | + +---------------+----------------------------------------------------------+ | ``value`` | immediate value or a pointer to this value | +---------------+----------------------------------------------------------+