From patchwork Fri Mar 19 01:07:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89524 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CACB9A0562; Fri, 19 Mar 2021 02:07:50 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8B40B140FFD; Fri, 19 Mar 2021 02:07:09 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 8AAFB140FC6 for ; Fri, 19 Mar 2021 02:06:57 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw2Q94z9175 for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:51 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:19 +0800 Message-ID: <1616116046-47578-2-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengwen Feng Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration. Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function. This patch support runtime config to select io burst function, which add two config: rx_func_hint and tx_func_hint, both could assign vec/sve/simple/common. The driver will use the following rules to select io burst func: a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function. b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function. c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function. d. if hint equal common then use the common function. e. if hint not set then: e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function. e.3. else use the common function. Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE). In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function. Signed-off-by: Chengwen Feng Signed-off-by: Min Hu (Connor) --- v6: - document hns3.rst about description of vec, common and simple. --- doc/guides/nics/hns3.rst | 19 +++++++++ doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- 6 files changed, 156 insertions(+), 14 deletions(-) diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst index 84bd7a3..8f48240 100644 --- a/doc/guides/nics/hns3.rst +++ b/doc/guides/nics/hns3.rst @@ -46,6 +46,25 @@ Prerequisites - Follow the DPDK :ref:`Getting Started Guide for Linux ` to setup the basic DPDK environment. +Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Rx usage condition then use the default vector Rx implementation, 'neon' for Kunpeng Arm platform. + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function which indicates the Scalar algorithm obtained from rte_eth_rx_burst_mode_get. + When equal "common" then use the common Rx function which indicates the Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get. + +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Tx usage condition then use the default vector Tx implementation, 'neon' for Kunpeng Arm platform. + When equal "sve" and meet the sve Tx usage condition then use the sve Tx function. + When equal "simple" and meet the simple Tx usage condition then use the simple Tx function which indicates the Scalar Simple algorithm obtained from rte_eth_tx_burst_mode_get. + When equal "common" then use the common Tx function which indicated the Scalar algorithm obtained from rte_eth_tx_burst_mode_get. + Driver compilation and testing ------------------------------ diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index dc5399f..1d85942 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -60,6 +60,7 @@ New Features * Added support for module EEPROM dumping. * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. + * Added support for runtime config to select IO burst function. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 9cbcc13..28aa27a 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "hns3_ethdev.h" #include "hns3_logs.h" @@ -6505,6 +6506,78 @@ hns3_get_module_info(struct rte_eth_dev *dev, return 0; } +static int +hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) +{ + uint32_t hint = HNS3_IO_FUNC_HINT_NONE; + + RTE_SET_USED(key); + + if (strcmp(value, "vec") == 0) + hint = HNS3_IO_FUNC_HINT_VEC; + else if (strcmp(value, "sve") == 0) + hint = HNS3_IO_FUNC_HINT_SVE; + else if (strcmp(value, "simple") == 0) + hint = HNS3_IO_FUNC_HINT_SIMPLE; + else if (strcmp(value, "common") == 0) + hint = HNS3_IO_FUNC_HINT_COMMON; + + /* If the hint is valid then update output parameters */ + if (hint != HNS3_IO_FUNC_HINT_NONE) + *(uint32_t *)extra_args = hint; + + return 0; +} + +static const char * +hns3_get_io_hint_func_name(uint32_t hint) +{ + switch (hint) { + case HNS3_IO_FUNC_HINT_VEC: + return "vec"; + case HNS3_IO_FUNC_HINT_SVE: + return "sve"; + case HNS3_IO_FUNC_HINT_SIMPLE: + return "simple"; + case HNS3_IO_FUNC_HINT_COMMON: + return "common"; + default: + return "none"; + } +} + +void +hns3_parse_devargs(struct rte_eth_dev *dev) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; + uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; + struct hns3_hw *hw = &hns->hw; + struct rte_kvargs *kvlist; + + if (dev->device->devargs == NULL) + return; + + kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); + if (!kvlist) + return; + + rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, + &hns3_parse_io_hint_func, &rx_func_hint); + rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, + &hns3_parse_io_hint_func, &tx_func_hint); + rte_kvargs_free(kvlist); + + if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, + hns3_get_io_hint_func_name(rx_func_hint)); + hns->rx_func_hint = rx_func_hint; + if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, + hns3_get_io_hint_func_name(tx_func_hint)); + hns->tx_func_hint = tx_func_hint; +} + static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, @@ -6625,6 +6698,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = false; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); /* * Set default max packet size according to the mtu @@ -6758,5 +6832,8 @@ static struct rte_pci_driver rte_hns3_pmd = { RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 932600d..ec4b475 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -772,9 +772,23 @@ struct hns3_adapter { bool tx_simple_allowed; bool tx_vec_allowed; + uint32_t rx_func_hint; + uint32_t tx_func_hint; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; +enum { + HNS3_IO_FUNC_HINT_NONE = 0, + HNS3_IO_FUNC_HINT_VEC, + HNS3_IO_FUNC_HINT_SVE, + HNS3_IO_FUNC_HINT_SIMPLE, + HNS3_IO_FUNC_HINT_COMMON +}; + +#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" +#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" + #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 @@ -975,6 +989,7 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); +void hns3_parse_devargs(struct rte_eth_dev *dev); static inline bool is_reset_pending(struct hns3_adapter *hns) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index fd20c52..f3eaefb 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2834,6 +2834,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = true; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); ret = hns3_reset_init(hw); if (ret) @@ -2962,3 +2963,6 @@ static struct rte_pci_driver rte_hns3vf_pmd = { RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 00167c4..f5c7d71 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2689,13 +2689,26 @@ hns3_get_rx_function(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; uint64_t offloads = dev->data->dev_conf.rxmode.offloads; + bool vec_allowed, sve_allowed, simple_allowed; + + vec_allowed = hns->rx_vec_allowed && + hns3_rx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->rx_simple_allowed && !dev->data->scattered_rx && + (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0; + + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_recv_pkts_vec; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_recv_pkts_vec_sve; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) + return hns3_recv_pkts; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON) + return hns3_recv_scattered_pkts; - if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0) - return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve : - hns3_recv_pkts_vec; - - if (hns->rx_simple_allowed && !dev->data->scattered_rx && - (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0) + if (vec_allowed) + return hns3_recv_pkts_vec; + if (simple_allowed) return hns3_recv_pkts; return hns3_recv_scattered_pkts; @@ -3930,19 +3943,32 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) { uint64_t offloads = dev->data->dev_conf.txmode.offloads; struct hns3_adapter *hns = dev->data->dev_private; + bool vec_allowed, sve_allowed, simple_allowed; - if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) { - *prep = NULL; - return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve : - hns3_xmit_pkts_vec; - } + vec_allowed = hns->tx_vec_allowed && + hns3_tx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->tx_simple_allowed && + offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); - if (hns->tx_simple_allowed && - offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) { - *prep = NULL; + *prep = NULL; + + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_xmit_pkts_vec; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_xmit_pkts_vec_sve; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) return hns3_xmit_pkts_simple; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) { + *prep = hns3_prep_pkts; + return hns3_xmit_pkts; } + if (vec_allowed) + return hns3_xmit_pkts_vec; + if (simple_allowed) + return hns3_xmit_pkts_simple; + *prep = hns3_prep_pkts; return hns3_xmit_pkts; } From patchwork Fri Mar 19 01:07:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89522 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5705A0562; Fri, 19 Mar 2021 02:07:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EEDF4140FF3; Fri, 19 Mar 2021 02:07:06 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 8A5DC140FBD for ; Fri, 19 Mar 2021 02:06:57 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw2ycqz917C for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:51 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:20 +0800 Message-ID: <1616116046-47578-3-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 2/8] net/hns3: support for outer UDP cksum X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang Kunpeng930 support outer UDP cksum, this patch add support for it. Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_cmd.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 3 ++ drivers/net/hns3/hns3_ethdev.h | 4 ++ drivers/net/hns3/hns3_ethdev_vf.c | 3 ++ drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- 8 files changed, 89 insertions(+), 19 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 1d85942..c3324d8 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -61,6 +61,7 @@ New Features * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. + * Added support for outer UDP checksum in Kunpeng930. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 8b9f075..03f8048 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -433,6 +433,9 @@ hns3_parse_capability(struct hns3_hw *hw, if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B)) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 1); + if (hns3_get_bit(caps, HNS3_CAPS_UDP_TUNNEL_CSUM_B)) + hns3_set_bit(hw->capability, + HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1); } static uint32_t diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 28aa27a..3949153 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2620,6 +2620,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index ec4b475..0fc0a1c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -798,6 +798,7 @@ enum { #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 #define HNS3_DEV_SUPPORT_STASH_B 0x7 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 +#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA #define hns3_dev_dcb_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) @@ -831,6 +832,9 @@ enum { #define hns3_dev_rxd_adv_layout_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) +#define hns3_dev_outer_udp_cksum_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) + #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index f3eaefb..e1e41b8 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -988,6 +988,9 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index f5c7d71..7529279 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2967,7 +2967,7 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc, hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ? rxm->outer_l2_len + rxm->outer_l3_len : 0; paylen = rxm->pkt_len - hdr_len; - desc->tx.paylen = rte_cpu_to_le_32(paylen); + desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen); hns3_set_tso(desc, paylen, rxm); /* @@ -3204,8 +3204,10 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, { struct hns3_desc *tx_ring = txq->tx_ring; struct hns3_desc *desc = &tx_ring[tx_desc_id]; + uint64_t ol_flags = m->ol_flags; uint32_t tmp_outer = 0; uint32_t tmp_inner = 0; + uint32_t tmp_ol4cs; int ret; /* @@ -3215,7 +3217,7 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * calculations, the length of the L2 header include the outer and * inner, will be filled during the parsing of tunnel packects. */ - if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) { + if (!(ol_flags & PKT_TX_TUNNEL_MASK)) { /* * For non tunnel type the tunnel type id is 0, so no need to * assign a value to it. Only the inner(normal) L2 header length @@ -3230,7 +3232,8 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * inner l2_len. It would lead a cksum error. So driver has to * calculate the header length. */ - if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) && + if (unlikely(!(ol_flags & + (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) && m->outer_l2_len == 0)) { struct rte_net_hdr_lens hdr_len; (void)rte_net_get_ptype(m, &hdr_len, @@ -3247,6 +3250,9 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer); desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner); + tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ? + BIT(HNS3_TXD_OL4CS_B) : 0; + desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs); return 0; } @@ -3376,31 +3382,78 @@ hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num, return false; } +static bool +hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv4_hdr *ipv4_hdr; + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) + ipv4_hdr->hdr_checksum = 0; + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags); + + return true; + } + *l4_proto = ipv4_hdr->next_proto_id; + return false; +} + +static bool +hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv6_hdr *ipv6_hdr; + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + + return true; + } + *l4_proto = ipv6_hdr->proto; + return false; +} + static void hns3_outer_header_cksum_prepare(struct rte_mbuf *m) { uint64_t ol_flags = m->ol_flags; uint32_t paylen, hdr_len, l4_proto; + struct rte_udp_hdr *udp_hdr; if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6))) return; if (ol_flags & PKT_TX_OUTER_IPV4) { - struct rte_ipv4_hdr *ipv4_hdr; - ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, - m->outer_l2_len); - l4_proto = ipv4_hdr->next_proto_id; - if (ol_flags & PKT_TX_OUTER_IP_CKSUM) - ipv4_hdr->hdr_checksum = 0; + if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto)) + return; } else { - struct rte_ipv6_hdr *ipv6_hdr; - ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, - m->outer_l2_len); - l4_proto = ipv6_hdr->proto; + if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto)) + return; } + /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */ if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) { - struct rte_udp_hdr *udp_hdr; hdr_len = m->l2_len + m->l3_len + m->l4_len; hdr_len += m->outer_l2_len + m->outer_l3_len; paylen = m->pkt_len - hdr_len; @@ -3686,7 +3739,7 @@ hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); @@ -3702,7 +3755,7 @@ hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 9adeb24..cd04200 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -149,6 +149,7 @@ #define HNS3_TXD_MSS_S 0 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) +#define HNS3_TXD_OL4CS_B 22 #define HNS3_L2_LEN_UNIT 1UL #define HNS3_L3_LEN_UNIT 2UL #define HNS3_L4_LEN_UNIT 2UL @@ -234,7 +235,7 @@ struct hns3_desc { }; }; - uint32_t paylen; + uint32_t paylen_fd_dop_ol4cs; uint16_t tp_fe_sc_vld_ra_ri; uint16_t mss; } tx; @@ -503,6 +504,7 @@ struct hns3_queue_info { }; #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_OUTER_UDP_CKSUM | \ PKT_TX_OUTER_IP_CKSUM | \ PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \ diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c index 2a22a1a..90e45c6 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_sve.c +++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c @@ -408,8 +408,9 @@ hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq, (uint64_t *)&txdp->tx.outer_vlan_tag, offsets, svdup_n_u64(0)); /* save offset 24~31byte of every BD */ - svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen, - offsets, svdup_n_u64(valid_bit)); + svst1_scatter_u64offset_u64(pg, + (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs, + offsets, svdup_n_u64(valid_bit)); /* Increment bytes counter */ uint32_t idx; From patchwork Fri Mar 19 01:07:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89523 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE5E0A0562; Fri, 19 Mar 2021 02:07:43 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 561B0140FF5; Fri, 19 Mar 2021 02:07:08 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 515604003F for ; Fri, 19 Mar 2021 02:06:57 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw3WVgz917M for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:51 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:21 +0800 Message-ID: <1616116046-47578-4-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 3/8] net/hns3: adjust the format of RAS related structures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng Adjust the format of hns3 RAS related structures to resolve the static check warnings. Signed-off-by: Hongbo Zheng Signed-off-by: Min Hu (Connor) --- v3: - change code styles. --- drivers/net/hns3/hns3_intr.c | 2126 ++++++++++++++++++++++++------------------ 1 file changed, 1224 insertions(+), 902 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 2563504..265dae8 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -28,282 +28,375 @@ static const char *reset_string[HNS3_MAX_RESET] = { }; static const struct hns3_hw_error mac_afifo_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "egu_cge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "egu_cge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "egu_lge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "egu_lge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "cge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "lge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "lge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "cge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "lge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "egu_cge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "egu_lge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "egu_ge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "egu_cge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "egu_cge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "egu_lge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "egu_lge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "cge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "lge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "lge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "cge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "lge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "egu_cge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "egu_lge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "egu_ge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { - { .int_msk = 0xFFFFFFFF, - .msg = "rpu_rx_pkt_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = 0xFFFFFFFF, + .msg = "rpu_rx_pkt_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { - { .int_msk = BIT(13), - .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rcb_tx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rcb_rx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rcb_tx_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rcb_rx_ebd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rcb_tso_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rcb_tx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rcb_rx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tpu_tx_pkt_0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tpu_tx_pkt_1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "rd_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "wr_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "ooo_ecc_err_detect", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(31), - .msg = "ooo_ecc_err_multpl", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(13), + .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rcb_tx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rcb_rx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rcb_tx_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rcb_rx_ebd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rcb_tso_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rcb_tx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rcb_rx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tpu_tx_pkt_0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tpu_tx_pkt_1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "rd_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "wr_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "ooo_ecc_err_detect", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(31), + .msg = "ooo_ecc_err_multpl", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { - { .int_msk = BIT(29), - .msg = "rx_q_search_miss", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(29), + .msg = "rx_q_search_miss", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_pf_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "low_water_line_err_port", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "low_water_line_err_port", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_pf_abnormal_int[] = { - { .int_msk = BIT(0), - .msg = "tx_vlan_tag_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "rss_list_tc_unassigned_queue_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "tx_vlan_tag_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "rss_list_tc_unassigned_queue_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { - { .int_msk = BIT(3), - .msg = "tx_rd_fbd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(4), - .msg = "rx_rd_ebd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(3), + .msg = "tx_rd_fbd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(4), + .msg = "rx_rd_ebd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { - { .int_msk = BIT(0), - .msg = "over_8bd_no_fe", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tso_mss_cmp_min_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "tso_mss_cmp_max_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "buf_wait_timeout", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "over_8bd_no_fe", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tso_mss_cmp_min_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "tso_mss_cmp_max_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "buf_wait_timeout", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_tcm_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "imp_itcm0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "imp_itcm1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "imp_itcm2_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "imp_itcm3_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "imp_dtcm0_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "imp_dtcm0_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "imp_dtcm1_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "imp_dtcm1_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(17), - .msg = "imp_itcm4_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "imp_itcm0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "imp_itcm1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "imp_itcm2_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "imp_itcm3_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "imp_dtcm0_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "imp_dtcm0_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "imp_dtcm1_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "imp_dtcm1_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(17), + .msg = "imp_itcm4_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error cmdq_mem_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "cmdq_nic_rx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "cmdq_nic_tx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cmdq_nic_rx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "cmdq_nic_tx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "cmdq_nic_rx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "cmdq_nic_tx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "cmdq_nic_rx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "cmdq_nic_tx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "cmdq_nic_rx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "cmdq_nic_tx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cmdq_nic_rx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "cmdq_nic_tx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "cmdq_nic_rx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "cmdq_nic_tx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "cmdq_nic_rx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "cmdq_nic_tx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tqp_int_ecc_int[] = { - { .int_msk = BIT(6), - .msg = "tqp_int_cfg_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "tqp_int_cfg_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(8), - .msg = "tqp_int_ctrl_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "tqp_int_ctrl_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(10), - .msg = "tx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "rx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(6), + .msg = "tqp_int_cfg_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "tqp_int_cfg_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(8), + .msg = "tqp_int_ctrl_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "tqp_int_ctrl_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(10), + .msg = "tx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "rx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_rd_poison_int[] = { - { .int_msk = BIT(0), - .msg = "imp_rd_poison_int", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "imp_rd_poison_int", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; #define HNS3_SSU_MEM_ECC_ERR(x) \ - { .int_msk = BIT(x), \ - .msg = "ssu_mem" #x "_ecc_mbit_err", \ - .reset_level = HNS3_GLOBAL_RESET } +{ \ + .int_msk = BIT(x), \ + .msg = "ssu_mem" #x "_ecc_mbit_err", \ + .reset_level = HNS3_GLOBAL_RESET \ +} static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { HNS3_SSU_MEM_ECC_ERR(0), @@ -344,722 +437,951 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { }; static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { - { .int_msk = BIT(0), - .msg = "ssu_mem32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ssu_mem32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_common_ecc_int[] = { - { .int_msk = BIT(0), - .msg = "buf_sum_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "ppp_mb_num_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "ppp_mbid_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ppp_rlt_mac_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ppp_rlt_host_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "cks_edit_position_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "cks_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "vlan_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "vlan_num_ot_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "vlan_num_in_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "buf_sum_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "ppp_mb_num_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "ppp_mbid_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ppp_rlt_mac_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ppp_rlt_host_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "cks_edit_position_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "cks_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "vlan_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "vlan_num_ot_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "vlan_num_in_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_int[] = { - { .int_msk = BIT(0), - .msg = "igu_rx_buf0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_rx_buf1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "igu_rx_buf0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_rx_buf1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error msix_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "msix_nic_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "msix_nic_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { - { .int_msk = BIT(0), - .msg = "vf_vlan_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "umv_mcast_group_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "umv_key_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "umv_key_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "umv_key_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "umv_key_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "umv_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "rss_tc_mode_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rss_idt_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "rss_idt_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "rss_idt_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "rss_idt_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "rss_idt_mem4_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "rss_idt_mem5_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rss_idt_mem6_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rss_idt_mem7_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rss_idt_mem8_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rss_idt_mem9_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rss_idt_mem10_ecc_m1bit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rss_idt_mem11_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rss_idt_mem12_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rss_idt_mem13_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rss_idt_mem14_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rss_idt_mem15_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "port_vlan_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "mcast_linear_table_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "mcast_result_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "flow_director_ad_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "flow_director_ad_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "rx_vlan_tag_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "vf_vlan_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "umv_mcast_group_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "umv_key_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "umv_key_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "umv_key_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "umv_key_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "umv_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "rss_tc_mode_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rss_idt_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "rss_idt_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "rss_idt_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "rss_idt_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "rss_idt_mem4_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "rss_idt_mem5_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rss_idt_mem6_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rss_idt_mem7_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rss_idt_mem8_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rss_idt_mem9_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rss_idt_mem10_ecc_m1bit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rss_idt_mem11_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rss_idt_mem12_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rss_idt_mem13_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rss_idt_mem14_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rss_idt_mem15_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "port_vlan_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "mcast_linear_table_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "mcast_result_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "flow_director_ad_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "flow_director_ad_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "rx_vlan_tag_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(0), - .msg = "hfs_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rslt_descr_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tx_vlan_tag_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "FD_CN0_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "FD_CN1_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "GRO_AD_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "hfs_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rslt_descr_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tx_vlan_tag_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "FD_CN0_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "FD_CN1_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "GRO_AD_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(4), - .msg = "gro_bd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "gro_context_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_stash_cfg_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "axi_rd_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(4), + .msg = "gro_bd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "gro_context_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_stash_cfg_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "axi_rd_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tm_sch_int[] = { - { .int_msk = BIT(1), - .msg = "tm_sch_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tm_sch_port_shap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tm_sch_port_shap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "tm_sch_port_shap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "tm_sch_port_shap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "tm_sch_rq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "tm_sch_rq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tm_sch_nq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tm_sch_nq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "tm_sch_roce_up_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "tm_sch_roce_up_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "tm_sch_rcb_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "tm_sch_rcb_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "tm_sch_ssu_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(31), - .msg = "tm_sch_ssu_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "tm_sch_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tm_sch_port_shap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tm_sch_port_shap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "tm_sch_port_shap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "tm_sch_port_shap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "tm_sch_rq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "tm_sch_rq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tm_sch_nq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tm_sch_nq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "tm_sch_roce_up_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "tm_sch_roce_up_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "tm_sch_rcb_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "tm_sch_rcb_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "tm_sch_ssu_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(31), + .msg = "tm_sch_ssu_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_fifo_int[] = { - { .int_msk = BIT(0), - .msg = "qcn_shap_gp0_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "qcn_shap_gp0_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "qcn_shap_gp1_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_shap_gp1_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "qcn_shap_gp2_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_shap_gp2_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "qcn_shap_gp3_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_shap_gp3_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "qcn_shap_gp0_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_shap_gp0_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "qcn_shap_gp1_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_shap_gp1_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "qcn_shap_gp2_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_gp2_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "qcn_shap_gp3_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_shap_gp3_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "qcn_byte_info_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_byte_info_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "qcn_shap_gp0_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "qcn_shap_gp0_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "qcn_shap_gp1_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_shap_gp1_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "qcn_shap_gp2_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_shap_gp2_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "qcn_shap_gp3_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_shap_gp3_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "qcn_shap_gp0_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_shap_gp0_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "qcn_shap_gp1_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_shap_gp1_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "qcn_shap_gp2_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_gp2_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "qcn_shap_gp3_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_shap_gp3_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "qcn_byte_info_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_byte_info_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "qcn_byte_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_time_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_fb_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_link_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_rate_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_tmplt_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_cfg_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "qcn_gp3_barral_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "qcn_byte_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_time_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_fb_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_link_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_rate_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_tmplt_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_cfg_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "qcn_gp3_barral_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ncsi_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "ncsi_tx_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "ncsi_tx_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_fifo_overflow_int[] = { - { .int_msk = BIT(0), - .msg = "ig_mac_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ig_host_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ig_roc_buf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ig_host_data_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ig_host_key_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qm_eof_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "mb_rlt_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "dup_uncopy_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "dup_cnt_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "dup_cnt_drop_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "dup_cnt_wrb_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "host_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "mac_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "host_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "mac_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "dup_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "out_queue_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "bank2_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "bank1_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "bank0_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ig_mac_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ig_host_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ig_roc_buf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ig_host_data_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ig_host_key_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qm_eof_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "mb_rlt_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "dup_uncopy_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "dup_cnt_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "dup_cnt_drop_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "dup_cnt_wrb_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "host_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "mac_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "host_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "mac_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "dup_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "out_queue_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "bank2_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "bank1_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "bank0_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_ets_tcg_int[] = { - { .int_msk = BIT(0), - .msg = "ets_rd_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ets_wr_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ets_rd_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ets_wr_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ets_rd_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ets_wr_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ets_rd_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ets_wr_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_egu_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "rx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rx_stp_fifo_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "rx_stp_fifo_underflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tx_buf_underrun", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "rx_stp_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "rx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rx_stp_fifo_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "rx_stp_fifo_underflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tx_buf_underrun", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "rx_stp_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_err_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tpu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "roc_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tpu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "igu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "roc_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tpu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "igu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "ets_rd_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "ets_wr_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ets_rd_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "ets_wr_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tpu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "roc_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tpu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "igu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "roc_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tpu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "igu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "ets_rd_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "ets_wr_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ets_rd_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "ets_wr_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "IMP_TCM_ECC_INT_STS", - .hw_err = imp_tcm_ecc_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "CMDQ_MEM_ECC_INT_STS", - .hw_err = cmdq_mem_ecc_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "IMP_RD_POISON_INT_STS", - .hw_err = imp_rd_poison_int }, - { .desc_offset = 0, - .data_offset = 3, - .msg = "TQP_INT_ECC_INT_STS", - .hw_err = tqp_int_ecc_int }, - { .desc_offset = 0, - .data_offset = 4, - .msg = "MSIX_ECC_INT_STS", - .hw_err = msix_ecc_int }, - { .desc_offset = 2, - .data_offset = 2, - .msg = "SSU_ECC_MULTI_BIT_INT_0", - .hw_err = ssu_ecc_multi_bit_int_0 }, - { .desc_offset = 2, - .data_offset = 3, - .msg = "SSU_ECC_MULTI_BIT_INT_1", - .hw_err = ssu_ecc_multi_bit_int_1 }, - { .desc_offset = 2, - .data_offset = 4, - .msg = "SSU_COMMON_ERR_INT", - .hw_err = ssu_common_ecc_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "IGU_INT_STS", - .hw_err = igu_int }, - { .desc_offset = 4, - .data_offset = 1, - .msg = "PPP_MPF_ABNORMAL_INT_ST1", - .hw_err = ppp_mpf_abnormal_int_st1 }, - { .desc_offset = 4, - .data_offset = 3, - .msg = "PPP_MPF_ABNORMAL_INT_ST3", - .hw_err = ppp_mpf_abnormal_int_st3 }, - { .desc_offset = 5, - .data_offset = 1, - .msg = "PPU_MPF_ABNORMAL_INT_ST1", - .hw_err = ppu_mpf_abnormal_int_st1 }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", - .hw_err = ppu_mpf_abnormal_int_st2_ras }, - { .desc_offset = 5, - .data_offset = 3, - .msg = "PPU_MPF_ABNORMAL_INT_ST3", - .hw_err = ppu_mpf_abnormal_int_st3 }, - { .desc_offset = 6, - .data_offset = 0, - .msg = "TM_SCH_RINT", - .hw_err = tm_sch_int }, - { .desc_offset = 7, - .data_offset = 0, - .msg = "QCN_FIFO_RINT", - .hw_err = qcn_fifo_int }, - { .desc_offset = 7, - .data_offset = 1, - .msg = "QCN_ECC_RINT", - .hw_err = qcn_ecc_int }, - { .desc_offset = 9, - .data_offset = 0, - .msg = "NCSI_ECC_INT_RPT", - .hw_err = ncsi_ecc_int }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "IMP_TCM_ECC_INT_STS", + .hw_err = imp_tcm_ecc_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "CMDQ_MEM_ECC_INT_STS", + .hw_err = cmdq_mem_ecc_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "IMP_RD_POISON_INT_STS", + .hw_err = imp_rd_poison_int + }, { + .desc_offset = 0, + .data_offset = 3, + .msg = "TQP_INT_ECC_INT_STS", + .hw_err = tqp_int_ecc_int + }, { + .desc_offset = 0, + .data_offset = 4, + .msg = "MSIX_ECC_INT_STS", + .hw_err = msix_ecc_int + }, { + .desc_offset = 2, + .data_offset = 2, + .msg = "SSU_ECC_MULTI_BIT_INT_0", + .hw_err = ssu_ecc_multi_bit_int_0 + }, { + .desc_offset = 2, + .data_offset = 3, + .msg = "SSU_ECC_MULTI_BIT_INT_1", + .hw_err = ssu_ecc_multi_bit_int_1 + }, { + .desc_offset = 2, + .data_offset = 4, + .msg = "SSU_COMMON_ERR_INT", + .hw_err = ssu_common_ecc_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "IGU_INT_STS", + .hw_err = igu_int + }, { + .desc_offset = 4, + .data_offset = 1, + .msg = "PPP_MPF_ABNORMAL_INT_ST1", + .hw_err = ppp_mpf_abnormal_int_st1 + }, { + .desc_offset = 4, + .data_offset = 3, + .msg = "PPP_MPF_ABNORMAL_INT_ST3", + .hw_err = ppp_mpf_abnormal_int_st3 + }, { + .desc_offset = 5, + .data_offset = 1, + .msg = "PPU_MPF_ABNORMAL_INT_ST1", + .hw_err = ppu_mpf_abnormal_int_st1 + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", + .hw_err = ppu_mpf_abnormal_int_st2_ras + }, { + .desc_offset = 5, + .data_offset = 3, + .msg = "PPU_MPF_ABNORMAL_INT_ST3", + .hw_err = ppu_mpf_abnormal_int_st3 + }, { + .desc_offset = 6, + .data_offset = 0, + .msg = "TM_SCH_RINT", + .hw_err = tm_sch_int + }, { + .desc_offset = 7, + .data_offset = 0, + .msg = "QCN_FIFO_RINT", + .hw_err = qcn_fifo_int + }, { + .desc_offset = 7, + .data_offset = 1, + .msg = "QCN_ECC_RINT", + .hw_err = qcn_ecc_int + }, { + .desc_offset = 9, + .data_offset = 0, + .msg = "NCSI_ECC_INT_RPT", + .hw_err = ncsi_ecc_int + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_RAS", - .hw_err = ssu_port_based_err_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "SSU_FIFO_OVERFLOW_INT", - .hw_err = ssu_fifo_overflow_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "SSU_ETS_TCG_INT", - .hw_err = ssu_ets_tcg_int }, - { .desc_offset = 1, - .data_offset = 0, - .msg = "IGU_EGU_TNL_INT_STS", - .hw_err = igu_egu_tnl_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", - .hw_err = ppu_pf_abnormal_int_ras }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_RAS", + .hw_err = ssu_port_based_err_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "SSU_FIFO_OVERFLOW_INT", + .hw_err = ssu_fifo_overflow_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "SSU_ETS_TCG_INT", + .hw_err = ssu_ets_tcg_int + }, { + .desc_offset = 1, + .data_offset = 0, + .msg = "IGU_EGU_TNL_INT_STS", + .hw_err = igu_egu_tnl_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", + .hw_err = ppu_pf_abnormal_int_ras + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { - { .desc_offset = 1, - .data_offset = 0, - .msg = "MAC_AFIFO_TNL_INT_R", - .hw_err = mac_afifo_tnl_int }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", - .hw_err = ppu_mpf_abnormal_int_st2_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 1, + .data_offset = 0, + .msg = "MAC_AFIFO_TNL_INT_R", + .hw_err = mac_afifo_tnl_int + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", + .hw_err = ppu_mpf_abnormal_int_st2_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_MSIX", - .hw_err = ssu_port_based_pf_int }, - { .desc_offset = 2, - .data_offset = 0, - .msg = "PPP_PF_ABNORMAL_INT_ST0", - .hw_err = ppp_pf_abnormal_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", - .hw_err = ppu_pf_abnormal_int_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_MSIX", + .hw_err = ssu_port_based_pf_int + }, { + .desc_offset = 2, + .data_offset = 0, + .msg = "PPP_PF_ABNORMAL_INT_ST0", + .hw_err = ppp_pf_abnormal_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", + .hw_err = ppu_pf_abnormal_int_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; enum hns3_hw_err_type { From patchwork Fri Mar 19 01:07:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89521 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C72AA0562; Fri, 19 Mar 2021 02:07:32 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B0DF6140FEE; Fri, 19 Mar 2021 02:07:05 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 532EB40143 for ; Fri, 19 Mar 2021 02:06:57 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw38m9z917G for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:52 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:22 +0800 Message-ID: <1616116046-47578-5-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 4/8] net/hns3: delete redundant xstats RAS statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics. Signed-off-by: Hongbo Zheng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 2 - drivers/net/hns3/hns3_ethdev.h | 35 --------------- drivers/net/hns3/hns3_intr.c | 1 - drivers/net/hns3/hns3_stats.c | 100 +---------------------------------------- drivers/net/hns3/hns3_stats.h | 1 - 5 files changed, 1 insertion(+), 138 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3949153..139e893 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5768,14 +5768,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { hns3_warn(hw, "Detected IMP RD poison!"); - hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { hns3_warn(hw, "Detected IMP CMDQ error!"); - hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 0fc0a1c..314916c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -561,38 +561,6 @@ struct hns3_hw { #define HNS3_FLAG_TC_BASE_SCH_MODE 1 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_int_cnt; - uint64_t ppu_mpf_abn_int_st2_msix_cnt; - uint64_t ssu_port_based_pf_int_cnt; - uint64_t ppp_pf_abnormal_int_cnt; - uint64_t ppu_pf_abnormal_int_msix_cnt; - - uint64_t imp_tcm_ecc_int_cnt; - uint64_t cmdq_mem_ecc_int_cnt; - uint64_t imp_rd_poison_int_cnt; - uint64_t tqp_int_ecc_int_cnt; - uint64_t msix_ecc_int_cnt; - uint64_t ssu_ecc_multi_bit_int_0_cnt; - uint64_t ssu_ecc_multi_bit_int_1_cnt; - uint64_t ssu_common_ecc_int_cnt; - uint64_t igu_int_cnt; - uint64_t ppp_mpf_abnormal_int_st1_cnt; - uint64_t ppp_mpf_abnormal_int_st3_cnt; - uint64_t ppu_mpf_abnormal_int_st1_cnt; - uint64_t ppu_mpf_abn_int_st2_ras_cnt; - uint64_t ppu_mpf_abnormal_int_st3_cnt; - uint64_t tm_sch_int_cnt; - uint64_t qcn_fifo_int_cnt; - uint64_t qcn_ecc_int_cnt; - uint64_t ncsi_ecc_int_cnt; - uint64_t ssu_port_based_err_int_cnt; - uint64_t ssu_fifo_overflow_int_cnt; - uint64_t ssu_ets_tcg_int_cnt; - uint64_t igu_egu_tnl_int_cnt; - uint64_t ppu_pf_abnormal_int_ras_cnt; -}; - /* vlan entry information. */ struct hns3_user_vlan_table { LIST_ENTRY(hns3_user_vlan_table) next; @@ -738,9 +706,6 @@ struct hns3_pf { uint16_t max_umv_size; uint16_t used_umv_size; - /* Statistics information for abnormal interrupt */ - struct hns3_err_msix_intr_stats abn_int_stats; - bool support_sfp_query; uint32_t fec_mode; /* current FEC mode for ethdev */ diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 265dae8..c259f2e 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } - hns3_error_int_stats_add(hns, reg); } err++; } diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 941c75f..7cda36c 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -201,65 +201,6 @@ static const struct hns3_xstats_name_offset hns3_mac_strings[] = { HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)} }; -static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = { - {"MAC_AFIFO_TNL_INT_R", - HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)}, - {"SSU_PORT_BASED_ERR_INT_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)}, - {"PPP_PF_ABNORMAL_INT_ST0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)}, - {"IMP_TCM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)}, - {"CMDQ_MEM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)}, - {"IMP_RD_POISON_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)}, - {"TQP_INT_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)}, - {"MSIX_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)}, - {"SSU_COMMON_ERR_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)}, - {"IGU_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)}, - {"TM_SCH_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)}, - {"QCN_FIFO_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)}, - {"QCN_ECC_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)}, - {"NCSI_ECC_INT_RPT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)}, - {"SSU_PORT_BASED_ERR_INT_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)}, - {"SSU_FIFO_OVERFLOW_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)}, - {"SSU_ETS_TCG_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)}, - {"IGU_EGU_TNL_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)}, -}; - /* The statistic of reset */ static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = { {"REQ_RESET_CNT", @@ -333,9 +274,6 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ sizeof(hns3_mac_strings[0])) -#define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \ - sizeof(hns3_error_int_stats_strings[0])) - #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \ sizeof(hns3_reset_stats_strings[0])) @@ -363,7 +301,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \ +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -750,23 +688,6 @@ hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, } } -void -hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err) -{ - struct hns3_pf *pf = &hns->pf; - uint16_t i; - char *addr; - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - *(uint64_t *)addr += 1; - break; - } - } -} - static void hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, int *count) @@ -932,7 +853,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, unsigned int n) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; struct hns3_hw *hw = &hns->hw; struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; @@ -986,13 +906,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, count++; } - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } } /* Get the reset stat */ @@ -1134,13 +1047,6 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_imissed_stats_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_error_int_stats_strings[i].name); - count++; - } } for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, @@ -1358,7 +1264,6 @@ int hns3_dev_xstats_reset(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; int ret; /* Clear tqp stats */ @@ -1379,9 +1284,6 @@ hns3_dev_xstats_reset(struct rte_eth_dev *dev) if (ret) return ret; - /* Clear error stats */ - memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats)); - return 0; } diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 70a9c5b..8ea69b4 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint32_t size); int hns3_stats_reset(struct rte_eth_dev *dev); -void hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err); int hns3_tqp_stats_init(struct hns3_hw *hw); void hns3_tqp_stats_uninit(struct hns3_hw *hw); int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear); From patchwork Fri Mar 19 01:07:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89520 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37030A0562; Fri, 19 Mar 2021 02:07:24 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A8BB140FE2; Fri, 19 Mar 2021 02:07:03 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 59A2E140FC7 for ; Fri, 19 Mar 2021 02:06:56 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw21BSz90vX for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:52 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:23 +0800 Message-ID: <1616116046-47578-6-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 5/8] net/hns3: support imissed stats for PF/VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch added function level imissed stats for PF and VF. In kunpeng920, imissed is supported, only including RPU drop stats in PF. In kunpeng930, imissed is supported,including RPU drop stats and SSU drop stats in PF. Signed-off-by: Min Hu (Connor) --- v4: - rename variable name oq_glb_drop_cnt to oq_drop_cnt. --- drivers/net/hns3/hns3_cmd.h | 13 +++ drivers/net/hns3/hns3_ethdev.c | 2 + drivers/net/hns3/hns3_ethdev.h | 21 ++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 ++ drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_stats.c | 234 +++++++++++++++++++++++++++++--------- drivers/net/hns3/hns3_stats.h | 1 + 7 files changed, 230 insertions(+), 52 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 094bf7e..e704d0c 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -111,6 +111,8 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_DEV_SPECS = 0x0050, + HNS3_OPC_SSU_DROP_REG = 0x0065, + /* MAC command */ HNS3_OPC_CONFIG_MAC_MODE = 0x0301, HNS3_OPC_QUERY_LINK_STATUS = 0x0307, @@ -957,6 +959,17 @@ struct hns3_query_rpu_cmd { uint32_t rsv2[2]; }; +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { + uint8_t rxtx; + uint8_t rsv[3]; + uint32_t full_drop_cnt; + uint32_t part_drop_cnt; + uint32_t oq_drop_cnt; + uint32_t rev1[2]; +}; + #define HNS3_MAX_TQP_NUM_HIP08_PF 64 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 139e893..82538d4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -3122,6 +3122,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = false; @@ -3140,6 +3141,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = true; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 314916c..6e74ec8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -426,6 +426,9 @@ struct hns3_queue_intr { #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -544,6 +547,24 @@ struct hns3_hw { * port won't be copied to the function which has set promisc mode. */ uint8_t promisc_mode; + + /* + * drop_stats_mode mode. + * value range: + * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 + * + * - HNS3_PKTS_DROP_STATS_MODE1 + * This mode for kunpeng920. In this mode, port level imissed stats + * is supported. It only includes RPU drop stats. + * + * - HNS3_PKTS_DROP_STATS_MODE2 + * This mode for kunpeng930. In this mode, imissed stats and oerrors + * stats is supported. Function level imissed stats is supported. It + * includes RPU drop stats in VF, and includes both RPU drop stats + * and SSU drop stats in PF. Oerror stats is also supported in PF. + */ + uint8_t drop_stats_mode; + uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index e1e41b8..7ee468f 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1221,6 +1221,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; @@ -1238,6 +1239,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; @@ -1875,6 +1877,13 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) if (ret) goto err_get_config; + /* Hardware statistics of imissed registers cleared. */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + goto err_set_tc_queue; + } + ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); if (ret) { PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h index 0540554..e141fe1 100644 --- a/drivers/net/hns3/hns3_regs.h +++ b/drivers/net/hns3/hns3_regs.h @@ -36,6 +36,8 @@ #define HNS3_GLOBAL_RESET_REG 0x20A00 #define HNS3_FUN_RST_ING 0x20C00 #define HNS3_GRO_EN_REG 0x28000 + +#define HNS3_RPU_DROP_CNT_REG 0x28004 #define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008 /* Vector0 register bits for reset */ diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 7cda36c..e802c0b 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -269,6 +269,8 @@ static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = { static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { {"RPU_DROP_CNT", HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)}, + {"SSU_DROP_CNT", + HNS3_IMISSED_STATS_FIELD_OFFSET(ssu_rx_drop_cnt)}, }; #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ @@ -301,8 +303,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ - HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_RESET_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -419,7 +420,7 @@ hns3_query_update_mac_stats(struct rte_eth_dev *dev) } static int -hns3_update_rpu_drop_stats(struct hns3_hw *hw) +hns3_update_port_rpu_drop_stats(struct hns3_hw *hw) { struct hns3_rx_missed_stats *stats = &hw->imissed_stats; struct hns3_query_rpu_cmd *req; @@ -449,11 +450,90 @@ hns3_update_rpu_drop_stats(struct hns3_hw *hw) return 0; } +static void +hns3_update_function_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + + stats->rpu_rx_drop_cnt += hns3_read_dev(hw, HNS3_RPU_DROP_CNT_REG); +} + +static int +hns3_update_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret = 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && !hns->is_vf) + ret = hns3_update_port_rpu_drop_stats(hw); + else if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2) + hns3_update_function_rpu_drop_stats(hw); + + return ret; +} + +static int +hns3_get_ssu_drop_stats(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + int bd_num, bool is_rx) +{ + struct hns3_query_ssu_cmd *req; + int ret; + int i; + + for (i = 0; i < bd_num - 1; i++) { + hns3_cmd_setup_basic_desc(&desc[i], + HNS3_OPC_SSU_DROP_REG, true); + desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + } + hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_SSU_DROP_REG, true); + req = (struct hns3_query_ssu_cmd *)desc[0].data; + req->rxtx = is_rx ? 0 : 1; + ret = hns3_cmd_send(hw, desc, bd_num); + + return ret; +} + +static int +hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + true); + if (ret) { + hns3_err(hw, "failed to get Rx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + stats->ssu_rx_drop_cnt += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); int ret; + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) { + ret = hns3_update_port_rx_ssu_drop_stats(hw); + if (ret) + return ret; + } + ret = hns3_update_rpu_drop_stats(hw); if (ret) return ret; @@ -488,19 +568,17 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) uint16_t i; int ret; - if (!hns->is_vf) { - /* Update imissed stats */ - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt; + /* Update imissed stats */ + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt + + imissed_stats->ssu_rx_drop_cnt; - /* Reads all the stats of a rxq in a loop to keep them synchronized */ + /* Get the error stats and bytes of received packets */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) @@ -556,17 +634,14 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) uint16_t i; int ret; - if (!hns->is_vf) { - /* - * Note: Reading hardware statistics of imissed registers will - * clear them. - */ - ret = hns3_update_imissed_stats(hw, true); - if (ret) { - hns3_err(hw, "clear imissed stats failed, ret = %d", - ret); - return ret; - } + /* + * Note: Reading hardware statistics of imissed registers will + * clear them. + */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + return ret; } for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { @@ -630,6 +705,22 @@ hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev) return 0; } +static int +hns3_get_imissed_stats_num(struct hns3_adapter *hns) +{ +#define NO_IMISSED_STATS_NUM 0 +#define RPU_STATS_ITEM_NUM 1 + struct hns3_hw *hw = &hns->hw; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return NO_IMISSED_STATS_NUM; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) + return HNS3_NUM_IMISSED_XSTATS; + + return RPU_STATS_ITEM_NUM; +} + /* This function calculates the number of xstats based on the current config */ static int hns3_xstats_calc_num(struct rte_eth_dev *dev) @@ -647,13 +738,17 @@ hns3_xstats_calc_num(struct rte_eth_dev *dev) uint16_t nb_tx_q = dev->data->nb_tx_queues; int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM; int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM; + int stats_num; + + stats_num = rx_comm_stats_num + tx_comm_stats_num; + stats_num += hns3_get_imissed_stats_num(hns); if (hns->is_vf) - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_NUM_RESET_XSTATS; + stats_num += HNS3_NUM_RESET_XSTATS; else - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_FIX_NUM_STATS; + stats_num += HNS3_FIX_NUM_STATS; + + return stats_num; } static void @@ -835,6 +930,31 @@ hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, hns3_txq_basic_stats_get(dev, xstats, count); } +static void +hns3_imissed_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; + int imissed_stats_num; + int cnt = *count; + char *addr; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + addr = (char *)imissed_stats + + hns3_imissed_stats_strings[i].offset; + xstats[cnt].value = *(uint64_t *)addr; + xstats[cnt].id = cnt; + cnt++; + } + + *count = cnt; +} + /* * Retrieve extended(tqp | Mac) statistics of an Ethernet device. * @param dev @@ -854,7 +974,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, { struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; struct hns3_rx_bd_errors_stats *rx_err_stats; @@ -890,24 +1009,17 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, xstats[count].id = count; count++; } + } - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - addr = (char *)imissed_stats + - hns3_imissed_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } - + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + hns3_imissed_stats_get(dev, xstats, &count); + /* Get the reset stat */ for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset; @@ -992,6 +1104,28 @@ hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev, } } +static void +hns3_imissed_stats_name_get(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + uint32_t *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t cnt = *count; + int imissed_stats_num; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + snprintf(xstats_names[cnt].name, + sizeof(xstats_names[cnt].name), + "%s", hns3_imissed_stats_strings[i].name); + cnt++; + } + + *count = cnt; +} + /* * Retrieve names of extended statistics of an Ethernet device. * @@ -1040,14 +1174,10 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_mac_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_imissed_stats_strings[i].name); - count++; - } } + + hns3_imissed_stats_name_get(dev, xstats_names, &count); + for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 8ea69b4..273be42 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -112,6 +112,7 @@ struct hns3_mac_stats { struct hns3_rx_missed_stats { uint64_t rpu_rx_drop_cnt; + uint64_t ssu_rx_drop_cnt; }; /* store statistics names and its offset in stats structure */ From patchwork Fri Mar 19 01:07:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89518 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8220FA0562; Fri, 19 Mar 2021 02:07:11 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 72C13140FD3; Fri, 19 Mar 2021 02:07:00 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 4A7ED140FBD for ; Fri, 19 Mar 2021 02:06:56 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw3M0wz917N for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:53 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:24 +0800 Message-ID: <1616116046-47578-7-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 6/8] net/hns3: support oerrors stats in PF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch added oerrors stats for PF in kunpeng930. Signed-off-by: Min Hu (Connor) --- v4: - rename variable name oq_glb_drop_cnt to oq_drop_cnt. --- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_stats.c | 64 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 6e74ec8..f69e2d8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -443,6 +443,7 @@ struct hns3_hw { /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; struct hns3_rx_missed_stats imissed_stats; + uint64_t oerror_stats; uint32_t fw_version; uint16_t num_msi; diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index e802c0b..1af689f 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -519,6 +519,31 @@ hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) return 0; } +static int +hns3_update_port_tx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + false); + if (ret) { + hns3_err(hw, "failed to get Tx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + hw->oerror_stats += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { @@ -544,6 +569,25 @@ hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) return 0; } +static int +hns3_update_oerror_stats(struct hns3_hw *hw, bool is_clear) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 || hns->is_vf) + return 0; + + ret = hns3_update_port_tx_ssu_drop_stats(hw); + if (ret) + return ret; + + if (is_clear) + hw->oerror_stats = 0; + + return 0; +} + /* * Query tqp tx queue statistics ,opcode id: 0x0B03. * Query tqp rx queue statistics ,opcode id: 0x0B13. @@ -608,7 +652,14 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) rte_stats->obytes += txq->basic_stats.bytes; } - rte_stats->oerrors = 0; + ret = hns3_update_oerror_stats(hw, false); + if (ret) { + hns3_err(hw, "update oerror stats failed, ret = %d", + ret); + return ret; + } + rte_stats->oerrors = hw->oerror_stats; + /* * If HW statistics are reset by stats_reset, but a lot of residual * packets exist in the hardware queue and these packets are error @@ -644,6 +695,17 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) return ret; } + /* + * Note: Reading hardware statistics of oerror registers will + * clear them. + */ + ret = hns3_update_oerror_stats(hw, true); + if (ret) { + hns3_err(hw, "clear oerror stats failed, ret = %d", + ret); + return ret; + } + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) From patchwork Fri Mar 19 01:07:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89517 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B90CAA0562; Fri, 19 Mar 2021 02:07:04 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 37F2D140FCB; Fri, 19 Mar 2021 02:06:59 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 4817940143 for ; Fri, 19 Mar 2021 02:06:56 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw1qbpz90lW for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:53 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:25 +0800 Message-ID: <1616116046-47578-8-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 7/8] net/hns3: support query Tx descriptor status X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng Add support for query Tx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng Signed-off-by: Min Hu (Connor) --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 28 ++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 34 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 3aeea8e..2c0cb89 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index c796cd5..e60b09b 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -32,6 +32,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index c3324d8..e8b0c6e 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -62,6 +62,7 @@ New Features * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. + * Added support for query Tx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 82538d4..8c65be4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6774,6 +6774,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; return ret; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 7ee468f..4412da3 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2917,6 +2917,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 7529279..a84da15 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4044,6 +4044,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; + eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; } else { eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst; @@ -4256,6 +4257,33 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) return -ENOTSUP; } +int +hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + volatile struct hns3_desc *txdp; + struct hns3_tx_queue *txq; + struct rte_eth_dev *dev; + uint16_t desc_id; + + txq = (struct hns3_tx_queue *)tx_queue; + if (offset >= txq->nb_tx_desc) + return -EINVAL; + + dev = &rte_eth_devices[txq->port_id]; + if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && + dev->tx_pkt_burst != hns3_xmit_pkts && + dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && + dev->tx_pkt_burst != hns3_xmit_pkts_vec) + return RTE_ETH_TX_DESC_UNAVAIL; + + desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; + txdp = &txq->tx_ring[desc_id]; + if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) + return RTE_ETH_TX_DESC_FULL; + else + return RTE_ETH_TX_DESC_DONE; +} + uint32_t hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) { diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index cd04200..82d5aa0 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,5 +720,6 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */ From patchwork Fri Mar 19 01:07:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 89519 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BB84A0562; Fri, 19 Mar 2021 02:07:18 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BEFC7140FDB; Fri, 19 Mar 2021 02:07:01 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id 4CBA7140FC6 for ; Fri, 19 Mar 2021 02:06:56 +0100 (CET) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4F1lzw2Dvrz9170 for ; Fri, 19 Mar 2021 09:05:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Fri, 19 Mar 2021 09:06:53 +0800 From: "Min Hu (Connor)" To: CC: Date: Fri, 19 Mar 2021 09:07:26 +0800 Message-ID: <1616116046-47578-9-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616116046-47578-1-git-send-email-humin29@huawei.com> References: <1615357493-42394-1-git-send-email-humin29@huawei.com> <1616116046-47578-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v5 8/8] net/hns3: support query Rx descriptor status X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng Add support for query Rx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng Signed-off-by: Min Hu (Connor) --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 36 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 42 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 2c0cb89..3988be4 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y Tx descriptor status = Y Basic stats = Y Extended stats = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index e60b09b..1640669 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -33,6 +33,7 @@ Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y Tx descriptor status = Y +Rx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index e8b0c6e..6e1fc81 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -63,6 +63,7 @@ New Features * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. * Added support for query Tx descriptor status. + * Added support for query Rx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 8c65be4..b7bfac8 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6772,6 +6772,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 4412da3..34a6927 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2915,6 +2915,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index a84da15..feeb702 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4042,6 +4042,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) if (hns->hw.adapter_state == HNS3_NIC_STARTED && __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) { eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); + eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; @@ -4258,6 +4259,41 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) } int +hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + volatile struct hns3_desc *rxdp; + struct hns3_rx_queue *rxq; + struct rte_eth_dev *dev; + uint32_t bd_base_info; + uint16_t desc_id; + + rxq = (struct hns3_rx_queue *)rx_queue; + if (offset >= rxq->nb_rx_desc) + return -EINVAL; + + desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; + rxdp = &rxq->rx_ring[desc_id]; + bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); + dev = &rte_eth_devices[rxq->port_id]; + if (dev->rx_pkt_burst == hns3_recv_pkts || + dev->rx_pkt_burst == hns3_recv_scattered_pkts) { + if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || + dev->rx_pkt_burst == hns3_recv_pkts_vec_sve){ + if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) + return RTE_ETH_RX_DESC_UNAVAIL; + } else { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) + return RTE_ETH_RX_DESC_AVAIL; + else + return RTE_ETH_RX_DESC_DONE; +} + +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) { volatile struct hns3_desc *txdp; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 82d5aa0..f9b3048 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,6 +720,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */