From patchwork Wed Mar 17 08:04:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 89347 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 302A2A00C2; Wed, 17 Mar 2021 09:05:19 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 13310242B4A; Wed, 17 Mar 2021 09:05:19 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2EC8F4014D for ; Wed, 17 Mar 2021 09:05:18 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12H80Rhu017561; Wed, 17 Mar 2021 01:05:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=F+854lag1mrQR+M/igLzCZ8y2sZLHqUTgmZoOtX0NLg=; b=Mo3SRZAmJZUBCuGL57SeixGDuMWIihS7WyEgo1LqRJu9YNVkWAHAA5a2OTsJXGR5gX7B OSKTETnZPQmpGQc9l5IUTg7Ruxx0DM44EhhjlKEdXSUraQBkd71Vu7/pL+HvPsRMEOWp 7jFApExH/gu2Nm+dSwvJX9hjncNZF+NOtxsiCsxz+QvkWpqJYX9lYkCQl2bZ6OGysDDk DGJgEfhPnndXz0+wAEPggt5eF66tqIeV3D85mIGdP9avV97YkH7C2r0I00RBTnWLOpib cSBL373bMVQtCoC7IKbcpMLODMQ1FlhH6t85tpHfpne4hOa+sWCPApuhENEDzJbJ2L8A Xw== Received: from dc6wp-exch01.marvell.com ([4.21.29.232]) by mx0a-0016f401.pphosted.com with ESMTP id 37b5vdhbjg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Mar 2021 01:05:17 -0700 Received: from DC6WP-EXCH01.marvell.com (10.76.176.21) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Mar 2021 04:05:15 -0400 Received: from maili.marvell.com (10.76.176.51) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Mar 2021 04:05:15 -0400 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 94BAA3F703F; Wed, 17 Mar 2021 01:05:12 -0700 (PDT) From: Shijith Thotton To: Erik Gabriel Carrillo CC: Shijith Thotton , Pavan Nikhilesh , Jerin Jacob , Date: Wed, 17 Mar 2021 13:34:19 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-17_02:2021-03-17, 2021-03-17 signatures=0 Subject: [dpdk-dev] [PATCH v3 1/3] eventdev: introduce adapter flags for periodic mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A timer adapter in periodic mode can be used to arm periodic timers. This patch adds flags used to advertise capability and configure timer adapter in periodic mode. Capability flag should be set for adapters which support periodic mode. Below is a programming sequence on the usage: /* check for periodic mode support by reading capability. */ rte_event_timer_adapter_caps_get(...); /* create adapter in periodic mode by setting periodic flag (RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) and resolution. */ rte_event_timer_adapter_create_ext(...); /* arm periodic timer of configured resolution */ rte_event_timer_arm_burst(...); /* timer event will be periodically generated at configured resolution till cancel is called. */ while (running) { rte_event_dequeue_burst(...); } /* cancel periodic timer which stops generating events */ rte_event_timer_cancel_burst(...); Signed-off-by: Shijith Thotton Acked-by: Erik Gabriel Carrillo --- doc/guides/prog_guide/event_timer_adapter.rst | 16 +++++++++++++++- lib/librte_eventdev/rte_event_timer_adapter.h | 13 +++++++++++++ lib/librte_eventdev/rte_eventdev.h | 3 +++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/doc/guides/prog_guide/event_timer_adapter.rst b/doc/guides/prog_guide/event_timer_adapter.rst index a95efbe0d..8b18cd169 100644 --- a/doc/guides/prog_guide/event_timer_adapter.rst +++ b/doc/guides/prog_guide/event_timer_adapter.rst @@ -138,6 +138,18 @@ This function is passed a callback function that will be invoked if the adapter needs to create an event port, giving the application the opportunity to control how it is done. +Adapter modes +^^^^^^^^^^^^^ +An event timer adapter can be configured in either periodic or non-periodic mode +to support timers of the respective type. A periodic timer expires at a fixed +time interval repeatedly till it is cancelled. A non-periodic timer expires only +once. The periodic capability flag, ``RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC``, +can be set for implementations that support periodic mode if desired. To +configure an adapter in periodic mode, ``timer_adapter_flags`` of +``rte_event_timer_adapter_conf`` is set to include the periodic flag +``RTE_EVENT_TIMER_ADAPTER_F_PERIODIC``. Maximum timeout (``max_tmo_nsec``) does +not apply to periodic mode. + Retrieve Event Timer Adapter Contextual Information ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The event timer adapter implementation may have constraints on tick resolution @@ -229,7 +241,9 @@ Now we can arm the event timer with ``rte_event_timer_arm_burst()``: Once an event timer expires, the application may free it or rearm it as necessary. If the application will rearm the timer, the state should be reset -to RTE_EVENT_TIMER_NOT_ARMED by the application before rearming it. +to RTE_EVENT_TIMER_NOT_ARMED by the application before rearming it. Timer expiry +events will be generated once or periodically until the timer is cancelled based +on adapter mode. Multiple Event Timers with Same Expiry Value ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/lib/librte_eventdev/rte_event_timer_adapter.h b/lib/librte_eventdev/rte_event_timer_adapter.h index d2ebcb090..4e0d2a819 100644 --- a/lib/librte_eventdev/rte_event_timer_adapter.h +++ b/lib/librte_eventdev/rte_event_timer_adapter.h @@ -151,6 +151,14 @@ enum rte_event_timer_adapter_clk_src { * @see struct rte_event_timer_adapter_conf::flags */ +#define RTE_EVENT_TIMER_ADAPTER_F_PERIODIC (1ULL << 2) +/**< Flag to configure an event timer adapter in periodic mode; non-periodic + * mode is the default. A timer will fire once or periodically until the timer + * is cancelled based on the adapter mode. + * + * @see struct rte_event_timer_adapter_conf::flags + */ + /** * Timer adapter configuration structure */ @@ -551,6 +559,8 @@ struct rte_event_timer_adapter { * expiry event attributes, timeout ticks from now. * This function submits the event timer arm requests to the event timer adapter * and on expiry, the events will be injected to designated event queue. + * Timer expiry events will be generated once or periodically until cancellation + * based on the adapter mode. * * @param adapter * A pointer to an event timer adapter structure. @@ -570,6 +580,9 @@ struct rte_event_timer_adapter { * destination event queue. * - EAGAIN Specified timer adapter is not running * - EALREADY A timer was encountered that was already armed + * + * @see RTE_EVENT_TIMER_ADAPTER_F_PERIODIC + * */ static inline uint16_t rte_event_timer_arm_burst(const struct rte_event_timer_adapter *adapter, diff --git a/lib/librte_eventdev/rte_eventdev.h b/lib/librte_eventdev/rte_eventdev.h index ce1fc2ce0..9fc39e9ca 100644 --- a/lib/librte_eventdev/rte_eventdev.h +++ b/lib/librte_eventdev/rte_eventdev.h @@ -1154,6 +1154,9 @@ rte_event_eth_rx_adapter_caps_get(uint8_t dev_id, uint16_t eth_port_id, #define RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT (1ULL << 0) /**< This flag is set when the timer mechanism is in HW. */ +#define RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC (1ULL << 1) +/**< This flag is set if periodic mode is supported. */ + /** * Retrieve the event device's timer adapter capabilities. * From patchwork Wed Mar 17 08:04:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 89348 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C885A00C2; Wed, 17 Mar 2021 09:05:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5AE32242B55; Wed, 17 Mar 2021 09:05:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4B76D4014D for ; Wed, 17 Mar 2021 09:05:45 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12H80a5g017780; Wed, 17 Mar 2021 01:05:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=hgVcnlo3VkKA6sO7p9lpImpCS3k36Xs8l7FgewBQ59c=; b=hRwW7/J7+V1MBjgaGGbgYU8oLud7fJimMqfokcVlGyytQPUMGaH9fJpexcfhXwC1oqxo OyMPBMCXR2so6CqxwmvDo8nbyePfHd0YAt7AenUvbul+JvfJqotMtcUelfUwbICe0cZZ npFbNqVpQKRyA7CbOnio+NoXvEZd6QT7mquWkESVij3ZoQdbVDZLVi5HUR0nACSOUUmy DREcxPGrp/tBK9bvFvNHnRNNs6aUD/Pq3J5JQD1THPDCuIySJQok8TwrfNpdTc2DYGJc YjnvR7oWRmv1TopBSqn/NCssiPq+BVOHwvHLYm0WPtnyc0ZkL2iCVFI1Cq1ETrzkZNLd JQ== Received: from dc6wp-exch01.marvell.com ([4.21.29.232]) by mx0a-0016f401.pphosted.com with ESMTP id 37b5vdhbkh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Mar 2021 01:05:44 -0700 Received: from DC6WP-EXCH01.marvell.com (10.76.176.21) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Mar 2021 04:05:42 -0400 Received: from maili.marvell.com (10.76.176.51) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Mar 2021 04:05:42 -0400 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id 625D73F703F; Wed, 17 Mar 2021 01:05:40 -0700 (PDT) From: Shijith Thotton To: Erik Gabriel Carrillo CC: Shijith Thotton , Pavan Nikhilesh , Jerin Jacob , Date: Wed, 17 Mar 2021 13:34:20 +0530 Message-ID: <8be24528babf59590d137de77ccdc2ef86e19d39.1615967694.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-17_02:2021-03-17, 2021-03-17 signatures=0 Subject: [dpdk-dev] [PATCH v3 2/3] test/event: add unit tests for periodic timer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add tests to arm and cancel periodic timer. Signed-off-by: Shijith Thotton Acked-by: Erik Gabriel Carrillo --- app/test/test_event_timer_adapter.c | 138 +++++++++++++++++++++++++--- 1 file changed, 125 insertions(+), 13 deletions(-) diff --git a/app/test/test_event_timer_adapter.c b/app/test/test_event_timer_adapter.c index b536ddef4..c36ab32ac 100644 --- a/app/test/test_event_timer_adapter.c +++ b/app/test/test_event_timer_adapter.c @@ -283,7 +283,7 @@ test_port_conf_cb(uint16_t id, uint8_t event_dev_id, uint8_t *event_port_id, } static int -_timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) +_timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns, uint64_t flags) { struct rte_event_timer_adapter_info info; struct rte_event_timer_adapter_conf config = { @@ -292,7 +292,7 @@ _timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) .timer_tick_ns = bkt_tck_ns, .max_tmo_ns = max_tmo_ns, .nb_timers = MAX_TIMERS * 10, - .flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES, + .flags = flags, }; uint32_t caps = 0; const char *pool_name = "timdev_test_pool"; @@ -301,6 +301,13 @@ _timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) TEST_ASSERT_SUCCESS(rte_event_timer_adapter_caps_get(evdev, &caps), "failed to get adapter capabilities"); + + if (flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC && + !(caps & RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC)) { + printf("Adapter does not support periodic timers\n"); + return TEST_SKIPPED; + } + if (!(caps & RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT)) { timdev = rte_event_timer_adapter_create_ext(&config, test_port_conf_cb, @@ -338,42 +345,72 @@ _timdev_setup(uint64_t max_tmo_ns, uint64_t bkt_tck_ns) static int timdev_setup_usec(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + return using_services ? /* Max timeout is 10,000us and bucket interval is 100us */ - _timdev_setup(1E7, 1E5) : + _timdev_setup(1E7, 1E5, flags) : /* Max timeout is 100us and bucket interval is 1us */ - _timdev_setup(1E5, 1E3); + _timdev_setup(1E5, 1E3, flags); } static int timdev_setup_usec_multicore(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + return using_services ? /* Max timeout is 10,000us and bucket interval is 100us */ - _timdev_setup(1E7, 1E5) : + _timdev_setup(1E7, 1E5, flags) : /* Max timeout is 100us and bucket interval is 1us */ - _timdev_setup(1E5, 1E3); + _timdev_setup(1E5, 1E3, flags); } static int timdev_setup_msec(void) { - /* Max timeout is 2 mins, and bucket interval is 100 ms */ - return _timdev_setup(180 * NSECPERSEC, NSECPERSEC / 10); + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + + /* Max timeout is 3 mins, and bucket interval is 100 ms */ + return _timdev_setup(180 * NSECPERSEC, NSECPERSEC / 10, flags); +} + +static int +timdev_setup_msec_periodic(void) +{ + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES | + RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; + + /* Periodic mode with 100 ms resolution */ + return _timdev_setup(0, NSECPERSEC / 10, flags); } static int timdev_setup_sec(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + /* Max timeout is 100sec and bucket interval is 1sec */ - return _timdev_setup(1E11, 1E9); + return _timdev_setup(1E11, 1E9, flags); +} + +static int +timdev_setup_sec_periodic(void) +{ + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES | + RTE_EVENT_TIMER_ADAPTER_F_PERIODIC; + + /* Periodic mode with 1 sec resolution */ + return _timdev_setup(0, NSECPERSEC, flags); } static int timdev_setup_sec_multicore(void) { + uint64_t flags = RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES; + /* Max timeout is 100sec and bucket interval is 1sec */ - return _timdev_setup(1E11, 1E9); + return _timdev_setup(1E11, 1E9, flags); } static void @@ -513,6 +550,19 @@ test_timer_arm(void) return TEST_SUCCESS; } +static inline int +test_timer_arm_periodic(void) +{ + TEST_ASSERT_SUCCESS(_arm_timers(1, MAX_TIMERS), + "Failed to arm timers"); + /* With a resolution of 100ms and wait time of 1sec, + * there will be 10 * MAX_TIMERS periodic timer triggers. + */ + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + "Timer triggered count doesn't match arm count"); + return TEST_SUCCESS; +} + static int _arm_wrapper(void *arg) { @@ -588,6 +638,20 @@ test_timer_arm_burst(void) return TEST_SUCCESS; } +static inline int +test_timer_arm_burst_periodic(void) +{ + TEST_ASSERT_SUCCESS(_arm_timers_burst(1, MAX_TIMERS), + "Failed to arm timers"); + /* With a resolution of 100ms and wait time of 1sec, + * there will be 10 * MAX_TIMERS periodic timer triggers. + */ + TEST_ASSERT_SUCCESS(_wait_timer_triggers(1, 10 * MAX_TIMERS, 0), + "Timer triggered count doesn't match arm count"); + + return TEST_SUCCESS; +} + static int _arm_wrapper_burst(void *arg) { @@ -612,6 +676,48 @@ test_timer_arm_burst_multicore(void) return TEST_SUCCESS; } +static inline int +test_timer_cancel_periodic(void) +{ + uint64_t i; + struct rte_event_timer *ev_tim; + const struct rte_event_timer tim = { + .ev.op = RTE_EVENT_OP_NEW, + .ev.queue_id = 0, + .ev.sched_type = RTE_SCHED_TYPE_ATOMIC, + .ev.priority = RTE_EVENT_DEV_PRIORITY_NORMAL, + .ev.event_type = RTE_EVENT_TYPE_TIMER, + .state = RTE_EVENT_TIMER_NOT_ARMED, + .timeout_ticks = CALC_TICKS(1), + }; + + for (i = 0; i < MAX_TIMERS; i++) { + TEST_ASSERT_SUCCESS(rte_mempool_get(eventdev_test_mempool, + (void **)&ev_tim), + "mempool alloc failed"); + *ev_tim = tim; + ev_tim->ev.event_ptr = ev_tim; + + TEST_ASSERT_EQUAL(rte_event_timer_arm_burst(timdev, &ev_tim, + 1), 1, "Failed to arm timer %d", + rte_errno); + + rte_delay_us(100 + (i % 5000)); + + TEST_ASSERT_EQUAL(rte_event_timer_cancel_burst(timdev, + &ev_tim, 1), 1, + "Failed to cancel event timer %d", rte_errno); + rte_mempool_put(eventdev_test_mempool, ev_tim); + } + + + TEST_ASSERT_SUCCESS(_wait_timer_triggers(30, MAX_TIMERS, + MAX_TIMERS), + "Timer triggered count doesn't match arm, cancel count"); + + return TEST_SUCCESS; +} + static inline int test_timer_cancel(void) { @@ -1028,9 +1134,9 @@ adapter_lookup(void) static int adapter_start(void) { - TEST_ASSERT_SUCCESS(_timdev_setup(180 * NSECPERSEC, - NSECPERSEC / 10), - "Failed to start adapter"); + TEST_ASSERT_SUCCESS(_timdev_setup(180 * NSECPERSEC, NSECPERSEC / 10, + RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES), + "Failed to start adapter"); TEST_ASSERT_EQUAL(rte_event_timer_adapter_start(timdev), -EALREADY, "Timer adapter started without call to stop."); @@ -1786,10 +1892,16 @@ static struct unit_test_suite event_timer_adptr_functional_testsuite = { test_timer_state), TEST_CASE_ST(timdev_setup_usec, timdev_teardown, test_timer_arm), + TEST_CASE_ST(timdev_setup_msec_periodic, timdev_teardown, + test_timer_arm_periodic), TEST_CASE_ST(timdev_setup_usec, timdev_teardown, test_timer_arm_burst), + TEST_CASE_ST(timdev_setup_msec_periodic, timdev_teardown, + test_timer_arm_burst_periodic), TEST_CASE_ST(timdev_setup_sec, timdev_teardown, test_timer_cancel), + TEST_CASE_ST(timdev_setup_sec_periodic, timdev_teardown, + test_timer_cancel_periodic), TEST_CASE_ST(timdev_setup_sec, timdev_teardown, test_timer_cancel_random), TEST_CASE_ST(timdev_setup_usec_multicore, timdev_teardown, From patchwork Wed Mar 17 08:04:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 89349 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DB146A00C2; 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Wed, 17 Mar 2021 01:06:15 -0700 Received: from DC6WP-EXCH01.marvell.com (10.76.176.21) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Mar 2021 04:06:13 -0400 Received: from maili.marvell.com (10.76.176.51) by DC6WP-EXCH01.marvell.com (10.76.176.21) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Mar 2021 04:06:13 -0400 Received: from localhost.localdomain (unknown [10.28.34.29]) by maili.marvell.com (Postfix) with ESMTP id DAA473F7040; Wed, 17 Mar 2021 01:06:10 -0700 (PDT) From: Shijith Thotton To: Erik Gabriel Carrillo CC: Shijith Thotton , Pavan Nikhilesh , Jerin Jacob , Date: Wed, 17 Mar 2021 13:34:21 +0530 Message-ID: <51c875237a4f639dd566eca8cfc181aecc06b513.1615967694.git.sthotton@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-17_02:2021-03-17, 2021-03-17 signatures=0 Subject: [dpdk-dev] [PATCH v3 3/3] event/octeontx2: add timer periodic mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for periodic mode in event timer adapter. Signed-off-by: Shijith Thotton Acked-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 29 ++++++++++++++++++++---- drivers/event/octeontx2/otx2_tim_evdev.h | 1 + 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 4c24cc8a6..39a29f17f 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -65,7 +65,8 @@ otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr, struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv; adptr_info->max_tmo_ns = tim_ring->max_tout; - adptr_info->min_resolution_ns = tim_ring->tck_nsec; + adptr_info->min_resolution_ns = tim_ring->ena_periodic ? + tim_ring->max_tout : tim_ring->tck_nsec; rte_memcpy(&adptr_info->conf, &adptr->data->conf, sizeof(struct rte_event_timer_adapter_conf)); } @@ -163,7 +164,7 @@ tim_chnk_pool_create(struct otx2_tim_ring *tim_ring, } tim_ring->aura = npa_lf_aura_handle_to_aura( tim_ring->chunk_pool->pool_id); - tim_ring->ena_dfb = 0; + tim_ring->ena_dfb = tim_ring->ena_periodic ? 1 : 0; } else { tim_ring->chunk_pool = rte_mempool_create(pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, @@ -254,6 +255,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) struct tim_ring_req *free_req; struct tim_lf_alloc_req *req; struct tim_lf_alloc_rsp *rsp; + uint8_t is_periodic; int i, rc; if (dev == NULL) @@ -284,6 +286,20 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) } } + is_periodic = 0; + if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) { + if (rcfg->max_tmo_ns && + rcfg->max_tmo_ns != rcfg->timer_tick_ns) { + rc = -ERANGE; + goto rng_mem_err; + } + + /* Use 2 buckets to avoid contention */ + rcfg->max_tmo_ns = rcfg->timer_tick_ns; + rcfg->timer_tick_ns /= 2; + is_periodic = 1; + } + tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0); if (tim_ring == NULL) { rc = -ENOMEM; @@ -296,11 +312,13 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->clk_src = (int)rcfg->clk_src; tim_ring->ring_id = adptr->data->id; tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10); - tim_ring->max_tout = rcfg->max_tmo_ns; + tim_ring->max_tout = is_periodic ? + rcfg->timer_tick_ns * 2 : rcfg->max_tmo_ns; tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); tim_ring->chunk_sz = dev->chunk_sz; tim_ring->nb_timers = rcfg->nb_timers; tim_ring->disable_npa = dev->disable_npa; + tim_ring->ena_periodic = is_periodic; tim_ring->enable_stats = dev->enable_stats; for (i = 0; i < dev->ring_ctl_cnt ; i++) { @@ -348,7 +366,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) cfg_req->ring = tim_ring->ring_id; cfg_req->bigendian = false; cfg_req->clocksource = tim_ring->clk_src; - cfg_req->enableperiodic = false; + cfg_req->enableperiodic = tim_ring->ena_periodic; cfg_req->enabledontfreebuffer = tim_ring->ena_dfb; cfg_req->bucketsize = tim_ring->nb_bkts; cfg_req->chunksize = tim_ring->chunk_sz; @@ -568,7 +586,8 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; - *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT | + RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC; *ops = &otx2_tim_ops; return 0; diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index 44e3c7b51..82d116c09 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -155,6 +155,7 @@ struct otx2_tim_ring { uint8_t disable_npa; uint8_t optimized; uint8_t ena_dfb; + uint8_t ena_periodic; uint16_t ring_id; uint32_t aura; uint64_t nb_timers;