From patchwork Thu Feb 4 06:07:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 87715 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62C91A0A0E; Thu, 4 Feb 2021 07:15:27 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D3F5D240560; Thu, 4 Feb 2021 07:15:26 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 78CD4240558 for ; Thu, 4 Feb 2021 07:15:24 +0100 (CET) IronPort-SDR: w+vAdgfovjY5OyiJrMBgKZzA9IJUxrRRv2RSv40pO8Ox68nM/425nTYpxaAw/gXzKom8wARFsk 0K0L+zaNwfYw== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="181322378" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="181322378" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 22:15:23 -0800 IronPort-SDR: fYNg6iM1D1sFf7Q4D1+4Ea79DaQZVz7RzMmHQzZEdji6hrai/N5jFrDbZUSTx3noU/HT9FnPQM sOfOyfP/clow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="508027821" Received: from dpdk-yyzhang2.sh.intel.com ([10.67.117.129]) by orsmga004.jf.intel.com with ESMTP; 03 Feb 2021 22:15:21 -0800 From: Yuying Zhang To: dev@dpdk.org, qi.z.zhang@intel.com, haiyue.wang@intel.com Cc: qi.fu@intel.com, Yuying Zhang Date: Thu, 4 Feb 2021 06:07:51 +0000 Message-Id: <20210204060751.515216-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v1] net/ice: fix QinQ switch rule input set mask X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" QinQ switch rule doesn't support ethertype field match. QinQ ethertype pattern should not be created. Change the input set mask to fix the issue. Fixes: bb3386f348dd ("net/ice: enable QinQ filter for switch") Signed-off-by: Yuying Zhang Acked-by: Qi Zhang --- drivers/net/ice/ice_switch_filter.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index 5ca0985e21..6525e6c115 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -38,7 +38,8 @@ ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \ ICE_INSET_VLAN_INNER) #define ICE_SW_INSET_MAC_QINQ ( \ - ICE_SW_INSET_MAC_VLAN | ICE_INSET_VLAN_OUTER) + ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_VLAN_INNER | \ + ICE_INSET_VLAN_OUTER) #define ICE_SW_INSET_MAC_IPV4 ( \ ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)