From patchwork Sun Jan 24 11:02:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suanming Mou X-Patchwork-Id: 87156 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2B44EA052A; Sun, 24 Jan 2021 12:02:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6BFAB140DAA; Sun, 24 Jan 2021 12:02:21 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 9F198140D6D for ; Sun, 24 Jan 2021 12:02:16 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from suanmingm@nvidia.com) with SMTP; 24 Jan 2021 13:02:13 +0200 Received: from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10OB2AJ6003937; Sun, 24 Jan 2021 13:02:12 +0200 From: Suanming Mou To: viacheslavo@nvidia.com, matan@nvidia.com Cc: rasland@nvidia.com, dev@dpdk.org Date: Sun, 24 Jan 2021 19:02:03 +0800 Message-Id: <1611486126-84749-2-git-send-email-suanmingm@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> References: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> Subject: [dpdk-dev] [PATCH 1/4] net/mlx5: fix invalid multi-process ID X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The device port_id is used for inter-process communication and must be the same both for primary and secondary process This IPC port_id was configured with the invalid temporary value in port spawn routine. This temporary value was used by the function rte_eth_dev_get_port_by_name() to check whether the port exists. This commit corrects the mp port_id with rte_eth_dev port_id. Fixes: 2eb4d0107acc ("net/mlx5: refactor PCI probing on Linux") Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 9ac1d46..1d91b92 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -930,8 +930,6 @@ priv->dev_port = spawn->phys_port; priv->pci_dev = spawn->pci_dev; priv->mtu = RTE_ETHER_MTU; - priv->mp_id.port_id = port_id; - strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); /* Some internal functions rely on Netlink sockets, open them now. */ priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); @@ -1347,6 +1345,8 @@ eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; eth_dev->data->representor_id = priv->representor_id; } + priv->mp_id.port_id = eth_dev->data->port_id; + strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); /* * Store associated network device interface index. This index * is permanent throughout the lifetime of device. So, we may store From patchwork Sun Jan 24 11:02:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suanming Mou X-Patchwork-Id: 87154 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC6F5A052A; Sun, 24 Jan 2021 12:02:19 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EAC97140D8E; Sun, 24 Jan 2021 12:02:18 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id A39EA140D73 for ; Sun, 24 Jan 2021 12:02:16 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from suanmingm@nvidia.com) with SMTP; 24 Jan 2021 13:02:15 +0200 Received: from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10OB2AJ7003937; Sun, 24 Jan 2021 13:02:14 +0200 From: Suanming Mou To: viacheslavo@nvidia.com, matan@nvidia.com Cc: rasland@nvidia.com, dev@dpdk.org, stable@dpdk.org Date: Sun, 24 Jan 2021 19:02:04 +0800 Message-Id: <1611486126-84749-3-git-send-email-suanmingm@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> References: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> Subject: [dpdk-dev] [PATCH 2/4] net/mlx5: fix secondary process port detach crash X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When secondary process starts, in rte_eth_dev_attach_secondary() function, the secondary process port device data in struct rte_eth_dev will be initialized to be shared with primary process port. When failsafe sub-port hot-plug happens, both primary and secondary process will release the sub-port, and primary process will clear the sub-port device data in fs_dev_remove() deactivate stage first before request secondary process to release the sub-port. In this case, the secondary process will not be able to get the priv memory pointer from the shared device data memory anymore, since the device data memory has been cleared. Since what secondary process needs in port detach is the UAR table size to unmap the UAR addresses. It used Tx queue number as size of UAR table in priv. In fact the uar_table_sz in struct mlx5_proc_priv means the size of UAR register table - the number of UAR records. However, the code set this field incorrectly to the size of mlx5_proc_priv structure. This commit fixes UAR table size to match with relevant Tx queue number, uses the UAR table size directly to avoid the secondary process to access the priv pointer in the shared device data memory when unmapping the UAR address. Fixes: 120dc4a7dcd3 ("net/mlx5: remove device register remap") cc: stable@dpdk.org Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.c | 6 +++--- drivers/net/mlx5/mlx5_txq.c | 21 +++++++++++++-------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 3730f32..efedbb9 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1251,13 +1251,13 @@ struct mlx5_dev_ctx_shared * */ ppriv_size = sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); - ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE, - dev->device->numa_node); + ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size, + RTE_CACHE_LINE_SIZE, dev->device->numa_node); if (!ppriv) { rte_errno = ENOMEM; return -rte_errno; } - ppriv->uar_table_sz = ppriv_size; + ppriv->uar_table_sz = priv->txqs_n; dev->process_private = ppriv; return 0; } diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index b81bb4a..c53af10 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -634,18 +634,23 @@ void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev) { - struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_txq_data *txq; - struct mlx5_txq_ctrl *txq_ctrl; + struct mlx5_proc_priv *ppriv = (struct mlx5_proc_priv *) + dev->process_private; + const size_t page_size = rte_mem_page_size(); + void *addr; unsigned int i; + if (page_size == (size_t)-1) { + DRV_LOG(ERR, "Failed to get mem page size"); + return; + } MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY); - for (i = 0; i != priv->txqs_n; ++i) { - if (!(*priv->txqs)[i]) + for (i = 0; i != ppriv->uar_table_sz; ++i) { + if (!ppriv->uar_table[i]) continue; - txq = (*priv->txqs)[i]; - txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); - txq_uar_uninit_secondary(txq_ctrl); + addr = ppriv->uar_table[i]; + rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size); + } } From patchwork Sun Jan 24 11:02:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suanming Mou X-Patchwork-Id: 87157 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DBD91A052A; Sun, 24 Jan 2021 12:02:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A446A140DA5; Sun, 24 Jan 2021 12:02:22 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 3DF83140DA1 for ; Sun, 24 Jan 2021 12:02:21 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from suanmingm@nvidia.com) with SMTP; 24 Jan 2021 13:02:16 +0200 Received: from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10OB2AJ8003937; Sun, 24 Jan 2021 13:02:15 +0200 From: Suanming Mou To: viacheslavo@nvidia.com, matan@nvidia.com Cc: rasland@nvidia.com, dev@dpdk.org, stable@dpdk.org Date: Sun, 24 Jan 2021 19:02:05 +0800 Message-Id: <1611486126-84749-4-git-send-email-suanmingm@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> References: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> Subject: [dpdk-dev] [PATCH 3/4] net/mlx5: fix secondary process attach port Tx queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the secondary process port UAR register mapping used by Tx queue is done during port initializing. Unluckily, in port hot-plug case, the secondary process was requested to initialize the port when primary process did not complete the device configuration and the port Tx queue number is not configured yet. Hence, the secondary process getS the zero Tx queue number during probing, causing the UAR registers not be mapped in the correct fashion. This commit checks the configured number of Tx queues in secondary process when the port start is requested. In case the Tx queue number mismatch found the UAR mapping is reinitialized accordingly. Fixes: 2aac5b5d119f ("net/mlx5: sync stop/start with secondary process") cc: stable@dpdk.org Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_mp_os.c | 19 +++++++++++++++++++ drivers/net/mlx5/mlx5.c | 2 +- drivers/net/mlx5/mlx5.h | 6 +++++- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_mp_os.c b/drivers/net/mlx5/linux/mlx5_mp_os.c index 08ade75..95372e2 100644 --- a/drivers/net/mlx5/linux/mlx5_mp_os.c +++ b/drivers/net/mlx5/linux/mlx5_mp_os.c @@ -115,6 +115,7 @@ const struct mlx5_mp_param *param = (const struct mlx5_mp_param *)mp_msg->param; struct rte_eth_dev *dev; + struct mlx5_proc_priv *ppriv; struct mlx5_priv *priv; int ret; @@ -132,6 +133,20 @@ rte_mb(); dev->rx_pkt_burst = mlx5_select_rx_function(dev); dev->tx_pkt_burst = mlx5_select_tx_function(dev); + ppriv = (struct mlx5_proc_priv *)dev->process_private; + /* If Tx queue number changes, re-initialize UAR. */ + if (ppriv->uar_table_sz != priv->txqs_n) { + mlx5_tx_uar_uninit_secondary(dev); + mlx5_proc_priv_uninit(dev); + ret = mlx5_proc_priv_init(dev); + if (ret) + return -rte_errno; + ret = mlx5_tx_uar_init_secondary(dev, mp_msg->fds[0]); + if (ret) { + mlx5_proc_priv_uninit(dev); + return -rte_errno; + } + } mp_init_msg(&priv->mp_id, &mp_res, param->type); res->result = 0; ret = rte_mp_reply(&mp_res, peer); @@ -183,6 +198,10 @@ return; } mp_init_msg(&priv->mp_id, &mp_req, type); + if (type == MLX5_MP_REQ_START_RXTX) { + mp_req.num_fds = 1; + mp_req.fds[0] = ((struct ibv_context *)priv->sh->ctx)->cmd_fd; + } ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts); if (ret) { if (rte_errno != ENOTSUP) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index efedbb9..b82e767 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1268,7 +1268,7 @@ struct mlx5_dev_ctx_shared * * @param dev * Pointer to Ethernet device structure. */ -static void +void mlx5_proc_priv_uninit(struct rte_eth_dev *dev) { if (!dev->process_private) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 101e9c2..899241e 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -743,7 +743,10 @@ struct mlx5_dev_ctx_shared { struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; -/* Per-process private structure. */ +/* + * Per-process private structure. + * Caution, secondary pocess may rebuid the struct during port start. + */ struct mlx5_proc_priv { size_t uar_table_sz; /* Size of UAR register table. */ @@ -998,6 +1001,7 @@ struct rte_hairpin_peer_info { int mlx5_getenv_int(const char *); int mlx5_proc_priv_init(struct rte_eth_dev *dev); +void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, struct rte_eth_udp_tunnel *udp_tunnel); uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); From patchwork Sun Jan 24 11:02:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suanming Mou X-Patchwork-Id: 87158 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62CCBA052A; Sun, 24 Jan 2021 12:02:53 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34E20140DC9; Sun, 24 Jan 2021 12:02:24 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 46623140DA5 for ; Sun, 24 Jan 2021 12:02:21 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from suanmingm@nvidia.com) with SMTP; 24 Jan 2021 13:02:18 +0200 Received: from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10OB2AJ9003937; Sun, 24 Jan 2021 13:02:17 +0200 From: Suanming Mou To: viacheslavo@nvidia.com, matan@nvidia.com Cc: rasland@nvidia.com, dev@dpdk.org, stable@dpdk.org Date: Sun, 24 Jan 2021 19:02:06 +0800 Message-Id: <1611486126-84749-5-git-send-email-suanmingm@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> References: <1611486126-84749-1-git-send-email-suanmingm@nvidia.com> Subject: [dpdk-dev] [PATCH 4/4] net/mlx4: fix secondary process attach port Tx queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, the secondary process port UAR register mapping used by Tx queue is done during port initializing. Unluckily, in port hot-plug case, the secondary process will be requested to initialize the port when primary process probe the port. At that time, the port Tx queue number is still not configured, the secondary process get Tx queue number as 0. This causes the UAR register not be mapped as secondary process get Tx queue number 0. This commit adds the check of Tx queue number in secondary process when port starts is requested. Once the Tx queue number is not matching, do UAR mapping with the latest Tx queue number. Fixes: 0203d33a1059 ("net/mlx4: support secondary process") cc: stable@dpdk.org Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx4/mlx4.c | 10 +++++----- drivers/net/mlx4/mlx4.h | 4 ++++ drivers/net/mlx4/mlx4_mp.c | 24 ++++++++++++++++++++++++ drivers/net/mlx4/mlx4_rxtx.h | 1 + drivers/net/mlx4/mlx4_txq.c | 28 ++++++++++++++++++++++++++++ 5 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c index 495b4fc..919a934 100644 --- a/drivers/net/mlx4/mlx4.c +++ b/drivers/net/mlx4/mlx4.c @@ -195,7 +195,7 @@ struct mlx4_conf { * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -static int +int mlx4_proc_priv_init(struct rte_eth_dev *dev) { struct mlx4_proc_priv *ppriv; @@ -207,13 +207,13 @@ struct mlx4_conf { */ ppriv_size = sizeof(struct mlx4_proc_priv) + dev->data->nb_tx_queues * sizeof(void *); - ppriv = rte_malloc_socket("mlx4_proc_priv", ppriv_size, - RTE_CACHE_LINE_SIZE, dev->device->numa_node); + ppriv = rte_zmalloc_socket("mlx4_proc_priv", ppriv_size, + RTE_CACHE_LINE_SIZE, dev->device->numa_node); if (!ppriv) { rte_errno = ENOMEM; return -rte_errno; } - ppriv->uar_table_sz = ppriv_size; + ppriv->uar_table_sz = dev->data->nb_tx_queues; dev->process_private = ppriv; return 0; } @@ -224,7 +224,7 @@ struct mlx4_conf { * @param dev * Pointer to Ethernet device structure. */ -static void +void mlx4_proc_priv_uninit(struct rte_eth_dev *dev) { if (!dev->process_private) diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h index c6cb294..87710d3 100644 --- a/drivers/net/mlx4/mlx4.h +++ b/drivers/net/mlx4/mlx4.h @@ -197,6 +197,10 @@ struct mlx4_priv { #define PORT_ID(priv) ((priv)->dev_data->port_id) #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) +int mlx4_proc_priv_init(struct rte_eth_dev *dev); +void mlx4_proc_priv_uninit(struct rte_eth_dev *dev); + + /* mlx4_ethdev.c */ int mlx4_get_ifname(const struct mlx4_priv *priv, char (*ifname)[IF_NAMESIZE]); diff --git a/drivers/net/mlx4/mlx4_mp.c b/drivers/net/mlx4/mlx4_mp.c index eca0c20..3622d61 100644 --- a/drivers/net/mlx4/mlx4_mp.c +++ b/drivers/net/mlx4/mlx4_mp.c @@ -111,6 +111,9 @@ const struct mlx4_mp_param *param = (const struct mlx4_mp_param *)mp_msg->param; struct rte_eth_dev *dev; +#ifdef HAVE_IBV_MLX4_UAR_MMAP_OFFSET + struct mlx4_proc_priv *ppriv; +#endif int ret; MLX4_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY); @@ -126,6 +129,21 @@ rte_mb(); dev->tx_pkt_burst = mlx4_tx_burst; dev->rx_pkt_burst = mlx4_rx_burst; +#ifdef HAVE_IBV_MLX4_UAR_MMAP_OFFSET + ppriv = (struct mlx4_proc_priv *)dev->process_private; + if (ppriv->uar_table_sz != dev->data->nb_tx_queues) { + mlx4_tx_uar_uninit_secondary(dev); + mlx4_proc_priv_uninit(dev); + ret = mlx4_proc_priv_init(dev); + if (ret) + return -rte_errno; + ret = mlx4_tx_uar_init_secondary(dev, mp_msg->fds[0]); + if (ret) { + mlx4_proc_priv_uninit(dev); + return -rte_errno; + } + } +#endif mp_init_msg(dev, &mp_res, param->type); res->result = 0; ret = rte_mp_reply(&mp_res, peer); @@ -163,6 +181,7 @@ struct rte_mp_reply mp_rep; struct mlx4_mp_param *res __rte_unused; struct timespec ts = {.tv_sec = MLX4_MP_REQ_TIMEOUT_SEC, .tv_nsec = 0}; + struct mlx4_priv *priv; int ret; int i; @@ -175,6 +194,11 @@ return; } mp_init_msg(dev, &mp_req, type); + if (type == MLX4_MP_REQ_START_RXTX) { + priv = dev->data->dev_private; + mp_req.num_fds = 1; + mp_req.fds[0] = priv->ctx->cmd_fd; + } ret = rte_mp_request_sync(&mp_req, &mp_rep, &ts); if (ret) { if (rte_errno != ENOTSUP) diff --git a/drivers/net/mlx4/mlx4_rxtx.h b/drivers/net/mlx4/mlx4_rxtx.h index 9de6c59..136ca56 100644 --- a/drivers/net/mlx4/mlx4_rxtx.h +++ b/drivers/net/mlx4/mlx4_rxtx.h @@ -157,6 +157,7 @@ uint16_t mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, /* mlx4_txq.c */ int mlx4_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd); +void mlx4_tx_uar_uninit_secondary(struct rte_eth_dev *dev); uint64_t mlx4_get_tx_port_offloads(struct mlx4_priv *priv); int mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, diff --git a/drivers/net/mlx4/mlx4_txq.c b/drivers/net/mlx4/mlx4_txq.c index 37b8441..60560d9 100644 --- a/drivers/net/mlx4/mlx4_txq.c +++ b/drivers/net/mlx4/mlx4_txq.c @@ -157,6 +157,27 @@ } while (i--); return -rte_errno; } + +void +mlx4_tx_uar_uninit_secondary(struct rte_eth_dev *dev) +{ + struct mlx4_proc_priv *ppriv = + (struct mlx4_proc_priv *)dev->process_private; + const size_t page_size = sysconf(_SC_PAGESIZE); + void *addr; + size_t i; + + if (page_size == (size_t)-1) { + ERROR("Failed to get mem page size"); + return; + } + for (i = 0; i < ppriv->uar_table_sz; i++) { + addr = ppriv->uar_table[i]; + if (addr) + munmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size); + } +} + #else int mlx4_tx_uar_init_secondary(struct rte_eth_dev *dev __rte_unused, @@ -167,6 +188,13 @@ rte_errno = ENOTSUP; return -rte_errno; } + +void +mlx4_tx_uar_uninit_secondary(struct rte_eth_dev *dev __rte_unused) +{ + assert(rte_eal_process_type() == RTE_PROC_SECONDARY); + ERROR("UAR remap is not supported"); +} #endif /**