From patchwork Tue Jan 12 07:24:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Amber, Kumar" X-Patchwork-Id: 86385 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9AA3A04B5; Tue, 12 Jan 2021 08:33:32 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5D8BA140CFE; Tue, 12 Jan 2021 08:33:32 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id F1503140CFD for ; Tue, 12 Jan 2021 08:33:29 +0100 (CET) IronPort-SDR: t+eYdq2bGJBcaY2sv80e+d65D/R9U/68FkhIyZBs6k01T8jjfjpNdWORIDqCQlsPzFrzXqK9YZ AxJTJJl14KyA== X-IronPort-AV: E=McAfee;i="6000,8403,9861"; a="165081704" X-IronPort-AV: E=Sophos;i="5.79,340,1602572400"; d="scan'208";a="165081704" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2021 23:33:28 -0800 IronPort-SDR: Fc428WPzVKq0nXFxQO7K7H95vh+egB3Qm5Huqgrd7yc56Xfg3CDg0+PCjOj2MR+KCPYWMcYxP0 vhFEpYrmMRGg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,340,1602572400"; d="scan'208";a="569011467" Received: from bmca4bf01706bbf.iind.intel.com (HELO localhost.localdomain) ([10.190.213.111]) by fmsmga006.fm.intel.com with ESMTP; 11 Jan 2021 23:33:26 -0800 From: kumar amber To: dev@dpdk.org Cc: bruce.richardson@intel.com Date: Tue, 12 Jan 2021 12:54:46 +0530 Message-Id: <20210112072446.880122-1-kumar.amber@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v1] lib/hash: support non sse42 cpu architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" add _SSE42_ flag to enable compilation of sse42 specific instructions only on supported architecture Signed-off-by: kumar amber --- lib/librte_hash/rte_hash_crc.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h index 3e131aa6bb..e9f063780c 100644 --- a/lib/librte_hash/rte_hash_crc.h +++ b/lib/librte_hash/rte_hash_crc.h @@ -358,7 +358,7 @@ crc32c_2words(uint64_t data, uint32_t init_val) return crc; } -#if defined(RTE_ARCH_X86) +#if defined(RTE_ARCH_X86) && defined(__SSE42__) static inline uint32_t crc32c_sse42_u8(uint8_t data, uint32_t init_val) { @@ -404,7 +404,7 @@ crc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val) } #endif -#ifdef RTE_ARCH_X86_64 +#if defined(RTE_ARCH_X86_64) && defined(__SSE42__) static inline uint32_t crc32c_sse42_u64(uint64_t data, uint64_t init_val) { @@ -442,7 +442,7 @@ static uint8_t crc32_alg = CRC32_SW; static inline void rte_hash_crc_set_alg(uint8_t alg) { -#if defined(RTE_ARCH_X86) +#if defined(RTE_ARCH_X86) && defined(__SSE42__) if (alg == CRC32_SSE42_x64 && !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) alg = CRC32_SSE42; @@ -471,7 +471,7 @@ RTE_INIT(rte_hash_crc_init_alg) static inline uint32_t rte_hash_crc_1byte(uint8_t data, uint32_t init_val) { -#if defined RTE_ARCH_X86 +#if defined(RTE_ARCH_X86) && defined(__SSE42__) if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u8(data, init_val); #endif @@ -494,7 +494,7 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val) static inline uint32_t rte_hash_crc_2byte(uint16_t data, uint32_t init_val) { -#if defined RTE_ARCH_X86 +#if defined(RTE_ARCH_X86) && defined(__SSE42__) if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u16(data, init_val); #endif @@ -517,7 +517,7 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val) static inline uint32_t rte_hash_crc_4byte(uint32_t data, uint32_t init_val) { -#if defined RTE_ARCH_X86 +#if defined(RTE_ARCH_X86) && defined(__SSE42__) if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u32(data, init_val); #endif @@ -540,12 +540,12 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) static inline uint32_t rte_hash_crc_8byte(uint64_t data, uint32_t init_val) { -#ifdef RTE_ARCH_X86_64 +#if defined(RTE_ARCH_X86) && defined(__SSE42__) if (likely(crc32_alg == CRC32_SSE42_x64)) return crc32c_sse42_u64(data, init_val); #endif -#if defined RTE_ARCH_X86 +#if defined(RTE_ARCH_X86) && defined(__SSE42__) if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u64_mimic(data, init_val); #endif