From patchwork Wed Dec 2 10:11:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84675 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E159A04DB; Wed, 2 Dec 2020 11:13:08 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E7FB4C9E0; Wed, 2 Dec 2020 11:12:27 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id F3BA5C9A8; Wed, 2 Dec 2020 11:12:23 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKE0024169; Wed, 2 Dec 2020 02:12:22 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; 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Wed, 2 Dec 2020 02:12:17 -0800 From: To: CC: , Yuri Chipchev , , Liron Himi Date: Wed, 2 Dec 2020 12:11:35 +0200 Message-ID: <20201202101212.4717-2-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 01/38] net/mvpp2: fix stack corruption X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev Fixes stack corruption in mrvl_fill_bpool function in case num > MRVL_PP2_RXD_MAX Fixes: c3637258d894 ("net/mrvl: fix Rx descriptors number") Cc: stable@dpdk.org Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index f25cf9e46..93fb30cdb 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1614,8 +1614,8 @@ mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) { - struct buff_release_entry entries[MRVL_PP2_RXD_MAX]; - struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX]; + struct buff_release_entry entries[num]; + struct rte_mbuf *mbufs[num]; int i, ret; unsigned int core_id; struct pp2_hif *hif; From patchwork Wed Dec 2 10:11:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84674 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3619A04DB; Wed, 2 Dec 2020 11:12:44 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 20029C9C8; Wed, 2 Dec 2020 11:12:26 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 4D014C9C0; Wed, 2 Dec 2020 11:12:23 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A56KX001864; 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Wed, 2 Dec 2020 02:12:20 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:19 -0800 From: To: CC: , Liron Himi , Date: Wed, 2 Dec 2020 12:11:36 +0200 Message-ID: <20201202101212.4717-3-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 02/38] net/mvpp2: remove debug log on fast-path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi in case of non-ip frame the current code reached the 'default' case which result with function call to log a msg. those kind of calls should not be performed on fast-path. The performance for this kind of frames increased by 50% Fixes: acab7d58c ("net/mvpp2: convert to dynamic logging") Cc: stable@dpdk.org Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 93fb30cdb..8c3278ec4 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2171,7 +2171,6 @@ mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, *l4_offset = *l3_offset + MRVL_ARP_LENGTH; break; default: - MRVL_LOG(DEBUG, "Failed to recognise l3 packet type"); break; } @@ -2183,7 +2182,6 @@ mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, packet_type |= RTE_PTYPE_L4_UDP; break; default: - MRVL_LOG(DEBUG, "Failed to recognise l4 packet type"); break; } From patchwork Wed Dec 2 10:11:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84676 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C3B5FA04DB; Wed, 2 Dec 2020 11:13:30 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B15E7C9F2; Wed, 2 Dec 2020 11:12:29 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 65325C9C8; Wed, 2 Dec 2020 11:12:24 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A5G20001975; Wed, 2 Dec 2020 02:12:23 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; 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Wed, 2 Dec 2020 02:12:21 -0800 From: To: CC: , Yuri Chipchev , , Liron Himi Date: Wed, 2 Dec 2020 12:11:37 +0200 Message-ID: <20201202101212.4717-4-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 03/38] net/mvpp2: fix rx/tx bytes statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev 4B of CRC was not included in the bytes statistics Fixes: bdffe0c70 ("net/mrvl: support basic stats") Cc: stable@dpdk.org Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 8c3278ec4..ebd2bb1c8 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1278,7 +1278,6 @@ mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) rx_stats.drop_fullq + rx_stats.drop_bm + rxq->drop_mac; - stats->ibytes += rxq->bytes_recv; drop_mac += rxq->drop_mac; } @@ -1306,7 +1305,6 @@ mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) stats->q_opackets[idx] = tx_stats.deq_desc; stats->q_obytes[idx] = txq->bytes_sent; - stats->obytes += txq->bytes_sent; } ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); @@ -1315,6 +1313,8 @@ mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) return ret; } + stats->ibytes += ppio_stats.rx_bytes; + stats->obytes += ppio_stats.tx_bytes; stats->ipackets += ppio_stats.rx_packets - drop_mac; stats->opackets += ppio_stats.tx_packets; stats->imissed += ppio_stats.rx_fullq_dropped + From patchwork Wed Dec 2 10:11:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84677 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9C977A04DB; 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Wed, 02 Dec 2020 02:12:25 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:23 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:23 -0800 From: To: CC: , Liron Himi , Date: Wed, 2 Dec 2020 12:11:38 +0200 Message-ID: <20201202101212.4717-5-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 04/38] net/mvpp2: skip vlan flush X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi vlan-flush in MUSDK is not supported yet. until it does, the code should be skipped as currently an redundant error message is displayed. Fixes: a8f3d6783 ("net/mrvl: support VLAN filtering") Cc: stable@dpdk.org Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index ebd2bb1c8..0985ccebe 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -672,15 +672,15 @@ mrvl_dev_start(struct rte_eth_dev *dev) } if (!priv->vlan_flushed) { - ret = pp2_ppio_flush_vlan(priv->ppio); - if (ret) { - MRVL_LOG(ERR, "Failed to flush vlan list"); - /* - * TODO - * once pp2_ppio_flush_vlan() is supported jump to out - * goto out; - */ - } + /* + * TODO + * once pp2_ppio_flush_vlan() is supported call it + * ret = pp2_ppio_flush_vlan(priv->ppio); + * if (ret) { + * MRVL_LOG(ERR, "Failed to flush vlan list"); + * goto out; + * } + */ priv->vlan_flushed = 1; } ret = mrvl_mtu_set(dev, dev->data->mtu); From patchwork Wed Dec 2 10:11:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84678 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 094EDA04DB; Wed, 2 Dec 2020 11:14:13 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 38964CA0E; Wed, 2 Dec 2020 11:12:33 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id B7CBBC9F4; Wed, 2 Dec 2020 11:12:29 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKgB024170; Wed, 2 Dec 2020 02:12:28 -0800 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r4q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Dec 2020 02:12:28 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:26 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:24 -0800 From: To: CC: , Liron Himi , , Yuri Chipchev Date: Wed, 2 Dec 2020 12:11:39 +0200 Message-ID: <20201202101212.4717-6-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 05/38] net/mvpp2: remove CRC len from MRU validation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi CRC is being removed by HW before packet get write to the buffer, so CRC len should not be included in MRU validation Fixes: 79ec62028 ("net/mvpp2: update MTU and MRU related calculations") Cc: stable@dpdk.org Signed-off-by: Liron Himi Reviewed-by: Yuri Chipchev Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Yuri Chipchev --- drivers/net/mvpp2/mrvl_ethdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 0985ccebe..dbb193496 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -441,8 +441,8 @@ mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) * when this feature has not been enabled/supported so far * (TODO check scattered_rx flag here once scattered RX is supported). */ - if (mru + MRVL_PKT_OFFS > mbuf_data_size) { - mru = mbuf_data_size - MRVL_PKT_OFFS; + if (mru - RTE_ETHER_CRC_LEN + MRVL_PKT_OFFS > mbuf_data_size) { + mru = mbuf_data_size + RTE_ETHER_CRC_LEN - MRVL_PKT_OFFS; mtu = MRVL_PP2_MRU_TO_MTU(mru); MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted " "by current mbuf size: %u. Set MTU to %u, MRU to %u", From patchwork Wed Dec 2 10:11:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84680 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B0E61A04DB; Wed, 2 Dec 2020 11:14:58 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 70582CA41; Wed, 2 Dec 2020 11:12:37 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 733A8CA24; Wed, 2 Dec 2020 11:12:34 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKqZ024171; Wed, 2 Dec 2020 02:12:32 -0800 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r4r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Dec 2020 02:12:30 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:28 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:27 -0800 From: To: CC: , Liron Himi , , Yuri Chipchev Date: Wed, 2 Dec 2020 12:11:40 +0200 Message-ID: <20201202101212.4717-7-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 06/38] net/mvpp2: fix frame size checking X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi need to add CRC len to the frame-size to compare against max_rx_pkt_len which includes it. Fixes: 79ec62028 ("net/mvpp2: update MTU and MRU related calculations") Cc: stable@dpdk.org Signed-off-by: Liron Himi Reviewed-by: Yuri Chipchev Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Yuri Chipchev --- drivers/net/mvpp2/mrvl_ethdev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index dbb193496..3f05ebe00 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1711,7 +1711,8 @@ mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, return -EFAULT; } - frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS; + frame_size = buf_size - RTE_PKTMBUF_HEADROOM - + MRVL_PKT_EFFEC_OFFS + RTE_ETHER_CRC_LEN; if (frame_size < max_rx_pkt_len) { MRVL_LOG(WARNING, "Mbuf size must be increased to %u bytes to hold up " From patchwork Wed Dec 2 10:11:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84679 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 88085A04DB; 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Wed, 2 Dec 2020 02:12:29 -0800 From: To: CC: , Liron Himi , , Dana Tearosh Date: Wed, 2 Dec 2020 12:11:41 +0200 Message-ID: <20201202101212.4717-8-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 07/38] net/mvpp2: reduce prints on rx path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi Fixes: acab7d58c ("net/mvpp2: convert to dynamic logging") Cc: stable@dpdk.org Signed-off-by: Liron Himi Reviewed-by: Dana Tearosh Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Dana Tearosh --- drivers/net/mvpp2/mrvl_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 3f05ebe00..d81b86c02 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2320,7 +2320,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) (!rx_done && num < q->priv->bpool_init_size))) { ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE); if (ret) - MRVL_LOG(ERR, "Failed to fill bpool"); + MRVL_LOG(DEBUG, "Failed to fill bpool"); } else if (unlikely(num > q->priv->bpool_max_size)) { int i; int pkt_to_remove = num - q->priv->bpool_init_size; From patchwork Wed Dec 2 10:11:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84681 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E6F8A04DC; Wed, 2 Dec 2020 11:15:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AF849C9D3; Wed, 2 Dec 2020 11:12:38 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 5F125CA36 for ; Wed, 2 Dec 2020 11:12:35 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A5G23001975 for ; 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Wed, 2 Dec 2020 02:12:33 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:33 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:32 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:42 +0200 Message-ID: <20201202101212.4717-9-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 08/38] net/mvpp2: rss reservation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev reserve 4 rss tables for lk-4.14 support Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index d81b86c02..46e7260be 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -33,7 +33,7 @@ /* bitmask with reserved bpools */ #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 /* bitmask with reserved kernel RSS tables */ -#define MRVL_MUSDK_RSS_RESERVED 0x01 +#define MRVL_MUSDK_RSS_RESERVED 0x0F /* maximum number of available hifs */ #define MRVL_MUSDK_HIFS_MAX 9 From patchwork Wed Dec 2 10:11:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84682 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0AA33A04DB; Wed, 2 Dec 2020 11:15:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 55CFBCA4E; Wed, 2 Dec 2020 11:12:40 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id E418FCA4C for ; Wed, 2 Dec 2020 11:12:37 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKgC024170 for ; Wed, 2 Dec 2020 02:12:37 -0800 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r4y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:12:37 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:35 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:34 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:43 +0200 Message-ID: <20201202101212.4717-10-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 09/38] net/mvpp2: extend xstats support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev add xstats_by_id callbacks Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 90 +++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 46e7260be..e81d5ee91 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2027,6 +2027,94 @@ mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused, } } +/** + * DPDK callback to get xstats by id. + * + * @param dev + * Pointer to the device structure. + * @param ids + * Pointer to the ids table. + * @param values + * Pointer to the values table. + * @param n + * Values table size. + * @returns + * Number of read values, negative value otherwise. + */ +static int +mrvl_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, + uint64_t *values, unsigned int n) +{ + unsigned int i, num = RTE_DIM(mrvl_xstats_tbl); + uint64_t vals[n]; + int ret; + + if (!ids) { + struct rte_eth_xstat xstats[num]; + int j; + + ret = mrvl_xstats_get(dev, xstats, num); + for (j = 0; j < ret; i++) + values[j] = xstats[j].value; + + return ret; + } + + ret = mrvl_xstats_get_by_id(dev, NULL, vals, n); + if (ret < 0) + return ret; + + for (i = 0; i < n; i++) { + if (ids[i] >= num) { + MRVL_LOG(ERR, "id value is not valid\n"); + return -1; + } + + values[i] = vals[ids[i]]; + } + + return n; +} + +/** + * DPDK callback to get xstats names by ids. + * + * @param dev + * Pointer to the device structure. + * @param xstats_names + * Pointer to table with xstats names. + * @param ids + * Pointer to table with ids. + * @param size + * Xstats names table size. + * @returns + * Number of names read, negative value otherwise. + */ +static int +mrvl_xstats_get_names_by_id(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + const uint64_t *ids, unsigned int size) +{ + unsigned int i, num = RTE_DIM(mrvl_xstats_tbl); + struct rte_eth_xstat_name names[num]; + + if (!ids) + return mrvl_xstats_get_names(dev, xstats_names, size); + + mrvl_xstats_get_names(dev, names, size); + for (i = 0; i < size; i++) { + if (ids[i] >= num) { + MRVL_LOG(ERR, "id value is not valid"); + return -1; + } + + snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, + "%s", names[ids[i]].name); + } + + return size; +} + /** * DPDK callback to get rte_mtr callbacks. * @@ -2102,6 +2190,8 @@ static const struct eth_dev_ops mrvl_ops = { .rss_hash_update = mrvl_rss_hash_update, .rss_hash_conf_get = mrvl_rss_hash_conf_get, .filter_ctrl = mrvl_eth_filter_ctrl, + .xstats_get_by_id = mrvl_xstats_get_by_id, + .xstats_get_names_by_id = mrvl_xstats_get_names_by_id, .mtr_ops_get = mrvl_mtr_ops_get, .tm_ops_get = mrvl_tm_ops_get, }; From patchwork Wed Dec 2 10:11:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84683 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6B6C7A04DB; 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Wed, 2 Dec 2020 02:12:36 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:44 +0200 Message-ID: <20201202101212.4717-11-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 10/38] net/mvpp2: cosmetic changes to cookie usage X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev No need to add high address to cookie on transmit side, as it has already 64bit value Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index e81d5ee91..130f5221d 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1643,14 +1643,16 @@ mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK) != cookie_addr_high) { MRVL_LOG(ERR, - "mbuf virtual addr high 0x%lx out of range", - (uint64_t)mbufs[i] >> 32); + "mbuf virtual addr high is out of range " + "0x%x instead of 0x%x\n", + (uint32_t)((uint64_t)mbufs[i] >> 32), + (uint32_t)(cookie_addr_high >> 32)); goto out; } entries[i].buff.addr = rte_mbuf_data_iova_default(mbufs[i]); - entries[i].buff.cookie = (uint64_t)mbufs[i]; + entries[i].buff.cookie = (uintptr_t)mbufs[i]; entries[i].bpool = bpool; } @@ -2549,8 +2551,7 @@ mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, if (unlikely(!entry->bpool)) { struct rte_mbuf *mbuf; - mbuf = (struct rte_mbuf *) - (cookie_addr_high | entry->buff.cookie); + mbuf = (struct rte_mbuf *)entry->buff.cookie; rte_pktmbuf_free(mbuf); skip_bufs = 1; goto skip; @@ -2663,7 +2664,7 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) for (i = nb_pkts; i < num; i++) { sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & MRVL_PP2_TX_SHADOWQ_MASK; - addr = cookie_addr_high | sq->ent[sq->head].buff.cookie; + addr = sq->ent[sq->head].buff.cookie; bytes_sent -= rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); } From patchwork Wed Dec 2 10:11:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84684 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6607FA04DB; Wed, 2 Dec 2020 11:16:12 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2F049CA58; Wed, 2 Dec 2020 11:12:46 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 2359ECA58 for ; Wed, 2 Dec 2020 11:12:44 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKE1024169 for ; Wed, 2 Dec 2020 02:12:43 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 2 Dec 2020 02:12:38 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:45 +0200 Message-ID: <20201202101212.4717-12-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 11/38] net/mvpp2: align checking order X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev first check for 'isolated' and then for '!ppio' Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 130f5221d..76847b303 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1007,10 +1007,10 @@ mrvl_promiscuous_enable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; - if (!priv->ppio) + if (priv->isolated) return 0; - if (priv->isolated) + if (!priv->ppio) return 0; ret = pp2_ppio_set_promisc(priv->ppio, 1); @@ -1037,10 +1037,10 @@ mrvl_allmulticast_enable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; - if (!priv->ppio) + if (priv->isolated) return 0; - if (priv->isolated) + if (!priv->ppio) return 0; ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); @@ -1067,6 +1067,9 @@ mrvl_promiscuous_disable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (priv->isolated) + return 0; + if (!priv->ppio) return 0; @@ -1094,6 +1097,9 @@ mrvl_allmulticast_disable(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (priv->isolated) + return 0; + if (!priv->ppio) return 0; @@ -1121,10 +1127,10 @@ mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) char buf[RTE_ETHER_ADDR_FMT_SIZE]; int ret; - if (!priv->ppio) + if (priv->isolated) return; - if (priv->isolated) + if (!priv->ppio) return; ret = pp2_ppio_remove_mac_addr(priv->ppio, @@ -1209,12 +1215,12 @@ mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) struct mrvl_priv *priv = dev->data->dev_private; int ret; - if (!priv->ppio) - return 0; - if (priv->isolated) return -ENOTSUP; + if (!priv->ppio) + return 0; + ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); if (ret) { char buf[RTE_ETHER_ADDR_FMT_SIZE]; @@ -1590,12 +1596,12 @@ mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) { struct mrvl_priv *priv = dev->data->dev_private; - if (!priv->ppio) - return -EPERM; - if (priv->isolated) return -ENOTSUP; + if (!priv->ppio) + return 0; + return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : pp2_ppio_remove_vlan(priv->ppio, vlan_id); } From patchwork Wed Dec 2 10:11:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84685 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B3BDA04DB; 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Wed, 2 Dec 2020 02:12:40 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:46 +0200 Message-ID: <20201202101212.4717-13-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 12/38] net/mvpp2: save initial configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev save configuration that was done prior 'start' as only then the ppio is being configured. Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 107 +++++++++++++++++++++++++++----- 1 file changed, 92 insertions(+), 15 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 76847b303..c70a8fe93 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2017 Marvell International Ltd. - * Copyright(c) 2017 Semihalf. + * Copyright(c) 2018 Marvell International Ltd. + * Copyright(c) 2018 Semihalf. * All rights reserved. */ @@ -146,6 +146,15 @@ static int rte_pmd_mrvl_remove(struct rte_vdev_device *vdev); static void mrvl_deinit_pp2(void); static void mrvl_deinit_hifs(void); +static int +mrvl_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, + uint32_t index, uint32_t vmdq __rte_unused); +static int +mrvl_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); +static int +mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); +static int mrvl_promiscuous_enable(struct rte_eth_dev *dev); +static int mrvl_allmulticast_enable(struct rte_eth_dev *dev); #define MRVL_XSTATS_TBL_ENTRY(name) { \ #name, offsetof(struct pp2_ppio_statistics, name), \ @@ -402,8 +411,12 @@ mrvl_dev_configure(struct rte_eth_dev *dev) return 0; } - return mrvl_configure_rss(priv, - &dev->data->dev_conf.rx_adv_conf.rss_conf); + ret = mrvl_configure_rss(priv, + &dev->data->dev_conf.rx_adv_conf.rss_conf); + if (ret < 0) + return ret; + + return 0; } /** @@ -490,8 +503,10 @@ mrvl_dev_set_link_up(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; - if (!priv->ppio) - return -EPERM; + if (!priv->ppio) { + dev->data->dev_link.link_status = ETH_LINK_UP; + return 0; + } ret = pp2_ppio_enable(priv->ppio); if (ret) @@ -505,10 +520,13 @@ mrvl_dev_set_link_up(struct rte_eth_dev *dev) * Set mtu to default DPDK value here. */ ret = mrvl_mtu_set(dev, dev->data->mtu); - if (ret) + if (ret) { pp2_ppio_disable(priv->ppio); + return ret; + } - return ret; + dev->data->dev_link.link_status = ETH_LINK_UP; + return 0; } /** @@ -524,11 +542,18 @@ static int mrvl_dev_set_link_down(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; + int ret; - if (!priv->ppio) - return -EPERM; + if (!priv->ppio) { + dev->data->dev_link.link_status = ETH_LINK_DOWN; + return 0; + } + ret = pp2_ppio_disable(priv->ppio); + if (ret) + return ret; - return pp2_ppio_disable(priv->ppio); + dev->data->dev_link.link_status = ETH_LINK_DOWN; + return 0; } /** @@ -610,6 +635,9 @@ mrvl_dev_start(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; char match[MRVL_MATCH_LEN]; int ret = 0, i, def_init_size; + uint32_t j; + struct rte_vlan_filter_conf *vfc; + struct rte_ether_addr *mac_addr; if (priv->ppio) return mrvl_dev_set_link_up(dev); @@ -687,6 +715,47 @@ mrvl_dev_start(struct rte_eth_dev *dev) if (ret) MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu); + if (!rte_is_zero_ether_addr(&dev->data->mac_addrs[0])) + mrvl_mac_addr_set(dev, &dev->data->mac_addrs[0]); + + for (i = 1; i < MRVL_MAC_ADDRS_MAX; i++) { + mac_addr = &dev->data->mac_addrs[i]; + + /* skip zero address */ + if (rte_is_zero_ether_addr(mac_addr)) + continue; + + mrvl_mac_addr_add(dev, mac_addr, i, 0); + } + + if (dev->data->all_multicast == 1) + mrvl_allmulticast_enable(dev); + + vfc = &dev->data->vlan_filter_conf; + for (j = 0; j < RTE_DIM(vfc->ids); j++) { + uint64_t vlan; + uint64_t vbit; + uint64_t ids = vfc->ids[j]; + + if (ids == 0) + continue; + + while (ids) { + vlan = 64 * j; + /* count trailing zeroes */ + vbit = ~ids & (ids - 1); + /* clear least significant bit set */ + ids ^= (ids ^ (ids - 1)) ^ vbit; + for (; vbit; vlan++) + vbit >>= 1; + ret = mrvl_vlan_filter_set(dev, vlan, 1); + if (ret) { + MRVL_LOG(ERR, "Failed to setup VLAN filter\n"); + goto out; + } + } + } + /* For default QoS config, don't start classifier. */ if (mrvl_qos_cfg && mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) { @@ -697,10 +766,16 @@ mrvl_dev_start(struct rte_eth_dev *dev) } } - ret = mrvl_dev_set_link_up(dev); - if (ret) { - MRVL_LOG(ERR, "Failed to set link up"); - goto out; + if (dev->data->promiscuous == 1) + mrvl_promiscuous_enable(dev); + + if (dev->data->dev_link.link_status == ETH_LINK_UP) { + ret = mrvl_dev_set_link_up(dev); + if (ret) { + MRVL_LOG(ERR, "Failed to set link up"); + dev->data->dev_link.link_status = ETH_LINK_DOWN; + goto out; + } } /* start tx queues */ @@ -2963,6 +3038,8 @@ mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) eth_dev->dev_ops = &mrvl_ops; eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; + eth_dev->data->dev_link.link_status = ETH_LINK_UP; + rte_eth_dev_probing_finish(eth_dev); return 0; out_free: From patchwork Wed Dec 2 10:11:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84686 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CC72CA04DB; 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Wed, 02 Dec 2020 02:12:44 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:43 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:42 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:47 +0200 Message-ID: <20201202101212.4717-14-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 13/38] net/mvpp2: add loopback support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev add support for loopback mode Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index c70a8fe93..5cd9ee38d 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -766,6 +766,12 @@ mrvl_dev_start(struct rte_eth_dev *dev) } } + ret = pp2_ppio_set_loopback(priv->ppio, dev->data->dev_conf.lpbk_mode); + if (ret) { + MRVL_LOG(ERR, "Failed to set loopback"); + goto out; + } + if (dev->data->promiscuous == 1) mrvl_promiscuous_enable(dev); From patchwork Wed Dec 2 10:11:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84687 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8EA25A04DB; Wed, 2 Dec 2020 11:17:13 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BDF56CA90; Wed, 2 Dec 2020 11:12:50 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id DF50ACA68 for ; Wed, 2 Dec 2020 11:12:48 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKqa024171 for ; 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Wed, 2 Dec 2020 02:12:45 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:44 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:48 +0200 Message-ID: <20201202101212.4717-15-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 14/38] net/mvpp2: add vlan offload support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev enable vlan filter configuration Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 110 +++++++++++++++++++++++++------- 1 file changed, 86 insertions(+), 24 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 5cd9ee38d..a87336a4c 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -620,6 +620,51 @@ mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id) return 0; } +/** + * Populate Vlan Filter configuration. + * + * @param dev + * Pointer to Ethernet device structure. + * @param on + * Toggle filter. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int mrvl_populate_vlan_table(struct rte_eth_dev *dev, int on) +{ + uint32_t j; + int ret; + struct rte_vlan_filter_conf *vfc; + + vfc = &dev->data->vlan_filter_conf; + for (j = 0; j < RTE_DIM(vfc->ids); j++) { + uint64_t vlan; + uint64_t vbit; + uint64_t ids = vfc->ids[j]; + + if (ids == 0) + continue; + + while (ids) { + vlan = 64 * j; + /* count trailing zeroes */ + vbit = ~ids & (ids - 1); + /* clear least significant bit set */ + ids ^= (ids ^ (ids - 1)) ^ vbit; + for (; vbit; vlan++) + vbit >>= 1; + ret = mrvl_vlan_filter_set(dev, vlan, on); + if (ret) { + MRVL_LOG(ERR, "Failed to setup VLAN filter\n"); + return ret; + } + } + } + + return 0; +} + /** * DPDK callback to start the device. * @@ -635,8 +680,6 @@ mrvl_dev_start(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; char match[MRVL_MATCH_LEN]; int ret = 0, i, def_init_size; - uint32_t j; - struct rte_vlan_filter_conf *vfc; struct rte_ether_addr *mac_addr; if (priv->ppio) @@ -731,28 +774,11 @@ mrvl_dev_start(struct rte_eth_dev *dev) if (dev->data->all_multicast == 1) mrvl_allmulticast_enable(dev); - vfc = &dev->data->vlan_filter_conf; - for (j = 0; j < RTE_DIM(vfc->ids); j++) { - uint64_t vlan; - uint64_t vbit; - uint64_t ids = vfc->ids[j]; - - if (ids == 0) - continue; - - while (ids) { - vlan = 64 * j; - /* count trailing zeroes */ - vbit = ~ids & (ids - 1); - /* clear least significant bit set */ - ids ^= (ids ^ (ids - 1)) ^ vbit; - for (; vbit; vlan++) - vbit >>= 1; - ret = mrvl_vlan_filter_set(dev, vlan, 1); - if (ret) { - MRVL_LOG(ERR, "Failed to setup VLAN filter\n"); - goto out; - } + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { + ret = mrvl_populate_vlan_table(dev, 1); + if (ret) { + MRVL_LOG(ERR, "Failed to populate vlan table"); + goto out; } } @@ -1687,6 +1713,41 @@ mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) pp2_ppio_remove_vlan(priv->ppio, vlan_id); } +/** + * DPDK callback to Configure VLAN offload. + * + * @param dev + * Pointer to Ethernet device structure. + * @param mask + * VLAN offload mask. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int mrvl_vlan_offload_set(struct rte_eth_dev *dev, int mask) +{ + uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; + int ret; + + if (mask & ETH_VLAN_STRIP_MASK) + MRVL_LOG(ERR, "VLAN stripping is not supported\n"); + + if (mask & ETH_VLAN_FILTER_MASK) { + if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) + ret = mrvl_populate_vlan_table(dev, 1); + else + ret = mrvl_populate_vlan_table(dev, 0); + + if (ret) + return ret; + } + + if (mask & ETH_VLAN_EXTEND_MASK) + MRVL_LOG(ERR, "Extend VLAN not supported\n"); + + return 0; +} + /** * Release buffers to hardware bpool (buffer-pool) * @@ -2268,6 +2329,7 @@ static const struct eth_dev_ops mrvl_ops = { .rxq_info_get = mrvl_rxq_info_get, .txq_info_get = mrvl_txq_info_get, .vlan_filter_set = mrvl_vlan_filter_set, + .vlan_offload_set = mrvl_vlan_offload_set, .tx_queue_start = mrvl_tx_queue_start, .tx_queue_stop = mrvl_tx_queue_stop, .rx_queue_setup = mrvl_rx_queue_setup, From patchwork Wed Dec 2 10:11:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84688 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 51AA0A04DB; Wed, 2 Dec 2020 11:17:32 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E4446CA9D; Wed, 2 Dec 2020 11:12:51 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 1C567CA8B for ; Wed, 2 Dec 2020 11:12:49 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A56Kb001864 for ; Wed, 2 Dec 2020 02:12:48 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=anEhY/TrdZQ3ljZKn7DOAqGBj2jxUNtEMVC6nMah274=; b=Vwgmfg2F2QFuGkImBW/cg6zumX1GDIk6MyBAknlwRlaFyjoMqv4HZ1lh5jTo3+GngZZi NN1cgl1LIgL6AkhjVl9DNJU9D06Y+sEu4CmMYSVkAEi19SeMl+pOg1qBmpl99hrj/f1q CKTtxzLFdgNBk9J/h/ktb5qZIQ0RALZZ6FZ5Q9BMX++nJdcq6EPl+XH6qjMEQ9O22Kza IJlx6aZv1h+DRIQfNpzsOHJGFwyhppCYthloBBz8Oj18wTlCHhX2uSfVt4gmQq4AuJ3b oPM8TRhdPcbBjzNH/9fdJejIlSfTv7/4n47FHsE0QYclvuT/SGpn/QnlT7waA8AA3PpI Xg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 3568jf828t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:12:48 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:47 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:46 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:49 +0200 Message-ID: <20201202101212.4717-16-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 15/38] net/mvpp2: only use ol_flags for checksum generation offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi according to the dpdk spec, only 'ol_flags' should be used for tx checksum generation Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 60 ++++++++++++++------------------- 1 file changed, 26 insertions(+), 34 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index a87336a4c..a03d39aee 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -63,11 +63,16 @@ DEV_RX_OFFLOAD_CHECKSUM) /** Port Tx offloads capabilities */ -#define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ - DEV_TX_OFFLOAD_UDP_CKSUM | \ - DEV_TX_OFFLOAD_TCP_CKSUM | \ +#define MRVL_TX_OFFLOAD_CHECKSUM (DEV_TX_OFFLOAD_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_UDP_CKSUM | \ + DEV_TX_OFFLOAD_TCP_CKSUM) +#define MRVL_TX_OFFLOADS (MRVL_TX_OFFLOAD_CHECKSUM | \ DEV_TX_OFFLOAD_MULTI_SEGS) +#define MRVL_TX_PKT_OFFLOADS (PKT_TX_IP_CKSUM | \ + PKT_TX_TCP_CKSUM | \ + PKT_TX_UDP_CKSUM) + static const char * const valid_args[] = { MRVL_IFACE_NAME_ARG, MRVL_CFG_ARG, @@ -2596,8 +2601,6 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) * * @param ol_flags * Offload flags. - * @param packet_type - * Packet type bitfield. * @param l3_type * Pointer to the pp2_ouq_l3_type structure. * @param l4_type @@ -2606,12 +2609,9 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) * Will be set to 1 in case l3 checksum is computed. * @param l4_cksum * Will be set to 1 in case l4 checksum is computed. - * - * @return - * 0 on success, negative error value otherwise. */ -static inline int -mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, +static inline void +mrvl_prepare_proto_info(uint64_t ol_flags, enum pp2_outq_l3_type *l3_type, enum pp2_outq_l4_type *l4_type, int *gen_l3_cksum, @@ -2621,26 +2621,22 @@ mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, * Based on ol_flags prepare information * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor * for offloading. + * in most of the checksum cases ipv4 must be set, so this is the + * default value */ - if (ol_flags & PKT_TX_IPV4) { - *l3_type = PP2_OUTQ_L3_TYPE_IPV4; - *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; - } else if (ol_flags & PKT_TX_IPV6) { + *l3_type = PP2_OUTQ_L3_TYPE_IPV4; + *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; + + if (ol_flags & PKT_TX_IPV6) { *l3_type = PP2_OUTQ_L3_TYPE_IPV6; /* no checksum for ipv6 header */ *gen_l3_cksum = 0; - } else { - /* if something different then stop processing */ - return -1; } - ol_flags &= PKT_TX_L4_MASK; - if ((packet_type & RTE_PTYPE_L4_TCP) && - ol_flags == PKT_TX_TCP_CKSUM) { + if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) { *l4_type = PP2_OUTQ_L4_TYPE_TCP; *gen_l4_cksum = 1; - } else if ((packet_type & RTE_PTYPE_L4_UDP) && - ol_flags == PKT_TX_UDP_CKSUM) { + } else if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM) { *l4_type = PP2_OUTQ_L4_TYPE_UDP; *gen_l4_cksum = 1; } else { @@ -2648,8 +2644,6 @@ mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, /* no checksum for other type */ *gen_l4_cksum = 0; } - - return 0; } /** @@ -2750,7 +2744,7 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) struct pp2_hif *hif; struct pp2_ppio_desc descs[nb_pkts]; unsigned int core_id = rte_lcore_id(); - int i, ret, bytes_sent = 0; + int i, bytes_sent = 0; uint16_t num, sq_free_size; uint64_t addr; @@ -2794,11 +2788,10 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) * in case unsupported ol_flags were passed * do not update descriptor offload information */ - ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, - &l3_type, &l4_type, &gen_l3_cksum, - &gen_l4_cksum); - if (unlikely(ret)) + if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) continue; + mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, + &gen_l3_cksum, &gen_l4_cksum); pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, mbuf->l2_len, @@ -2848,7 +2841,7 @@ mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, struct pp2_ppio_sg_pkts pkts; uint8_t frags[nb_pkts]; unsigned int core_id = rte_lcore_id(); - int i, j, ret, bytes_sent = 0; + int i, j, bytes_sent = 0; int tail, tail_first; uint16_t num, sq_free_size; uint16_t nb_segs, total_descs = 0; @@ -2935,11 +2928,10 @@ mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, /* In case unsupported ol_flags were passed * do not update descriptor offload information */ - ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, - &l3_type, &l4_type, &gen_l3_cksum, - &gen_l4_cksum); - if (unlikely(ret)) + if (!(mbuf->ol_flags & MRVL_TX_PKT_OFFLOADS)) continue; + mrvl_prepare_proto_info(mbuf->ol_flags, &l3_type, &l4_type, + &gen_l3_cksum, &gen_l4_cksum); pp2_ppio_outq_desc_set_proto_info(&descs[tail_first], l3_type, l4_type, mbuf->l2_len, From patchwork Wed Dec 2 10:11:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84690 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F1CC5A04DB; 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Wed, 02 Dec 2020 02:12:50 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:48 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:47 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:50 +0200 Message-ID: <20201202101212.4717-17-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 16/38] net/mvpp2: add dsa mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi extend the config file with 'start-hdr' field. currently 'eth' (default) and 'dsa' headers are supported. Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 4 ++ drivers/net/mvpp2/mrvl_qos.c | 65 ++++++++++++++++++++++++++------- drivers/net/mvpp2/mrvl_qos.h | 1 + 3 files changed, 57 insertions(+), 13 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index a03d39aee..d1bb4c35a 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -693,6 +693,10 @@ mrvl_dev_start(struct rte_eth_dev *dev) snprintf(match, sizeof(match), "ppio-%d:%d", priv->pp_id, priv->ppio_id); priv->ppio_params.match = match; + priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH; + if (mrvl_qos_cfg) + priv->ppio_params.eth_start_hdr = + mrvl_qos_cfg->port[dev->data->port_id].eth_start_hdr; /* * Calculate the minimum bpool size for refill feature as follows: diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index 7fd970309..976cb06a8 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -19,6 +19,10 @@ /* Parsing tokens. Defined conveniently, so that any correction is easy. */ #define MRVL_TOK_DEFAULT "default" +#define MRVL_TOK_DSA_MODE "dsa_mode" +#define MRVL_TOK_DSA_MODE_NONE "none" +#define MRVL_TOK_DSA_MODE_DSA "dsa" +#define MRVL_TOK_DSA_MODE_EXT_DSA "ext_dsa" #define MRVL_TOK_DEFAULT_TC "default_tc" #define MRVL_TOK_DSCP "dscp" #define MRVL_TOK_MAPPING_PRIORITY "mapping_priority" @@ -494,16 +498,19 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, const char *entry; char sec_name[32]; - if (file == NULL) - rte_exit(EXIT_FAILURE, "Cannot load configuration %s\n", path); + if (file == NULL) { + MRVL_LOG(ERR, "Cannot load configuration %s\n", path); + return -1; + } /* Create configuration. This is never accessed on the fast path, * so we can ignore socket. */ *cfg = rte_zmalloc("mrvl_qos_cfg", sizeof(struct mrvl_qos_cfg), 0); - if (*cfg == NULL) - rte_exit(EXIT_FAILURE, "Cannot allocate configuration %s\n", - path); + if (*cfg == NULL) { + MRVL_LOG(ERR, "Cannot allocate configuration %s\n", path); + return -1; + } n = rte_cfgfile_num_sections(file, MRVL_TOK_PORT, sizeof(MRVL_TOK_PORT) - 1); @@ -528,6 +535,31 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, continue; } + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_DSA_MODE); + if (entry) { + if (!strncmp(entry, MRVL_TOK_DSA_MODE_NONE, + sizeof(MRVL_TOK_DSA_MODE_NONE))) + (*cfg)->port[n].eth_start_hdr = + PP2_PPIO_HDR_ETH; + else if (!strncmp(entry, MRVL_TOK_DSA_MODE_DSA, + sizeof(MRVL_TOK_DSA_MODE_DSA))) + (*cfg)->port[n].eth_start_hdr = + PP2_PPIO_HDR_ETH_DSA; + else if (!strncmp(entry, MRVL_TOK_DSA_MODE_EXT_DSA, + sizeof(MRVL_TOK_DSA_MODE_EXT_DSA))) { + (*cfg)->port[n].eth_start_hdr = + PP2_PPIO_HDR_ETH_EXT_DSA; + } else { + MRVL_LOG(ERR, + "Error in parsing %s value (%s)!\n", + MRVL_TOK_DSA_MODE, entry); + return -1; + } + } else { + (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH; + } + /* * Read per-port rate limiting. Setting that will * disable per-queue rate limiting. @@ -575,13 +607,15 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, (*cfg)->port[n].mapping_priority = PP2_CLS_QOS_TBL_IP_PRI; else if (!strncmp(entry, MRVL_TOK_VLAN, - sizeof(MRVL_TOK_VLAN))) + sizeof(MRVL_TOK_VLAN))) { (*cfg)->port[n].mapping_priority = PP2_CLS_QOS_TBL_VLAN_PRI; - else - rte_exit(EXIT_FAILURE, + } else { + MRVL_LOG(ERR, "Error in parsing %s value (%s)!\n", MRVL_TOK_MAPPING_PRIORITY, entry); + return -1; + } } else { (*cfg)->port[n].mapping_priority = PP2_CLS_QOS_TBL_VLAN_IP_PRI; @@ -604,18 +638,22 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, for (i = 0; i < MRVL_PP2_RXQ_MAX; ++i) { ret = get_outq_cfg(file, n, i, *cfg); - if (ret < 0) - rte_exit(EXIT_FAILURE, + if (ret < 0) { + MRVL_LOG(ERR, "Error %d parsing port %d outq %d!\n", ret, n, i); + return -1; + } } for (i = 0; i < MRVL_PP2_TC_MAX; ++i) { ret = parse_tc_cfg(file, n, i, *cfg); - if (ret < 0) - rte_exit(EXIT_FAILURE, + if (ret < 0) { + MRVL_LOG(ERR, "Error %d parsing port %d tc %d!\n", ret, n, i); + return -1; + } } entry = rte_cfgfile_get_entry(file, sec_name, @@ -628,7 +666,8 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, } else { if ((*cfg)->port[n].use_global_defaults == 0) { MRVL_LOG(ERR, - "Default Traffic Class required in custom configuration!"); + "Default Traffic Class required in " + "custom configuration!"); return -1; } } diff --git a/drivers/net/mvpp2/mrvl_qos.h b/drivers/net/mvpp2/mrvl_qos.h index f03e7731c..0934752cf 100644 --- a/drivers/net/mvpp2/mrvl_qos.h +++ b/drivers/net/mvpp2/mrvl_qos.h @@ -20,6 +20,7 @@ /* QoS config. */ struct mrvl_qos_cfg { struct port_cfg { + enum pp2_ppio_eth_start_hdr eth_start_hdr; int rate_limit_enable; struct pp2_ppio_rate_limit_params rate_limit_params; struct { From patchwork Wed Dec 2 10:11:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84689 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 919CFA04DB; Wed, 2 Dec 2020 11:17:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2BAB4CA1E; Wed, 2 Dec 2020 11:12:55 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id CD7D1CA1E for ; Wed, 2 Dec 2020 11:12:53 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKqc024171 for ; Wed, 2 Dec 2020 02:12:52 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=U4C9JW9cVJNXhBDAozfPubHQfU5HhDf6a3SH4LElBxg=; b=TbOh6TltZ0oy8kbIgfCMlheFbHV1SXxPeO9CQINPSjy+6EIlH/m+CbrNq7vwYmpye669 LeyGhqt6fZ54MaegmOq3Uc51iS3OvbbymP6CxHersUyE6tQNZJLMYUHHwlRufbTYExL2 HKK7Zatf467wnZZCd0xpMffgZkJZEVcpnKxuQqugyDkg4cVUtf8DoeKfpHb3WqsM/eFz THPXsdnHhN/4Nd5Gi+2NksdrnSweyfSvKXx/zAnGVxtlXQMwXCl/aUq4RWZJ+rrWMck1 mYMd9+3CQFN1bkGtUENkL6/9ICM4iE1DmM7HrV8gtglVDMmLjLOWXNZt+VFMsJyEs8YV Qg== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r5h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:12:52 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:50 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:49 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:11:51 +0200 Message-ID: <20201202101212.4717-18-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 17/38] net/mvpp2: add TX flow control X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev add tx flow control operations. Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 59 ++++++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 8 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index d1bb4c35a..f80843c63 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2049,6 +2049,19 @@ mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE; + ret = pp2_ppio_get_tx_pause(priv->ppio, &en); + if (ret) { + MRVL_LOG(ERR, "Failed to read tx pause state"); + return ret; + } + + if (en) { + if (fc_conf->mode == RTE_FC_NONE) + fc_conf->mode = RTE_FC_TX_PAUSE; + else + fc_conf->mode = RTE_FC_FULL; + } + return 0; } @@ -2067,6 +2080,9 @@ static int mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) { struct mrvl_priv *priv = dev->data->dev_private; + struct pp2_ppio_tx_pause_params mrvl_pause_params; + int ret; + int rx_en, tx_en; if (!priv) return -EPERM; @@ -2081,16 +2097,43 @@ mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return -EINVAL; } - if (fc_conf->mode == RTE_FC_NONE || - fc_conf->mode == RTE_FC_RX_PAUSE) { - int ret, en; + switch (fc_conf->mode) { + case RTE_FC_FULL: + rx_en = 1; + tx_en = 1; + break; + case RTE_FC_TX_PAUSE: + rx_en = 0; + tx_en = 1; + break; + case RTE_FC_RX_PAUSE: + rx_en = 1; + tx_en = 0; + break; + case RTE_FC_NONE: + rx_en = 0; + tx_en = 0; + break; + default: + MRVL_LOG(ERR, "Incorrect Flow control flag (%d)", + fc_conf->mode); + return -EINVAL; + } - en = fc_conf->mode == RTE_FC_NONE ? 0 : 1; - ret = pp2_ppio_set_rx_pause(priv->ppio, en); - if (ret) - MRVL_LOG(ERR, - "Failed to change flowctrl on RX side"); + /* Set RX flow control */ + ret = pp2_ppio_set_rx_pause(priv->ppio, rx_en); + if (ret) { + MRVL_LOG(ERR, "Failed to change RX flowctrl"); + return ret; + } + /* Set TX flow control */ + mrvl_pause_params.en = tx_en; + /* all inqs participate in xon/xoff decision */ + mrvl_pause_params.use_tc_pause_inqs = 0; + ret = pp2_ppio_set_tx_pause(priv->ppio, &mrvl_pause_params); + if (ret) { + MRVL_LOG(ERR, "Failed to change TX flowctrl"); return ret; } From patchwork Wed Dec 2 10:11:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84691 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A078A04DB; Wed, 2 Dec 2020 11:18:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 033FDCABE; Wed, 2 Dec 2020 11:12:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 4A713CAA3 for ; Wed, 2 Dec 2020 11:12:54 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKgD024170 for ; Wed, 2 Dec 2020 02:12:53 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=exOAELenFlL31wtuSpdHE4KVTBYB3brI+k27BNgLYfE=; b=iDCFgJml2UmZDrBFg7r2m/5FEdHejzJ0GStTIrSPwxSh5fY/yB3qYqA9z/p5trnjzOi0 KSUOq32SF20jgXXq640OpaD1qtXbOniiMmmysUo8CPdzOBCE735LR+6hcDKqewswtF5w RvVETq8YAfC4vYq7E1HBcXBjXUaK8SCy4OvvT4WRBIkU6GO1RTPoREYfKR+bQ0+avkgc zBHDihuR1zBF27w9lJizOvPos+vDm9Pclx7auTV9Dzu5JfkHmqJb721EXZo9kuiQgjJS ylOhmkcb2GWnkNhlwQN8hkdNaLi2liX15B11AiZXBXTQ7hXwlSG23oOmedmlmiROK0YE ZQ== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r5j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:12:53 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:52 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:51 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:52 +0200 Message-ID: <20201202101212.4717-19-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 18/38] net/mvpp2: adjust the number of unicast address X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi HW support 25 mac address for filtering plus one for the primary mac address. Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index f80843c63..1be607b61 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -40,8 +40,10 @@ /* prefetch shift */ #define MRVL_MUSDK_PREFETCH_SHIFT 2 -/* TCAM has 25 entries reserved for uc/mc filter entries */ -#define MRVL_MAC_ADDRS_MAX 25 +/* TCAM has 25 entries reserved for uc/mc filter entries + * + 1 for primary mac address + */ +#define MRVL_MAC_ADDRS_MAX (1 + 25) #define MRVL_MATCH_LEN 16 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) /* Maximum allowable packet size */ From patchwork Wed Dec 2 10:11:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84692 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 471C1A04DB; Wed, 2 Dec 2020 11:18:56 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 62750CAC4; Wed, 2 Dec 2020 11:12:59 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id DEE02CAA7 for ; Wed, 2 Dec 2020 11:12:56 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A58Vn001876 for ; Wed, 2 Dec 2020 02:12:55 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=9hs/la9+LJp7v9826f3h8X2D1y63WeZOw/gBNaslWhY=; b=MhFSKmd5FBmY+3txi7h45Lv3htfilMRNFtHnS7C5GkPviKQx3EFiAnvavVavXz48XdfD PIXAYAus50t5SjEhyO62ZDKpmeEw2zHFXlcySoTWviORT0Rlpydujfru5SgLxScUp072 gEtWGckf1A7EoBKeW7lu69kbqrq1X2y/4uRUpETwCaqLc+TGnTyBTiJoHCknhp9FM+t+ Bc4HXguroUChikdlvW0TkeoxyRA0AkQ2/3YXNBM6i0WJGfMS2/FenozZcFe5USPOGZ3L QtZ8NVLg5sbg35bNoFZcJAvD0XK4qd/x/3DZ9Thh579UY1dEMTd/yOQILo41lR3i6K/k bg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3568jf8299-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:12:54 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:53 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:53 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:52 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:53 +0200 Message-ID: <20201202101212.4717-20-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 19/38] net/mvpp2: replace 'qos_cfg' with 'cfg' X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi as the config file is not just for 'qos' it is more accurate to replace the name from 'qos_cfg' to 'cfg' Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 12 ++++++------ drivers/net/mvpp2/mrvl_qos.c | 31 +++++++++++++++---------------- drivers/net/mvpp2/mrvl_qos.h | 13 ++++++------- 3 files changed, 27 insertions(+), 29 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 1be607b61..6bd3b0430 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -696,9 +696,9 @@ mrvl_dev_start(struct rte_eth_dev *dev) priv->pp_id, priv->ppio_id); priv->ppio_params.match = match; priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH; - if (mrvl_qos_cfg) + if (mrvl_cfg) priv->ppio_params.eth_start_hdr = - mrvl_qos_cfg->port[dev->data->port_id].eth_start_hdr; + mrvl_cfg->port[dev->data->port_id].eth_start_hdr; /* * Calculate the minimum bpool size for refill feature as follows: @@ -794,8 +794,8 @@ mrvl_dev_start(struct rte_eth_dev *dev) } /* For default QoS config, don't start classifier. */ - if (mrvl_qos_cfg && - mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) { + if (mrvl_cfg && + mrvl_cfg->port[dev->data->port_id].use_global_defaults == 0) { ret = mrvl_start_qos_mapping(priv); if (ret) { MRVL_LOG(ERR, "Failed to setup QoS mapping"); @@ -3237,7 +3237,7 @@ rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) * The below system initialization should be done only once, * on the first provided configuration file */ - if (!mrvl_qos_cfg) { + if (!mrvl_cfg) { cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); MRVL_LOG(INFO, "Parsing config file!"); if (cfgnum > 1) { @@ -3245,7 +3245,7 @@ rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) goto out_free_kvlist; } else if (cfgnum == 1) { rte_kvargs_process(kvlist, MRVL_CFG_ARG, - mrvl_get_qoscfg, &mrvl_qos_cfg); + mrvl_get_cfg, &mrvl_cfg); } } diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index 976cb06a8..18cf470dd 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -71,8 +71,8 @@ /** Maximum possible value of DSCP. */ #define MAX_DSCP 63 -/** Global QoS configuration. */ -struct mrvl_qos_cfg *mrvl_qos_cfg; +/** Global configuration. */ +struct mrvl_cfg *mrvl_cfg; /** * Convert string to uint32_t with extra checks for result correctness. @@ -104,12 +104,12 @@ get_val_securely(const char *string, uint32_t *val) * @param file Path to the configuration file. * @param port Port number. * @param outq Out queue number. - * @param cfg Pointer to the Marvell QoS configuration structure. + * @param cfg Pointer to the Marvell configuration structure. * @returns 0 in case of success, negative value otherwise. */ static int get_outq_cfg(struct rte_cfgfile *file, int port, int outq, - struct mrvl_qos_cfg *cfg) + struct mrvl_cfg *cfg) { char sec_name[32]; const char *entry; @@ -315,7 +315,7 @@ get_entry_values(const char *entry, uint8_t *tab, */ static int parse_tc_cfg(struct rte_cfgfile *file, int port, int tc, - struct mrvl_qos_cfg *cfg) + struct mrvl_cfg *cfg) { char sec_name[32]; const char *entry; @@ -409,7 +409,7 @@ parse_tc_cfg(struct rte_cfgfile *file, int port, int tc, */ static int parse_policer(struct rte_cfgfile *file, int port, const char *sec_name, - struct mrvl_qos_cfg *cfg) + struct mrvl_cfg *cfg) { const char *entry; uint32_t val; @@ -478,7 +478,7 @@ parse_policer(struct rte_cfgfile *file, int port, const char *sec_name, } /** - * Parse QoS configuration - rte_kvargs_process handler. + * Parse configuration - rte_kvargs_process handler. * * Opens configuration file and parses its content. * @@ -488,10 +488,9 @@ parse_policer(struct rte_cfgfile *file, int port, const char *sec_name, * @returns 0 in case of success, exits otherwise. */ int -mrvl_get_qoscfg(const char *key __rte_unused, const char *path, - void *extra_args) +mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) { - struct mrvl_qos_cfg **cfg = extra_args; + struct mrvl_cfg **cfg = extra_args; struct rte_cfgfile *file = rte_cfgfile_load(path, 0); uint32_t val; int n, i, ret; @@ -506,7 +505,7 @@ mrvl_get_qoscfg(const char *key __rte_unused, const char *path, /* Create configuration. This is never accessed on the fast path, * so we can ignore socket. */ - *cfg = rte_zmalloc("mrvl_qos_cfg", sizeof(struct mrvl_qos_cfg), 0); + *cfg = rte_zmalloc("mrvl_cfg", sizeof(struct mrvl_cfg), 0); if (*cfg == NULL) { MRVL_LOG(ERR, "Cannot allocate configuration %s\n", path); return -1; @@ -764,8 +763,8 @@ mrvl_configure_rxqs(struct mrvl_priv *priv, uint16_t portid, { size_t i, tc; - if (mrvl_qos_cfg == NULL || - mrvl_qos_cfg->port[portid].use_global_defaults) { + if (mrvl_cfg == NULL || + mrvl_cfg->port[portid].use_global_defaults) { /* * No port configuration, use default: 1 TC, no QoS, * TC color set to green. @@ -783,7 +782,7 @@ mrvl_configure_rxqs(struct mrvl_priv *priv, uint16_t portid, } /* We need only a subset of configuration. */ - struct port_cfg *port_cfg = &mrvl_qos_cfg->port[portid]; + struct port_cfg *port_cfg = &mrvl_cfg->port[portid]; priv->qos_tbl_params.type = port_cfg->mapping_priority; @@ -896,10 +895,10 @@ mrvl_configure_txqs(struct mrvl_priv *priv, uint16_t portid, uint16_t max_queues) { /* We need only a subset of configuration. */ - struct port_cfg *port_cfg = &mrvl_qos_cfg->port[portid]; + struct port_cfg *port_cfg = &mrvl_cfg->port[portid]; int i; - if (mrvl_qos_cfg == NULL) + if (mrvl_cfg == NULL) return 0; priv->ppio_params.rate_limit_enable = port_cfg->rate_limit_enable; diff --git a/drivers/net/mvpp2/mrvl_qos.h b/drivers/net/mvpp2/mrvl_qos.h index 0934752cf..928cfe366 100644 --- a/drivers/net/mvpp2/mrvl_qos.h +++ b/drivers/net/mvpp2/mrvl_qos.h @@ -17,8 +17,8 @@ /** Value used as "unknown". */ #define MRVL_UNKNOWN_TC (0xFF) -/* QoS config. */ -struct mrvl_qos_cfg { +/* config. */ +struct mrvl_cfg { struct port_cfg { enum pp2_ppio_eth_start_hdr eth_start_hdr; int rate_limit_enable; @@ -48,11 +48,11 @@ struct mrvl_qos_cfg { } port[RTE_MAX_ETHPORTS]; }; -/** Global QoS configuration. */ -extern struct mrvl_qos_cfg *mrvl_qos_cfg; +/** Global configuration. */ +extern struct mrvl_cfg *mrvl_cfg; /** - * Parse QoS configuration - rte_kvargs_process handler. + * Parse configuration - rte_kvargs_process handler. * * Opens configuration file and parses its content. * @@ -62,8 +62,7 @@ extern struct mrvl_qos_cfg *mrvl_qos_cfg; * @returns 0 in case of success, exits otherwise. */ int -mrvl_get_qoscfg(const char *key __rte_unused, const char *path, - void *extra_args); +mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args); /** * Configure RX Queues in a given port. From patchwork Wed Dec 2 10:11:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84694 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 206BEA04DB; Wed, 2 Dec 2020 11:19:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3A4DACAD0; Wed, 2 Dec 2020 11:13:05 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A4BCECAC9 for ; Wed, 2 Dec 2020 11:13:01 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKqe024171 for ; Wed, 2 Dec 2020 02:13:00 -0800 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r5s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:12:57 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:55 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:54 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:54 +0200 Message-ID: <20201202101212.4717-21-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 20/38] net/mvpp2: flow: support generic pattern combinations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi Currently only specific pattern combinations are supported. this makes it hard to support additional pattern. in addition there is no a real limitation that prevent any combination. This patch iterate the input patterns and convert them to a mvpp2 API. Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_flow.c | 1254 +++++---------------------------- 1 file changed, 158 insertions(+), 1096 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_flow.c b/drivers/net/mvpp2/mrvl_flow.c index ea4325528..a1a748529 100644 --- a/drivers/net/mvpp2/mrvl_flow.c +++ b/drivers/net/mvpp2/mrvl_flow.c @@ -20,185 +20,12 @@ /** Size of the classifier key and mask strings. */ #define MRVL_CLS_STR_SIZE_MAX 40 -static const enum rte_flow_item_type pattern_eth[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_vlan[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_vlan_ip[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_vlan_ip6[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_ip4[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_ip4_tcp[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_TCP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_ip4_udp[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_UDP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_ip6[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_ip6_tcp[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_TCP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_eth_ip6_udp[] = { - RTE_FLOW_ITEM_TYPE_ETH, - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_UDP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_vlan[] = { - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_vlan_ip[] = { - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_vlan_ip_tcp[] = { - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_TCP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_vlan_ip_udp[] = { - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_UDP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_vlan_ip6[] = { - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_vlan_ip6_tcp[] = { - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_TCP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_vlan_ip6_udp[] = { - RTE_FLOW_ITEM_TYPE_VLAN, - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_UDP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_ip[] = { - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_ip6[] = { - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_ip_tcp[] = { - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_TCP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_ip6_tcp[] = { - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_TCP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_ip_udp[] = { - RTE_FLOW_ITEM_TYPE_IPV4, - RTE_FLOW_ITEM_TYPE_UDP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_ip6_udp[] = { - RTE_FLOW_ITEM_TYPE_IPV6, - RTE_FLOW_ITEM_TYPE_UDP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_tcp[] = { - RTE_FLOW_ITEM_TYPE_TCP, - RTE_FLOW_ITEM_TYPE_END -}; - -static const enum rte_flow_item_type pattern_udp[] = { - RTE_FLOW_ITEM_TYPE_UDP, - RTE_FLOW_ITEM_TYPE_END -}; - #define MRVL_VLAN_ID_MASK 0x0fff #define MRVL_VLAN_PRI_MASK 0x7000 #define MRVL_IPV4_DSCP_MASK 0xfc #define MRVL_IPV4_ADDR_MASK 0xffffffff #define MRVL_IPV6_FLOW_MASK 0x0fffff -/** - * Given a flow item, return the next non-void one. - * - * @param items Pointer to the item in the table. - * @returns Next not-void item, NULL otherwise. - */ -static const struct rte_flow_item * -mrvl_next_item(const struct rte_flow_item *items) -{ - const struct rte_flow_item *item = items; - - for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { - if (item->type != RTE_FLOW_ITEM_TYPE_VOID) - return item; - } - - return NULL; -} - /** * Allocate memory for classifier rule key and mask fields. * @@ -361,9 +188,6 @@ mrvl_parse_mac(const struct rte_flow_item_eth *spec, struct pp2_cls_rule_key_field *key_field; const uint8_t *k, *m; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - if (parse_dst) { k = spec->dst.addr_bytes; m = mask->dst.addr_bytes; @@ -441,9 +265,6 @@ mrvl_parse_type(const struct rte_flow_item_eth *spec, struct pp2_cls_rule_key_field *key_field; uint16_t k; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 2; @@ -475,9 +296,6 @@ mrvl_parse_vlan_id(const struct rte_flow_item_vlan *spec, struct pp2_cls_rule_key_field *key_field; uint16_t k; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 2; @@ -509,9 +327,6 @@ mrvl_parse_vlan_pri(const struct rte_flow_item_vlan *spec, struct pp2_cls_rule_key_field *key_field; uint16_t k; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 1; @@ -543,9 +358,6 @@ mrvl_parse_ip4_dscp(const struct rte_flow_item_ipv4 *spec, struct pp2_cls_rule_key_field *key_field; uint8_t k, m; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 1; @@ -582,9 +394,6 @@ mrvl_parse_ip4_addr(const struct rte_flow_item_ipv4 *spec, struct in_addr k; uint32_t m; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - memset(&k, 0, sizeof(k)); if (parse_dst) { k.s_addr = spec->hdr.dst_addr; @@ -660,9 +469,6 @@ mrvl_parse_ip4_proto(const struct rte_flow_item_ipv4 *spec, struct pp2_cls_rule_key_field *key_field; uint8_t k = spec->hdr.next_proto_id; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 1; @@ -696,9 +502,6 @@ mrvl_parse_ip6_addr(const struct rte_flow_item_ipv6 *spec, int size = sizeof(spec->hdr.dst_addr); struct in6_addr k, m; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - memset(&k, 0, sizeof(k)); if (parse_dst) { memcpy(k.s6_addr, spec->hdr.dst_addr, size); @@ -775,9 +578,6 @@ mrvl_parse_ip6_flow(const struct rte_flow_item_ipv6 *spec, uint32_t k = rte_be_to_cpu_32(spec->hdr.vtc_flow) & MRVL_IPV6_FLOW_MASK, m = rte_be_to_cpu_32(mask->hdr.vtc_flow) & MRVL_IPV6_FLOW_MASK; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 3; @@ -809,9 +609,6 @@ mrvl_parse_ip6_next_hdr(const struct rte_flow_item_ipv6 *spec, struct pp2_cls_rule_key_field *key_field; uint8_t k = spec->hdr.proto; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 1; @@ -844,9 +641,6 @@ mrvl_parse_tcp_port(const struct rte_flow_item_tcp *spec, struct pp2_cls_rule_key_field *key_field; uint16_t k; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 2; @@ -920,9 +714,6 @@ mrvl_parse_udp_port(const struct rte_flow_item_udp *spec, struct pp2_cls_rule_key_field *key_field; uint16_t k; - if (flow->rule.num_fields >= PP2_CLS_TBL_MAX_NUM_FIELDS) - return -ENOSPC; - key_field = &flow->rule.fields[flow->rule.num_fields]; mrvl_alloc_key_mask(key_field); key_field->size = 2; @@ -1243,8 +1034,8 @@ mrvl_parse_tcp(const struct rte_flow_item *item, int ret; ret = mrvl_parse_init(item, (const void **)&spec, (const void **)&mask, - &rte_flow_item_ipv4_mask, - sizeof(struct rte_flow_item_ipv4), error); + &rte_flow_item_tcp_mask, + sizeof(struct rte_flow_item_tcp), error); if (ret) return ret; @@ -1298,8 +1089,8 @@ mrvl_parse_udp(const struct rte_flow_item *item, int ret; ret = mrvl_parse_init(item, (const void **)&spec, (const void **)&mask, - &rte_flow_item_ipv4_mask, - sizeof(struct rte_flow_item_ipv4), error); + &rte_flow_item_udp_mask, + sizeof(struct rte_flow_item_udp), error); if (ret) return ret; @@ -1332,923 +1123,196 @@ mrvl_parse_udp(const struct rte_flow_item *item, } /** - * Parse flow pattern composed of the the eth item. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. + * Structure used to map specific flow pattern to the pattern parse callback + * which will iterate over each pattern item and extract relevant data. */ -static int -mrvl_parse_pattern_eth(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_eth(pattern, flow, error); -} +static const struct { + const enum rte_flow_item_type pattern_type; + int (*parse)(const struct rte_flow_item *pattern, + struct rte_flow *flow, + struct rte_flow_error *error); +} mrvl_patterns[] = { + { RTE_FLOW_ITEM_TYPE_ETH, mrvl_parse_eth }, + { RTE_FLOW_ITEM_TYPE_VLAN, mrvl_parse_vlan }, + { RTE_FLOW_ITEM_TYPE_IPV4, mrvl_parse_ip4 }, + { RTE_FLOW_ITEM_TYPE_IPV6, mrvl_parse_ip6 }, + { RTE_FLOW_ITEM_TYPE_TCP, mrvl_parse_tcp }, + { RTE_FLOW_ITEM_TYPE_UDP, mrvl_parse_udp }, + { RTE_FLOW_ITEM_TYPE_END, NULL } +}; /** - * Parse flow pattern composed of the eth and vlan items. + * Parse flow attribute. * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. + * This will check whether the provided attribute's flags are supported. + * + * @param priv Unused + * @param attr Pointer to the flow attribute. + * @param flow Unused * @param error Pointer to the flow error. * @returns 0 in case of success, negative value otherwise. */ static int -mrvl_parse_pattern_eth_vlan(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) +mrvl_flow_parse_attr(struct mrvl_priv *priv __rte_unused, + const struct rte_flow_attr *attr, + struct rte_flow *flow __rte_unused, + struct rte_flow_error *error) { - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = mrvl_parse_eth(item, flow, error); - if (ret) - return ret; + if (!attr) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, + NULL, "NULL attribute"); + return -rte_errno; + } - item = mrvl_next_item(item + 1); + if (attr->group) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, + "Groups are not supported"); + return -rte_errno; + } + if (attr->priority) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, NULL, + "Priorities are not supported"); + return -rte_errno; + } + if (!attr->ingress) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, NULL, + "Only ingress is supported"); + return -rte_errno; + } + if (attr->egress) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, + "Egress is not supported"); + return -rte_errno; + } + if (attr->transfer) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL, + "Transfer is not supported"); + return -rte_errno; + } - return mrvl_parse_vlan(item, flow, error); + return 0; } /** - * Parse flow pattern composed of the eth, vlan and ip4/ip6 items. + * Parse flow pattern. + * + * Specific classifier rule will be created as well. * - * @param pattern Pointer to the flow pattern table. + * @param priv Unused + * @param pattern Pointer to the flow pattern. * @param flow Pointer to the flow. * @param error Pointer to the flow error. - * @param ip6 1 to parse ip6 item, 0 to parse ip4 item. * @returns 0 in case of success, negative value otherwise. */ static int -mrvl_parse_pattern_eth_vlan_ip4_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int ip6) +mrvl_flow_parse_pattern(struct mrvl_priv *priv __rte_unused, + const struct rte_flow_item pattern[], + struct rte_flow *flow, + struct rte_flow_error *error) { - const struct rte_flow_item *item = mrvl_next_item(pattern); + unsigned int i, j; int ret; - ret = mrvl_parse_eth(item, flow, error); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - ret = mrvl_parse_vlan(item, flow, error); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); + for (i = 0; pattern[i].type != RTE_FLOW_ITEM_TYPE_END; i++) { + if (pattern[i].type == RTE_FLOW_ITEM_TYPE_VOID) + continue; + for (j = 0; mrvl_patterns[j].pattern_type != + RTE_FLOW_ITEM_TYPE_END; j++) { + if (mrvl_patterns[j].pattern_type != pattern[i].type) + continue; + + if (flow->rule.num_fields >= + PP2_CLS_TBL_MAX_NUM_FIELDS) { + rte_flow_error_set(error, ENOSPC, + RTE_FLOW_ERROR_TYPE_ITEM_NUM, + NULL, + "too many pattern (max %d)"); + return -rte_errno; + } - return ip6 ? mrvl_parse_ip6(item, flow, error) : - mrvl_parse_ip4(item, flow, error); -} + ret = mrvl_patterns[j].parse(&pattern[i], flow, error); + if (ret) { + mrvl_free_all_key_mask(&flow->rule); + return ret; + } + break; + } + if (mrvl_patterns[j].pattern_type == RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Unsupported pattern"); + return -rte_errno; + } + } -/** - * Parse flow pattern composed of the eth, vlan and ipv4 items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_eth_vlan_ip4(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_eth_vlan_ip4_ip6(pattern, flow, error, 0); + return 0; } /** - * Parse flow pattern composed of the eth, vlan and ipv6 items. + * Parse flow actions. * - * @param pattern Pointer to the flow pattern table. + * @param priv Pointer to the port's private data. + * @param actions Pointer the action table. * @param flow Pointer to the flow. * @param error Pointer to the flow error. * @returns 0 in case of success, negative value otherwise. */ static int -mrvl_parse_pattern_eth_vlan_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) +mrvl_flow_parse_actions(struct mrvl_priv *priv, + const struct rte_flow_action actions[], + struct rte_flow *flow, + struct rte_flow_error *error) { - return mrvl_parse_pattern_eth_vlan_ip4_ip6(pattern, flow, error, 1); -} + const struct rte_flow_action *action = actions; + int specified = 0; -/** - * Parse flow pattern composed of the eth and ip4/ip6 items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @param ip6 1 to parse ip6 item, 0 to parse ip4 item. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_eth_ip4_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int ip6) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; + for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { + if (action->type == RTE_FLOW_ACTION_TYPE_VOID) + continue; - ret = mrvl_parse_eth(item, flow, error); - if (ret) - return ret; + if (action->type == RTE_FLOW_ACTION_TYPE_DROP) { + flow->cos.ppio = priv->ppio; + flow->cos.tc = 0; + flow->action.type = PP2_CLS_TBL_ACT_DROP; + flow->action.cos = &flow->cos; + specified++; + } else if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) { + const struct rte_flow_action_queue *q = + (const struct rte_flow_action_queue *) + action->conf; - item = mrvl_next_item(item + 1); + if (q->index > priv->nb_rx_queues) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, + "Queue index out of range"); + return -rte_errno; + } - return ip6 ? mrvl_parse_ip6(item, flow, error) : - mrvl_parse_ip4(item, flow, error); -} + if (priv->rxq_map[q->index].tc == MRVL_UNKNOWN_TC) { + /* + * Unknown TC mapping, mapping will not have + * a correct queue. + */ + MRVL_LOG(ERR, + "Unknown TC mapping for queue %hu eth%hhu", + q->index, priv->ppio_id); -/** - * Parse flow pattern composed of the eth and ipv4 items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_eth_ip4(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_eth_ip4_ip6(pattern, flow, error, 0); -} + rte_flow_error_set(error, EFAULT, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, NULL); + return -rte_errno; + } -/** - * Parse flow pattern composed of the eth and ipv6 items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_eth_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_eth_ip4_ip6(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the eth, ip4 and tcp/udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @param tcp 1 to parse tcp item, 0 to parse udp item. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_eth_ip4_tcp_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int tcp) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = mrvl_parse_pattern_eth_ip4_ip6(pattern, flow, error, 0); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - item = mrvl_next_item(item + 1); - - if (tcp) - return mrvl_parse_tcp(item, flow, error); - - return mrvl_parse_udp(item, flow, error); -} - -/** - * Parse flow pattern composed of the eth, ipv4 and tcp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_eth_ip4_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_eth_ip4_tcp_udp(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the eth, ipv4 and udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_eth_ip4_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_eth_ip4_tcp_udp(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the eth, ipv6 and tcp/udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @param tcp 1 to parse tcp item, 0 to parse udp item. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_eth_ip6_tcp_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int tcp) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = mrvl_parse_pattern_eth_ip4_ip6(pattern, flow, error, 1); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - item = mrvl_next_item(item + 1); - - if (tcp) - return mrvl_parse_tcp(item, flow, error); - - return mrvl_parse_udp(item, flow, error); -} - -/** - * Parse flow pattern composed of the eth, ipv6 and tcp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_eth_ip6_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_eth_ip6_tcp_udp(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the eth, ipv6 and udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_eth_ip6_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_eth_ip6_tcp_udp(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the vlan item. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_vlan(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - - return mrvl_parse_vlan(item, flow, error); -} - -/** - * Parse flow pattern composed of the vlan and ip4/ip6 items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @param ip6 1 to parse ip6 item, 0 to parse ip4 item. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_vlan_ip4_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int ip6) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = mrvl_parse_vlan(item, flow, error); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - - return ip6 ? mrvl_parse_ip6(item, flow, error) : - mrvl_parse_ip4(item, flow, error); -} - -/** - * Parse flow pattern composed of the vlan and ipv4 items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_vlan_ip4(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_vlan_ip4_ip6(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the vlan, ipv4 and tcp/udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_vlan_ip_tcp_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int tcp) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = mrvl_parse_pattern_vlan_ip4_ip6(pattern, flow, error, 0); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - item = mrvl_next_item(item + 1); - - if (tcp) - return mrvl_parse_tcp(item, flow, error); - - return mrvl_parse_udp(item, flow, error); -} - -/** - * Parse flow pattern composed of the vlan, ipv4 and tcp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_vlan_ip_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_vlan_ip_tcp_udp(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the vlan, ipv4 and udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_vlan_ip_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_vlan_ip_tcp_udp(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the vlan and ipv6 items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_vlan_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_vlan_ip4_ip6(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the vlan, ipv6 and tcp/udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_vlan_ip6_tcp_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int tcp) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = mrvl_parse_pattern_vlan_ip4_ip6(pattern, flow, error, 1); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - item = mrvl_next_item(item + 1); - - if (tcp) - return mrvl_parse_tcp(item, flow, error); - - return mrvl_parse_udp(item, flow, error); -} - -/** - * Parse flow pattern composed of the vlan, ipv6 and tcp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_vlan_ip6_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_vlan_ip6_tcp_udp(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the vlan, ipv6 and udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_vlan_ip6_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_vlan_ip6_tcp_udp(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the ip4/ip6 item. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @param ip6 1 to parse ip6 item, 0 to parse ip4 item. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_ip4_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int ip6) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - - return ip6 ? mrvl_parse_ip6(item, flow, error) : - mrvl_parse_ip4(item, flow, error); -} - -/** - * Parse flow pattern composed of the ipv4 item. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_ip4(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_ip4_ip6(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the ipv6 item. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_ip6(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_ip4_ip6(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the ip4/ip6 and tcp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @param ip6 1 to parse ip6 item, 0 to parse ip4 item. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_ip4_ip6_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int ip6) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = ip6 ? mrvl_parse_ip6(item, flow, error) : - mrvl_parse_ip4(item, flow, error); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - - return mrvl_parse_tcp(item, flow, error); -} - -/** - * Parse flow pattern composed of the ipv4 and tcp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_ip4_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_ip4_ip6_tcp(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the ipv6 and tcp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_ip6_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_ip4_ip6_tcp(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the ipv4/ipv6 and udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @param ip6 1 to parse ip6 item, 0 to parse ip4 item. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_ip4_ip6_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error, int ip6) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - int ret; - - ret = ip6 ? mrvl_parse_ip6(item, flow, error) : - mrvl_parse_ip4(item, flow, error); - if (ret) - return ret; - - item = mrvl_next_item(item + 1); - - return mrvl_parse_udp(item, flow, error); -} - -/** - * Parse flow pattern composed of the ipv4 and udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_ip4_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_ip4_ip6_udp(pattern, flow, error, 0); -} - -/** - * Parse flow pattern composed of the ipv6 and udp items. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static inline int -mrvl_parse_pattern_ip6_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - return mrvl_parse_pattern_ip4_ip6_udp(pattern, flow, error, 1); -} - -/** - * Parse flow pattern composed of the tcp item. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_tcp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - - return mrvl_parse_tcp(item, flow, error); -} - -/** - * Parse flow pattern composed of the udp item. - * - * @param pattern Pointer to the flow pattern table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_parse_pattern_udp(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - const struct rte_flow_item *item = mrvl_next_item(pattern); - - return mrvl_parse_udp(item, flow, error); -} - -/** - * Structure used to map specific flow pattern to the pattern parse callback - * which will iterate over each pattern item and extract relevant data. - */ -static const struct { - const enum rte_flow_item_type *pattern; - int (*parse)(const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error); -} mrvl_patterns[] = { - { pattern_eth, mrvl_parse_pattern_eth }, - { pattern_eth_vlan, mrvl_parse_pattern_eth_vlan }, - { pattern_eth_vlan_ip, mrvl_parse_pattern_eth_vlan_ip4 }, - { pattern_eth_vlan_ip6, mrvl_parse_pattern_eth_vlan_ip6 }, - { pattern_eth_ip4, mrvl_parse_pattern_eth_ip4 }, - { pattern_eth_ip4_tcp, mrvl_parse_pattern_eth_ip4_tcp }, - { pattern_eth_ip4_udp, mrvl_parse_pattern_eth_ip4_udp }, - { pattern_eth_ip6, mrvl_parse_pattern_eth_ip6 }, - { pattern_eth_ip6_tcp, mrvl_parse_pattern_eth_ip6_tcp }, - { pattern_eth_ip6_udp, mrvl_parse_pattern_eth_ip6_udp }, - { pattern_vlan, mrvl_parse_pattern_vlan }, - { pattern_vlan_ip, mrvl_parse_pattern_vlan_ip4 }, - { pattern_vlan_ip_tcp, mrvl_parse_pattern_vlan_ip_tcp }, - { pattern_vlan_ip_udp, mrvl_parse_pattern_vlan_ip_udp }, - { pattern_vlan_ip6, mrvl_parse_pattern_vlan_ip6 }, - { pattern_vlan_ip6_tcp, mrvl_parse_pattern_vlan_ip6_tcp }, - { pattern_vlan_ip6_udp, mrvl_parse_pattern_vlan_ip6_udp }, - { pattern_ip, mrvl_parse_pattern_ip4 }, - { pattern_ip_tcp, mrvl_parse_pattern_ip4_tcp }, - { pattern_ip_udp, mrvl_parse_pattern_ip4_udp }, - { pattern_ip6, mrvl_parse_pattern_ip6 }, - { pattern_ip6_tcp, mrvl_parse_pattern_ip6_tcp }, - { pattern_ip6_udp, mrvl_parse_pattern_ip6_udp }, - { pattern_tcp, mrvl_parse_pattern_tcp }, - { pattern_udp, mrvl_parse_pattern_udp } -}; - -/** - * Check whether provided pattern matches any of the supported ones. - * - * @param type_pattern Pointer to the pattern type. - * @param item_pattern Pointer to the flow pattern. - * @returns 1 in case of success, 0 value otherwise. - */ -static int -mrvl_patterns_match(const enum rte_flow_item_type *type_pattern, - const struct rte_flow_item *item_pattern) -{ - const enum rte_flow_item_type *type = type_pattern; - const struct rte_flow_item *item = item_pattern; - - for (;;) { - if (item->type == RTE_FLOW_ITEM_TYPE_VOID) { - item++; - continue; - } - - if (*type == RTE_FLOW_ITEM_TYPE_END || - item->type == RTE_FLOW_ITEM_TYPE_END) - break; - - if (*type != item->type) - break; - - item++; - type++; - } - - return *type == item->type; -} - -/** - * Parse flow attribute. - * - * This will check whether the provided attribute's flags are supported. - * - * @param priv Unused - * @param attr Pointer to the flow attribute. - * @param flow Unused - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_flow_parse_attr(struct mrvl_priv *priv __rte_unused, - const struct rte_flow_attr *attr, - struct rte_flow *flow __rte_unused, - struct rte_flow_error *error) -{ - if (!attr) { - rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ATTR, - NULL, "NULL attribute"); - return -rte_errno; - } - - if (attr->group) { - rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, - "Groups are not supported"); - return -rte_errno; - } - if (attr->priority) { - rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, NULL, - "Priorities are not supported"); - return -rte_errno; - } - if (!attr->ingress) { - rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, NULL, - "Only ingress is supported"); - return -rte_errno; - } - if (attr->egress) { - rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, - "Egress is not supported"); - return -rte_errno; - } - if (attr->transfer) { - rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, NULL, - "Transfer is not supported"); - return -rte_errno; - } - - return 0; -} - -/** - * Parse flow pattern. - * - * Specific classifier rule will be created as well. - * - * @param priv Unused - * @param pattern Pointer to the flow pattern. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_flow_parse_pattern(struct mrvl_priv *priv __rte_unused, - const struct rte_flow_item pattern[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - unsigned int i; - int ret; - - for (i = 0; i < RTE_DIM(mrvl_patterns); i++) { - if (!mrvl_patterns_match(mrvl_patterns[i].pattern, pattern)) - continue; - - ret = mrvl_patterns[i].parse(pattern, flow, error); - if (ret) - mrvl_free_all_key_mask(&flow->rule); - - return ret; - } - - rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "Unsupported pattern"); - - return -rte_errno; -} - -/** - * Parse flow actions. - * - * @param priv Pointer to the port's private data. - * @param actions Pointer the action table. - * @param flow Pointer to the flow. - * @param error Pointer to the flow error. - * @returns 0 in case of success, negative value otherwise. - */ -static int -mrvl_flow_parse_actions(struct mrvl_priv *priv, - const struct rte_flow_action actions[], - struct rte_flow *flow, - struct rte_flow_error *error) -{ - const struct rte_flow_action *action = actions; - int specified = 0; - - for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { - if (action->type == RTE_FLOW_ACTION_TYPE_VOID) - continue; - - if (action->type == RTE_FLOW_ACTION_TYPE_DROP) { - flow->cos.ppio = priv->ppio; - flow->cos.tc = 0; - flow->action.type = PP2_CLS_TBL_ACT_DROP; - flow->action.cos = &flow->cos; - specified++; - } else if (action->type == RTE_FLOW_ACTION_TYPE_QUEUE) { - const struct rte_flow_action_queue *q = - (const struct rte_flow_action_queue *) - action->conf; - - if (q->index > priv->nb_rx_queues) { - rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ACTION, - NULL, - "Queue index out of range"); - return -rte_errno; - } - - if (priv->rxq_map[q->index].tc == MRVL_UNKNOWN_TC) { - /* - * Unknown TC mapping, mapping will not have - * a correct queue. - */ - MRVL_LOG(ERR, - "Unknown TC mapping for queue %hu eth%hhu", - q->index, priv->ppio_id); - - rte_flow_error_set(error, EFAULT, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, NULL); - return -rte_errno; - } - - MRVL_LOG(DEBUG, - "Action: Assign packets to queue %d, tc:%d, q:%d", - q->index, priv->rxq_map[q->index].tc, - priv->rxq_map[q->index].inq); + MRVL_LOG(DEBUG, + "Action: Assign packets to queue %d, tc:%d, q:%d", + q->index, priv->rxq_map[q->index].tc, + priv->rxq_map[q->index].inq); flow->cos.ppio = priv->ppio; flow->cos.tc = priv->rxq_map[q->index].tc; @@ -2755,6 +1819,11 @@ mrvl_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error) rte_free(flow); } + if (priv->cls_tbl) { + pp2_cls_tbl_deinit(priv->cls_tbl); + priv->cls_tbl = NULL; + } + return 0; } @@ -2813,12 +1882,5 @@ mrvl_flow_init(struct rte_eth_dev *dev) void mrvl_flow_deinit(struct rte_eth_dev *dev) { - struct mrvl_priv *priv = dev->data->dev_private; - mrvl_flow_flush(dev, NULL); - - if (priv->cls_tbl) { - pp2_cls_tbl_deinit(priv->cls_tbl); - priv->cls_tbl = NULL; - } } From patchwork Wed Dec 2 10:11:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84693 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 138DEA04DB; Wed, 2 Dec 2020 11:19:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A2237CAC9; Wed, 2 Dec 2020 11:13:03 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id BCEF6CACA for ; Wed, 2 Dec 2020 11:13:00 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2ABMlW025655 for ; Wed, 2 Dec 2020 02:13:00 -0800 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r5w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:00 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:57 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:56 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:55 +0200 Message-ID: <20201202101212.4717-22-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 21/38] net/mvpp2: flow: build table key along with rule X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi build table key along with rule Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.h | 33 +--- drivers/net/mvpp2/mrvl_flow.c | 257 +++++++++++++------------------- 2 files changed, 106 insertions(+), 184 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index db6632f5b..e7f75067f 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -82,43 +82,13 @@ /** Maximum length of a match string */ #define MRVL_MATCH_LEN 16 -/** Parsed fields in processed rte_flow_item. */ -enum mrvl_parsed_fields { - /* eth flags */ - F_DMAC = BIT(0), - F_SMAC = BIT(1), - F_TYPE = BIT(2), - /* vlan flags */ - F_VLAN_PRI = BIT(3), - F_VLAN_ID = BIT(4), - F_VLAN_TCI = BIT(5), /* not supported by MUSDK yet */ - /* ip4 flags */ - F_IP4_TOS = BIT(6), - F_IP4_SIP = BIT(7), - F_IP4_DIP = BIT(8), - F_IP4_PROTO = BIT(9), - /* ip6 flags */ - F_IP6_TC = BIT(10), /* not supported by MUSDK yet */ - F_IP6_SIP = BIT(11), - F_IP6_DIP = BIT(12), - F_IP6_FLOW = BIT(13), - F_IP6_NEXT_HDR = BIT(14), - /* tcp flags */ - F_TCP_SPORT = BIT(15), - F_TCP_DPORT = BIT(16), - /* udp flags */ - F_UDP_SPORT = BIT(17), - F_UDP_DPORT = BIT(18), -}; - /** PMD-specific definition of a flow rule handle. */ struct mrvl_mtr; struct rte_flow { LIST_ENTRY(rte_flow) next; struct mrvl_mtr *mtr; - enum mrvl_parsed_fields pattern; - + struct pp2_cls_tbl_key table_key; struct pp2_cls_tbl_rule rule; struct pp2_cls_cos_desc cos; struct pp2_cls_tbl_action action; @@ -197,7 +167,6 @@ struct mrvl_priv { struct pp2_cls_tbl_params cls_tbl_params; struct pp2_cls_tbl *cls_tbl; - uint32_t cls_tbl_pattern; LIST_HEAD(mrvl_flows, rte_flow) flows; struct pp2_cls_plcr *default_policer; diff --git a/drivers/net/mvpp2/mrvl_flow.c b/drivers/net/mvpp2/mrvl_flow.c index a1a748529..ffa47a12e 100644 --- a/drivers/net/mvpp2/mrvl_flow.c +++ b/drivers/net/mvpp2/mrvl_flow.c @@ -192,12 +192,14 @@ mrvl_parse_mac(const struct rte_flow_item_eth *spec, k = spec->dst.addr_bytes; m = mask->dst.addr_bytes; - flow->pattern |= F_DMAC; + flow->table_key.proto_field[flow->rule.num_fields].field.eth = + MV_NET_ETH_F_DA; } else { k = spec->src.addr_bytes; m = mask->src.addr_bytes; - flow->pattern |= F_SMAC; + flow->table_key.proto_field[flow->rule.num_fields].field.eth = + MV_NET_ETH_F_SA; } key_field = &flow->rule.fields[flow->rule.num_fields]; @@ -212,6 +214,10 @@ mrvl_parse_mac(const struct rte_flow_item_eth *spec, "%02x:%02x:%02x:%02x:%02x:%02x", m[0], m[1], m[2], m[3], m[4], m[5]); + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_ETH; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -272,7 +278,12 @@ mrvl_parse_type(const struct rte_flow_item_eth *spec, k = rte_be_to_cpu_16(spec->type); snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); - flow->pattern |= F_TYPE; + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_ETH; + flow->table_key.proto_field[flow->rule.num_fields].field.eth = + MV_NET_ETH_F_TYPE; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -303,7 +314,12 @@ mrvl_parse_vlan_id(const struct rte_flow_item_vlan *spec, k = rte_be_to_cpu_16(spec->tci) & MRVL_VLAN_ID_MASK; snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); - flow->pattern |= F_VLAN_ID; + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_VLAN; + flow->table_key.proto_field[flow->rule.num_fields].field.vlan = + MV_NET_VLAN_F_ID; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -334,7 +350,12 @@ mrvl_parse_vlan_pri(const struct rte_flow_item_vlan *spec, k = (rte_be_to_cpu_16(spec->tci) & MRVL_VLAN_PRI_MASK) >> 13; snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); - flow->pattern |= F_VLAN_PRI; + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_VLAN; + flow->table_key.proto_field[flow->rule.num_fields].field.vlan = + MV_NET_VLAN_F_PRI; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -367,7 +388,12 @@ mrvl_parse_ip4_dscp(const struct rte_flow_item_ipv4 *spec, snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); snprintf((char *)key_field->mask, MRVL_CLS_STR_SIZE_MAX, "%u", m); - flow->pattern |= F_IP4_TOS; + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_IP4; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv4 = + MV_NET_IP4_F_DSCP; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -399,12 +425,14 @@ mrvl_parse_ip4_addr(const struct rte_flow_item_ipv4 *spec, k.s_addr = spec->hdr.dst_addr; m = rte_be_to_cpu_32(mask->hdr.dst_addr); - flow->pattern |= F_IP4_DIP; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv4 = + MV_NET_IP4_F_DA; } else { k.s_addr = spec->hdr.src_addr; m = rte_be_to_cpu_32(mask->hdr.src_addr); - flow->pattern |= F_IP4_SIP; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv4 = + MV_NET_IP4_F_SA; } key_field = &flow->rule.fields[flow->rule.num_fields]; @@ -414,6 +442,10 @@ mrvl_parse_ip4_addr(const struct rte_flow_item_ipv4 *spec, inet_ntop(AF_INET, &k, (char *)key_field->key, MRVL_CLS_STR_SIZE_MAX); snprintf((char *)key_field->mask, MRVL_CLS_STR_SIZE_MAX, "0x%x", m); + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_IP4; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -475,7 +507,12 @@ mrvl_parse_ip4_proto(const struct rte_flow_item_ipv4 *spec, snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); - flow->pattern |= F_IP4_PROTO; + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_IP4; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv4 = + MV_NET_IP4_F_PROTO; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -507,12 +544,14 @@ mrvl_parse_ip6_addr(const struct rte_flow_item_ipv6 *spec, memcpy(k.s6_addr, spec->hdr.dst_addr, size); memcpy(m.s6_addr, mask->hdr.dst_addr, size); - flow->pattern |= F_IP6_DIP; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv6 = + MV_NET_IP6_F_DA; } else { memcpy(k.s6_addr, spec->hdr.src_addr, size); memcpy(m.s6_addr, mask->hdr.src_addr, size); - flow->pattern |= F_IP6_SIP; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv6 = + MV_NET_IP6_F_SA; } key_field = &flow->rule.fields[flow->rule.num_fields]; @@ -522,6 +561,10 @@ mrvl_parse_ip6_addr(const struct rte_flow_item_ipv6 *spec, inet_ntop(AF_INET6, &k, (char *)key_field->key, MRVL_CLS_STR_SIZE_MAX); inet_ntop(AF_INET6, &m, (char *)key_field->mask, MRVL_CLS_STR_SIZE_MAX); + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_IP6; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -585,7 +628,12 @@ mrvl_parse_ip6_flow(const struct rte_flow_item_ipv6 *spec, snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); snprintf((char *)key_field->mask, MRVL_CLS_STR_SIZE_MAX, "%u", m); - flow->pattern |= F_IP6_FLOW; + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_IP6; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv6 = + MV_NET_IP6_F_FLOW; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -615,7 +663,12 @@ mrvl_parse_ip6_next_hdr(const struct rte_flow_item_ipv6 *spec, snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); - flow->pattern |= F_IP6_NEXT_HDR; + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_IP6; + flow->table_key.proto_field[flow->rule.num_fields].field.ipv6 = + MV_NET_IP6_F_NEXT_HDR; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -648,15 +701,21 @@ mrvl_parse_tcp_port(const struct rte_flow_item_tcp *spec, if (parse_dst) { k = rte_be_to_cpu_16(spec->hdr.dst_port); - flow->pattern |= F_TCP_DPORT; + flow->table_key.proto_field[flow->rule.num_fields].field.tcp = + MV_NET_TCP_F_DP; } else { k = rte_be_to_cpu_16(spec->hdr.src_port); - flow->pattern |= F_TCP_SPORT; + flow->table_key.proto_field[flow->rule.num_fields].field.tcp = + MV_NET_TCP_F_SP; } snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_TCP; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -721,15 +780,21 @@ mrvl_parse_udp_port(const struct rte_flow_item_udp *spec, if (parse_dst) { k = rte_be_to_cpu_16(spec->hdr.dst_port); - flow->pattern |= F_UDP_DPORT; + flow->table_key.proto_field[flow->rule.num_fields].field.udp = + MV_NET_UDP_F_DP; } else { k = rte_be_to_cpu_16(spec->hdr.src_port); - flow->pattern |= F_UDP_SPORT; + flow->table_key.proto_field[flow->rule.num_fields].field.udp = + MV_NET_UDP_F_SP; } snprintf((char *)key_field->key, MRVL_CLS_STR_SIZE_MAX, "%u", k); + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_PROTO_UDP; + flow->table_key.key_size += key_field->size; + flow->rule.num_fields += 1; return 0; @@ -832,7 +897,7 @@ mrvl_parse_vlan(const struct rte_flow_item *item, { const struct rte_flow_item_vlan *spec = NULL, *mask = NULL; uint16_t m; - int ret; + int ret, i; ret = mrvl_parse_init(item, (const void **)&spec, (const void **)&mask, &rte_flow_item_vlan_mask, @@ -855,12 +920,6 @@ mrvl_parse_vlan(const struct rte_flow_item *item, goto out; } - if (flow->pattern & F_TYPE) { - rte_flow_error_set(error, ENOTSUP, - RTE_FLOW_ERROR_TYPE_ITEM, item, - "VLAN TPID matching is not supported"); - return -rte_errno; - } if (mask->inner_type) { struct rte_flow_item_eth spec_eth = { .type = spec->inner_type, @@ -869,6 +928,21 @@ mrvl_parse_vlan(const struct rte_flow_item *item, .type = mask->inner_type, }; + /* TPID is not supported so if ETH_TYPE was selected, + * error is return. else, classify eth-type with the tpid value + */ + for (i = 0; i < flow->rule.num_fields; i++) + if (flow->table_key.proto_field[i].proto == + MV_NET_PROTO_ETH && + flow->table_key.proto_field[i].field.eth == + MV_NET_ETH_F_TYPE) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + item, + "VLAN TPID matching is not supported"); + return -rte_errno; + } + MRVL_LOG(WARNING, "inner eth type mask is ignored"); ret = mrvl_parse_type(&spec_eth, &mask_eth, flow); if (ret) @@ -1250,6 +1324,8 @@ mrvl_flow_parse_pattern(struct mrvl_priv *priv __rte_unused, } } + flow->table_key.num_fields = flow->rule.num_fields; + return 0; } @@ -1462,134 +1538,9 @@ mrvl_create_cls_table(struct rte_eth_dev *dev, struct rte_flow *first_flow) priv->cls_tbl_params.max_num_rules = MRVL_CLS_MAX_NUM_RULES; priv->cls_tbl_params.default_act.type = PP2_CLS_TBL_ACT_DONE; priv->cls_tbl_params.default_act.cos = &first_flow->cos; - - if (first_flow->pattern & F_DMAC) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_ETH; - key->proto_field[key->num_fields].field.eth = MV_NET_ETH_F_DA; - key->key_size += 6; - key->num_fields += 1; - } - - if (first_flow->pattern & F_SMAC) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_ETH; - key->proto_field[key->num_fields].field.eth = MV_NET_ETH_F_SA; - key->key_size += 6; - key->num_fields += 1; - } - - if (first_flow->pattern & F_TYPE) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_ETH; - key->proto_field[key->num_fields].field.eth = MV_NET_ETH_F_TYPE; - key->key_size += 2; - key->num_fields += 1; - } - - if (first_flow->pattern & F_VLAN_ID) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_VLAN; - key->proto_field[key->num_fields].field.vlan = MV_NET_VLAN_F_ID; - key->key_size += 2; - key->num_fields += 1; - } - - if (first_flow->pattern & F_VLAN_PRI) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_VLAN; - key->proto_field[key->num_fields].field.vlan = - MV_NET_VLAN_F_PRI; - key->key_size += 1; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP4_TOS) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP4; - key->proto_field[key->num_fields].field.ipv4 = - MV_NET_IP4_F_DSCP; - key->key_size += 1; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP4_SIP) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP4; - key->proto_field[key->num_fields].field.ipv4 = MV_NET_IP4_F_SA; - key->key_size += 4; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP4_DIP) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP4; - key->proto_field[key->num_fields].field.ipv4 = MV_NET_IP4_F_DA; - key->key_size += 4; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP4_PROTO) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP4; - key->proto_field[key->num_fields].field.ipv4 = - MV_NET_IP4_F_PROTO; - key->key_size += 1; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP6_SIP) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP6; - key->proto_field[key->num_fields].field.ipv6 = MV_NET_IP6_F_SA; - key->key_size += 16; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP6_DIP) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP6; - key->proto_field[key->num_fields].field.ipv6 = MV_NET_IP6_F_DA; - key->key_size += 16; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP6_FLOW) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP6; - key->proto_field[key->num_fields].field.ipv6 = - MV_NET_IP6_F_FLOW; - key->key_size += 3; - key->num_fields += 1; - } - - if (first_flow->pattern & F_IP6_NEXT_HDR) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_IP6; - key->proto_field[key->num_fields].field.ipv6 = - MV_NET_IP6_F_NEXT_HDR; - key->key_size += 1; - key->num_fields += 1; - } - - if (first_flow->pattern & F_TCP_SPORT) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_TCP; - key->proto_field[key->num_fields].field.tcp = MV_NET_TCP_F_SP; - key->key_size += 2; - key->num_fields += 1; - } - - if (first_flow->pattern & F_TCP_DPORT) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_TCP; - key->proto_field[key->num_fields].field.tcp = MV_NET_TCP_F_DP; - key->key_size += 2; - key->num_fields += 1; - } - - if (first_flow->pattern & F_UDP_SPORT) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_UDP; - key->proto_field[key->num_fields].field.udp = MV_NET_UDP_F_SP; - key->key_size += 2; - key->num_fields += 1; - } - - if (first_flow->pattern & F_UDP_DPORT) { - key->proto_field[key->num_fields].proto = MV_NET_PROTO_UDP; - key->proto_field[key->num_fields].field.udp = MV_NET_UDP_F_DP; - key->key_size += 2; - key->num_fields += 1; - } + memcpy(key, &first_flow->table_key, sizeof(struct pp2_cls_tbl_key)); ret = pp2_cls_tbl_init(&priv->cls_tbl_params, &priv->cls_tbl); - if (!ret) - priv->cls_tbl_pattern = first_flow->pattern; return ret; } @@ -1604,8 +1555,10 @@ mrvl_create_cls_table(struct rte_eth_dev *dev, struct rte_flow *first_flow) static inline int mrvl_flow_can_be_added(struct mrvl_priv *priv, const struct rte_flow *flow) { - return flow->pattern == priv->cls_tbl_pattern && - mrvl_engine_type(flow) == priv->cls_tbl_params.type; + int same = memcmp(&flow->table_key, &priv->cls_tbl_params.key, + sizeof(struct pp2_cls_tbl_key)) == 0; + + return same && mrvl_engine_type(flow) == priv->cls_tbl_params.type; } /** From patchwork Wed Dec 2 10:11:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84695 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53335A04DB; Wed, 2 Dec 2020 11:20:03 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 42A64CAFC; Wed, 2 Dec 2020 11:13:07 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A0136CAC9 for ; Wed, 2 Dec 2020 11:13:02 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A5G28001975 for ; Wed, 2 Dec 2020 02:13:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=RxJUdk3M1JU9SOXUnN/ghkKg0jsXXkmM00Y5fygkGq8=; b=NjT4OV7QH5n69qdf+Zl2IbQ2cmcq1WHZ962/WZLcuIODmG0JBoIPHXKGW+7qZ3Y7Q588 suhAjVpZyT2RiShrL2/beh5ZGEevQRtY8heiwBVm23IUjnyL8SHjoTYx7Jd/b8TtzriI 07xaXHKnenh8OfcD4DD2NofIDZ/YK72/dhu1p+AuZk1FCIM6+d3/Jqx0l3FJwn4dWGSo FawI331JQetoKU8mneBgof3GeY/Q2s030cfieA+4G6Rnv5h7HY+QnOFgVbBvEMimVI8L /NKeJ/lGuZK5Cyvn9yvn2A1UH3HpR5swvyE6aBfdhCoL0S1xPlRXhlW6pQhGyZO8Oan0 xw== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3568jf829j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:00 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:12:59 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:12:58 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:56 +0200 Message-ID: <20201202101212.4717-23-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 22/38] net/mvpp2: flow: add support for RAW type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi add support for RAW type and connect it to MUSDK UDF Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.h | 1 + drivers/net/mvpp2/mrvl_flow.c | 141 ++++++++++++++++++++++++++++++++ 2 files changed, 142 insertions(+) diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index e7f75067f..be5e5a51b 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -92,6 +92,7 @@ struct rte_flow { struct pp2_cls_tbl_rule rule; struct pp2_cls_cos_desc cos; struct pp2_cls_tbl_action action; + uint8_t next_udf_id; }; struct mrvl_mtr_profile { diff --git a/drivers/net/mvpp2/mrvl_flow.c b/drivers/net/mvpp2/mrvl_flow.c index ffa47a12e..3c8052f06 100644 --- a/drivers/net/mvpp2/mrvl_flow.c +++ b/drivers/net/mvpp2/mrvl_flow.c @@ -1196,6 +1196,146 @@ mrvl_parse_udp(const struct rte_flow_item *item, return -rte_errno; } +static int +mrvl_string_to_hex_values(const uint8_t *input_string, + uint8_t *hex_key, + uint8_t *length) +{ + char tmp_arr[3], tmp_string[MRVL_CLS_STR_SIZE_MAX], *string_iter; + int i; + + strcpy(tmp_string, (const char *)input_string); + string_iter = tmp_string; + + string_iter += 2; /* skip the '0x' */ + *length = ((*length - 2) + 1) / 2; + + for (i = 0; i < *length; i++) { + strncpy(tmp_arr, string_iter, 2); + tmp_arr[2] = '\0'; + if (get_val_securely8(tmp_arr, 16, + &hex_key[*length - 1 - i]) < 0) + return -1; + string_iter += 2; + } + + return 0; +} + +/** + * Parse raw flow item. + * + * @param item Pointer to the flow item. + * @param flow Pointer to the flow. + * @param error Pointer to the flow error. + * @returns 0 on success, negative value otherwise. + */ +static int +mrvl_parse_raw(const struct rte_flow_item *item, + struct rte_flow *flow, + struct rte_flow_error *error) +{ + const struct rte_flow_item_raw *spec = NULL, *mask = NULL; + struct pp2_cls_rule_key_field *key_field; + struct mv_net_udf *udf_params; + uint8_t length; + int ret; + + ret = mrvl_parse_init(item, (const void **)&spec, (const void **)&mask, + &rte_flow_item_raw_mask, + sizeof(struct rte_flow_item_raw), error); + if (ret) + return ret; + + if (!spec->pattern) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "pattern pointer MUST be given\n"); + return -rte_errno; + } + + /* Only hex string is supported; so, it must start with '0x' */ + if (strncmp((const char *)spec->pattern, "0x", 2) != 0) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "'pattern' string must start with '0x'\n"); + return -rte_errno; + } + + if (mask->pattern && + strncmp((const char *)mask->pattern, "0x", 2) != 0) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "'mask-pattern' string must start with '0x'\n"); + return -rte_errno; + } + + if (mask->search && spec->search) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "'search' option must be '0'\n"); + return -rte_errno; + } + + if (mask->offset && spec->offset != 0) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "'offset' option must be '0'\n"); + return -rte_errno; + } + + if (!mask->relative || !spec->relative) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "'relative' option must be given and enabled\n"); + return -rte_errno; + } + + length = spec->length & mask->length; + if (!length) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, "'length' option must be given bigger than '0'\n"); + return -rte_errno; + } + + key_field = &flow->rule.fields[flow->rule.num_fields]; + mrvl_alloc_key_mask(key_field); + + /* pattern and length refer to string bytes. we need to convert it to + * values. + */ + key_field->size = length; + ret = mrvl_string_to_hex_values(spec->pattern, key_field->key, + &key_field->size); + if (ret) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, + "can't convert pattern from string to hex\n"); + return -rte_errno; + } + if (mask->pattern) { + ret = mrvl_string_to_hex_values(mask->pattern, key_field->mask, + &length); + if (ret) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + NULL, + "can't convert mask-pattern from string to hex\n"); + return -rte_errno; + } + } else { + rte_free(key_field->mask); + key_field->mask = NULL; + } + + flow->table_key.proto_field[flow->rule.num_fields].proto = + MV_NET_UDF; + udf_params = + &flow->table_key.proto_field[flow->rule.num_fields].field.udf; + udf_params->id = flow->next_udf_id++; + udf_params->size = key_field->size; + flow->table_key.key_size += key_field->size; + + flow->rule.num_fields += 1; + + return 0; +} + /** * Structure used to map specific flow pattern to the pattern parse callback * which will iterate over each pattern item and extract relevant data. @@ -1212,6 +1352,7 @@ static const struct { { RTE_FLOW_ITEM_TYPE_IPV6, mrvl_parse_ip6 }, { RTE_FLOW_ITEM_TYPE_TCP, mrvl_parse_tcp }, { RTE_FLOW_ITEM_TYPE_UDP, mrvl_parse_udp }, + { RTE_FLOW_ITEM_TYPE_RAW, mrvl_parse_raw }, { RTE_FLOW_ITEM_TYPE_END, NULL } }; From patchwork Wed Dec 2 10:11:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84696 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4804CA04DB; Wed, 2 Dec 2020 11:20:21 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A9D8CCB05; Wed, 2 Dec 2020 11:13:08 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 197BACACD for ; Wed, 2 Dec 2020 11:13:03 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A5HPc002008 for ; Wed, 2 Dec 2020 02:13:02 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 2 Dec 2020 02:13:00 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:57 +0200 Message-ID: <20201202101212.4717-24-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 23/38] net/mvpp2: skip qos init if not requested X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi skip qos init if not requested Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_qos.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index 18cf470dd..d8f6dd5c6 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -617,7 +617,7 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) } } else { (*cfg)->port[n].mapping_priority = - PP2_CLS_QOS_TBL_VLAN_IP_PRI; + PP2_CLS_QOS_TBL_NONE; } /* Parse policer configuration (if any) */ @@ -933,6 +933,9 @@ mrvl_start_qos_mapping(struct mrvl_priv *priv) { size_t i; + if (priv->qos_tbl_params.type == PP2_CLS_QOS_TBL_NONE) + return 0; + if (priv->ppio == NULL) { MRVL_LOG(ERR, "ppio must not be NULL here!"); return -1; From patchwork Wed Dec 2 10:11:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84697 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93098A04DB; Wed, 2 Dec 2020 11:20:38 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 187D4CB11; Wed, 2 Dec 2020 11:13:10 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 6A8CFCB00 for ; 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Wed, 02 Dec 2020 02:13:05 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:02 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:01 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:58 +0200 Message-ID: <20201202101212.4717-25-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 24/38] net/mvpp2: move common functions to common location X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi move common functions to common location Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.h | 41 +++++++++++++++++++++++++++++++++ drivers/net/mvpp2/mrvl_qos.c | 24 ------------------- 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index be5e5a51b..5dbd8b46c 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -197,4 +197,45 @@ extern int mrvl_logtype; rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \ __func__, ##args) +/** + * Convert string to uint32_t with extra checks for result correctness. + * + * @param string String to convert. + * @param val Conversion result. + * @returns 0 in case of success, negative value otherwise. + */ +static int +get_val_securely(const char *string, uint32_t *val) +{ + char *endptr; + size_t len = strlen(string); + + if (len == 0) + return -1; + + errno = 0; + *val = strtoul(string, &endptr, 0); + if (errno != 0 || RTE_PTR_DIFF(endptr, string) != len) + return -2; + + return 0; +} + +static int +get_val_securely8(const char *string, uint32_t base, uint8_t *val) +{ + char *endptr; + size_t len = strlen(string); + + if (len == 0) + return -1; + + errno = 0; + *val = (uint8_t)strtoul(string, &endptr, base); + if (errno != 0 || RTE_PTR_DIFF(endptr, string) != len) + return -2; + + return 0; +} + #endif /* _MRVL_ETHDEV_H_ */ diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index d8f6dd5c6..1c65b5276 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -74,30 +74,6 @@ /** Global configuration. */ struct mrvl_cfg *mrvl_cfg; -/** - * Convert string to uint32_t with extra checks for result correctness. - * - * @param string String to convert. - * @param val Conversion result. - * @returns 0 in case of success, negative value otherwise. - */ -static int -get_val_securely(const char *string, uint32_t *val) -{ - char *endptr; - size_t len = strlen(string); - - if (len == 0) - return -1; - - errno = 0; - *val = strtoul(string, &endptr, 0); - if (errno != 0 || RTE_PTR_DIFF(endptr, string) != len) - return -2; - - return 0; -} - /** * Read out-queue configuration from file. * From patchwork Wed Dec 2 10:11:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84698 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CFF76A04DB; Wed, 2 Dec 2020 11:20:58 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6D6A3CB26; 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Wed, 02 Dec 2020 02:13:06 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:04 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:03 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:11:59 +0200 Message-ID: <20201202101212.4717-26-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 25/38] net/mvpp2: support udf configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi extend the config file with 'udf' (user-defined) settings Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 4 +- drivers/net/mvpp2/mrvl_qos.c | 212 ++++++++++++++++++++++++++++++++ drivers/net/mvpp2/mrvl_qos.h | 3 + 3 files changed, 218 insertions(+), 1 deletion(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 6bd3b0430..5ff11e2c9 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -3027,7 +3027,9 @@ mrvl_init_pp2(void) init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; - + if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) + memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, + sizeof(struct pp2_parse_udfs)); return pp2_init(&init_params); } diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index 1c65b5276..f5275efc7 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -35,6 +35,7 @@ #define MRVL_TOK_TXQ "txq" #define MRVL_TOK_VLAN "vlan" #define MRVL_TOK_VLAN_IP "vlan/ip" +#define MRVL_TOK_PARSER_UDF "parser udf" /* egress specific configuration tokens */ #define MRVL_TOK_BURST_SIZE "burst_size" @@ -62,6 +63,18 @@ #define MRVL_TOK_PLCR_DEFAULT_COLOR_YELLOW "yellow" #define MRVL_TOK_PLCR_DEFAULT_COLOR_RED "red" +/* paser udf specific configuration tokens */ +#define MRVL_TOK_PARSER_UDF_PROTO "proto" +#define MRVL_TOK_PARSER_UDF_FIELD "field" +#define MRVL_TOK_PARSER_UDF_KEY "key" +#define MRVL_TOK_PARSER_UDF_MASK "mask" +#define MRVL_TOK_PARSER_UDF_OFFSET "offset" +#define MRVL_TOK_PARSER_UDF_PROTO_ETH "eth" +#define MRVL_TOK_PARSER_UDF_FIELD_ETH_TYPE "type" +#define MRVL_TOK_PARSER_UDF_PROTO_UDP "udp" +#define MRVL_TOK_PARSER_UDF_FIELD_UDP_DPORT "dport" + + /** Number of tokens in range a-b = 2. */ #define MAX_RNG_TOKENS 2 @@ -453,6 +466,175 @@ parse_policer(struct rte_cfgfile *file, int port, const char *sec_name, return 0; } +/** + * Parse parser udf. + * + * @param file Config file handle. + * @param sec_name section name + * @param udf udf index + * @param cfg[out] Parsing results. + * @returns 0 in case of success, negative value otherwise. + */ +static int +parse_udf(struct rte_cfgfile *file, const char *sec_name, int udf, + struct mrvl_cfg *cfg) +{ + struct pp2_parse_udf_params *udf_params; + const char *entry, *entry_field; + uint32_t val, i; + uint8_t field_size; + char malloc_name[32], tmp_arr[3]; + /* field len in chars equal to '0x' + rest of data */ +#define FIELD_LEN_IN_CHARS(field_size) (uint32_t)(2 + (field_size) * 2) + + udf_params = &cfg->pp2_cfg.prs_udfs.udfs[udf]; + + /* Read 'proto' field */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PARSER_UDF_PROTO); + if (!entry) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field must be set\n", udf, + MRVL_TOK_PARSER_UDF_PROTO); + return -1; + } + + /* Read 'field' field */ + entry_field = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PARSER_UDF_FIELD); + if (!entry_field) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field must be set\n", udf, + MRVL_TOK_PARSER_UDF_FIELD); + return -1; + } + + if (!strncmp(entry, MRVL_TOK_PARSER_UDF_PROTO_ETH, + sizeof(MRVL_TOK_PARSER_UDF_PROTO_ETH))) { + udf_params->match_proto = MV_NET_PROTO_ETH; + if (!strncmp(entry_field, MRVL_TOK_PARSER_UDF_FIELD_ETH_TYPE, + sizeof(MRVL_TOK_PARSER_UDF_FIELD_ETH_TYPE))) { + udf_params->match_field.eth = MV_NET_ETH_F_TYPE; + field_size = 2; + } else { + MRVL_LOG(ERR, "UDF[%d]: mismatch between '%s' proto " + "and '%s' field\n", udf, + MRVL_TOK_PARSER_UDF_PROTO_ETH, + entry_field); + return -1; + } + } else if (!strncmp(entry, MRVL_TOK_PARSER_UDF_PROTO_UDP, + sizeof(MRVL_TOK_PARSER_UDF_PROTO_UDP))) { + udf_params->match_proto = MV_NET_PROTO_UDP; + if (!strncmp(entry_field, MRVL_TOK_PARSER_UDF_FIELD_UDP_DPORT, + sizeof(MRVL_TOK_PARSER_UDF_FIELD_UDP_DPORT))) { + udf_params->match_field.udp = MV_NET_UDP_F_DP; + field_size = 2; + } else { + MRVL_LOG(ERR, "UDF[%d]: mismatch between '%s' proto " + "and '%s' field\n", udf, + MRVL_TOK_PARSER_UDF_PROTO_UDP, + entry_field); + return -1; + } + } else { + MRVL_LOG(ERR, "UDF[%d]: Unsupported '%s' proto\n", udf, entry); + return -1; + } + + snprintf(malloc_name, sizeof(malloc_name), "mrvl_udf_%d_key", udf); + udf_params->match_key = rte_zmalloc(malloc_name, field_size, 0); + if (udf_params->match_key == NULL) { + MRVL_LOG(ERR, "Cannot allocate udf %d key\n", udf); + return -1; + } + snprintf(malloc_name, sizeof(malloc_name), "mrvl_udf_%d_mask", udf); + udf_params->match_mask = rte_zmalloc(malloc_name, field_size, 0); + if (udf_params->match_mask == NULL) { + MRVL_LOG(ERR, "Cannot allocate udf %d mask\n", udf); + return -1; + } + + /* Read 'key' field */ + entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_PARSER_UDF_KEY); + if (!entry) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field must be set\n", udf, + MRVL_TOK_PARSER_UDF_KEY); + return -1; + } + + if (strncmp(entry, "0x", 2) != 0) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field must start with '0x'\n", + udf, MRVL_TOK_PARSER_UDF_KEY); + return -EINVAL; + } + + if (strlen(entry) != FIELD_LEN_IN_CHARS(field_size)) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field's len must be %d\n", udf, + MRVL_TOK_PARSER_UDF_KEY, + FIELD_LEN_IN_CHARS(field_size)); + return -EINVAL; + } + + entry += 2; /* skip the '0x' */ + for (i = 0; i < field_size; i++) { + strncpy(tmp_arr, entry, 2); + tmp_arr[2] = '\0'; + if (get_val_securely8(tmp_arr, 16, + &udf_params->match_key[i]) < 0) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field's value is not in " + "hex format\n", udf, MRVL_TOK_PARSER_UDF_KEY); + return -EINVAL; + } + entry += 2; + } + + /* Read 'mask' field */ + entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_PARSER_UDF_MASK); + if (!entry) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field must be set\n", udf, + MRVL_TOK_PARSER_UDF_MASK); + return -1; + } + if (strncmp(entry, "0x", 2) != 0) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field must start with '0x'\n", + udf, MRVL_TOK_PARSER_UDF_MASK); + return -EINVAL; + } + + if (strlen(entry) != FIELD_LEN_IN_CHARS(field_size)) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field's len must be %d\n", udf, + MRVL_TOK_PARSER_UDF_MASK, + FIELD_LEN_IN_CHARS(field_size)); + return -EINVAL; + } + + entry += 2; /* skip the '0x' */ + for (i = 0; i < field_size; i++) { + strncpy(tmp_arr, entry, 2); + tmp_arr[2] = '\0'; + if (get_val_securely8(tmp_arr, 16, + &udf_params->match_mask[i]) < 0) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field's value is not in " + "hex format\n", udf, MRVL_TOK_PARSER_UDF_MASK); + return -EINVAL; + } + entry += 2; + } + + /* Read offset */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_PARSER_UDF_OFFSET); + if (!entry) { + MRVL_LOG(ERR, "UDF[%d]: '%s' field must be set\n", udf, + MRVL_TOK_PARSER_UDF_OFFSET); + return -1; + } + if (get_val_securely(entry, &val) < 0) + return -1; + udf_params->offset = val; + + return 0; +} + /** * Parse configuration - rte_kvargs_process handler. * @@ -487,6 +669,36 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) return -1; } + /* PP2 configuration */ + n = rte_cfgfile_num_sections(file, MRVL_TOK_PARSER_UDF, + sizeof(MRVL_TOK_PARSER_UDF) - 1); + + if (n && n > PP2_MAX_UDFS_SUPPORTED) { + MRVL_LOG(ERR, "found %d udf sections, but only %d are supported\n", + n, PP2_MAX_UDFS_SUPPORTED); + return -1; + } + (*cfg)->pp2_cfg.prs_udfs.num_udfs = n; + for (i = 0; i < n; i++) { + snprintf(sec_name, sizeof(sec_name), "%s %d", + MRVL_TOK_PARSER_UDF, i); + + /* udf sections must be sequential. */ + if (rte_cfgfile_num_sections(file, sec_name, + strlen(sec_name)) <= 0) { + MRVL_LOG(ERR, "udf sections must be sequential (0 - %d)\n", + PP2_MAX_UDFS_SUPPORTED - 1); + return -1; + } + + ret = parse_udf(file, sec_name, i, *cfg); + if (ret) { + MRVL_LOG(ERR, "Error in parsing %s!\n", sec_name); + return -1; + } + } + + /* PP2 Ports configuration */ n = rte_cfgfile_num_sections(file, MRVL_TOK_PORT, sizeof(MRVL_TOK_PORT) - 1); diff --git a/drivers/net/mvpp2/mrvl_qos.h b/drivers/net/mvpp2/mrvl_qos.h index 928cfe366..daf4776ec 100644 --- a/drivers/net/mvpp2/mrvl_qos.h +++ b/drivers/net/mvpp2/mrvl_qos.h @@ -19,6 +19,9 @@ /* config. */ struct mrvl_cfg { + struct { + struct pp2_parse_udfs prs_udfs; + } pp2_cfg; struct port_cfg { enum pp2_ppio_eth_start_hdr eth_start_hdr; int rate_limit_enable; From patchwork Wed Dec 2 10:12:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84699 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 94904A04DB; Wed, 2 Dec 2020 11:21:18 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B2621CB2F; Wed, 2 Dec 2020 11:13:12 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 54650CB1A for ; Wed, 2 Dec 2020 11:13:10 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AALwU024189 for ; Wed, 2 Dec 2020 02:13:08 -0800 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r66-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:08 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:06 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:05 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:05 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:12:00 +0200 Message-ID: <20201202101212.4717-27-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 26/38] net/mvpp2: rearrange functions order X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi rearrange functions order Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 98 ++++++++++++++++----------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 5ff11e2c9..127861a82 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -189,6 +189,39 @@ static struct { MRVL_XSTATS_TBL_ENTRY(tx_errors) }; +/** + * Initialize packet processor. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_init_pp2(void) +{ + struct pp2_init_params init_params; + + memset(&init_params, 0, sizeof(init_params)); + init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; + init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; + init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; + if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) + memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, + sizeof(struct pp2_parse_udfs)); + return pp2_init(&init_params); +} + +/** + * Deinitialize packet processor. + * + * @return + * 0 on success, negative error value otherwise. + */ +static void +mrvl_deinit_pp2(void) +{ + pp2_deinit(); +} + static inline void mrvl_fill_shadowq(struct mrvl_shadow_txq *sq, struct rte_mbuf *buf) { @@ -292,6 +325,22 @@ mrvl_get_hif(struct mrvl_priv *priv, int core_id) return hifs[core_id]; } +/** + * Deinitialize per-lcore MUSDK hardware interfaces (hifs). + */ +static void +mrvl_deinit_hifs(void) +{ + int i; + + for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { + if (hifs[i]) + pp2_hif_deinit(hifs[i]); + } + used_hifs = MRVL_MUSDK_HIFS_RESERVED; + memset(hifs, 0, sizeof(hifs)); +} + /** * Set tx burst function according to offload flag * @@ -3012,39 +3061,6 @@ mrvl_tx_sg_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, return nb_pkts; } -/** - * Initialize packet processor. - * - * @return - * 0 on success, negative error value otherwise. - */ -static int -mrvl_init_pp2(void) -{ - struct pp2_init_params init_params; - - memset(&init_params, 0, sizeof(init_params)); - init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; - init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; - init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; - if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) - memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, - sizeof(struct pp2_parse_udfs)); - return pp2_init(&init_params); -} - -/** - * Deinitialize packet processor. - * - * @return - * 0 on success, negative error value otherwise. - */ -static void -mrvl_deinit_pp2(void) -{ - pp2_deinit(); -} - /** * Create private device structure. * @@ -3184,22 +3200,6 @@ mrvl_get_ifnames(const char *key __rte_unused, const char *value, return 0; } -/** - * Deinitialize per-lcore MUSDK hardware interfaces (hifs). - */ -static void -mrvl_deinit_hifs(void) -{ - int i; - - for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { - if (hifs[i]) - pp2_hif_deinit(hifs[i]); - } - used_hifs = MRVL_MUSDK_HIFS_RESERVED; - memset(hifs, 0, sizeof(hifs)); -} - /** * DPDK callback to register the virtual device. * From patchwork Wed Dec 2 10:12:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84700 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 537C5A04DB; Wed, 2 Dec 2020 11:21:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0521ECB3E; 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Wed, 02 Dec 2020 02:13:08 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:07 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:06 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:12:01 +0200 Message-ID: <20201202101212.4717-28-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 27/38] net/mvpp2: dummy pool creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi Currently the HW is configured with only one pool which its buffer size may be larger than the rx-fifo-size. In that situation, frame size larger than the fifo-size is gets dropped due to fifo overrun. this is cause because the HW works in cut-through mode which waits to have in the fifo at least the amount of bytes as define in the smallest pool's buffer size. This patch add a dummy pool which its buffer size is very small (smaller than 64B frame). this tricks the HW and any frame size is gets passed from the FIFO to the PP2. Signed-off-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 71 ++++++++++++++++++++++++++------- drivers/net/mvpp2/mrvl_ethdev.h | 2 + drivers/net/mvpp2/mrvl_qos.c | 1 + 3 files changed, 60 insertions(+), 14 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 127861a82..1f9489d77 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -90,6 +90,8 @@ static int used_bpools[PP2_NUM_PKT_PROC] = { static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; +static int dummy_pool_id[PP2_NUM_PKT_PROC]; +struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC] = {0}; struct mrvl_ifnames { const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; @@ -189,6 +191,19 @@ static struct { MRVL_XSTATS_TBL_ENTRY(tx_errors) }; +static inline int +mrvl_reserve_bit(int *bitmap, int max) +{ + int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); + + if (n >= max) + return -1; + + *bitmap |= 1 << n; + + return n; +} + /** * Initialize packet processor. * @@ -199,6 +214,9 @@ static int mrvl_init_pp2(void) { struct pp2_init_params init_params; + struct pp2_bpool_params bpool_params; + char name[15]; + int err, i; memset(&init_params, 0, sizeof(init_params)); init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; @@ -207,7 +225,36 @@ mrvl_init_pp2(void) if (mrvl_cfg && mrvl_cfg->pp2_cfg.prs_udfs.num_udfs) memcpy(&init_params.prs_udfs, &mrvl_cfg->pp2_cfg.prs_udfs, sizeof(struct pp2_parse_udfs)); - return pp2_init(&init_params); + err = pp2_init(&init_params); + if (err != 0) { + MRVL_LOG(ERR, "PP2 init failed"); + return -1; + } + + memset(dummy_pool, 0, sizeof(dummy_pool)); + for (i = 0; i < pp2_get_num_inst(); i++) { + dummy_pool_id[i] = mrvl_reserve_bit(&used_bpools[i], + PP2_BPOOL_NUM_POOLS); + if (dummy_pool_id[i] < 0) { + MRVL_LOG(ERR, "Can't find free pool\n"); + return -1; + } + + memset(name, 0, sizeof(name)); + snprintf(name, sizeof(name), "pool-%d:%d", i, dummy_pool_id[i]); + memset(&bpool_params, 0, sizeof(bpool_params)); + bpool_params.match = name; + bpool_params.buff_len = MRVL_PKT_OFFS; + bpool_params.dummy_short_pool = 1; + err = pp2_bpool_init(&bpool_params, &dummy_pool[i]); + if (err != 0 || !dummy_pool[i]) { + MRVL_LOG(ERR, "BPool init failed!\n"); + used_bpools[i] &= ~(1 << dummy_pool_id[i]); + return -1; + } + } + + return 0; } /** @@ -219,6 +266,15 @@ mrvl_init_pp2(void) static void mrvl_deinit_pp2(void) { + int i; + + for (i = 0; i < PP2_NUM_PKT_PROC; i++) { + if (!dummy_pool[i]) + continue; + pp2_bpool_deinit(dummy_pool[i]); + used_bpools[i] &= ~(1 << dummy_pool_id[i]); + } + pp2_deinit(); } @@ -259,19 +315,6 @@ mrvl_get_bpool_size(int pp2_id, int pool_id) return size; } -static inline int -mrvl_reserve_bit(int *bitmap, int max) -{ - int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap); - - if (n >= max) - return -1; - - *bitmap |= 1 << n; - - return n; -} - static int mrvl_init_hif(int core_id) { diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index 5dbd8b46c..24dbe20d7 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -197,6 +197,8 @@ extern int mrvl_logtype; rte_log(RTE_LOG_ ## level, mrvl_logtype, "%s(): " fmt "\n", \ __func__, ##args) +extern struct pp2_bpool *dummy_pool[PP2_NUM_PKT_PROC]; + /** * Convert string to uint32_t with extra checks for result correctness. * diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index f5275efc7..23a014ade 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -881,6 +881,7 @@ setup_tc(struct pp2_ppio_tc_params *param, uint8_t inqs, param->pkt_offset = MRVL_PKT_OFFS; param->pools[0][0] = bpool; + param->pools[0][1] = dummy_pool[bpool->pp2_id]; param->default_color = color; inq_params = rte_zmalloc_socket("inq_params", From patchwork Wed Dec 2 10:12:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84701 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 31AFFA04DB; Wed, 2 Dec 2020 11:21:58 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A1977CB46; Wed, 2 Dec 2020 11:13:15 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id F355DCB2F for ; Wed, 2 Dec 2020 11:13:10 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A56Kf001864 for ; Wed, 2 Dec 2020 02:13:10 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ODmQZh+JcvCKlIFL/un40OD2HPFvIjS4CF/WEB7ADbw=; b=Lz7KO25PZQs9xXbs0OW7WlnjaQgPs8fmnhxkVxQuvN7GDKI1IqXJlxgQDKiVPduK7YmF vKMscCFqC7fHl15wTGJIh29gDQCfvhHFDAdtMJGrJqUxwuimbmPAMv00XapbRFRdn/S1 4mDPfIn3vdNLC+6HSfe72KYY26FVG/q444LntH11FWIdxY1qWro/mFeYy35JegjYHX5O Mu2hUK+/WSFiwr8BFqS0g6g8QT80N4h5bnr273Skaynf2MN0dIS0QPULiT7ruE9MKLmg PdTYKCnN/b/OwfJ8xOuilu6nwI0SdiqQeHPIW3oRFyZ+CSPeG2ktQynKGJhI4oO5BfwG qA== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3568jf82a6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:10 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:08 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:08 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:12:02 +0200 Message-ID: <20201202101212.4717-29-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 28/38] net/mvpp2: propagate port-id in udata64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi mbuf->port can be override and used for eventdev so saving the port-id information in another field tht can be query by application Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 1f9489d77..66c3c8e57 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2693,6 +2693,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) mbuf->l2_len = l3_offset; mbuf->l3_len = l4_offset - l3_offset; + mbuf->udata64 = q->port_id; if (likely(q->cksum_enabled)) mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); From patchwork Wed Dec 2 10:12:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84702 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8923A04DB; Wed, 2 Dec 2020 11:22:15 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F2998CB56; Wed, 2 Dec 2020 11:13:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id DA633C9C4 for ; Wed, 2 Dec 2020 11:13:13 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A58xc001879 for ; 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Wed, 2 Dec 2020 02:13:11 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:10 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:09 -0800 From: To: CC: , Yuri Chipchev , Liron Himi Date: Wed, 2 Dec 2020 12:12:03 +0200 Message-ID: <20201202101212.4717-30-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 29/38] net/mvpp2: autoneg disable handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Yuri Chipchev flow control autoneg disable is not supported Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Yuri Chipchev Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 66c3c8e57..535d7cc60 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2135,6 +2135,7 @@ mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) if (!priv) return -EPERM; + fc_conf->autoneg = 1; ret = pp2_ppio_get_rx_pause(priv->ppio, &en); if (ret) { MRVL_LOG(ERR, "Failed to read rx pause state"); @@ -2184,13 +2185,17 @@ mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time || - fc_conf->mac_ctrl_frame_fwd || - fc_conf->autoneg) { + fc_conf->mac_ctrl_frame_fwd) { MRVL_LOG(ERR, "Flowctrl parameter is not supported"); return -EINVAL; } + if (fc_conf->autoneg == 0) { + MRVL_LOG(ERR, "Flowctrl Autoneg disable is not supported"); + return -EINVAL; + } + switch (fc_conf->mode) { case RTE_FC_FULL: rx_en = 1; From patchwork Wed Dec 2 10:12:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84703 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5ED2A04DB; Wed, 2 Dec 2020 11:22:33 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A85ABCB7B; Wed, 2 Dec 2020 11:13:19 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 5A2B7CB77 for ; Wed, 2 Dec 2020 11:13:17 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AALwV024189 for ; Wed, 2 Dec 2020 02:13:15 -0800 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r6f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:15 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:13 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:11 -0800 From: To: CC: , Liron Himi , Yuri Chipchev Date: Wed, 2 Dec 2020 12:12:04 +0200 Message-ID: <20201202101212.4717-31-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 30/38] net/mvpp2: expose max mtu size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi expose max-mtu based on the max frame size that l4 checksum generation can be done by HW. Signed-off-by: Liron Himi Reviewed-by: Yuri Chipchev Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Yuri Chipchev --- drivers/net/mvpp2/mrvl_ethdev.c | 24 ++++++++++++++++++++++-- drivers/net/mvpp2/mrvl_ethdev.h | 1 + 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 535d7cc60..9fd9269eb 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -477,9 +477,17 @@ mrvl_dev_configure(struct rte_eth_dev *dev) return -EINVAL; } - if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - MRVL_PP2_ETH_HDRS_LEN; + if (dev->data->mtu > priv->max_mtu) { + MRVL_LOG(ERR, "inherit MTU %u from max_rx_pkt_len %u is larger than max_mtu %u\n", + dev->data->mtu, + dev->data->dev_conf.rxmode.max_rx_pkt_len, + priv->max_mtu); + return -EINVAL; + } + } if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_MULTI_SEGS) priv->multiseg = 1; @@ -1676,9 +1684,11 @@ mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused, * Info structure output buffer. */ static int -mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, +mrvl_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) { + struct mrvl_priv *priv = dev->data->dev_private; + info->speed_capa = ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | @@ -1710,6 +1720,7 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, info->default_rxconf.rx_drop_en = 1; info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; + info->max_mtu = priv->max_mtu; return 0; } @@ -3125,6 +3136,7 @@ mrvl_priv_create(const char *dev_name) struct pp2_bpool_params bpool_params; char match[MRVL_MATCH_LEN]; struct mrvl_priv *priv; + uint16_t max_frame_size; int ret, bpool_bit; priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id()); @@ -3136,6 +3148,14 @@ mrvl_priv_create(const char *dev_name) if (ret) goto out_free_priv; + ret = pp2_ppio_get_l4_cksum_max_frame_size(priv->pp_id, priv->ppio_id, + &max_frame_size); + if (ret) + goto out_free_priv; + + priv->max_mtu = max_frame_size + RTE_ETHER_CRC_LEN - + MRVL_PP2_ETH_HDRS_LEN; + bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id], PP2_BPOOL_NUM_POOLS); if (bpool_bit < 0) diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index 24dbe20d7..ada2c51b2 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -160,6 +160,7 @@ struct mrvl_priv { uint8_t vlan_flushed; uint8_t isolated; uint8_t multiseg; + uint16_t max_mtu; struct pp2_ppio_params ppio_params; struct pp2_cls_qos_tbl_params qos_tbl_params; From patchwork Wed Dec 2 10:12:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84704 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF432A04DB; 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Wed, 02 Dec 2020 02:13:16 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:15 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:14 -0800 From: To: CC: , Meir Levi , Liron Himi Date: Wed, 2 Dec 2020 12:12:05 +0200 Message-ID: <20201202101212.4717-32-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 31/38] net/mvpp2: add support of LINK_SPEED_2_5G X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Meir Levi update capability with 2.5G support Signed-off-by: Meir Levi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Meir Levi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 9fd9269eb..d388fde96 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1193,6 +1193,9 @@ mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) case SPEED_1000: dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G; break; + case SPEED_2500: + dev->data->dev_link.link_speed = ETH_SPEED_NUM_2_5G; + break; case SPEED_10000: dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G; break; @@ -1692,6 +1695,7 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev, info->speed_capa = ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | + ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_10G; info->max_rx_queues = MRVL_PP2_RXQ_MAX; From patchwork Wed Dec 2 10:12:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84706 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C426A04DB; Wed, 2 Dec 2020 11:23:30 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 66975C9DA; Wed, 2 Dec 2020 11:13:28 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 27263C9C2 for ; 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Wed, 02 Dec 2020 02:13:21 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:16 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:15 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:12:06 +0200 Message-ID: <20201202101212.4717-33-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 32/38] net/mvpp2: apply flow-ctrl after port init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi in case ppio was not initialized yet (only at 'start' function) the flow-ctrl setting should be saved for later stage. Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 26 +++++++++++++++++++++----- drivers/net/mvpp2/mrvl_ethdev.h | 2 ++ 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index d388fde96..fe5fd90ef 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -164,6 +164,8 @@ static int mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); static int mrvl_promiscuous_enable(struct rte_eth_dev *dev); static int mrvl_allmulticast_enable(struct rte_eth_dev *dev); +static int +mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); #define MRVL_XSTATS_TBL_ENTRY(name) { \ #name, offsetof(struct pp2_ppio_statistics, name), \ @@ -912,6 +914,15 @@ mrvl_dev_start(struct rte_eth_dev *dev) if (dev->data->promiscuous == 1) mrvl_promiscuous_enable(dev); + if (priv->flow_ctrl) { + ret = mrvl_flow_ctrl_set(dev, &priv->fc_conf); + if (ret) { + MRVL_LOG(ERR, "Failed to configure flow control"); + goto out; + } + priv->flow_ctrl = 0; + } + if (dev->data->dev_link.link_status == ETH_LINK_UP) { ret = mrvl_dev_set_link_up(dev); if (ret) { @@ -2147,8 +2158,10 @@ mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) struct mrvl_priv *priv = dev->data->dev_private; int ret, en; - if (!priv) - return -EPERM; + if (!priv->ppio) { + memcpy(fc_conf, &priv->fc_conf, sizeof(struct rte_eth_fc_conf)); + return 0; + } fc_conf->autoneg = 1; ret = pp2_ppio_get_rx_pause(priv->ppio, &en); @@ -2194,9 +2207,6 @@ mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) int ret; int rx_en, tx_en; - if (!priv) - return -EPERM; - if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time || @@ -2211,6 +2221,12 @@ mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return -EINVAL; } + if (!priv->ppio) { + memcpy(&priv->fc_conf, fc_conf, sizeof(struct rte_eth_fc_conf)); + priv->flow_ctrl = 1; + return 0; + } + switch (fc_conf->mode) { case RTE_FC_FULL: rx_en = 1; diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index ada2c51b2..148f2acba 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -161,6 +161,8 @@ struct mrvl_priv { uint8_t isolated; uint8_t multiseg; uint16_t max_mtu; + uint8_t flow_ctrl; + struct rte_eth_fc_conf fc_conf; struct pp2_ppio_params ppio_params; struct pp2_cls_qos_tbl_params qos_tbl_params; From patchwork Wed Dec 2 10:12:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84705 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 759A6A04DB; Wed, 2 Dec 2020 11:23:13 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 05A95CBB4; Wed, 2 Dec 2020 11:13:24 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id F210FCBA2 for ; Wed, 2 Dec 2020 11:13:21 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2A52Ms001859 for ; Wed, 2 Dec 2020 02:13:20 -0800 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3568jf82aw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:20 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:18 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:17 -0800 From: To: CC: , Dana Vardi , Liron Himi Date: Wed, 2 Dec 2020 12:12:07 +0200 Message-ID: <20201202101212.4717-34-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 33/38] net/mvpp2: change dsa_mode naming X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dana Vardi change 'dsa_mode' to 'start_hdr' in config file Signed-off-by: Dana Vardi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Dana Vardi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_qos.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index 23a014ade..c7bd8825c 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -20,9 +20,10 @@ /* Parsing tokens. Defined conveniently, so that any correction is easy. */ #define MRVL_TOK_DEFAULT "default" #define MRVL_TOK_DSA_MODE "dsa_mode" -#define MRVL_TOK_DSA_MODE_NONE "none" -#define MRVL_TOK_DSA_MODE_DSA "dsa" -#define MRVL_TOK_DSA_MODE_EXT_DSA "ext_dsa" +#define MRVL_TOK_START_HDR "start_hdr" +#define MRVL_TOK_START_HDR_NONE "none" +#define MRVL_TOK_START_HDR_DSA "dsa" +#define MRVL_TOK_START_HDR_EXT_DSA "ext_dsa" #define MRVL_TOK_DEFAULT_TC "default_tc" #define MRVL_TOK_DSCP "dscp" #define MRVL_TOK_MAPPING_PRIORITY "mapping_priority" @@ -722,25 +723,33 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) continue; } + /* MRVL_TOK_START_HDR replaces MRVL_TOK_DSA_MODE parameter. + * MRVL_TOK_DSA_MODE will be supported for backward + * compatibillity. + */ entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_START_HDR); + /* if start_hsr is missing, check if dsa_mode exist instead */ + if (entry == NULL) + entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_DSA_MODE); if (entry) { - if (!strncmp(entry, MRVL_TOK_DSA_MODE_NONE, - sizeof(MRVL_TOK_DSA_MODE_NONE))) + if (!strncmp(entry, MRVL_TOK_START_HDR_NONE, + sizeof(MRVL_TOK_START_HDR_NONE))) (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH; - else if (!strncmp(entry, MRVL_TOK_DSA_MODE_DSA, - sizeof(MRVL_TOK_DSA_MODE_DSA))) + else if (!strncmp(entry, MRVL_TOK_START_HDR_DSA, + sizeof(MRVL_TOK_START_HDR_DSA))) (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH_DSA; - else if (!strncmp(entry, MRVL_TOK_DSA_MODE_EXT_DSA, - sizeof(MRVL_TOK_DSA_MODE_EXT_DSA))) { + else if (!strncmp(entry, MRVL_TOK_START_HDR_EXT_DSA, + sizeof(MRVL_TOK_START_HDR_EXT_DSA))) { (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH_EXT_DSA; } else { MRVL_LOG(ERR, "Error in parsing %s value (%s)!\n", - MRVL_TOK_DSA_MODE, entry); + MRVL_TOK_START_HDR, entry); return -1; } } else { From patchwork Wed Dec 2 10:12:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84707 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 55400A04DB; Wed, 2 Dec 2020 11:23:46 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9A1F7CBDC; Wed, 2 Dec 2020 11:13:29 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 44659CB86 for ; Wed, 2 Dec 2020 11:13:27 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2ABMla025655 for ; Wed, 2 Dec 2020 02:13:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/aMSfgCVpyXh8FVTwsUINflRn+7Skbubutl1HY2oCm8=; b=HEm1kkvY0zwuII8s3irsk+tWrkOIusy8HUulqnY+LRLNoVOSqXz8jdpi/Kb0KazZNelx b9MCYAFEpE+mzF3HCQu9F+OfUSFk/nUZAVeHRBZVk7Z96l/p2ZNpOES84ZIu8U8IH/0z ZuuSUnAfnr67Je2ephdYXtX3MIPPu+ZRKdi57o/xsgwbWdFXqGgsJyUbkUOXDV/v+lim RJb8taAWIher7eDkFo543h613l+y7Jj1usClPZ3eN4d9k88ZDuIe3Y9XDCKhlMKbeGPS bx5IPRxYzIx34yusM2bGoOQEq42lWlzAoAZYXVsguihWJeYYyNPAGlc3DtHygKTOnWdP 8g== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r6s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:22 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:20 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:19 -0800 From: To: CC: , Liron Himi Date: Wed, 2 Dec 2020 12:12:08 +0200 Message-ID: <20201202101212.4717-35-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 34/38] net/mvpp2: consider ptype in cksum info X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Liron Himi provide checksum information based on the ptype. Signed-off-by: Liron Himi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Liron Himi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 34 +++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index fe5fd90ef..cb792300b 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -2622,23 +2622,27 @@ mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, * Mbuf offload flags. */ static inline uint64_t -mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc) +mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc, uint64_t packet_type) { - uint64_t flags; + uint64_t flags = 0; enum pp2_inq_desc_status status; - status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); - if (unlikely(status != PP2_DESC_ERR_OK)) - flags = PKT_RX_IP_CKSUM_BAD; - else - flags = PKT_RX_IP_CKSUM_GOOD; - - status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); - if (unlikely(status != PP2_DESC_ERR_OK)) - flags |= PKT_RX_L4_CKSUM_BAD; - else - flags |= PKT_RX_L4_CKSUM_GOOD; + if (RTE_ETH_IS_IPV4_HDR(packet_type)) { + status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); + if (unlikely(status != PP2_DESC_ERR_OK)) + flags |= PKT_RX_IP_CKSUM_BAD; + else + flags |= PKT_RX_IP_CKSUM_GOOD; + } + if (((packet_type & RTE_PTYPE_L4_UDP) == RTE_PTYPE_L4_UDP) || + ((packet_type & RTE_PTYPE_L4_TCP) == RTE_PTYPE_L4_TCP)) { + status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); + if (unlikely(status != PP2_DESC_ERR_OK)) + flags |= PKT_RX_L4_CKSUM_BAD; + else + flags |= PKT_RX_L4_CKSUM_GOOD; + } return flags; } @@ -2731,7 +2735,9 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) mbuf->udata64 = q->port_id; if (likely(q->cksum_enabled)) - mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); + mbuf->ol_flags = + mrvl_desc_to_ol_flags(&descs[i], + mbuf->packet_type); rx_pkts[rx_done++] = mbuf; q->bytes_recv += mbuf->pkt_len; From patchwork Wed Dec 2 10:12:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84708 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 20DADA04DB; Wed, 2 Dec 2020 11:24:06 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4F21FCC1C; Wed, 2 Dec 2020 11:13:32 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7A5FBCBDB for ; Wed, 2 Dec 2020 11:13:30 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2ABMlc025655 for ; Wed, 2 Dec 2020 02:13:27 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=e+usa4V4iUohWe9SC8vyLMu8eZsfZ+mGlL70RcdAvY0=; b=PIElLjJxMhxOnCNWJ6gwLowATrmaCKO5oLRoUvio3/DXDcKpxn2Ni1t16qk+8mLOSUID hvQsxBMGMxalqJynB4LcwqP+KZ+Cu+7m04WY6dUnYi9eEmqX7TdrKQY95ujoL3hO8Qez Esx42cLnG2lPnUIKx5d6YvJCYHqijwSFwwZo1UJYowrLd/EOzEDcwyG11RLfD83l+EVt 9Yae7GVhM8t1/bj1sF4V8yRpsYH1KW41LCGQr8bsVIf5AE5O6mRcRf7JoDX3zqxCjFRH 56dBWqaheHq12Q/yuYNF4n9CC5NtipGyXc4b+g83+c3ekJTGNr3GTdgdI/hNFDTyfhmh OQ== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r6w-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:26 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:22 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:21 -0800 From: To: CC: , Dana Vardi , Liron Himi Date: Wed, 2 Dec 2020 12:12:09 +0200 Message-ID: <20201202101212.4717-36-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 35/38] net/mvpp2: support custom header before ethernet X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dana Vardi extend 'start_hdr' options with custom header. Signed-off-by: Dana Vardi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Dana Vardi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_qos.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index c7bd8825c..10e8636b4 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -23,6 +23,7 @@ #define MRVL_TOK_START_HDR "start_hdr" #define MRVL_TOK_START_HDR_NONE "none" #define MRVL_TOK_START_HDR_DSA "dsa" +#define MRVL_TOK_START_HDR_CUSTOM "custom" #define MRVL_TOK_START_HDR_EXT_DSA "ext_dsa" #define MRVL_TOK_DEFAULT_TC "default_tc" #define MRVL_TOK_DSCP "dscp" @@ -742,6 +743,10 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) sizeof(MRVL_TOK_START_HDR_DSA))) (*cfg)->port[n].eth_start_hdr = PP2_PPIO_HDR_ETH_DSA; + else if (!strncmp(entry, MRVL_TOK_START_HDR_CUSTOM, + sizeof(MRVL_TOK_START_HDR_CUSTOM))) + (*cfg)->port[n].eth_start_hdr = + PP2_PPIO_HDR_ETH_CUSTOM; else if (!strncmp(entry, MRVL_TOK_START_HDR_EXT_DSA, sizeof(MRVL_TOK_START_HDR_EXT_DSA))) { (*cfg)->port[n].eth_start_hdr = From patchwork Wed Dec 2 10:12:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84709 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EDBA2A04DB; Wed, 2 Dec 2020 11:24:23 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 80B3FCC19; Wed, 2 Dec 2020 11:13:33 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 87AEECC19 for ; Wed, 2 Dec 2020 11:13:31 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAT4k024223 for ; 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Wed, 2 Dec 2020 02:13:24 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:24 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:23 -0800 From: To: CC: , Dana Vardi , Liron Himi Date: Wed, 2 Dec 2020 12:12:10 +0200 Message-ID: <20201202101212.4717-37-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 36/38] net/mvpp2: forward bad packets support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dana Vardi extend the config file with option to forward packets that were marked as "l2 bad pkts". by default the driver drop those packets Signed-off-by: Dana Vardi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Dana Vardi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 10 ++++++++-- drivers/net/mvpp2/mrvl_ethdev.h | 2 ++ drivers/net/mvpp2/mrvl_qos.c | 17 +++++++++++++++++ drivers/net/mvpp2/mrvl_qos.h | 1 + 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index cb792300b..4b5c4f075 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -798,9 +798,14 @@ mrvl_dev_start(struct rte_eth_dev *dev) priv->pp_id, priv->ppio_id); priv->ppio_params.match = match; priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH; - if (mrvl_cfg) + priv->forward_bad_frames = 0; + + if (mrvl_cfg) { priv->ppio_params.eth_start_hdr = mrvl_cfg->port[dev->data->port_id].eth_start_hdr; + priv->forward_bad_frames = + mrvl_cfg->port[dev->data->port_id].forward_bad_frames; + } /* * Calculate the minimum bpool size for refill feature as follows: @@ -2709,7 +2714,8 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) /* drop packet in case of mac, overrun or resource error */ status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); - if (unlikely(status != PP2_DESC_ERR_OK)) { + if ((unlikely(status != PP2_DESC_ERR_OK)) && + !(q->priv->forward_bad_frames)) { struct pp2_buff_inf binf = { .addr = rte_mbuf_data_iova_default(mbuf), .cookie = (uint64_t)mbuf, diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index 148f2acba..2c1c159b9 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -182,6 +182,8 @@ struct mrvl_priv { LIST_HEAD(shaper_profiles, mrvl_tm_shaper_profile) shaper_profiles; LIST_HEAD(nodes, mrvl_tm_node) nodes; uint64_t rate_max; + + uint8_t forward_bad_frames; }; /** Flow operations forward declaration. */ diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index 10e8636b4..f3936aec4 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -76,6 +76,8 @@ #define MRVL_TOK_PARSER_UDF_PROTO_UDP "udp" #define MRVL_TOK_PARSER_UDF_FIELD_UDP_DPORT "dport" +/* paser forward bad frames tokens */ +#define MRVL_TOK_FWD_BAD_FRAMES "forward_bad_frames" /** Number of tokens in range a-b = 2. */ #define MAX_RNG_TOKENS 2 @@ -872,6 +874,21 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) return -1; } } + + /* Parse forward bad frames option */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_FWD_BAD_FRAMES); + if (entry) { + if (get_val_securely(entry, &val) < 0) { + MRVL_LOG(ERR, + "Error in parsing %s value (%s)!\n", + MRVL_TOK_FWD_BAD_FRAMES, entry); + return -1; + } + (*cfg)->port[n].forward_bad_frames = (uint8_t)val; + } else { + (*cfg)->port[n].forward_bad_frames = 0; + } } return 0; diff --git a/drivers/net/mvpp2/mrvl_qos.h b/drivers/net/mvpp2/mrvl_qos.h index daf4776ec..f2e341c37 100644 --- a/drivers/net/mvpp2/mrvl_qos.h +++ b/drivers/net/mvpp2/mrvl_qos.h @@ -48,6 +48,7 @@ struct mrvl_cfg { uint8_t use_global_defaults; struct pp2_cls_plcr_params policer_params; uint8_t setup_policer; + uint8_t forward_bad_frames; } port[RTE_MAX_ETHPORTS]; }; From patchwork Wed Dec 2 10:12:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84710 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB984A04DB; Wed, 2 Dec 2020 11:24:43 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DA1ABCB83; Wed, 2 Dec 2020 11:13:36 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 22659CC48 for ; Wed, 2 Dec 2020 11:13:34 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAKQr024174 for ; Wed, 2 Dec 2020 02:13:30 -0800 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 355w509r73-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 02 Dec 2020 02:13:28 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Dec 2020 02:13:26 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:24 -0800 From: To: CC: , Dana Vardi , Liron Himi Date: Wed, 2 Dec 2020 12:12:11 +0200 Message-ID: <20201202101212.4717-38-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 37/38] net/mvpp2: update qos defaults parameter name X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dana Vardi 'global_default' is only being used for 'qos' so adding 'qos' into its name Signed-off-by: Dana Vardi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Dana Vardi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 2 +- drivers/net/mvpp2/mrvl_qos.c | 12 ++++++------ drivers/net/mvpp2/mrvl_qos.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 4b5c4f075..ca94805fb 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -902,7 +902,7 @@ mrvl_dev_start(struct rte_eth_dev *dev) /* For default QoS config, don't start classifier. */ if (mrvl_cfg && - mrvl_cfg->port[dev->data->port_id].use_global_defaults == 0) { + mrvl_cfg->port[dev->data->port_id].use_qos_global_defaults == 0) { ret = mrvl_start_qos_mapping(priv); if (ret) { MRVL_LOG(ERR, "Failed to setup QoS mapping"); diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index f3936aec4..d9af07c3d 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -321,7 +321,7 @@ parse_tc_cfg(struct rte_cfgfile *file, int port, int tc, if (rte_cfgfile_num_sections(file, sec_name, strlen(sec_name)) <= 0) return 0; - cfg->port[port].use_global_defaults = 0; + cfg->port[port].use_qos_global_defaults = 0; entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_RXQ); if (entry) { n = get_entry_values(entry, @@ -718,7 +718,7 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) MRVL_TOK_PORT, n, MRVL_TOK_DEFAULT); /* Use global defaults, unless an override occurs */ - (*cfg)->port[n].use_global_defaults = 1; + (*cfg)->port[n].use_qos_global_defaults = 1; /* Skip ports non-existing in configuration. */ if (rte_cfgfile_num_sections(file, sec_name, @@ -796,7 +796,7 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_MAPPING_PRIORITY); if (entry) { - (*cfg)->port[n].use_global_defaults = 0; + (*cfg)->port[n].use_qos_global_defaults = 0; if (!strncmp(entry, MRVL_TOK_VLAN_IP, sizeof(MRVL_TOK_VLAN_IP))) (*cfg)->port[n].mapping_priority = @@ -828,7 +828,7 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) entry = rte_cfgfile_get_entry(file, sec_name, MRVL_TOK_PLCR_DEFAULT); if (entry) { - (*cfg)->port[n].use_global_defaults = 0; + (*cfg)->port[n].use_qos_global_defaults = 0; if (get_val_securely(entry, &val) < 0) return -1; @@ -867,7 +867,7 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) return -1; (*cfg)->port[n].default_tc = (uint8_t)val; } else { - if ((*cfg)->port[n].use_global_defaults == 0) { + if ((*cfg)->port[n].use_qos_global_defaults == 0) { MRVL_LOG(ERR, "Default Traffic Class required in " "custom configuration!"); @@ -984,7 +984,7 @@ mrvl_configure_rxqs(struct mrvl_priv *priv, uint16_t portid, size_t i, tc; if (mrvl_cfg == NULL || - mrvl_cfg->port[portid].use_global_defaults) { + mrvl_cfg->port[portid].use_qos_global_defaults) { /* * No port configuration, use default: 1 TC, no QoS, * TC color set to green. diff --git a/drivers/net/mvpp2/mrvl_qos.h b/drivers/net/mvpp2/mrvl_qos.h index f2e341c37..763130bf1 100644 --- a/drivers/net/mvpp2/mrvl_qos.h +++ b/drivers/net/mvpp2/mrvl_qos.h @@ -45,7 +45,7 @@ struct mrvl_cfg { uint16_t inqs; uint16_t outqs; uint8_t default_tc; - uint8_t use_global_defaults; + uint8_t use_qos_global_defaults; struct pp2_cls_plcr_params policer_params; uint8_t setup_policer; uint8_t forward_bad_frames; From patchwork Wed Dec 2 10:12:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liron Himi X-Patchwork-Id: 84711 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 849D9A04DB; Wed, 2 Dec 2020 11:25:01 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 64237CC54; Wed, 2 Dec 2020 11:13:38 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id BE74CCC48 for ; Wed, 2 Dec 2020 11:13:35 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0B2AAT4m024223 for ; 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Wed, 2 Dec 2020 02:13:28 -0800 Received: from pt-lxl0023.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Dec 2020 02:13:27 -0800 From: To: CC: , Dana Vardi , Liron Himi Date: Wed, 2 Dec 2020 12:12:12 +0200 Message-ID: <20201202101212.4717-39-lironh@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202101212.4717-1-lironh@marvell.com> References: <20201202101212.4717-1-lironh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-02_04:2020-11-30, 2020-12-02 signatures=0 Subject: [dpdk-dev] [PATCH v1 38/38] net/mvpp2: add fill_bpool_buffs to cfg file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Dana Vardi extend config file with 'fill_bpool_buffs' which control the amount of refill buffers Signed-off-by: Dana Vardi Reviewed-by: Liron Himi Reviewed-by: Michael Shamis Signed-off-by: Dana Vardi Reviewed-by: Liron Himi --- drivers/net/mvpp2/mrvl_ethdev.c | 7 ++++--- drivers/net/mvpp2/mrvl_ethdev.h | 3 +++ drivers/net/mvpp2/mrvl_qos.c | 21 +++++++++++++++++++++ drivers/net/mvpp2/mrvl_qos.h | 1 + 4 files changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index ca94805fb..725ecced4 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -52,8 +52,6 @@ #define MRVL_IFACE_NAME_ARG "iface" #define MRVL_CFG_ARG "cfg" -#define MRVL_BURST_SIZE 64 - #define MRVL_ARP_LENGTH 28 #define MRVL_COOKIE_ADDR_INVALID ~0ULL @@ -799,12 +797,15 @@ mrvl_dev_start(struct rte_eth_dev *dev) priv->ppio_params.match = match; priv->ppio_params.eth_start_hdr = PP2_PPIO_HDR_ETH; priv->forward_bad_frames = 0; + priv->fill_bpool_buffs = MRVL_BURST_SIZE; if (mrvl_cfg) { priv->ppio_params.eth_start_hdr = mrvl_cfg->port[dev->data->port_id].eth_start_hdr; priv->forward_bad_frames = mrvl_cfg->port[dev->data->port_id].forward_bad_frames; + priv->fill_bpool_buffs = + mrvl_cfg->port[dev->data->port_id].fill_bpool_buffs; } /* @@ -2754,7 +2755,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) if (unlikely(num <= q->priv->bpool_min_size || (!rx_done && num < q->priv->bpool_init_size))) { - ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE); + ret = mrvl_fill_bpool(q, q->priv->fill_bpool_buffs); if (ret) MRVL_LOG(DEBUG, "Failed to fill bpool"); } else if (unlikely(num > q->priv->bpool_max_size)) { diff --git a/drivers/net/mvpp2/mrvl_ethdev.h b/drivers/net/mvpp2/mrvl_ethdev.h index 2c1c159b9..fc4f3b799 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.h +++ b/drivers/net/mvpp2/mrvl_ethdev.h @@ -82,6 +82,8 @@ /** Maximum length of a match string */ #define MRVL_MATCH_LEN 16 +#define MRVL_BURST_SIZE 64 + /** PMD-specific definition of a flow rule handle. */ struct mrvl_mtr; struct rte_flow { @@ -184,6 +186,7 @@ struct mrvl_priv { uint64_t rate_max; uint8_t forward_bad_frames; + uint32_t fill_bpool_buffs; }; /** Flow operations forward declaration. */ diff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c index d9af07c3d..8a6ad5d3b 100644 --- a/drivers/net/mvpp2/mrvl_qos.c +++ b/drivers/net/mvpp2/mrvl_qos.c @@ -79,6 +79,9 @@ /* paser forward bad frames tokens */ #define MRVL_TOK_FWD_BAD_FRAMES "forward_bad_frames" +/* parse fill bpool buffers tokens */ +#define MRVL_TOK_FILL_BPOOL_BUFFS "fill_bpool_buffs" + /** Number of tokens in range a-b = 2. */ #define MAX_RNG_TOKENS 2 @@ -720,6 +723,11 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) /* Use global defaults, unless an override occurs */ (*cfg)->port[n].use_qos_global_defaults = 1; + /* Set non-zero defaults before the decision to continue to next + * port or to parse the port section in config file + */ + (*cfg)->port[n].fill_bpool_buffs = MRVL_BURST_SIZE; + /* Skip ports non-existing in configuration. */ if (rte_cfgfile_num_sections(file, sec_name, strlen(sec_name)) <= 0) { @@ -889,6 +897,19 @@ mrvl_get_cfg(const char *key __rte_unused, const char *path, void *extra_args) } else { (*cfg)->port[n].forward_bad_frames = 0; } + + /* Parse fill bpool buffs option */ + entry = rte_cfgfile_get_entry(file, sec_name, + MRVL_TOK_FILL_BPOOL_BUFFS); + if (entry) { + if (get_val_securely(entry, &val) < 0) { + MRVL_LOG(ERR, + "Error in parsing %s value (%s)!\n", + MRVL_TOK_FILL_BPOOL_BUFFS, entry); + return -1; + } + (*cfg)->port[n].fill_bpool_buffs = val; + } } return 0; diff --git a/drivers/net/mvpp2/mrvl_qos.h b/drivers/net/mvpp2/mrvl_qos.h index 763130bf1..38ea309ca 100644 --- a/drivers/net/mvpp2/mrvl_qos.h +++ b/drivers/net/mvpp2/mrvl_qos.h @@ -49,6 +49,7 @@ struct mrvl_cfg { struct pp2_cls_plcr_params policer_params; uint8_t setup_policer; uint8_t forward_bad_frames; + uint32_t fill_bpool_buffs; } port[RTE_MAX_ETHPORTS]; };