From patchwork Thu Oct 22 07:50:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankur Dwivedi X-Patchwork-Id: 81737 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D1E0A04DD; Thu, 22 Oct 2020 09:50:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F323972F3; Thu, 22 Oct 2020 09:50:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 426D372F1 for ; Thu, 22 Oct 2020 09:50:46 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09M7eq3i009585; Thu, 22 Oct 2020 00:50:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=fHfAMuSDZMhap/lhrtBNAmtJOfZYOfDN0eGBhNmQIXA=; b=LhrX2HUbGZtH4ybv2oH/bbAkgiuwnZDcpzIsCkm9og0bcNOJijsWDVi8crjizQN1P7pV So7sqHPnW03XxlSaamOxf07IJEMOqDPH5a0lRUwqAR1/v2q8BzF9RG3yrWxCK4ycnalP 7IItFqiu01CJ1rjAo/O8UsFcFbXqvLC7aSBzwSPzq7MYkbtgYzYNaeVLRv4A0RgaXhJL fE2Af6D5qDjei77XiMj9UFvAtl3fatGKD4KwT3zd+LBtWj+da3q1gvyfaDx4zBk9CHUy qYpo3bsQZhMrO89fYhEA9l7AIp2KSsEcqrYrpTqufX6f8z2KdhuptsSGRlcBjsyc8Wwv /Q== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 34asbe2cd8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 22 Oct 2020 00:50:44 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 00:50:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 00:50:43 -0700 Received: from hyd1349.t110.caveonetworks.com (unknown [10.29.45.13]) by maili.marvell.com (Postfix) with ESMTP id 8D2FF3F7041; Thu, 22 Oct 2020 00:50:38 -0700 (PDT) From: Ankur Dwivedi To: CC: , , , "Ankur Dwivedi" Date: Thu, 22 Oct 2020 13:20:00 +0530 Message-ID: <20201022075000.18940-1-adwivedi@marvell.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-22_02:2020-10-20, 2020-10-22 signatures=0 Subject: [dpdk-dev] [PATCH 20.11] crypto/octeontx2: fix for multi process X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" During crypto device probe few functions should be called only for the primary process. This patch fixes this issue. Fixes: 818d138bcce9 ("crypto/octeontx2: add init sequence in probe") Signed-off-by: Ankur Dwivedi Reviewed-by: Anoob Joseph --- drivers/crypto/octeontx2/otx2_cryptodev.c | 57 +++++++++++-------- drivers/crypto/octeontx2/otx2_cryptodev.h | 2 + drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 13 ++++- 3 files changed, 44 insertions(+), 28 deletions(-) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index 02d2fd83b..1de04f4a6 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -70,36 +70,39 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, otx2_dev = &vf->otx2_dev; - /* Initialize the base otx2_dev object */ - ret = otx2_dev_init(pci_dev, otx2_dev); - if (ret) { - CPT_LOG_ERR("Could not initialize otx2_dev"); - goto pmd_destroy; - } + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + /* Initialize the base otx2_dev object */ + ret = otx2_dev_init(pci_dev, otx2_dev); + if (ret) { + CPT_LOG_ERR("Could not initialize otx2_dev"); + goto pmd_destroy; + } - /* Get number of queues available on the device */ - ret = otx2_cpt_available_queues_get(dev, &nb_queues); - if (ret) { - CPT_LOG_ERR("Could not determine the number of queues available"); - goto otx2_dev_fini; - } + /* Get number of queues available on the device */ + ret = otx2_cpt_available_queues_get(dev, &nb_queues); + if (ret) { + CPT_LOG_ERR("Could not determine the number of queues available"); + goto otx2_dev_fini; + } - /* Don't exceed the limits set per VF */ - nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF); + /* Don't exceed the limits set per VF */ + nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF); - if (nb_queues == 0) { - CPT_LOG_ERR("No free queues available on the device"); - goto otx2_dev_fini; - } + if (nb_queues == 0) { + CPT_LOG_ERR("No free queues available on the device"); + goto otx2_dev_fini; + } - vf->max_queues = nb_queues; + vf->max_queues = nb_queues; - CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues); + CPT_LOG_INFO("Max queues supported by device: %d", + vf->max_queues); - ret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps); - if (ret) { - CPT_LOG_ERR("Could not determine hardware capabilities"); - goto otx2_dev_fini; + ret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps); + if (ret) { + CPT_LOG_ERR("Could not determine hardware capabilities"); + goto otx2_dev_fini; + } } otx2_crypto_capabilities_init(vf->hw_caps); @@ -121,10 +124,14 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, RTE_CRYPTODEV_FF_SYM_SESSIONLESS | RTE_CRYPTODEV_FF_SECURITY; + if (rte_eal_process_type() == RTE_PROC_SECONDARY) + otx2_cpt_set_enqdeq_fns(dev); + return 0; otx2_dev_fini: - otx2_dev_fini(pci_dev, otx2_dev); + if (rte_eal_process_type() == RTE_PROC_PRIMARY) + otx2_dev_fini(pci_dev, otx2_dev); pmd_destroy: rte_cryptodev_pmd_destroy(dev); exit: diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h index 7b1b64863..febb4ee74 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev.h @@ -51,4 +51,6 @@ extern int otx2_cpt_logtype; */ extern uint8_t otx2_cryptodev_driver_id; +void otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev); + #endif /* _OTX2_CRYPTODEV_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index 790af02dc..be37d3cac 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -1019,6 +1019,15 @@ otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) return nb_completed; } +void +otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev) +{ + dev->enqueue_burst = otx2_cpt_enqueue_burst; + dev->dequeue_burst = otx2_cpt_dequeue_burst; + + rte_mb(); +} + /* PMD ops */ static int @@ -1081,10 +1090,8 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev, goto intr_unregister; } - dev->enqueue_burst = otx2_cpt_enqueue_burst; - dev->dequeue_burst = otx2_cpt_dequeue_burst; + otx2_cpt_set_enqdeq_fns(dev); - rte_mb(); return 0; intr_unregister: