From patchwork Thu Oct 15 10:37:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80857 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EB9CBA04DB; Thu, 15 Oct 2020 12:38:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D24F51DEA5; Thu, 15 Oct 2020 12:38:25 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 59F491DE95 for ; Thu, 15 Oct 2020 12:38:23 +0200 (CEST) IronPort-SDR: rYttuRdzwgbVwxJE7WrwTT4JD+iHaVx7rYidFBBwDc5erM/tSRGwDfAvzD4uBtNzZZM102asNs 1lo1M1pkUUEw== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964228" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964228" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:22 -0700 IronPort-SDR: G5uTBgPqcX7KL43wOcxTXEEiq1nICAHTv05a2DlVfVN2Swis96snKkZE3Sr4xBPjAEC7x9JELv np6Gbiy/0F3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728497" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:18 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Honnappa Nagarahalli , Dmitry Kozlyuk , Narcisa Ana Maria Vasile , Dmitry Malloy , Pallavi Kadam , Ray Kinsella , Neil Horman Date: Thu, 15 Oct 2020 11:37:57 +0100 Message-Id: <20201015103814.253636-2-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 01/18] eal: add max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds a max SIMD bitwidth EAL configuration. The API allows for an app to set this value. It can also be set using EAL argument --force-max-simd-bitwidth, which will lock the value and override any modifications made by the app. Each arch has a define for the default SIMD bitwidth value, this is used on EAL init to set the config max SIMD bitwidth. Cc: Ruifeng Wang Cc: Jerin Jacob Cc: Honnappa Nagarahalli Cc: David Christensen Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev Reviewed-by: Ruifeng Wang --- v4: - Used RTE_SIMD_MAX instead of UINT16_MAX. - Renamed enums to better reflect usage. - Added functions to windows symbol export file. - Modified Doxygen comments. - Modified enum name. - Changed RTE_SIMD_MAX value to a power of 2. - Merged patch 2 into this patch. - Enum now used for default value defines. - Fixed some small comments on v3. v3: - Added enum value to essentially disable using max SIMD to choose paths, intended for use by ARM SVE. - Fixed parsing bitwidth argument to return an error for values greater than uint16_t. - Removed unnecessary define in generic rte_vect.h - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE. v2: - Added to Doxygen comment for API. - Changed default bitwidth for Arm to 128. --- lib/librte_eal/arm/include/rte_vect.h | 2 + lib/librte_eal/common/eal_common_options.c | 66 ++++++++++++++++++++++ lib/librte_eal/common/eal_internal_cfg.h | 8 +++ lib/librte_eal/common/eal_options.h | 2 + lib/librte_eal/include/rte_eal.h | 40 +++++++++++++ lib/librte_eal/ppc/include/rte_vect.h | 2 + lib/librte_eal/rte_eal_exports.def | 2 + lib/librte_eal/rte_eal_version.map | 2 + lib/librte_eal/x86/include/rte_vect.h | 2 + 9 files changed, 126 insertions(+) diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h index f6a455b4e7..df8fb8b670 100644 --- a/lib/librte_eal/arm/include/rte_vect.h +++ b/lib/librte_eal/arm/include/rte_vect.h @@ -14,6 +14,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_MAX + typedef int32x4_t xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c index a5426e1234..8c79f1b2fc 100644 --- a/lib/librte_eal/common/eal_common_options.c +++ b/lib/librte_eal/common/eal_common_options.c @@ -35,6 +35,7 @@ #ifndef RTE_EXEC_ENV_WINDOWS #include #endif +#include #include "eal_internal_cfg.h" #include "eal_options.h" @@ -102,6 +103,7 @@ eal_long_options[] = { {OPT_MATCH_ALLOCATIONS, 0, NULL, OPT_MATCH_ALLOCATIONS_NUM}, {OPT_TELEMETRY, 0, NULL, OPT_TELEMETRY_NUM }, {OPT_NO_TELEMETRY, 0, NULL, OPT_NO_TELEMETRY_NUM }, + {OPT_FORCE_MAX_SIMD_BITWIDTH, 1, NULL, OPT_FORCE_MAX_SIMD_BITWIDTH_NUM}, {0, 0, NULL, 0 } }; @@ -343,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg) internal_cfg->user_mbuf_pool_ops_name = NULL; CPU_ZERO(&internal_cfg->ctrl_cpuset); internal_cfg->init_complete = 0; + internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH; + internal_cfg->max_simd_bitwidth.forced = 0; } static int @@ -1309,6 +1313,34 @@ eal_parse_iova_mode(const char *name) return 0; } +static int +eal_parse_simd_bitwidth(const char *arg) +{ + char *end; + unsigned long bitwidth; + int ret; + struct internal_config *internal_conf = + eal_get_internal_configuration(); + + if (arg == NULL || arg[0] == '\0') + return -1; + + errno = 0; + bitwidth = strtoul(arg, &end, 0); + + /* check for errors */ + if (errno != 0 || end == NULL || *end != '\0' || bitwidth > RTE_SIMD_MAX) + return -1; + + if (bitwidth == 0) + bitwidth = (unsigned long) RTE_SIMD_MAX; + ret = rte_set_max_simd_bitwidth(bitwidth); + if (ret < 0) + return -1; + internal_conf->max_simd_bitwidth.forced = 1; + return 0; +} + static int eal_parse_base_virtaddr(const char *arg) { @@ -1707,6 +1739,13 @@ eal_parse_common_option(int opt, const char *optarg, case OPT_NO_TELEMETRY_NUM: conf->no_telemetry = 1; break; + case OPT_FORCE_MAX_SIMD_BITWIDTH_NUM: + if (eal_parse_simd_bitwidth(optarg) < 0) { + RTE_LOG(ERR, EAL, "invalid parameter for --" + OPT_FORCE_MAX_SIMD_BITWIDTH "\n"); + return -1; + } + break; /* don't know what to do, leave this to caller */ default: @@ -1903,6 +1942,32 @@ eal_check_common_options(struct internal_config *internal_cfg) return 0; } +uint16_t +rte_get_max_simd_bitwidth(void) +{ + const struct internal_config *internal_conf = + eal_get_internal_configuration(); + return internal_conf->max_simd_bitwidth.bitwidth; +} + +int +rte_set_max_simd_bitwidth(uint16_t bitwidth) +{ + struct internal_config *internal_conf = + eal_get_internal_configuration(); + if (internal_conf->max_simd_bitwidth.forced) { + RTE_LOG(NOTICE, EAL, "Cannot set max SIMD bitwidth - user runtime override enabled"); + return -EPERM; + } + + if (bitwidth < RTE_SIMD_DISABLED || !rte_is_power_of_2(bitwidth)) { + RTE_LOG(ERR, EAL, "Invalid bitwidth value!\n"); + return -EINVAL; + } + internal_conf->max_simd_bitwidth.bitwidth = bitwidth; + return 0; +} + void eal_common_usage(void) { @@ -1981,6 +2046,7 @@ eal_common_usage(void) " --"OPT_BASE_VIRTADDR" Base virtual address\n" " --"OPT_TELEMETRY" Enable telemetry support (on by default)\n" " --"OPT_NO_TELEMETRY" Disable telemetry support\n" + " --"OPT_FORCE_MAX_SIMD_BITWIDTH" Force the max SIMD bitwidth\n" "\nEAL options for DEBUG use only:\n" " --"OPT_HUGE_UNLINK" Unlink hugepage files after init\n" " --"OPT_NO_HUGE" Use malloc instead of hugetlbfs\n" diff --git a/lib/librte_eal/common/eal_internal_cfg.h b/lib/librte_eal/common/eal_internal_cfg.h index de627c7627..51dbe86e2b 100644 --- a/lib/librte_eal/common/eal_internal_cfg.h +++ b/lib/librte_eal/common/eal_internal_cfg.h @@ -33,6 +33,12 @@ struct hugepage_info { int lock_descriptor; /**< file descriptor for hugepage dir */ }; +struct simd_bitwidth { + bool forced; + /**< flag indicating if bitwidth is forced and can't be modified */ + uint16_t bitwidth; /**< bitwidth value */ +}; + /** * internal configuration */ @@ -85,6 +91,8 @@ struct internal_config { volatile unsigned int init_complete; /**< indicates whether EAL has completed initialization */ unsigned int no_telemetry; /**< true to disable Telemetry */ + struct simd_bitwidth max_simd_bitwidth; + /**< max simd bitwidth path to use */ }; void eal_reset_internal_config(struct internal_config *internal_cfg); diff --git a/lib/librte_eal/common/eal_options.h b/lib/librte_eal/common/eal_options.h index 89769d48b4..ef33979664 100644 --- a/lib/librte_eal/common/eal_options.h +++ b/lib/librte_eal/common/eal_options.h @@ -85,6 +85,8 @@ enum { OPT_TELEMETRY_NUM, #define OPT_NO_TELEMETRY "no-telemetry" OPT_NO_TELEMETRY_NUM, +#define OPT_FORCE_MAX_SIMD_BITWIDTH "force-max-simd-bitwidth" + OPT_FORCE_MAX_SIMD_BITWIDTH_NUM, OPT_LONG_MAX_NUM }; diff --git a/lib/librte_eal/include/rte_eal.h b/lib/librte_eal/include/rte_eal.h index e3c2ef185e..706d3cca5a 100644 --- a/lib/librte_eal/include/rte_eal.h +++ b/lib/librte_eal/include/rte_eal.h @@ -43,6 +43,23 @@ enum rte_proc_type_t { RTE_PROC_INVALID }; +/** + * The max SIMD bitwidth value to limit vector path selection. + */ +enum rte_max_simd { + RTE_SIMD_DISABLED = 64, + /**< Limits path selection to scalar, disables all vector paths. */ + RTE_SIMD_128 = 128, + /**< Limits path selection to SSE/NEON/Altivec or below. */ + RTE_SIMD_256 = 256, /**< Limits path selection to AVX2 or below. */ + RTE_SIMD_512 = 512, /**< Limits path selection to AVX512 or below. */ + RTE_SIMD_MAX = INT16_MAX + 1, + /**< + * Disables limiting by max SIMD bitwidth, allows all suitable paths. + * This value is used as it is a large number and a power of 2. + */ +}; + /** * Get the process type in a multi-process setup * @@ -51,6 +68,29 @@ enum rte_proc_type_t { */ enum rte_proc_type_t rte_eal_process_type(void); +/** + * Get the supported SIMD bitwidth. + * + * @return + * uint16_t bitwidth. + */ +__rte_experimental +uint16_t rte_get_max_simd_bitwidth(void); + +/** + * Set the supported SIMD bitwidth. + * This API should only be called once at initialization, before EAL init. + * + * @param bitwidth + * uint16_t bitwidth. + * @return + * - 0 on success. + * - -EINVAL on invalid bitwidth parameter. + * - -EPERM if bitwidth is forced. + */ +__rte_experimental +int rte_set_max_simd_bitwidth(uint16_t bitwidth); + /** * Request iopl privilege for all RPL. * diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h index b0545c878c..a69aabc568 100644 --- a/lib/librte_eal/ppc/include/rte_vect.h +++ b/lib/librte_eal/ppc/include/rte_vect.h @@ -15,6 +15,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_256 + typedef vector signed int xmm_t; #define XMM_SIZE (sizeof(xmm_t)) diff --git a/lib/librte_eal/rte_eal_exports.def b/lib/librte_eal/rte_eal_exports.def index 16f8e33874..3516aacfe4 100644 --- a/lib/librte_eal/rte_eal_exports.def +++ b/lib/librte_eal/rte_eal_exports.def @@ -60,6 +60,7 @@ EXPORTS rte_exit rte_free rte_get_master_lcore + rte_get_max_simd_bitwidth rte_get_next_lcore rte_get_tsc_hz rte_hexdump @@ -148,6 +149,7 @@ EXPORTS rte_service_set_stats_enable rte_service_start_with_defaults rte_set_application_usage_hook + rte_set_max_simd_bitwidth rte_socket_count rte_socket_id rte_socket_id_by_idx diff --git a/lib/librte_eal/rte_eal_version.map b/lib/librte_eal/rte_eal_version.map index a93dea9fe6..714be49377 100644 --- a/lib/librte_eal/rte_eal_version.map +++ b/lib/librte_eal/rte_eal_version.map @@ -400,6 +400,8 @@ EXPERIMENTAL { # added in 20.11 __rte_eal_trace_generic_size_t; rte_service_lcore_may_be_active; + rte_get_max_simd_bitwidth; + rte_set_max_simd_bitwidth; }; INTERNAL { diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h index 64383c3606..f0aad9615e 100644 --- a/lib/librte_eal/x86/include/rte_vect.h +++ b/lib/librte_eal/x86/include/rte_vect.h @@ -36,6 +36,8 @@ extern "C" { #endif +#define RTE_DEFAULT_SIMD_BITWIDTH RTE_SIMD_256 + typedef __m128i xmm_t; #define XMM_SIZE (sizeof(xmm_t)) From patchwork Thu Oct 15 10:37:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80858 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 01146A04DB; Thu, 15 Oct 2020 12:39:06 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 499E11DEB3; Thu, 15 Oct 2020 12:38:28 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 1B7881DE8A for ; Thu, 15 Oct 2020 12:38:26 +0200 (CEST) IronPort-SDR: V4RU2UsRZptqOJSfG/rgUpOF04o/gx8nY/uuR3xfexU9CdZTKOv1/b9yknDVm19474cuVGpn6n jAu7/2X3/Fmg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964234" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964234" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:25 -0700 IronPort-SDR: U6oJBa1K9UjuKxBbPtbH+dq3sTqEIzCBzv2l2xR6Y+hkPtCVOZSaQNuMlzXjszTlJjulUHWR2H qPFa87k6chzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728502" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:22 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Anatoly Burakov , John McNamara , Marko Kovacevic Date: Thu, 15 Oct 2020 11:37:58 +0100 Message-Id: <20201015103814.253636-3-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 02/18] doc: add detail on using max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds documentation on the usage of the max SIMD bitwidth EAL setting, and how to use it to enable AVX-512 at runtime. Cc: Anatoly Burakov Cc: John McNamara Cc: Marko Kovacevic Signed-off-by: Ciara Power Acked-by: Kevin Laatz --- v6: Updated enum value. v4: Updated docs to reflect renamed enum. v3: - Added enum value for disabling use of max SIMD to doc. - Added entry to HowTo index. --- doc/guides/howto/avx512.rst | 36 +++++++++++++++++++ doc/guides/howto/index.rst | 1 + doc/guides/linux_gsg/eal_args.include.rst | 16 +++++++++ .../prog_guide/env_abstraction_layer.rst | 32 +++++++++++++++++ 4 files changed, 85 insertions(+) create mode 100644 doc/guides/howto/avx512.rst diff --git a/doc/guides/howto/avx512.rst b/doc/guides/howto/avx512.rst new file mode 100644 index 0000000000..6eb3755775 --- /dev/null +++ b/doc/guides/howto/avx512.rst @@ -0,0 +1,36 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2020 Intel Corporation. + + +Using AVX-512 with DPDK +======================= + +AVX-512 is not used by default in DPDK, but it can be selected at runtime by apps through the use of EAL API, +and by the user with a commandline argument. DPDK has a setting for max SIMD bitwidth, +which can be modified and will then limit the vector path taken by the code. + + +Using the API in apps +--------------------- + +Apps can request DPDK uses AVX-512 at runtime, if it provides improved application performance. +This can be done by modifying the EAL setting for max SIMD bitwidth to 512, as by default it is 256, +which does not allow for AVX-512. + +.. code-block:: c + + rte_set_max_simd_bitwidth(RTE_SIMD_512); + +This API should only be called once at initialization, before EAL init. +For more information on the possible enum values to use as a parameter, go to :ref:`max_simd_bitwidth`: + + +Using the command-line argument +--------------------------------------------- + +The user can select to use AVX-512 at runtime, using the following argument to set the max bitwidth:: + + ./app/dpdk-testpmd --force-max-simd-bitwidth=512 + +This will override any further changes to the max SIMD bitwidth in DPDK, +which is useful for testing purposes. diff --git a/doc/guides/howto/index.rst b/doc/guides/howto/index.rst index 5a97ea508c..c2a2c60ddb 100644 --- a/doc/guides/howto/index.rst +++ b/doc/guides/howto/index.rst @@ -20,3 +20,4 @@ HowTo Guides telemetry debug_troubleshoot openwrt + avx512 diff --git a/doc/guides/linux_gsg/eal_args.include.rst b/doc/guides/linux_gsg/eal_args.include.rst index 0fe4457968..a0bfbd1a98 100644 --- a/doc/guides/linux_gsg/eal_args.include.rst +++ b/doc/guides/linux_gsg/eal_args.include.rst @@ -210,3 +210,19 @@ Other options * ``--no-telemetry``: Disable telemetry. + +* ``--force-max-simd-bitwidth=``: + + Specify the maximum SIMD bitwidth size to handle. This limits which vector paths, + if any, are taken, as any paths taken must use a bitwidth below the max bitwidth limit. + For example, to allow all SIMD bitwidths up to and including AVX-512:: + + --force-max-simd-bitwidth=512 + + The following example shows limiting the bitwidth to 64-bits to disable all vector code:: + + --force-max-simd-bitwidth=64 + + To disable use of max SIMD bitwidth limit:: + + --force-max-simd-bitwidth=0 diff --git a/doc/guides/prog_guide/env_abstraction_layer.rst b/doc/guides/prog_guide/env_abstraction_layer.rst index 936c885081..90e43d2c1f 100644 --- a/doc/guides/prog_guide/env_abstraction_layer.rst +++ b/doc/guides/prog_guide/env_abstraction_layer.rst @@ -486,6 +486,38 @@ the desired addressing mode when virtual devices that are not directly attached To facilitate forcing the IOVA mode to a specific value the EAL command line option ``--iova-mode`` can be used to select either physical addressing('pa') or virtual addressing('va'). +.. _max_simd_bitwidth: + + +Max SIMD bitwidth +~~~~~~~~~~~~~~~~~ + +The EAL provides a single setting to limit the max SIMD bitwidth used by DPDK, +which is used in determining the vector path, if any, chosen by a component. +The value can be set at runtime by an application using the 'rte_set_max_simd_bitwidth(uint16_t bitwidth)' function, +which should only be called once at initialization, before EAL init. +The value can be overridden by the user using the EAL command-line option '--force-max-simd-bitwidth'. + +When choosing a vector path, along with checking the CPU feature support, +the value of the max SIMD bitwidth must also be checked, and can be retrieved using the 'rte_get_max_simd_bitwidth()' function. +The value should be compared against the enum values for accepted max SIMD bitwidths: + +.. code-block:: c + + enum rte_max_simd { + RTE_SIMD_DISABLED = 64, + RTE_SIMD_128 = 128, + RTE_SIMD_256 = 256, + RTE_SIMD_512 = 512, + RTE_SIMD_MAX = INT16_MAX + 1, + }; + + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_512) + /* Take AVX-512 vector path */ + else if (rte_get_max_simd_bitwidth() >= RTE_SIMD_256) + /* Take AVX2 vector path */ + + Memory Segments and Memory Zones (memzone) ------------------------------------------ From patchwork Thu Oct 15 10:37:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80859 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4249CA04DB; Thu, 15 Oct 2020 12:39:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3122B1DEC1; Thu, 15 Oct 2020 12:38:32 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 254311DE8A for ; Thu, 15 Oct 2020 12:38:28 +0200 (CEST) IronPort-SDR: O/cSEQI9rwBM7rjYm8jVR54WIoM5VCqiDPQSVCGcNgWFGv+u3vRMhYQGYj9iNZjhcRTbedpqwJ jcVFMloxJTLg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964236" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964236" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:27 -0700 IronPort-SDR: /HeGv7JEatFJZ39aWOxceJ8th3U0iA/3dEfkE60/cIBTf9Rdf7aT2HgvkWNZ0vO5D+9aSMCzui yoNhg7QKZdpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728510" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:25 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Beilei Xing , Jeff Guo Date: Thu, 15 Oct 2020 11:37:59 +0100 Message-Id: <20201015103814.253636-4-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 03/18] net/i40e: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Beilei Xing Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev --- v4: Updated enum names. --- drivers/net/i40e/i40e_rxtx.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index f2844d3f74..925fa9cc69 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -3098,7 +3098,8 @@ static eth_rx_burst_t i40e_get_latest_rx_vec(bool scatter) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3115,7 +3116,8 @@ i40e_get_recommend_rx_vec(bool scatter) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return scatter ? i40e_recv_scattered_pkts_vec_avx2 : i40e_recv_pkts_vec_avx2; #endif @@ -3154,7 +3156,8 @@ i40e_set_rx_function(struct rte_eth_dev *dev) } } - if (ad->rx_vec_allowed) { + if (ad->rx_vec_allowed && rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { /* Vec Rx path */ PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.", dev->data->port_id); @@ -3268,7 +3271,8 @@ static eth_tx_burst_t i40e_get_latest_tx_vec(void) { #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3283,7 +3287,8 @@ i40e_get_recommend_tx_vec(void) * use of AVX2 version to later plaforms, not all those that could * theoretically run it. */ - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) return i40e_xmit_pkts_vec_avx2; #endif return i40e_xmit_pkts_vec; @@ -3311,7 +3316,8 @@ i40e_set_tx_function(struct rte_eth_dev *dev) } if (ad->tx_simple_allowed) { - if (ad->tx_vec_allowed) { + if (ad->tx_vec_allowed && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_INIT_LOG(DEBUG, "Vector tx finally be used."); if (ad->use_latest_vec) dev->tx_pkt_burst = From patchwork Thu Oct 15 10:38:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80860 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7ADC2A04DB; Thu, 15 Oct 2020 12:39:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B0FE01DEC8; Thu, 15 Oct 2020 12:38:34 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 9AB7E1DEB7 for ; Thu, 15 Oct 2020 12:38:30 +0200 (CEST) IronPort-SDR: Zmp7cTozem4BoLc+kI2cHekkHiIbgQhS/KUIrZeba4bqP+gq42Lt3H/4F50IJ+YpGBU1tbITk6 r3s1HYOMy3Ug== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964239" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964239" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:30 -0700 IronPort-SDR: 21oHHf78+zrF94kvE50ZNjdHYb1xpvghbrTiabGc16IO1s985xor4cvdSaTKpFr7dwyCIazp/o oVOzv8Dxb25w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728514" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:28 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Somalapuram Amaranath Date: Thu, 15 Oct 2020 11:38:00 +0100 Message-Id: <20201015103814.253636-5-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 04/18] net/axgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Somalapuram Amaranath Signed-off-by: Ciara Power Acked-by: Amaranath Somalapuram --- v4: Updated enum name. --- drivers/net/axgbe/axgbe_rxtx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index bc93becaa5..5386bd86f8 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -557,7 +557,8 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, if (!pdata->tx_queues) pdata->tx_queues = dev->data->tx_queues; - if (txq->vector_disable) + if (txq->vector_disable || rte_get_max_simd_bitwidth() + < RTE_SIMD_128) dev->tx_pkt_burst = &axgbe_xmit_pkts; else #ifdef RTE_ARCH_X86 From patchwork Thu Oct 15 10:38:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80861 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E0D7FA04DB; Thu, 15 Oct 2020 12:40:12 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 031D81DED0; Thu, 15 Oct 2020 12:38:36 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id D90691DEC5 for ; Thu, 15 Oct 2020 12:38:32 +0200 (CEST) IronPort-SDR: 1wbwCZPoYqIZp6O2S9K1iaoAeaygYWA1PSoPhfyXsJ9DJVBTae37KogkMdHhBY6QJB8ZAba07M TQOwXd0rk3FA== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964240" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964240" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:32 -0700 IronPort-SDR: 5MgYI5ufK3iVNq7PfJv2OTYvBYGWrKboyAzBuUmKduPO0Ibx7RIjMdi9Yuik5A0Wm3pDxJooiC vZejFw1wMuzw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728517" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:30 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Ajit Khaparde , Somnath Kotur Date: Thu, 15 Oct 2020 11:38:01 +0100 Message-Id: <20201015103814.253636-6-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 05/18] net/bnxt: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Ajit Khaparde Cc: Somnath Kotur Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/bnxt/bnxt_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 8b63134c39..07d1a1a6ab 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1169,7 +1169,8 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_VLAN_FILTER)) && - !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) { + !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", eth_dev->data->port_id); bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; @@ -1202,7 +1203,8 @@ bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) */ if (!eth_dev->data->scattered_rx && !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && - !BNXT_TRUFLOW_EN(bp)) { + !BNXT_TRUFLOW_EN(bp) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", eth_dev->data->port_id); return bnxt_xmit_pkts_vec; From patchwork Thu Oct 15 10:38:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80862 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3E6DA04DB; Thu, 15 Oct 2020 12:40:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C8B681DED8; Thu, 15 Oct 2020 12:38:38 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 4DB1B1DECE for ; Thu, 15 Oct 2020 12:38:35 +0200 (CEST) IronPort-SDR: 3vEgFvrjUZkjOceaULnFgBfe2XXsN3Kpk1kF272AwvhEiJtIu7IgPtZBVcxgklI3wrxzM5UCBe OmnIb5uEzkoQ== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964241" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964241" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:34 -0700 IronPort-SDR: dvL2ZujVeL8cYZWob1AEcvptMC6aPANKTISJ5NAiiAm8ML0JtsGsuLLUK6WET+M9E43ksf+tv9 UlngXt5rXWWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728524" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:32 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , John Daley , Hyong Youb Kim Date: Thu, 15 Oct 2020 11:38:02 +0100 Message-Id: <20201015103814.253636-7-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 06/18] net/enic: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: John Daley Cc: Hyong Youb Kim Acked-by: Hyong Youb Kim Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/enic/enic_rxtx_vec_avx2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/enic/enic_rxtx_vec_avx2.c b/drivers/net/enic/enic_rxtx_vec_avx2.c index 676b9f5fdb..75e9172177 100644 --- a/drivers/net/enic/enic_rxtx_vec_avx2.c +++ b/drivers/net/enic/enic_rxtx_vec_avx2.c @@ -821,7 +821,8 @@ enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev) fconf = ð_dev->data->dev_conf.fdir_conf; if (fconf->mode != RTE_FDIR_MODE_NONE) return false; - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) { + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) { ENICPMD_LOG(DEBUG, " use the non-scatter avx2 Rx handler"); eth_dev->rx_pkt_burst = &enic_noscatter_vec_recv_pkts; enic->use_noscatter_vec_rx_handler = 1; From patchwork Thu Oct 15 10:38:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80863 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED525A04DB; Thu, 15 Oct 2020 12:40:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D274F1DEDE; Thu, 15 Oct 2020 12:38:41 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id A0EF71DED4 for ; Thu, 15 Oct 2020 12:38:37 +0200 (CEST) IronPort-SDR: qaJfFFx3JYPNOPDSsRN36/nE0J3l6uYpqi9QiHAT4LScE43E6rXbmAzA//DmoNxM7hz42xW7FG gRWvCNn+8Zcw== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964247" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964247" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:37 -0700 IronPort-SDR: xrdmgAwo7f3FBlQT+0BFQX+rkMLzq69pu1NCRlSz8Cfd6Jsy2SJYt5brihLFxxzMXTL7r+m2Ld +4Nmjss5s7FQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728533" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:35 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Qi Zhang , Xiao Wang Date: Thu, 15 Oct 2020 11:38:03 +0100 Message-Id: <20201015103814.253636-8-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 07/18] net/fm10k: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qi Zhang Cc: Xiao Wang Signed-off-by: Ciara Power Acked-by: Qi Zhang --- v4: Updated enum name. --- drivers/net/fm10k/fm10k_ethdev.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c index c4a6fdf7f0..78c81bf35b 100644 --- a/drivers/net/fm10k/fm10k_ethdev.c +++ b/drivers/net/fm10k/fm10k_ethdev.c @@ -2937,7 +2937,9 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) if (rte_eal_process_type() != RTE_PROC_PRIMARY) { /* primary process has set the ftag flag and offloads */ txq = dev->data->tx_queues[0]; - if (fm10k_tx_vec_condition_check(txq)) { + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() + < RTE_SIMD_128) { dev->tx_pkt_burst = fm10k_xmit_pkts; dev->tx_pkt_prepare = fm10k_prep_pkts; PMD_INIT_LOG(DEBUG, "Use regular Tx func"); @@ -2956,7 +2958,8 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) txq = dev->data->tx_queues[i]; txq->tx_ftag_en = tx_ftag_en; /* Check if Vector Tx is satisfied */ - if (fm10k_tx_vec_condition_check(txq)) + if (fm10k_tx_vec_condition_check(txq) || + rte_get_max_simd_bitwidth() < RTE_SIMD_128) use_sse = 0; } @@ -2990,7 +2993,9 @@ fm10k_set_rx_function(struct rte_eth_dev *dev) * conditions to be met. */ if (!fm10k_rx_vec_condition_check(dev) && - dev_info->rx_vec_allowed && !rx_ftag_en) { + dev_info->rx_vec_allowed && !rx_ftag_en && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { if (dev->data->scattered_rx) dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec; else From patchwork Thu Oct 15 10:38:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80864 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA4C6A04DB; Thu, 15 Oct 2020 12:41:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AB4DF1DEE4; Thu, 15 Oct 2020 12:38:43 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id F27CC1DEDD for ; Thu, 15 Oct 2020 12:38:39 +0200 (CEST) IronPort-SDR: duV/0VLRwsDfotU6sNWTa9UPaOQSRcZN7PirmDqjyaLGCFCXbL5F65H6OTuPvIADOSFodz3b1g DpoA8oS4ishg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964251" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964251" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:39 -0700 IronPort-SDR: KsVT8u+d53KN1DyRRc//tVrNdruDShRD/B4xLGGWIpNNkQqblELv1tn35OPGZtrgRt5A947nVh Xt1jzZRjCe+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728540" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:37 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Jingjing Wu , Beilei Xing Date: Thu, 15 Oct 2020 11:38:04 +0100 Message-Id: <20201015103814.253636-9-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 08/18] net/iavf: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Jingjing Wu Cc: Beilei Xing Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/iavf/iavf_rxtx.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index 1b0efe0433..7c27d5beec 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -2104,14 +2104,16 @@ iavf_set_rx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_rx_vec_dev_check(dev)) { + if (!iavf_rx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; (void)iavf_rxq_vec_setup(rxq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) use_avx2 = true; if (dev->data->scattered_rx) { @@ -2177,7 +2179,8 @@ iavf_set_tx_function(struct rte_eth_dev *dev) int i; bool use_avx2 = false; - if (!iavf_tx_vec_dev_check(dev)) { + if (!iavf_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) { for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; if (!txq) @@ -2185,8 +2188,9 @@ iavf_set_tx_function(struct rte_eth_dev *dev) iavf_txq_vec_setup(txq); } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) use_avx2 = true; PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).", From patchwork Thu Oct 15 10:38:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80865 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7F5C1A04DB; Thu, 15 Oct 2020 12:41:29 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7E4351DEEB; Thu, 15 Oct 2020 12:38:45 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 927851DED4 for ; Thu, 15 Oct 2020 12:38:42 +0200 (CEST) IronPort-SDR: lDSoZmxDFfPEoluSngS6UH9sIeChXYvWgS76B6mtzWoN1z+1lzF+U3PosACgQjB5kHhTNNL44u veyn0QwUrNGg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964257" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964257" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:42 -0700 IronPort-SDR: G6oahwbNScElrlq1ahMQR5ZRKqOUQWc0JkyPxjABS0J3sFx3QJ8uXClVkg4faUnWsbzcsysGZk VOwV/jiHYqYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728545" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:39 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Qiming Yang , Qi Zhang Date: Thu, 15 Oct 2020 11:38:05 +0100 Message-Id: <20201015103814.253636-10-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 09/18] net/ice: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qiming Yang Cc: Qi Zhang Signed-off-by: Ciara Power Acked-by: Qi Zhang --- v4: Updated enum name. --- drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 79e6df11f4..a1a6d4ac56 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -2989,7 +2989,9 @@ ice_set_rx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->rx_vec_allowed = true; for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; @@ -2999,8 +3001,10 @@ ice_set_rx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { @@ -3167,7 +3171,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_tx_vec_dev_check(dev)) { + if (!ice_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->tx_vec_allowed = true; for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; @@ -3177,8 +3183,10 @@ ice_set_tx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { From patchwork Thu Oct 15 10:38:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80866 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C1D4A04DB; Thu, 15 Oct 2020 12:41:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 238A31DEF1; Thu, 15 Oct 2020 12:38:48 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 236961DEB9 for ; Thu, 15 Oct 2020 12:38:44 +0200 (CEST) IronPort-SDR: evOlpbmZhC+B5+2J2BPaPxsIgCTn90O7QHYPneW6nsopmaM8RaVg0HMHudcPZcF4tDCoT5Fn5y JhpmhaaArhOA== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964263" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964263" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:44 -0700 IronPort-SDR: 4ygCuQHR8xh3S70z1J0xyGrxjm/MBEcMfOe9txYpPi3GyudK3P+1dz0aMJatMASQca3/bi0SFL X8kkamBb4mWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728553" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:42 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Wei Zhao , Jeff Guo , Haiyue Wang Date: Thu, 15 Oct 2020 11:38:06 +0100 Message-Id: <20201015103814.253636-11-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 10/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Wei Zhao Cc: Jeff Guo Signed-off-by: Ciara Power Acked-by: Konstantin Ananyev Reviewed-by: Haiyue Wang --- v4: - Updated enum name. - Moved placement of condition check. - Added condition check to tx cleanup path selection. --- drivers/net/ixgbe/ixgbe_rxtx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 29d385c062..3141398e10 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2405,6 +2405,7 @@ ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) #endif txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) { if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || txq->sw_ring_v != NULL)) { return ixgbe_tx_done_cleanup_vec(txq, free_cnt); @@ -2503,6 +2504,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq) PMD_INIT_LOG(DEBUG, "Using simple tx code path"); dev->tx_pkt_prepare = NULL; if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128 && (rte_eal_process_type() != RTE_PROC_PRIMARY || ixgbe_txq_vec_setup(txq) == 0)) { PMD_INIT_LOG(DEBUG, "Vector tx enabled."); @@ -4744,7 +4746,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev) * conditions to be met and Rx Bulk Allocation should be allowed. */ if (ixgbe_rx_vec_dev_conf_condition_check(dev) || - !adapter->rx_bulk_alloc_allowed) { + !adapter->rx_bulk_alloc_allowed || + rte_get_max_simd_bitwidth() < RTE_SIMD_128) { PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx " "preconditions", dev->data->port_id); From patchwork Thu Oct 15 10:38:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80867 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 495C2A04DB; Thu, 15 Oct 2020 12:42:18 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1BF0A1DF94; Thu, 15 Oct 2020 12:38:50 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 354DE1DEF2 for ; Thu, 15 Oct 2020 12:38:48 +0200 (CEST) IronPort-SDR: u5DSwItd9f459Jp51OQSc7hbT7JmCMzns38KiriNNuFWb4VcyEppWhqu+4O+zZzhYbA0hiZ6Lb pAohOnoCYRzg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964269" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964269" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:47 -0700 IronPort-SDR: lwofzGUGb+v02yqlHeURopKq7Yi59M117fpz8cm9R/oNWWmHinCPVOAvl0ZXg8z37dSrJmLWMO H38V101X0C/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728560" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:44 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko , Viacheslav Ovsiienko , Matan Azrad , Shahaf Shuler Date: Thu, 15 Oct 2020 11:38:07 +0100 Message-Id: <20201015103814.253636-12-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 11/18] net/mlx5: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Matan Azrad Cc: Shahaf Shuler Cc: Viacheslav Ovsiienko Signed-off-by: Ciara Power Acked-by: Viacheslav Ovsiienko --- v4: Updated enum name. v2: Moved check for max bitwidth into existing check vec support function. --- drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index 711dcd35fa..49f1b61ff8 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -148,6 +148,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; uint32_t i; + if (rte_get_max_simd_bitwidth() < RTE_SIMD_128) + return -ENOTSUP; if (!priv->config.rx_vec_en) return -ENOTSUP; if (mlx5_mprq_enabled(dev)) From patchwork Thu Oct 15 10:38:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80868 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C5EAA04DB; Thu, 15 Oct 2020 12:42:38 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B6A671DE51; Thu, 15 Oct 2020 12:38:52 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id C4E331DE78 for ; Thu, 15 Oct 2020 12:38:50 +0200 (CEST) IronPort-SDR: O9PAH5JWitXPzf83jKSLaonAfltWWAxcoQNTfQpXF4Jbjqmeax4Fw99yL0AZHjyr4GkFiO/1Oa 29BlNA9Tbdig== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964270" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964270" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:50 -0700 IronPort-SDR: 4BgspUqH+Wsa1OBuxfkbf9eHAF2klKTsCwO4N0QNK5iAwEl9u/ZLkUwxwkKo2IKMVjnEpzW5wX 0uWELfAzNtSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728565" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:48 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Maxime Coquelin , Chenbo Xia , Zhihong Wang Date: Thu, 15 Oct 2020 11:38:08 +0100 Message-Id: <20201015103814.253636-13-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 12/18] net/virtio: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Maxime Coquelin Cc: Chenbo Xia Cc: Zhihong Wang Signed-off-by: Ciara Power Reviewed-by: Chenbo Xia --- v4: Updated enum name. v3: Moved max SIMD bitwidth check to configure function with other vec support checks. --- drivers/net/virtio/virtio_ethdev.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c index 65eefa2a31..8560c406de 100644 --- a/drivers/net/virtio/virtio_ethdev.c +++ b/drivers/net/virtio/virtio_ethdev.c @@ -2313,7 +2313,8 @@ virtio_dev_configure(struct rte_eth_dev *dev) if ((hw->use_vec_rx || hw->use_vec_tx) && (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) || !vtpci_with_feature(hw, VIRTIO_F_IN_ORDER) || - !vtpci_with_feature(hw, VIRTIO_F_VERSION_1))) { + !vtpci_with_feature(hw, VIRTIO_F_VERSION_1) || + rte_get_max_simd_bitwidth() < RTE_SIMD_512)) { PMD_DRV_LOG(INFO, "disabled packed ring vectorized path for requirements not met"); hw->use_vec_rx = 0; @@ -2366,6 +2367,12 @@ virtio_dev_configure(struct rte_eth_dev *dev) "disabled split ring vectorized rx for offloading enabled"); hw->use_vec_rx = 0; } + + if (rte_get_max_simd_bitwidth() < RTE_SIMD_128) { + PMD_DRV_LOG(INFO, + "disabled split ring vectorized rx, max SIMD bitwidth too low"); + hw->use_vec_rx = 0; + } } } From patchwork Thu Oct 15 10:38:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80869 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 04B03A04DB; Thu, 15 Oct 2020 12:42:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 562051DFE3; Thu, 15 Oct 2020 12:38:56 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 085681DFE4 for ; Thu, 15 Oct 2020 12:38:52 +0200 (CEST) IronPort-SDR: lUaadMKOv17hTFBOZVfIDtSPHpgi1OTUcyFVbpd8tFKEZyTXK7aZEia89tv76ugnmcAS9ZXU66 awDIf1e8Ar/g== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964278" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964278" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:52 -0700 IronPort-SDR: Dp+C39x2bafAIsqJ543PoA20jFBOe0PwNCI0jGRSjVuLVkLRARjCcVv8FIeUMP5io48Ck3mCfX 6JOkYMvLJweQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728571" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:50 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , David Hunt Date: Thu, 15 Oct 2020 11:38:09 +0100 Message-Id: <20201015103814.253636-14-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 13/18] distributor: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: David Hunt Signed-off-by: Ciara Power Acked-by: David Hunt --- v4: Updated enum name. --- lib/librte_distributor/rte_distributor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_distributor/rte_distributor.c b/lib/librte_distributor/rte_distributor.c index 1c047f065a..05e61dddfc 100644 --- a/lib/librte_distributor/rte_distributor.c +++ b/lib/librte_distributor/rte_distributor.c @@ -636,7 +636,8 @@ rte_distributor_create(const char *name, d->dist_match_fn = RTE_DIST_MATCH_SCALAR; #if defined(RTE_ARCH_X86) - d->dist_match_fn = RTE_DIST_MATCH_VECTOR; + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + d->dist_match_fn = RTE_DIST_MATCH_VECTOR; #endif /* From patchwork Thu Oct 15 10:38:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80870 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 90A11A04DB; Thu, 15 Oct 2020 12:43:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DCB321DFEE; Thu, 15 Oct 2020 12:38:58 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 5F1141DFE3 for ; Thu, 15 Oct 2020 12:38:55 +0200 (CEST) IronPort-SDR: IL/Gxyt4OMx6H4uRnd0E9DkIK4BTLxOhQzESKnT5lkRSPeBCF7tvLxELbYMchjj6toi+XsCz7r sxYHMXHMr/wA== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964283" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964283" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:55 -0700 IronPort-SDR: aaBYhh4tP5t4PU0RbNsoifNLaGIZ5441LiGr9PWBzUEOHY1u0ppPeem2SGTO4OiGxkewXF6XGl R+6lVXHeLU6g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728577" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:52 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Yipeng Wang , Sameh Gobriel Date: Thu, 15 Oct 2020 11:38:10 +0100 Message-Id: <20201015103814.253636-15-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 14/18] member: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Yipeng Wang Cc: Sameh Gobriel Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- v4: Updated enum name. --- lib/librte_member/rte_member_ht.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_member/rte_member_ht.c b/lib/librte_member/rte_member_ht.c index 3ea293a094..98c8aac248 100644 --- a/lib/librte_member/rte_member_ht.c +++ b/lib/librte_member/rte_member_ht.c @@ -113,7 +113,8 @@ rte_member_create_ht(struct rte_member_setsum *ss, } #if defined(RTE_ARCH_X86) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && - RTE_MEMBER_BUCKET_ENTRIES == 16) + RTE_MEMBER_BUCKET_ENTRIES == 16 && + rte_get_max_simd_bitwidth() >= RTE_SIMD_256) ss->sig_cmp_fn = RTE_MEMBER_COMPARE_AVX2; else #endif From patchwork Thu Oct 15 10:38:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80871 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C0E76A04DB; Thu, 15 Oct 2020 12:43:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 866411E31A; Thu, 15 Oct 2020 12:39:00 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id BA51C1DFEE for ; Thu, 15 Oct 2020 12:38:57 +0200 (CEST) IronPort-SDR: uCmPb9InFvp6iTT8q40eXMUyFKfOX7V32DXt59hyVxemgdNE2gUmloPXTdskEprTwqP5nfOhKb GGij7zOAevpg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964288" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964288" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:38:57 -0700 IronPort-SDR: M5HBR78Ca0iQ1s/T6FY+xD9gijnh6ZJj9rOs7b0g3MwmfqMvWMtvLuJcTqnPfPVehRz9KCiYEN 7bcCtD9LgrxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728586" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:55 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Byron Marohn , Yipeng Wang Date: Thu, 15 Oct 2020 11:38:11 +0100 Message-Id: <20201015103814.253636-16-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 15/18] efd: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Byron Marohn Cc: Yipeng Wang Signed-off-by: Ciara Power Acked-by: Yipeng Wang --- v4: Updated enum name. --- lib/librte_efd/rte_efd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/librte_efd/rte_efd.c b/lib/librte_efd/rte_efd.c index 6a799556d4..e925b73a9c 100644 --- a/lib/librte_efd/rte_efd.c +++ b/lib/librte_efd/rte_efd.c @@ -645,7 +645,9 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * For less than 4 bits, scalar function performs better * than vectorised version */ - if (RTE_EFD_VALUE_NUM_BITS > 3 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (RTE_EFD_VALUE_NUM_BITS > 3 + && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) + && rte_get_max_simd_bitwidth() >= RTE_SIMD_256) table->lookup_fn = EFD_LOOKUP_AVX2; else #endif @@ -655,7 +657,8 @@ rte_efd_create(const char *name, uint32_t max_num_rules, uint32_t key_len, * than vectorised version */ if (RTE_EFD_VALUE_NUM_BITS > 16 && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) + rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && + rte_get_max_simd_bitwidth() >= RTE_SIMD_128) table->lookup_fn = EFD_LOOKUP_NEON; else #endif From patchwork Thu Oct 15 10:38:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80872 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81E02A04DB; Thu, 15 Oct 2020 12:43:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CA3761E48F; Thu, 15 Oct 2020 12:39:03 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id C36F81E31E for ; Thu, 15 Oct 2020 12:39:00 +0200 (CEST) IronPort-SDR: gnFEQXg5+nRc+qcJLwwXNMAaOUD5bDJ7CghgjyQs9ABujKno6gtJFY6lhj5G5rKgd2GFHCjqYR x0DhHi2TFJyA== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964294" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964294" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:39:00 -0700 IronPort-SDR: xMx0T1ZG2UPv9BDtNz4hTBz7RyS/Xxz64rMgJdVDbFEvchKWeEuiRkA1daw/2ItfE8+6Ope4B3 3w3XzSdsk3RA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728592" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:38:57 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Jasvinder Singh , Olivier Matz Date: Thu, 15 Oct 2020 11:38:12 +0100 Message-Id: <20201015103814.253636-17-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 16/18] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. The vector path was initially chosen in RTE_INIT, however this is no longer suitable as we cannot check the max SIMD bitwidth at that time. Default handlers are now chosen on initialisation, these default handlers are used the first time the crc calc is called, and they set the suitable handlers to be used going forward. Suggested-by: Jasvinder Singh Suggested-by: Olivier Matz Signed-off-by: Ciara Power --- v6: - Moved log variable and macro to c file instead of public header. - Added the max_simd_bitwidth condition check to the recently added handler helper functions. - Modified default handlers to follow the approach of the set alg function. v4: - Added default handlers to be set at RTE_INIT time, rather than choosing scalar handlers. - Modified logging. - Updated enum name. v3: - Moved choosing vector paths out of RTE_INIT. - Moved checking max_simd_bitwidth into the set_alg function. --- lib/librte_net/rte_net_crc.c | 117 +++++++++++++++++++++++++---------- 1 file changed, 86 insertions(+), 31 deletions(-) diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c index 32a3665908..bce5f5f15b 100644 --- a/lib/librte_net/rte_net_crc.c +++ b/lib/librte_net/rte_net_crc.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include "net_crc.h" @@ -22,6 +24,12 @@ static uint32_t crc32_eth_lut[CRC_LUT_SIZE]; static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE]; +static uint32_t +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len); + +static uint32_t +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len); + static uint32_t rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len); @@ -31,7 +39,12 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len); typedef uint32_t (*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len); -static const rte_net_crc_handler *handlers; +static rte_net_crc_handler handlers_default[] = { + [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_default_handler, + [RTE_NET_CRC32_ETH] = rte_crc32_eth_default_handler, +}; + +static const rte_net_crc_handler *handlers = handlers_default; static const rte_net_crc_handler handlers_scalar[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler, @@ -56,6 +69,15 @@ static const rte_net_crc_handler handlers_neon[] = { }; #endif +static uint16_t max_simd_bitwidth; +extern int libnet_logtype; + +#define NET_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, libnet_logtype, "%s(): " fmt "\n", \ + __func__, ## args) + +RTE_LOG_REGISTER(libnet_logtype, lib.net, INFO); + /* Scalar handling */ /** @@ -155,22 +177,21 @@ static const rte_net_crc_handler * avx512_vpclmulqdq_get_handlers(void) { #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT - if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) + if (AVX512_VPCLMULQDQ_CPU_SUPPORTED && + max_simd_bitwidth >= RTE_SIMD_512) return handlers_avx512; #endif + NET_LOG(INFO, "Requirements not met, can't use AVX512\n"); return NULL; } -static uint8_t +static void avx512_vpclmulqdq_init(void) { #ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT - if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) { + if (AVX512_VPCLMULQDQ_CPU_SUPPORTED) rte_net_crc_avx512_init(); - return 1; - } #endif - return 0; } /* SSE4.2/PCLMULQDQ handling */ @@ -182,22 +203,21 @@ static const rte_net_crc_handler * sse42_pclmulqdq_get_handlers(void) { #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT - if (SSE42_PCLMULQDQ_CPU_SUPPORTED) + if (SSE42_PCLMULQDQ_CPU_SUPPORTED && + max_simd_bitwidth >= RTE_SIMD_128) return handlers_sse42; #endif + NET_LOG(INFO, "Requirements not met, can't use SSE\n"); return NULL; } -static uint8_t +static void sse42_pclmulqdq_init(void) { #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT - if (SSE42_PCLMULQDQ_CPU_SUPPORTED) { + if (SSE42_PCLMULQDQ_CPU_SUPPORTED) rte_net_crc_sse42_init(); - return 1; - } #endif - return 0; } /* NEON/PMULL handling */ @@ -209,22 +229,63 @@ static const rte_net_crc_handler * neon_pmull_get_handlers(void) { #ifdef CC_ARM64_NEON_PMULL_SUPPORT - if (NEON_PMULL_CPU_SUPPORTED) + if (NEON_PMULL_CPU_SUPPORTED && + max_simd_bitwidth >= RTE_SIMD_128) return handlers_neon; #endif + NET_LOG(INFO, "Requirements not met, can't use NEON\n"); return NULL; } -static uint8_t +static void neon_pmull_init(void) { #ifdef CC_ARM64_NEON_PMULL_SUPPORT - if (NEON_PMULL_CPU_SUPPORTED) { + if (NEON_PMULL_CPU_SUPPORTED) rte_net_crc_neon_init(); - return 1; - } #endif - return 0; +} + +/* Default handling */ + +static uint32_t +rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len) +{ + handlers = NULL; + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + + handlers = avx512_vpclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC16_CCITT](data, data_len); + handlers = sse42_pclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC16_CCITT](data, data_len); + handlers = neon_pmull_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC16_CCITT](data, data_len); + handlers = handlers_scalar; + return handlers[RTE_NET_CRC16_CCITT](data, data_len); +} + +static uint32_t +rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len) +{ + handlers = NULL; + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + + handlers = avx512_vpclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC32_ETH](data, data_len); + handlers = sse42_pclmulqdq_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC32_ETH](data, data_len); + handlers = neon_pmull_get_handlers(); + if (handlers != NULL) + return handlers[RTE_NET_CRC32_ETH](data, data_len); + handlers = handlers_scalar; + return handlers[RTE_NET_CRC32_ETH](data, data_len); } /* Public API */ @@ -233,6 +294,8 @@ void rte_net_crc_set_alg(enum rte_net_crc_alg alg) { handlers = NULL; + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); switch (alg) { case RTE_NET_CRC_AVX512: @@ -270,19 +333,11 @@ rte_net_crc_calc(const void *data, return ret; } -/* Select highest available crc algorithm as default one */ +/* Call initialisation helpers for all crc algorithm handlers */ RTE_INIT(rte_net_crc_init) { - enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR; - rte_net_crc_scalar_init(); - - if (sse42_pclmulqdq_init()) - alg = RTE_NET_CRC_SSE42; - if (avx512_vpclmulqdq_init()) - alg = RTE_NET_CRC_AVX512; - if (neon_pmull_init()) - alg = RTE_NET_CRC_NEON; - - rte_net_crc_set_alg(alg); + sse42_pclmulqdq_init(); + avx512_vpclmulqdq_init(); + neon_pmull_init(); } From patchwork Thu Oct 15 10:38:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80873 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54118A04DB; Thu, 15 Oct 2020 12:44:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BC8531E497; Thu, 15 Oct 2020 12:39:07 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 84AA61DED3 for ; Thu, 15 Oct 2020 12:39:03 +0200 (CEST) IronPort-SDR: 5am/bpGVI4rL5Y1Tp88qbEkPHkWEOY96NYWak+kTs1FELdRsmmV7yTLU6vc/uRzDxLpYyMr92U UKB3LKny93Rg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964297" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964297" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:39:03 -0700 IronPort-SDR: nrwFIYIJC2UvifXhvUIcUA/dUfTzQMSAte9p3w8hgB+KVdlcboWLgNwhwAUZ3MsGwchwcmrY5F sZdsInw7veiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728602" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:39:00 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Nithin Dabilpuram , Pavan Nikhilesh , Kiran Kumar K Date: Thu, 15 Oct 2020 11:38:13 +0100 Message-Id: <20201015103814.253636-18-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 17/18] node: choose vector path at runtime X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing the vector path, max SIMD bitwidth is now checked to ensure the vector path is suitable. To do this, the scalar function is chosen by default in the struct, but at node initialisation time, this function pointer is updated to the vector version if supported, and if it is within the max SIMD bitwidth limit. Cc: Nithin Dabilpuram Cc: Pavan Nikhilesh Cc: Jerin Jacob Cc: Kiran Kumar K Signed-off-by: Ciara Power Acked-by: Nithin Dabilpuram --- v6: - Removed generic process function. - Change the process function pointer at node init time to vector function if suitable. --- lib/librte_node/ip4_lookup.c | 14 +++++++++----- lib/librte_node/ip4_lookup_neon.h | 2 +- lib/librte_node/ip4_lookup_sse.h | 2 +- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/lib/librte_node/ip4_lookup.c b/lib/librte_node/ip4_lookup.c index 293c77f39e..934a6d7eab 100644 --- a/lib/librte_node/ip4_lookup.c +++ b/lib/librte_node/ip4_lookup.c @@ -34,10 +34,10 @@ static struct ip4_lookup_node_main ip4_lookup_nm; #include "ip4_lookup_neon.h" #elif defined(RTE_ARCH_X86) #include "ip4_lookup_sse.h" -#else +#endif static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_scalar(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_ipv4_hdr *ipv4_hdr; @@ -109,8 +109,6 @@ ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, return nb_objs; } -#endif - int rte_node_ip4_route_add(uint32_t ip, uint8_t depth, uint16_t next_hop, enum rte_node_ip4_lookup_next next_node) @@ -194,13 +192,19 @@ ip4_lookup_node_init(const struct rte_graph *graph, struct rte_node *node) init_once = 1; } *lpm_p = ip4_lookup_nm.lpm_tbl[graph->socket]; + +#if defined(__ARM_NEON) || defined(RTE_ARCH_X86) + if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128) + node->process = ip4_lookup_node_process_vec; +#endif + node_dbg("ip4_lookup", "Initialized ip4_lookup node"); return 0; } static struct rte_node_register ip4_lookup_node = { - .process = ip4_lookup_node_process, + .process = ip4_lookup_node_process_scalar, .name = "ip4_lookup", .init = ip4_lookup_node_init, diff --git a/lib/librte_node/ip4_lookup_neon.h b/lib/librte_node/ip4_lookup_neon.h index 5e5a7d87be..0ad2763b82 100644 --- a/lib/librte_node/ip4_lookup_neon.h +++ b/lib/librte_node/ip4_lookup_neon.h @@ -7,7 +7,7 @@ /* ARM64 NEON */ static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts; diff --git a/lib/librte_node/ip4_lookup_sse.h b/lib/librte_node/ip4_lookup_sse.h index a071cc5919..264c986071 100644 --- a/lib/librte_node/ip4_lookup_sse.h +++ b/lib/librte_node/ip4_lookup_sse.h @@ -7,7 +7,7 @@ /* X86 SSE */ static uint16_t -ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node, +ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node, void **objs, uint16_t nb_objs) { struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts; From patchwork Thu Oct 15 10:38:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 80874 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C1BD9A04DB; Thu, 15 Oct 2020 12:44:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CB17D1E4A5; Thu, 15 Oct 2020 12:39:10 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id C00F91E497 for ; Thu, 15 Oct 2020 12:39:05 +0200 (CEST) IronPort-SDR: 6SZHugyy7Hmo+kdAuwUVoXaKy6Yx5d91EcGKnlLU+G7AUgsF0eIWfnYsN1t2D6PqHQZKK/CWOM rhZj3bIlFwGQ== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964303" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964303" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:39:05 -0700 IronPort-SDR: n+hO8bATkXrczSHu0PDX2EvUXEv1hTJ+X7xnBkUV8MX08aFuizu8WuW2sl3M1kIXhK4U4ukAVC w7d1y7ymGWAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728609" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:39:03 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power Date: Thu, 15 Oct 2020 11:38:14 +0100 Message-Id: <20201015103814.253636-19-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 18/18] acl: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. These checks are added in the check alg helper functions. Cc: Konstantin Ananyev Signed-off-by: Ciara Power --- lib/librte_acl/rte_acl.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c index 7c2f60b2d6..4ec6c982c9 100644 --- a/lib/librte_acl/rte_acl.c +++ b/lib/librte_acl/rte_acl.c @@ -16,6 +16,8 @@ static struct rte_tailq_elem rte_acl_tailq = { }; EAL_REGISTER_TAILQ(rte_acl_tailq) +uint16_t max_simd_bitwidth; + #ifndef CC_AVX512_SUPPORT /* * If the compiler doesn't support AVX512 instructions, @@ -114,9 +116,13 @@ acl_check_alg_arm(enum rte_acl_classify_alg alg) { if (alg == RTE_ACL_CLASSIFY_NEON) { #if defined(RTE_ARCH_ARM64) - return 0; + if (max_simd_bitwidth >= RTE_SIMD_128) + return 0; + else + return -ENOTSUP; #elif defined(RTE_ARCH_ARM) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && + max_simd_bitwidth >= RTE_SIMD_128) return 0; return -ENOTSUP; #else @@ -136,7 +142,10 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg) { if (alg == RTE_ACL_CLASSIFY_ALTIVEC) { #if defined(RTE_ARCH_PPC_64) - return 0; + if (max_simd_bitwidth >= RTE_SIMD_128) + return 0; + else + return -ENOTSUP; #else return -ENOTSUP; #endif @@ -158,7 +167,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW)) + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) && + max_simd_bitwidth >= RTE_SIMD_512) return 0; #endif return -ENOTSUP; @@ -166,7 +176,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (alg == RTE_ACL_CLASSIFY_AVX2) { #ifdef CC_AVX2_SUPPORT - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + max_simd_bitwidth >= RTE_SIMD_256) return 0; #endif return -ENOTSUP; @@ -174,7 +185,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (alg == RTE_ACL_CLASSIFY_SSE) { #ifdef RTE_ARCH_X86 - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) && + max_simd_bitwidth >= RTE_SIMD_128) return 0; #endif return -ENOTSUP; @@ -406,6 +418,9 @@ rte_acl_create(const struct rte_acl_param *param) TAILQ_INSERT_TAIL(acl_list, te, next); } + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + exit: rte_mcfg_tailq_write_unlock(); return ctx;