From patchwork Thu Oct 15 09:28:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Connolly, Padraig J" X-Patchwork-Id: 80844 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 24A40A04DB; Thu, 15 Oct 2020 11:29:54 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EB3ED1DD02; Thu, 15 Oct 2020 11:29:52 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 68E041DCFF; Thu, 15 Oct 2020 11:29:50 +0200 (CEST) IronPort-SDR: 09wyc6x/MEePf4PsxAtvRLf49OJCe1V3Du1bSOXojzPR5aKYRgxEqFWxqVr5FT4R/YrEnpeyuK xFx6BOs7tRNg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227950857" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227950857" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 02:29:35 -0700 IronPort-SDR: gGZdAVfbyRV1tlwdIFUIP3DcpAC832Lv8Jz71VIPLRK5ULDwcCT0ul4VgAfPRBpp0nAsV4p5VY c2Lm+D8TIQ8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="318962414" Received: from silpixa00400050.ir.intel.com ([10.237.213.66]) by orsmga006.jf.intel.com with ESMTP; 15 Oct 2020 02:29:33 -0700 From: Padraig Connolly To: beilei.xing@intel.com Cc: dev@dpdk.org, Padraig Connolly , bernard.iremonger@intel.com, stable@dpdk.org Date: Thu, 15 Oct 2020 10:28:58 +0100 Message-Id: <20201015092858.84731-1-padraig.j.connolly@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201014163047.69981-1> References: <20201014163047.69981-1> Subject: [dpdk-dev] [PATCH v3] net/i40e: fix qinq flow pattern to allow non full mask X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Issue reported by customer that only full mask was allowed on inner and outer VLAN tag, thus not allowing mask to set VLAN ID filter only. Removed check thatenforces inner vlan and outer vlan equal I40E_TCI_MASK (full mask 0xffff). Fixes: d37705068ee8 ("net/i40e: parse QinQ pattern") Cc: bernard.iremonger@intel.com Cc: stable@dpdk.org Tested-by: Padraig Connolly Signed-off-by: Padraig Connolly Acked-by: Bernard Iremonger --- drivers/net/i40e/i40e_flow.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index adc5da1c5..8e7a9989b 100644 --- a/drivers/net/i40e/i40e_flow.c +++ b/drivers/net/i40e/i40e_flow.c @@ -4649,14 +4649,9 @@ i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, } /* Get filter specification */ - if ((o_vlan_mask != NULL) && (o_vlan_mask->tci == - rte_cpu_to_be_16(I40E_TCI_MASK)) && - (i_vlan_mask != NULL) && - (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) { - filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci) - & I40E_TCI_MASK; - filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci) - & I40E_TCI_MASK; + if (o_vlan_mask != NULL && i_vlan_mask != NULL) { + filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci); + filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci); } else { rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,