From patchwork Wed Oct 14 16:30:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Connolly, Padraig J" X-Patchwork-Id: 80775 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83FCEA04DB; Wed, 14 Oct 2020 18:31:50 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D58EA1D707; Wed, 14 Oct 2020 18:31:48 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id D39C21D6FD; Wed, 14 Oct 2020 18:31:45 +0200 (CEST) IronPort-SDR: gPQY32lMsp/njGD06WsU06NVDnqxzdBxkDGQVQjK42q9WHTyuvHICxekr9g6HnC0p3gn1L66UB 7SDQB3D5OhGg== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="230316416" X-IronPort-AV: E=Sophos;i="5.77,375,1596524400"; d="scan'208";a="230316416" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2020 09:31:05 -0700 IronPort-SDR: S7qnyXgJT8TdvF7ZTpUye49S0Ymuej6YVPjBPNEUfBriwEiqB5h0xiipGhb03m7g+TQ+q0AYqb 7lCWDdO2sXmA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,375,1596524400"; d="scan'208";a="351545262" Received: from silpixa00400050.ir.intel.com ([10.237.213.66]) by fmsmga002.fm.intel.com with ESMTP; 14 Oct 2020 09:31:03 -0700 From: Padraig Connolly To: beilei.xing@intel.com Cc: dev@dpdk.org, Padraig Connolly , bernard.iremonger@intel.com, stable@dpdk.org Date: Wed, 14 Oct 2020 17:30:47 +0100 Message-Id: <20201014163047.69981-1-padraig.j.connolly@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201013135756.23193-1> References: <20201013135756.23193-1> Subject: [dpdk-dev] [PATCH v2] net/i40e: fix qinq flow pattern to allow non full mask X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Issue reported by customer that only full mask was allowed on inner and outer VLAN tag, thus not allowing mask to set VLAN ID filter only. Removed check that enforces inner vlan and outer vlan to equal I40E_TCI_MASK (full mask 0xffff). Fixes: c2be7f9b232f ("net/i40e: fix parsing QinQ pattern") Fixes: d37705068ee8 ("net/i40e: parse QinQ pattern") Cc: bernard.iremonger@intel.com Cc: stable@dpdk.org Tested-by: Padraig Connolly Signed-off-by: Padraig Connolly Acked-by: Bernard Iremonger --- drivers/net/i40e/i40e_flow.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index adc5da1c5..8e7a9989b 100644 --- a/drivers/net/i40e/i40e_flow.c +++ b/drivers/net/i40e/i40e_flow.c @@ -4649,14 +4649,9 @@ i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev, } /* Get filter specification */ - if ((o_vlan_mask != NULL) && (o_vlan_mask->tci == - rte_cpu_to_be_16(I40E_TCI_MASK)) && - (i_vlan_mask != NULL) && - (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) { - filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci) - & I40E_TCI_MASK; - filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci) - & I40E_TCI_MASK; + if (o_vlan_mask != NULL && i_vlan_mask != NULL) { + filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci); + filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci); } else { rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,