From patchwork Wed Sep 30 12:19:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dekel Peled X-Patchwork-Id: 79336 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 91027A04B5; Wed, 30 Sep 2020 14:20:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 75A3D1DB07; Wed, 30 Sep 2020 14:20:01 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 9F5941D6F3 for ; Wed, 30 Sep 2020 14:19:58 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from dekelp@nvidia.com) with SMTP; 30 Sep 2020 15:19:51 +0300 Received: from mtl-vdi-280.wap.labs.mlnx. (mtl-vdi-280.wap.labs.mlnx [10.228.134.250]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 08UCJphH017317; Wed, 30 Sep 2020 15:19:51 +0300 From: Dekel Peled To: viacheslavo@nvidia.com, shahafs@nvidia.com, matan@nvidia.com Cc: dev@dpdk.org, stable@dpdk.org Date: Wed, 30 Sep 2020 15:19:36 +0300 Message-Id: X-Mailer: git-send-email 1.7.1 Subject: [dpdk-dev] [PATCH] net/mlx5: fix DevX CQ attributes values X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Previous patch wrongly used rdma-core defined values, when preparing attributes for creating DevX CQ object. This patch adds the correct value definition and uses them instead. Fixes: 08d1838f645a ("net/mlx5: implement CQ for Rx using DevX API") Cc: stable@dpdk.org Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 8 ++++++++ drivers/net/mlx5/mlx5_devx.c | 14 ++++---------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 563e7c8..20f2fcc 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2835,6 +2835,14 @@ struct mlx5_mini_cqe8 { uint32_t byte_cnt; }; +/* Mini CQE responder format. */ +enum { + MLX5_CQE_RESP_FORMAT_HASH = 0x0, + MLX5_CQE_RESP_FORMAT_CSUM = 0x1, + MLX5_CQE_RESP_FORMAT_CSUM_FLOW_TAG = 0x2, + MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, +}; + /* srTCM PRM flow meter parameters. */ enum { MLX5_FLOW_COLOR_RED = 0, diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 3e81fcc..cb4a522 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -367,15 +367,11 @@ } if (priv->config.cqe_comp && !rxq_data->hw_timestamp && !rxq_data->lro) { - cq_attr.cqe_comp_en = MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE; -#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT + cq_attr.cqe_comp_en = 1u; cq_attr.mini_cqe_res_format = mlx5_rxq_mprq_enabled(rxq_data) ? - MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX : - MLX5DV_CQE_RES_FORMAT_HASH; -#else - cq_attr.mini_cqe_res_format = MLX5DV_CQE_RES_FORMAT_HASH; -#endif + MLX5_CQE_RESP_FORMAT_CSUM_STRIDX : + MLX5_CQE_RESP_FORMAT_HASH; /* * For vectorized Rx, it must not be doubled in order to * make cq_ci and rq_ci aligned. @@ -392,10 +388,8 @@ "Port %u Rx CQE compression is disabled for LRO.", dev->data->port_id); } -#ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD if (priv->config.cqe_pad) - cq_attr.cqe_size = MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD; -#endif + cq_attr.cqe_size = MLX5_CQE_SIZE_128B; log_cqe_n = log2above(cqe_n); cq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n); /* Query the EQN for this core. */