From patchwork Mon Sep 14 15:10:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Van Haaren, Harry" X-Patchwork-Id: 77632 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2DF1FA04C7; Mon, 14 Sep 2020 17:09:06 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0F5E31C0C9; Mon, 14 Sep 2020 17:09:06 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 7314B1C0C2 for ; Mon, 14 Sep 2020 17:09:04 +0200 (CEST) IronPort-SDR: WMUncuVoYLg+c8bnivDnvGClU22bXm+j8IzUUs2dC+zIZ/h2YcfG/P7eu6pc3AAa4VL0eaZIta 6zgXd62zp5Vw== X-IronPort-AV: E=McAfee;i="6000,8403,9744"; a="139105119" X-IronPort-AV: E=Sophos;i="5.76,426,1592895600"; d="scan'208";a="139105119" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2020 08:09:02 -0700 IronPort-SDR: 3TM+n5Qrq6GZ+XznM/pt1jWA6OI+wfvloJ7KGJUB/srUBoSbga7JNGOQbRTQtnVX4OlZ4txwEH nP5laGKMBrCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,426,1592895600"; d="scan'208";a="301782474" Received: from silpixa00399779.ir.intel.com (HELO silpixa00399779.ger.corp.intel.com) ([10.237.222.209]) by orsmga003.jf.intel.com with ESMTP; 14 Sep 2020 08:09:01 -0700 From: Harry van Haaren To: dev@dpdk.org Cc: pbhagavatula@marvell.com, Harry van Haaren Date: Mon, 14 Sep 2020 16:10:21 +0100 Message-Id: <20200914151021.23806-1-harry.van.haaren@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200911091919.62167-1-harry.van.haaren@intel.com> References: <20200911091919.62167-1-harry.van.haaren@intel.com> Subject: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds a new rte_prefetch0_write() variants, suggesting to the compiler to use a prefetch instruction with intention to write. As a compiler builtin, the compiler can choose based on compilation target what the best implementation for this instruction is. Signed-off-by: Harry van Haaren Reviewed-by: Jerin Jacob Reviewed-by: Ruifeng Wang --- v2: - Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan) The integer constants passed to the builtin are not available as a #define value, and doing #defines just for this write variant does not seems a nice solution to me... particularly for those using IDEs where any #define value is auto-hinted for code-completion. --- lib/librte_eal/include/generic/rte_prefetch.h | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h index 6e47bdfbad..3dfca77a74 100644 --- a/lib/librte_eal/include/generic/rte_prefetch.h +++ b/lib/librte_eal/include/generic/rte_prefetch.h @@ -51,4 +51,53 @@ static inline void rte_prefetch2(const volatile void *p); */ static inline void rte_prefetch_non_temporal(const volatile void *p); +/** + * Prefetch a cache line into all cache levels, with intention to write. This + * prefetch variant hints to the CPU that the program is expecting to write to + * the cache line being prefetched. + * + * @param p Address to prefetch + */ +static inline void rte_prefetch0_write(const void *p) +{ + /* 1 indicates intention to write, 3 sets target cache level to L1. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 3); +} + +/** + * Prefetch a cache line into all cache levels, except the 0th, with intention + * to write. This prefetch variant hints to the CPU that the program is + * expecting to write to the cache line being prefetched. + * + * @param p Address to prefetch + */ +static inline void rte_prefetch1_write(const void *p) +{ + /* 1 indicates intention to write, 2 sets target cache level to L2. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 2); +} + +/** + * Prefetch a cache line into all cache levels, except the 0th and 1st, with + * intention to write. This prefetch variant hints to the CPU that the program + * is expecting to write to the cache line being prefetched. + * + * @param p Address to prefetch + */ +static inline void rte_prefetch2_write(const void *p) +{ + /* 1 indicates intention to write, 1 sets target cache level to L3. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 1); +} + + #endif /* _RTE_PREFETCH_H_ */