From patchwork Tue Jul 21 08:13:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 74533 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 063FCA0526; Tue, 21 Jul 2020 10:14:12 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6A99E1BFE3; Tue, 21 Jul 2020 10:14:11 +0200 (CEST) Received: from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130]) by dpdk.org (Postfix) with ESMTP id 7E43E1BFBA for ; Tue, 21 Jul 2020 10:14:09 +0200 (CEST) From: Bing Zhao To: viacheslavo@mellanox.com, matan@mellanox.com Cc: dev@dpdk.org Date: Tue, 21 Jul 2020 16:13:40 +0800 Message-Id: <1595319220-173871-1-git-send-email-bingz@mellanox.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH] vdpa/mlx5: fix the compatibility with MISC4 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When dynamic flex parser feature is introduced, the support for misc parameters 4 of flow table entry (FTE) match set is needed. The structure of "mlx5_ifc_fte_match_param_bits" is extended with "mlx5_ifc_fte_match_set_misc4_bits" at the end of it. The total size of the FTE match set will be changed into 384 bytes from 320 bytes. Low level user space driver (rdma-core) will have the validation of the length of FTE match set. In the old release that no MISC4 supported in the rdma-core, and this will break the backward compatibility, even if the MISC4 is not used in most cases, like in vDPA driver. In order not to break the compatibility old rdma-core, the length adjustment needs to be done. In mlx5 vDPA driver, the lengths of the matcher and value are both set to 320 without MISC4. There is no need to change the structure definition, all bytes of the MISC4 will be discarded if it is not needed. Since the MISC4 parameter is aligned with a 64B boundary and so does the whole FTE match set parameter, there is no need to take any padding and alignment into consideration when calculating the size. Fixes: 32132fb8517c ("net/mlx5: add flow translation of eCPRI header") Signed-off-by: Bing Zhao Acked-by: Matan Azrad Reviewed-by: Maxime Coquelin --- drivers/vdpa/mlx5/mlx5_vdpa_steer.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_steer.c b/drivers/vdpa/mlx5/mlx5_vdpa_steer.c index 406c7be..1fcd24c 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_steer.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_steer.c @@ -139,10 +139,12 @@ uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)]; /**< Matcher value. This value is used as the mask or a key. */ } matcher_mask = { - .size = sizeof(matcher_mask.buf), + .size = sizeof(matcher_mask.buf) - + MLX5_ST_SZ_BYTES(fte_match_set_misc4), }, matcher_value = { - .size = sizeof(matcher_value.buf), + .size = sizeof(matcher_value.buf) - + MLX5_ST_SZ_BYTES(fte_match_set_misc4), }; struct mlx5dv_flow_matcher_attr dv_attr = { .type = IBV_FLOW_ATTR_NORMAL,