From patchwork Fri Jul 17 09:49:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74302 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A1D35A053D; Fri, 17 Jul 2020 11:55:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AB3121BFB3; Fri, 17 Jul 2020 11:54:56 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 7601E1BFA3 for ; Fri, 17 Jul 2020 11:54:53 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id D8A611BBCD0; Fri, 17 Jul 2020 02:54:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com D8A611BBCD0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979693; bh=TxajJiERupqEw5cbAXjJha35KGmAohiRCY2J8PlQkik=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TsruDFNouspNcYtdUINlt19uz7IU39LngNX5njs/xWkW5EqX5FtFNfW+yMCRS5XaR 0GD3FbZ0E/m1GuLehoghylCf9nVQCG5pymWfEVi824L68TNYxmIN/JY/q/AIVYTFm8 lMdQFhHDk5B7iJPx+242aDSOR0eK5gmE3J5eqjjw= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:22 +0530 Message-Id: <20200717094935.9337-2-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 01/14] net/bnxt: changes to support new RM and multi-region X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Peter Spreadborough - Updated CFA resource types - Updated references - Add High/low Signed-off-by: Peter Spreadborough Reviewed-by: Farah Smith Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_core/cfa_resource_types.h | 194 ++++++++++++------------ drivers/net/bnxt/tf_core/tf_core.h | 12 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 14 +- drivers/net/bnxt/tf_core/tf_util.c | 12 +- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 10 +- drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 38 ++--- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 4 +- 7 files changed, 152 insertions(+), 132 deletions(-) diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index 6d6651f..45b26b2 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -18,53 +18,57 @@ */ #define CFA_RESOURCE_TYPE_INVALID 65535 -/* L2 Context TCAM */ -#define CFA_RESOURCE_TYPE_P59_L2_CTXT_TCAM 0x0UL -/* L2 Context REMAP */ -#define CFA_RESOURCE_TYPE_P59_L2_CTXT_REMAP 0x1UL +/* L2 Context TCAM High priority entries */ +#define CFA_RESOURCE_TYPE_P59_L2_CTXT_TCAM_HIGH 0x0UL +/* L2 Context TCAM Low priority entries */ +#define CFA_RESOURCE_TYPE_P59_L2_CTXT_TCAM_LOW 0x1UL +/* L2 Context REMAP high priority entries */ +#define CFA_RESOURCE_TYPE_P59_L2_CTXT_REMAP_HIGH 0x2UL +/* L2 Context REMAP Low priority entries */ +#define CFA_RESOURCE_TYPE_P59_L2_CTXT_REMAP_LOW 0x3UL /* Profile Func */ -#define CFA_RESOURCE_TYPE_P59_PROF_FUNC 0x2UL +#define CFA_RESOURCE_TYPE_P59_PROF_FUNC 0x4UL /* Profile TCAM */ -#define CFA_RESOURCE_TYPE_P59_PROF_TCAM 0x3UL +#define CFA_RESOURCE_TYPE_P59_PROF_TCAM 0x5UL /* Exact Match Profile Id */ -#define CFA_RESOURCE_TYPE_P59_EM_PROF_ID 0x4UL +#define CFA_RESOURCE_TYPE_P59_EM_PROF_ID 0x6UL /* Wildcard TCAM Profile Id */ -#define CFA_RESOURCE_TYPE_P59_WC_TCAM_PROF_ID 0x5UL +#define CFA_RESOURCE_TYPE_P59_WC_TCAM_PROF_ID 0x7UL /* Wildcard TCAM */ -#define CFA_RESOURCE_TYPE_P59_WC_TCAM 0x6UL +#define CFA_RESOURCE_TYPE_P59_WC_TCAM 0x8UL /* Meter Profile */ -#define CFA_RESOURCE_TYPE_P59_METER_PROF 0x7UL +#define CFA_RESOURCE_TYPE_P59_METER_PROF 0x9UL /* Meter */ -#define CFA_RESOURCE_TYPE_P59_METER 0x8UL +#define CFA_RESOURCE_TYPE_P59_METER 0xaUL /* Meter */ -#define CFA_RESOURCE_TYPE_P59_MIRROR 0x9UL +#define CFA_RESOURCE_TYPE_P59_MIRROR 0xbUL /* Source Properties TCAM */ -#define CFA_RESOURCE_TYPE_P59_SP_TCAM 0xaUL +#define CFA_RESOURCE_TYPE_P59_SP_TCAM 0xcUL /* Exact Match Flexible Key Builder */ -#define CFA_RESOURCE_TYPE_P59_EM_FKB 0xbUL +#define CFA_RESOURCE_TYPE_P59_EM_FKB 0xdUL /* Wildcard Flexible Key Builder */ -#define CFA_RESOURCE_TYPE_P59_WC_FKB 0xcUL +#define CFA_RESOURCE_TYPE_P59_WC_FKB 0xeUL /* Table Scope */ -#define CFA_RESOURCE_TYPE_P59_TBL_SCOPE 0xdUL +#define CFA_RESOURCE_TYPE_P59_TBL_SCOPE 0xfUL /* L2 Func */ -#define CFA_RESOURCE_TYPE_P59_L2_FUNC 0xeUL +#define CFA_RESOURCE_TYPE_P59_L2_FUNC 0x10UL /* EPOCH 0 */ -#define CFA_RESOURCE_TYPE_P59_EPOCH0 0xfUL +#define CFA_RESOURCE_TYPE_P59_EPOCH0 0x11UL /* EPOCH 1 */ -#define CFA_RESOURCE_TYPE_P59_EPOCH1 0x10UL +#define CFA_RESOURCE_TYPE_P59_EPOCH1 0x12UL /* Metadata */ -#define CFA_RESOURCE_TYPE_P59_METADATA 0x11UL +#define CFA_RESOURCE_TYPE_P59_METADATA 0x13UL /* Connection Tracking Rule TCAM */ -#define CFA_RESOURCE_TYPE_P59_CT_RULE_TCAM 0x12UL +#define CFA_RESOURCE_TYPE_P59_CT_RULE_TCAM 0x14UL /* Range Profile */ -#define CFA_RESOURCE_TYPE_P59_RANGE_PROF 0x13UL +#define CFA_RESOURCE_TYPE_P59_RANGE_PROF 0x15UL /* Range */ -#define CFA_RESOURCE_TYPE_P59_RANGE 0x14UL +#define CFA_RESOURCE_TYPE_P59_RANGE 0x16UL /* Link Aggrigation */ -#define CFA_RESOURCE_TYPE_P59_LAG 0x15UL +#define CFA_RESOURCE_TYPE_P59_LAG 0x17UL /* VEB TCAM */ -#define CFA_RESOURCE_TYPE_P59_VEB_TCAM 0x16UL -#define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM +#define CFA_RESOURCE_TYPE_P59_VEB_TCAM 0x18UL +#define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM /* Multicast Group */ @@ -81,40 +85,40 @@ #define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV4 0x5UL /* Source Property MAC and IPv6 */ #define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV6 0x6UL -/* Network Address Translation Source Port */ -#define CFA_RESOURCE_TYPE_P58_NAT_SPORT 0x7UL -/* Network Address Translation Destination Port */ -#define CFA_RESOURCE_TYPE_P58_NAT_DPORT 0x8UL -/* Network Address Translation Source IPv4 address */ -#define CFA_RESOURCE_TYPE_P58_NAT_S_IPV4 0x9UL -/* Network Address Translation Destination IPv4 address */ -#define CFA_RESOURCE_TYPE_P58_NAT_D_IPV4 0xaUL +/* Network Address Translation Port */ +#define CFA_RESOURCE_TYPE_P58_NAT_PORT 0x7UL +/* Network Address Translation IPv4 address */ +#define CFA_RESOURCE_TYPE_P58_NAT_IPV4 0x8UL /* Meter */ -#define CFA_RESOURCE_TYPE_P58_METER 0xbUL +#define CFA_RESOURCE_TYPE_P58_METER 0x9UL /* Flow State */ -#define CFA_RESOURCE_TYPE_P58_FLOW_STATE 0xcUL +#define CFA_RESOURCE_TYPE_P58_FLOW_STATE 0xaUL /* Full Action Records */ -#define CFA_RESOURCE_TYPE_P58_FULL_ACTION 0xdUL +#define CFA_RESOURCE_TYPE_P58_FULL_ACTION 0xbUL /* Action Record Format 0 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_0_ACTION 0xeUL +#define CFA_RESOURCE_TYPE_P58_FORMAT_0_ACTION 0xcUL /* Action Record Ext Format 0 */ -#define CFA_RESOURCE_TYPE_P58_EXT_FORMAT_0_ACTION 0xfUL +#define CFA_RESOURCE_TYPE_P58_EXT_FORMAT_0_ACTION 0xdUL /* Action Record Format 1 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_1_ACTION 0x10UL +#define CFA_RESOURCE_TYPE_P58_FORMAT_1_ACTION 0xeUL /* Action Record Format 2 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_2_ACTION 0x11UL +#define CFA_RESOURCE_TYPE_P58_FORMAT_2_ACTION 0xfUL /* Action Record Format 3 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_3_ACTION 0x12UL +#define CFA_RESOURCE_TYPE_P58_FORMAT_3_ACTION 0x10UL /* Action Record Format 4 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_4_ACTION 0x13UL +#define CFA_RESOURCE_TYPE_P58_FORMAT_4_ACTION 0x11UL /* Action Record Format 5 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_5_ACTION 0x14UL +#define CFA_RESOURCE_TYPE_P58_FORMAT_5_ACTION 0x12UL /* Action Record Format 6 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_6_ACTION 0x15UL -/* L2 Context TCAM */ -#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM 0x16UL -/* L2 Context REMAP */ -#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP 0x17UL +#define CFA_RESOURCE_TYPE_P58_FORMAT_6_ACTION 0x13UL +/* L2 Context TCAM High priority entries */ +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH 0x14UL +/* L2 Context TCAM Low priority entries */ +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW 0x15UL +/* L2 Context REMAP high priority entries */ +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x16UL +/* L2 Context REMAP Low priority entries */ +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW 0x17UL /* Profile Func */ #define CFA_RESOURCE_TYPE_P58_PROF_FUNC 0x18UL /* Profile TCAM */ @@ -158,40 +162,40 @@ #define CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 0x6UL /* 64B Counters */ #define CFA_RESOURCE_TYPE_P45_COUNTER_64B 0x7UL -/* Network Address Translation Source Port */ -#define CFA_RESOURCE_TYPE_P45_NAT_SPORT 0x8UL -/* Network Address Translation Destination Port */ -#define CFA_RESOURCE_TYPE_P45_NAT_DPORT 0x9UL -/* Network Address Translation Source IPv4 address */ -#define CFA_RESOURCE_TYPE_P45_NAT_S_IPV4 0xaUL -/* Network Address Translation Destination IPv4 address */ -#define CFA_RESOURCE_TYPE_P45_NAT_D_IPV4 0xbUL +/* Network Address Translation Port */ +#define CFA_RESOURCE_TYPE_P45_NAT_PORT 0x8UL +/* Network Address Translation IPv4 address */ +#define CFA_RESOURCE_TYPE_P45_NAT_IPV4 0x9UL /* Meter */ -#define CFA_RESOURCE_TYPE_P45_METER 0xcUL +#define CFA_RESOURCE_TYPE_P45_METER 0xaUL /* Flow State */ -#define CFA_RESOURCE_TYPE_P45_FLOW_STATE 0xdUL +#define CFA_RESOURCE_TYPE_P45_FLOW_STATE 0xbUL /* Full Action Records */ -#define CFA_RESOURCE_TYPE_P45_FULL_ACTION 0xeUL +#define CFA_RESOURCE_TYPE_P45_FULL_ACTION 0xcUL /* Action Record Format 0 */ -#define CFA_RESOURCE_TYPE_P45_FORMAT_0_ACTION 0xfUL +#define CFA_RESOURCE_TYPE_P45_FORMAT_0_ACTION 0xdUL /* Action Record Ext Format 0 */ -#define CFA_RESOURCE_TYPE_P45_EXT_FORMAT_0_ACTION 0x10UL +#define CFA_RESOURCE_TYPE_P45_EXT_FORMAT_0_ACTION 0xeUL /* Action Record Format 1 */ -#define CFA_RESOURCE_TYPE_P45_FORMAT_1_ACTION 0x11UL +#define CFA_RESOURCE_TYPE_P45_FORMAT_1_ACTION 0xfUL /* Action Record Format 2 */ -#define CFA_RESOURCE_TYPE_P45_FORMAT_2_ACTION 0x12UL +#define CFA_RESOURCE_TYPE_P45_FORMAT_2_ACTION 0x10UL /* Action Record Format 3 */ -#define CFA_RESOURCE_TYPE_P45_FORMAT_3_ACTION 0x13UL +#define CFA_RESOURCE_TYPE_P45_FORMAT_3_ACTION 0x11UL /* Action Record Format 4 */ -#define CFA_RESOURCE_TYPE_P45_FORMAT_4_ACTION 0x14UL +#define CFA_RESOURCE_TYPE_P45_FORMAT_4_ACTION 0x12UL /* Action Record Format 5 */ -#define CFA_RESOURCE_TYPE_P45_FORMAT_5_ACTION 0x15UL +#define CFA_RESOURCE_TYPE_P45_FORMAT_5_ACTION 0x13UL /* Action Record Format 6 */ -#define CFA_RESOURCE_TYPE_P45_FORMAT_6_ACTION 0x16UL -/* L2 Context TCAM */ -#define CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM 0x17UL -/* L2 Context REMAP */ -#define CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP 0x18UL +#define CFA_RESOURCE_TYPE_P45_FORMAT_6_ACTION 0x14UL +/* L2 Context TCAM High priority entries */ +#define CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH 0x15UL +/* L2 Context TCAM Low priority entries */ +#define CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW 0x16UL +/* L2 Context REMAP high priority entries */ +#define CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH 0x17UL +/* L2 Context REMAP Low priority entries */ +#define CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW 0x18UL /* Profile Func */ #define CFA_RESOURCE_TYPE_P45_PROF_FUNC 0x19UL /* Profile TCAM */ @@ -233,40 +237,40 @@ #define CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 0x6UL /* 64B Counters */ #define CFA_RESOURCE_TYPE_P4_COUNTER_64B 0x7UL -/* Network Address Translation Source Port */ -#define CFA_RESOURCE_TYPE_P4_NAT_SPORT 0x8UL -/* Network Address Translation Destination Port */ -#define CFA_RESOURCE_TYPE_P4_NAT_DPORT 0x9UL -/* Network Address Translation Source IPv4 address */ -#define CFA_RESOURCE_TYPE_P4_NAT_S_IPV4 0xaUL -/* Network Address Translation Destination IPv4 address */ -#define CFA_RESOURCE_TYPE_P4_NAT_D_IPV4 0xbUL +/* Network Address Translation Port */ +#define CFA_RESOURCE_TYPE_P4_NAT_PORT 0x8UL +/* Network Address Translation IPv4 address */ +#define CFA_RESOURCE_TYPE_P4_NAT_IPV4 0x9UL /* Meter */ -#define CFA_RESOURCE_TYPE_P4_METER 0xcUL +#define CFA_RESOURCE_TYPE_P4_METER 0xaUL /* Flow State */ -#define CFA_RESOURCE_TYPE_P4_FLOW_STATE 0xdUL +#define CFA_RESOURCE_TYPE_P4_FLOW_STATE 0xbUL /* Full Action Records */ -#define CFA_RESOURCE_TYPE_P4_FULL_ACTION 0xeUL +#define CFA_RESOURCE_TYPE_P4_FULL_ACTION 0xcUL /* Action Record Format 0 */ -#define CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION 0xfUL +#define CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION 0xdUL /* Action Record Ext Format 0 */ -#define CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION 0x10UL +#define CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION 0xeUL /* Action Record Format 1 */ -#define CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION 0x11UL +#define CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION 0xfUL /* Action Record Format 2 */ -#define CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION 0x12UL +#define CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION 0x10UL /* Action Record Format 3 */ -#define CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION 0x13UL +#define CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION 0x11UL /* Action Record Format 4 */ -#define CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION 0x14UL +#define CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION 0x12UL /* Action Record Format 5 */ -#define CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION 0x15UL +#define CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION 0x13UL /* Action Record Format 6 */ -#define CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION 0x16UL -/* L2 Context TCAM */ -#define CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM 0x17UL -/* L2 Context REMAP */ -#define CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP 0x18UL +#define CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION 0x14UL +/* L2 Context TCAM High priority entries */ +#define CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH 0x15UL +/* L2 Context TCAM Low priority entries */ +#define CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW 0x16UL +/* L2 Context REMAP high priority entries */ +#define CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH 0x17UL +/* L2 Context REMAP Low priority entries */ +#define CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW 0x18UL /* Profile Func */ #define CFA_RESOURCE_TYPE_P4_PROF_FUNC 0x19UL /* Profile TCAM */ diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 758685e..8fa734a 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -162,7 +162,13 @@ enum tf_identifier_type { * and can be used in WC TCAM or EM keys to virtualize further * lookups. */ - TF_IDENT_TYPE_L2_CTXT, + TF_IDENT_TYPE_L2_CTXT_HIGH, + /** + * The L2 Context is returned from the L2 Ctxt TCAM lookup + * and can be used in WC TCAM or EM keys to virtualize further + * lookups. + */ + TF_IDENT_TYPE_L2_CTXT_LOW, /** * The WC profile func is returned from the L2 Ctxt TCAM lookup * to enable virtualization of the profile TCAM. @@ -270,7 +276,9 @@ enum tf_tbl_type { */ enum tf_tcam_tbl_type { /** L2 Context TCAM */ - TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + /** L2 Context TCAM */ + TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, /** Profile TCAM */ TF_TCAM_TBL_TYPE_PROF_TCAM, /** Wildcard TCAM */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index 7fabb4b..06c3ecf 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -14,7 +14,8 @@ #include "tf_global_cfg.h" struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID }, @@ -23,7 +24,8 @@ struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { }; struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM }, @@ -45,10 +47,10 @@ struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_SPORT }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_DPORT }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_S_IPV4 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_D_IPV4 }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR }, diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index aeee3b3..bf6a6a3 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -24,8 +24,10 @@ const char * tf_ident_2_str(enum tf_identifier_type id_type) { switch (id_type) { - case TF_IDENT_TYPE_L2_CTXT: - return "l2_ctxt_remap"; + case TF_IDENT_TYPE_L2_CTXT_HIGH: + return "l2_ctxt_remap_high"; + case TF_IDENT_TYPE_L2_CTXT_LOW: + return "l2_ctxt_remap_low"; case TF_IDENT_TYPE_PROF_FUNC: return "prof_func"; case TF_IDENT_TYPE_WC_PROF: @@ -43,8 +45,10 @@ const char * tf_tcam_tbl_2_str(enum tf_tcam_tbl_type tcam_type) { switch (tcam_type) { - case TF_TCAM_TBL_TYPE_L2_CTXT_TCAM: - return "l2_ctxt_tcam"; + case TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH: + return "l2_ctxt_tcam_high"; + case TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW: + return "l2_ctxt_tcam_low"; case TF_TCAM_TBL_TYPE_PROF_TCAM: return "prof_tcam"; case TF_TCAM_TBL_TYPE_WC_TCAM: diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 6b0a403..c4ce003 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -86,7 +86,7 @@ ulp_ctx_session_open(struct bnxt *bp, resources = ¶ms.resources; /** RX **/ /* Identifiers */ - resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT] = 16; + resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 16; resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 8; resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 8; resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 8; @@ -96,7 +96,8 @@ ulp_ctx_session_open(struct bnxt *bp, resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 720; /* TCAMs */ - resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM] = 16; + resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = + 16; resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 8; resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 416; @@ -108,7 +109,7 @@ ulp_ctx_session_open(struct bnxt *bp, /** TX **/ /* Identifiers */ - resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT] = 8; + resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 8; resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 8; resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 8; resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 8; @@ -122,7 +123,8 @@ ulp_ctx_session_open(struct bnxt *bp, resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 16; /* TCAMs */ - resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM] = 8; + resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = + 8; resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 8; resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 8; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index feac30a..1fd5ab4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -162,7 +162,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -217,7 +217,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -264,7 +264,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -297,7 +297,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -316,7 +316,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -335,7 +335,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -390,7 +390,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -437,7 +437,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -470,7 +470,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -489,7 +489,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -522,7 +522,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, @@ -539,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -611,7 +611,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, .direction = TF_DIR_RX, @@ -628,7 +628,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_RX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -700,7 +700,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, .direction = TF_DIR_TX, @@ -717,7 +717,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, .direction = TF_DIR_TX, .priority = BNXT_ULP_PRIORITY_LEVEL_0, .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, @@ -5295,7 +5295,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 @@ -5309,7 +5309,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 @@ -5323,7 +5323,7 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .ident_type = TF_IDENT_TYPE_L2_CTXT, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 9a27cbf..24bde57 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -345,13 +345,13 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { }, [2] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_L2_CTXT, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID, .direction = TF_DIR_RX }, [3] = { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_L2_CTXT, + .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID, .direction = TF_DIR_TX }, From patchwork Fri Jul 17 09:49:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74303 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A30F7A053D; Fri, 17 Jul 2020 11:55:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 365071BFBB; Fri, 17 Jul 2020 11:54:59 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 9053D1BFA3 for ; Fri, 17 Jul 2020 11:54:54 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 309181BBD65; Fri, 17 Jul 2020 02:54:53 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 309181BBD65 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979695; bh=y9c3EnM5AOnZIszaRjxmd/T6owFDuPIg0SmhhT7+Mak=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=opg3RrnDC0qSBSQStHtsohHFqZuSA5/8IAy4jfTSPgL3ELYuP0u8ciLDcr/8hfH6K Q4fQyJhtMbiiOYkuVW69+ohfoINMGsoCEFgwCF9WZV6XxNVqdWv/HHNbFPEQRQ1K1P VuVZCvsAaB8VbpS/qDkPWqcBCZQGMNcjdhiSefiM= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:23 +0530 Message-Id: <20200717094935.9337-3-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 02/14] net/bnxt: initialize table scope rm parameters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Clear out rm_is_allocated parms before calling as base_index was added and is not used in this instance. Signed-off-by: Farah Smith Reviewed-by: Kishore Padmanabha Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_core/tf_em_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c index 10c3f16..0037fce 100644 --- a/drivers/net/bnxt/tf_core/tf_em_common.c +++ b/drivers/net/bnxt/tf_core/tf_em_common.c @@ -71,7 +71,7 @@ struct tf_tbl_scope_cb * tbl_scope_cb_find(uint32_t tbl_scope_id) { int i; - struct tf_rm_is_allocated_parms parms; + struct tf_rm_is_allocated_parms parms = { 0 }; int allocated; uint32_t rm_tbl_scope_id; From patchwork Fri Jul 17 09:49:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74304 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AE1A2A053D; Fri, 17 Jul 2020 11:55:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CD45E1BFD1; Fri, 17 Jul 2020 11:55:00 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id E6DF01BFB1 for ; Fri, 17 Jul 2020 11:54:55 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 840071BBDE1; Fri, 17 Jul 2020 02:54:55 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 840071BBDE1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979696; bh=6qPim9/BFaxVxKpeRdJJA3wij3T9l7YRpOQ+EkY5pww=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MnhKy4/pucku6RwHw3oqmaPQKPydhs8lGFO6lShoryKzMe1QRGDf0d1ECcb/m+OId 2u58HuhZF1cvaHKXXhyLQKFS4OU1tuhQfzP4hu4Usciine4LJpndjoYu1f4vvT/NHf wVFmmzU2HTvscbd2256aVpdpmEFOY5P5xX74YoSI= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:24 +0530 Message-Id: <20200717094935.9337-4-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 03/14] net/bnxt: enable default flows in truflow mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Removed the check to enable default flows only when VF representor are enabled. It should be enabled all the time in truflow mode. Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Signed-off-by: Somnath Kotur --- drivers/net/bnxt/bnxt_ethdev.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 318d6b3..0829493 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -1404,8 +1404,7 @@ static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) bnxt_cancel_fc_thread(bp); if (BNXT_TRUFLOW_EN(bp)) { - if (bp->rep_info != NULL) - bnxt_destroy_df_rules(bp); + bnxt_destroy_df_rules(bp); bnxt_ulp_deinit(bp); } @@ -1657,7 +1656,7 @@ static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) if (rc != 0) vnic->flags = old_flags; - if (BNXT_TRUFLOW_EN(bp) && bp->rep_info != NULL) + if (BNXT_TRUFLOW_EN(bp)) bnxt_create_df_rules(bp); return rc; From patchwork Fri Jul 17 09:49:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74305 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1ECDA053D; Fri, 17 Jul 2020 11:55:30 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 42C021BFE7; Fri, 17 Jul 2020 11:55:02 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 507271BFB6 for ; Fri, 17 Jul 2020 11:54:57 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id D7B031BBF15; Fri, 17 Jul 2020 02:54:56 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com D7B031BBF15 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979697; bh=1q6Wubh0xbjV9xIJehH5Eejy9Fur7k0o7K3/nhceG1o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FWB7bWrTCLEC8JiN9+YTRS0jjmLEx/DZ8dlN47JN8GxPU8kBdYD+9LBfPNBnwMjk9 m7+knVanUbNcTChouv1Y4KjHTkAPrFG16CNYdCqRmhzSuKEBTdGhLRnHbu+C8gzhei UW6R9H5zsmiL/JvSRFawuzURD4ftkMcDb3SOoyJE= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:25 +0530 Message-Id: <20200717094935.9337-5-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 04/14] net/bnxt: fix to avoid accumulation of flow counters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" OVS-DPDK is accumulating the flow counters that are returned as part of the flow_query API and it is being issued atleast 3 times every second. So there is no need to accumulate the counts internally in the driver. Fixes: 306c2d28e247 ("net/bnxt: add support for flow query with action_type COUNT") Reviewed-by: Venkat Duvvuru Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c index 34a6ec3..febda94 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c @@ -315,8 +315,8 @@ static int ulp_get_single_flow_stat(struct tf *tfp, /* TBD - Get PKT/BYTE COUNT SHIFT/MASK from Template */ sw_cntr_indx = hw_cntr_id - fc_info->shadow_hw_tbl[dir].start_idx; sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][sw_cntr_indx]; - sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats, dparms); - sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats, dparms); + sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms); + sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms); return rc; } From patchwork Fri Jul 17 09:49:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74306 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C79E1A053D; Fri, 17 Jul 2020 11:55:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B27A71BFED; Fri, 17 Jul 2020 11:55:03 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 9748C1BFB7 for ; Fri, 17 Jul 2020 11:54:58 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 3E4871BBF40; Fri, 17 Jul 2020 02:54:58 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 3E4871BBF40 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979699; bh=LvKZepKw8uId0JoAFhXKAJfBBv52gBLj/DBNfhLOKPs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uDmsl9fIXWehXhLCCl7vzbnNakdHjXRcwVj4cY9xD//CjXaCxXIYj/YPwiVE3LLQw ZzemQ+WAcWzsa70t/mc1n512KERRG8ktPZV3BqTwGIoHzcKZVbXUjKUPg9IlpAEljM SuR6jToIR/oesyIW/olEj3ji6ok4T/YiPDN5qUGk= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:26 +0530 Message-Id: <20200717094935.9337-6-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 05/14] net/bnxt: add protocol header info based on proto field data X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The protocol header are implicitly matched based on the proto field data. For instance, if ether type is set as 0x800 in the ether header then ipv4 protocol header is assumed to be present for template matching even if ipv4 header is not present in the given flow pattern. Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 180 +++++++++++++++++++------ drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 4 +- drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 + 3 files changed, 140 insertions(+), 45 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c index 4c1221a..3891bcd 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c +++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c @@ -16,6 +16,7 @@ #define ULP_VLAN_PRIORITY_SHIFT 13 /* First 3 bits */ #define ULP_VLAN_PRIORITY_MASK 0x700 #define ULP_VLAN_TAG_MASK 0xFFF /* Last 12 bits*/ +#define ULP_UDP_PORT_VXLAN 4789 /* Utility function to skip the void items. */ static inline int32_t @@ -209,6 +210,9 @@ bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params) } } + /* Merge the hdr_fp_bit into the proto header bit */ + params->hdr_bitmap.bits |= params->hdr_fp_bit.bits; + /* TBD: Handle the flow rejection scenarios */ return 0; } @@ -493,6 +497,34 @@ ulp_rte_phy_port_hdr_handler(const struct rte_flow_item *item, return BNXT_TF_RC_SUCCESS; } +/* Function to handle the update of proto header based on field values */ +static void +ulp_rte_l2_proto_type_update(struct ulp_rte_parser_params *param, + uint16_t type, uint32_t in_flag) +{ + if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV4)) { + if (in_flag) { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_I_IPV4); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_I_L3, 1); + } else { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_O_IPV4); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L3, 1); + } + } else if (type == tfp_cpu_to_be_16(RTE_ETHER_TYPE_IPV6)) { + if (in_flag) { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_I_IPV6); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_I_L3, 1); + } else { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_O_IPV6); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L3, 1); + } + } +} + /* Function to handle the parsing of RTE Flow item Ethernet Header. */ int32_t ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, @@ -502,8 +534,9 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, const struct rte_flow_item_eth *eth_mask = item->mask; struct ulp_rte_hdr_field *field; uint32_t idx = params->field_idx; - uint64_t set_flag = 0; uint32_t size; + uint16_t eth_type = 0; + uint32_t inner_flag = 0; /* * Copy the rte_flow_item for eth into hdr_field using ethernet @@ -521,6 +554,7 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(field, ð_spec->type, sizeof(eth_spec->type)); + eth_type = eth_spec->type; } if (eth_mask) { ulp_rte_prsr_mask_copy(params, &idx, eth_mask->dst.addr_bytes, @@ -535,17 +569,15 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item, params->vlan_idx = params->field_idx; params->field_idx += BNXT_ULP_PROTO_HDR_VLAN_NUM; - /* Update the hdr_bitmap with BNXT_ULP_HDR_PROTO_I_ETH */ - set_flag = ULP_BITMAP_ISSET(params->hdr_bitmap.bits, - BNXT_ULP_HDR_BIT_O_ETH); - if (set_flag) + /* Update the protocol hdr bitmap */ + if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH)) { ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_I_ETH); - else - ULP_BITMAP_RESET(params->hdr_bitmap.bits, - BNXT_ULP_HDR_BIT_I_ETH); - - /* update the hdr_bitmap with BNXT_ULP_HDR_PROTO_O_ETH */ - ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH); + inner_flag = 1; + } else { + ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH); + } + /* Update the field protocol hdr bitmap */ + ulp_rte_l2_proto_type_update(params, eth_type, inner_flag); return BNXT_TF_RC_SUCCESS; } @@ -563,6 +595,8 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, uint16_t vlan_tag, priority; uint32_t outer_vtag_num; uint32_t inner_vtag_num; + uint16_t eth_type = 0; + uint32_t inner_flag = 0; /* * Copy the rte_flow_item for vlan into hdr_field using Vlan @@ -583,6 +617,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(field, &vlan_spec->inner_type, sizeof(vlan_spec->inner_type)); + eth_type = vlan_spec->inner_type; } if (vlan_mask) { @@ -653,6 +688,7 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 1); ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_IO_VLAN); + inner_flag = 1; } else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) && ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) && inner_vtag_num == 1) { @@ -664,13 +700,44 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item, ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_ONE_VTAG, 0); ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_II_VLAN); + inner_flag = 1; } else { BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n"); return BNXT_TF_RC_ERROR; } + /* Update the field protocol hdr bitmap */ + ulp_rte_l2_proto_type_update(params, eth_type, inner_flag); return BNXT_TF_RC_SUCCESS; } +/* Function to handle the update of proto header based on field values */ +static void +ulp_rte_l3_proto_type_update(struct ulp_rte_parser_params *param, + uint8_t proto, uint32_t in_flag) +{ + if (proto == IPPROTO_UDP) { + if (in_flag) { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_I_UDP); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_I_L4, 1); + } else { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_O_UDP); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L4, 1); + } + } else if (proto == IPPROTO_TCP) { + if (in_flag) { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_I_TCP); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_I_L4, 1); + } else { + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_O_TCP); + ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L4, 1); + } + } +} + /* Function to handle the parsing of RTE Flow item IPV4 Header. */ int32_t ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, @@ -682,11 +749,14 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; uint32_t size; - uint32_t inner_l3, outer_l3; - - inner_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L3); - if (inner_l3) { - BNXT_TF_DBG(ERR, "Parse Error:Third L3 header not supported\n"); + uint8_t proto = 0; + uint32_t inner_flag = 0; + uint32_t cnt; + + /* validate there are no 3rd L3 header */ + cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_HDR_CNT); + if (cnt == 2) { + BNXT_TF_DBG(ERR, "Parse Err:Third L3 header not supported\n"); return BNXT_TF_RC_ERROR; } @@ -723,6 +793,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(field, &ipv4_spec->hdr.next_proto_id, size); + proto = ipv4_spec->hdr.next_proto_id; size = sizeof(ipv4_spec->hdr.hdr_checksum); field = ulp_rte_parser_fld_copy(field, &ipv4_spec->hdr.hdr_checksum, @@ -782,18 +853,19 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item, params->field_idx += BNXT_ULP_PROTO_HDR_IPV4_NUM; /* Set the ipv4 header bitmap and computed l3 header bitmaps */ - outer_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L3); - if (outer_l3 || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || + if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4); - inner_l3++; - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, inner_l3); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); + inner_flag = 1; } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4); - outer_l3++; - ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, outer_l3); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } + + /* Update the field protocol hdr bitmap */ + ulp_rte_l3_proto_type_update(params, proto, inner_flag); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); return BNXT_TF_RC_SUCCESS; } @@ -808,12 +880,15 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; uint32_t size; - uint32_t inner_l3, outer_l3; uint32_t vtcf, vtcf_mask; - - inner_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L3); - if (inner_l3) { - BNXT_TF_DBG(ERR, "Parse Error: 3'rd L3 header not supported\n"); + uint8_t proto = 0; + uint32_t inner_flag = 0; + uint32_t cnt; + + /* validate there are no 3rd L3 header */ + cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_HDR_CNT); + if (cnt == 2) { + BNXT_TF_DBG(ERR, "Parse Err:Third L3 header not supported\n"); return BNXT_TF_RC_ERROR; } @@ -847,6 +922,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(field, &ipv6_spec->hdr.proto, size); + proto = ipv6_spec->hdr.proto; size = sizeof(ipv6_spec->hdr.hop_limits); field = ulp_rte_parser_fld_copy(field, &ipv6_spec->hdr.hop_limits, @@ -899,19 +975,33 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item, params->field_idx += BNXT_ULP_PROTO_HDR_IPV6_NUM; /* Set the ipv6 header bitmap and computed l3 header bitmaps */ - outer_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L3); - if (outer_l3 || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || + if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) || ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1); + inner_flag = 1; } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1); } + + /* Update the field protocol hdr bitmap */ + ulp_rte_l3_proto_type_update(params, proto, inner_flag); + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt); + return BNXT_TF_RC_SUCCESS; } +/* Function to handle the update of proto header based on field values */ +static void +ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param, + uint16_t dst_port) +{ + if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) + ULP_BITMAP_SET(param->hdr_fp_bit.bits, + BNXT_ULP_HDR_BIT_T_VXLAN); +} + /* Function to handle the parsing of RTE Flow item UDP Header. */ int32_t ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, @@ -923,10 +1013,11 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; uint32_t size; - uint32_t inner_l4, outer_l4; + uint16_t dst_port = 0; + uint32_t cnt; - inner_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L4); - if (inner_l4) { + cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT); + if (cnt == 2) { BNXT_TF_DBG(ERR, "Parse Err:Third L4 header not supported\n"); return BNXT_TF_RC_ERROR; } @@ -944,6 +1035,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dst_port, size); + dst_port = udp_spec->hdr.dst_port; size = sizeof(udp_spec->hdr.dgram_len); field = ulp_rte_parser_fld_copy(field, &udp_spec->hdr.dgram_len, @@ -972,16 +1064,17 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item, params->field_idx += BNXT_ULP_PROTO_HDR_UDP_NUM; /* Set the udp header bitmap and computed l4 header bitmaps */ - outer_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L4); - if (outer_l4 || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) || + if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) || ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); } else { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); + /* Update the field protocol hdr bitmap */ + ulp_rte_l4_proto_type_update(params, dst_port); } + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt); return BNXT_TF_RC_SUCCESS; } @@ -996,11 +1089,11 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; uint32_t idx = params->field_idx; uint32_t size; - uint32_t inner_l4, outer_l4; + uint32_t cnt; - inner_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L4); - if (inner_l4) { - BNXT_TF_DBG(ERR, "Parse Error:Third L4 header not supported\n"); + cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT); + if (cnt == 2) { + BNXT_TF_DBG(ERR, "Parse Err:Third L4 header not supported\n"); return BNXT_TF_RC_ERROR; } @@ -1082,9 +1175,7 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, params->field_idx += BNXT_ULP_PROTO_HDR_TCP_NUM; /* Set the udp header bitmap and computed l4 header bitmaps */ - outer_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L4); - if (outer_l4 || - ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) || + if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) || ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) { ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1); @@ -1092,6 +1183,7 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item, ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP); ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1); } + ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L4_HDR_CNT, ++cnt); return BNXT_TF_RC_SUCCESS; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 6b68b95..a9295e0 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -132,7 +132,9 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_ACT_PORT_TYPE = 36, BNXT_ULP_CF_IDX_MATCH_PORT_TYPE = 37, BNXT_ULP_CF_IDX_VF_TO_VF = 38, - BNXT_ULP_CF_IDX_LAST = 39 + BNXT_ULP_CF_IDX_L3_HDR_CNT = 39, + BNXT_ULP_CF_IDX_L4_HDR_CNT = 40, + BNXT_ULP_CF_IDX_LAST = 41 }; enum bnxt_ulp_cond_opcode { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h index 2f2f9a2..b9a25b0 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h @@ -63,6 +63,7 @@ struct ulp_rte_act_prop { /* Structure to be used for passing all the parser functions */ struct ulp_rte_parser_params { struct ulp_rte_hdr_bitmap hdr_bitmap; + struct ulp_rte_hdr_bitmap hdr_fp_bit; struct ulp_rte_field_bitmap fld_bitmap; struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX]; uint32_t comp_fld[BNXT_ULP_CF_IDX_LAST]; From patchwork Fri Jul 17 09:49:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74307 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2B072A053D; Fri, 17 Jul 2020 11:55:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 420EF1BFF9; Fri, 17 Jul 2020 11:55:05 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id EF5B51BFBF for ; Fri, 17 Jul 2020 11:54:59 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 89CD61BBDAF; Fri, 17 Jul 2020 02:54:59 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 89CD61BBDAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979700; bh=FVV+/oXAKPF7XewWiX9CHn/mcqO86NtdFdFAN42QXEE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NnwnVTBKxyK1czP9WzX99LEDdlb4C2ZLoGHo9CxMRXdUJA2ol9VthA1MWuEjUCLiN STcZYE8XQntD4kr08Tcl00MA5WAr0iEGZsi2DK0Eg96WOPDnqjcNFQJSsp5rr4r3vn xF3pq2TOMmav0RN/N4kNdF2BNPGNhNXegrGYaGwo= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:27 +0530 Message-Id: <20200717094935.9337-7-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 06/14] net/bnxt: fix em message size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Farah Smith Fix incorrect EM message size fix for insert_em_internal. Fixes: 98487d729b4a ("net/bnxt: cleanup and refactor session management") Signed-off-by: Farah Smith Reviewed-by: Randy Schacher Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_core/tf_msg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 53515ad..2e2d426 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -27,7 +27,7 @@ * tf.yaml changes. */ #define TF_MSG_SET_GLOBAL_CFG_DATA_SIZE 16 -#define TF_MSG_EM_INSERT_KEY_SIZE 8 +#define TF_MSG_EM_INSERT_KEY_SIZE 64 #define TF_MSG_TCAM_SET_DEV_DATA_SIZE 88 #define TF_MSG_TBL_TYPE_SET_DATA_SIZE 88 From patchwork Fri Jul 17 09:49:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74308 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71692A053D; Fri, 17 Jul 2020 11:55:59 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2874A1BFFD; Fri, 17 Jul 2020 11:55:09 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 464C61BFE4 for ; Fri, 17 Jul 2020 11:55:01 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id DF7131BBCD0; Fri, 17 Jul 2020 02:55:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com DF7131BBCD0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979701; bh=fTHmNmI6w0eTRSSd08SuWL9BWu7UjWuKAPgf/1zdIZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LPcprdrWr1ZhM9IiLBQewWJ/njzouszaIV3Wh/+T1LjygEKle1YH7HsEAXuFrx50W vd2EYBaSJvDw5Hn4KX3H63zuJe1JiPFWxsGqnjweZVjg74IuQhQ128dLBDCmqv/MGg plWEh4/6B1h7eze94TusX/ZEvQuu0WBU2Vv8EAkY= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:28 +0530 Message-Id: <20200717094935.9337-8-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 07/14] net/bnxt: replace NAT IPv4 action SRC/DEST X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding Use NAT IPv4 instead of NAT IPv4 SRC and DST. Signed-off-by: Jay Ding Reviewed-by: Kishore Padmanabha Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_core/tf_core.h | 4 +--- drivers/net/bnxt/tf_core/tf_device_p4.h | 1 - drivers/net/bnxt/tf_core/tf_util.c | 6 ++---- 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index 8fa734a..67415ad 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -228,9 +228,7 @@ enum tf_tbl_type { /** Wh+/SR Action Modify L4 Dest Port */ TF_TBL_TYPE_ACT_MODIFY_DPORT, /** Wh+/SR Action Modify IPv4 Source */ - TF_TBL_TYPE_ACT_MODIFY_IPV4_SRC, - /** Wh+/SR Action _Modify L4 Dest Port */ - TF_TBL_TYPE_ACT_MODIFY_IPV4_DEST, + TF_TBL_TYPE_ACT_MODIFY_IPV4, /** Meter Profiles */ TF_TBL_TYPE_METER_PROF, /** Meter Instance */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index 06c3ecf..7e58469 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -50,7 +50,6 @@ struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 }, - { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER }, { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR }, diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c index bf6a6a3..34f4305 100644 --- a/drivers/net/bnxt/tf_core/tf_util.c +++ b/drivers/net/bnxt/tf_core/tf_util.c @@ -92,10 +92,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type) return "NAT Source Port"; case TF_TBL_TYPE_ACT_MODIFY_DPORT: return "NAT Destination Port"; - case TF_TBL_TYPE_ACT_MODIFY_IPV4_SRC: - return "NAT IPv4 Source"; - case TF_TBL_TYPE_ACT_MODIFY_IPV4_DEST: - return "NAT IPv4 Destination"; + case TF_TBL_TYPE_ACT_MODIFY_IPV4: + return "NAT IPv4"; case TF_TBL_TYPE_METER_PROF: return "Meter Profile"; case TF_TBL_TYPE_METER_INST: From patchwork Fri Jul 17 09:49:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74309 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37A75A053D; Fri, 17 Jul 2020 11:56:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8C8181C00F; Fri, 17 Jul 2020 11:55:10 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id ACB6C1BFC3 for ; Fri, 17 Jul 2020 11:55:02 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 35A0A1BBF15; Fri, 17 Jul 2020 02:55:02 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 35A0A1BBF15 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979703; bh=+Vbc1sbYlWD/8M70x+WilbyoPv/lw3WThDpQ8UHViL0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NwXhx1m4/p8MYstUY8PcI7RhrYzR0mzwkHnz7hqHIgbgLaTWokY7WnaYCrB2QyeB9 8ukvrDBuFETVYx4rwp0525968JauejsUz7bSmtHY/WE3bf5+ggK+j9V11EjbwU20FW uV61pMp+TTfdnoHprdguKQl0bJ43EGus/cUMumSU= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:29 +0530 Message-Id: <20200717094935.9337-9-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 08/14] net/bnxt: clean up em message definition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Randy Schacher Remove unused define Signed-off-by: Randy Schacher Reviewed-by: Randy Schacher Reviewed-by: Shahaji Bhosle Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_core/tf_msg.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c index 2e2d426..db471f6 100644 --- a/drivers/net/bnxt/tf_core/tf_msg.c +++ b/drivers/net/bnxt/tf_core/tf_msg.c @@ -28,7 +28,6 @@ */ #define TF_MSG_SET_GLOBAL_CFG_DATA_SIZE 16 #define TF_MSG_EM_INSERT_KEY_SIZE 64 -#define TF_MSG_TCAM_SET_DEV_DATA_SIZE 88 #define TF_MSG_TBL_TYPE_SET_DATA_SIZE 88 /* Compile check - Catch any msg changes that we depend on, like the From patchwork Fri Jul 17 09:49:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74310 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BCB91A053D; Fri, 17 Jul 2020 11:56:18 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D51361C021; Fri, 17 Jul 2020 11:55:11 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id EF7FD1BFF0 for ; Fri, 17 Jul 2020 11:55:03 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 8BB591BC075; Fri, 17 Jul 2020 02:55:03 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 8BB591BC075 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979704; bh=WyzQCD85JITC/GvLh+cnqLtT40O9w2OHikvjarDgoQ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s7iTAdV7RAzHo9GlahUe1FX0LBddV6zlUkyFzO96ifyKi2BPqOFHswjGHF0gEVFLI HAkdGQ+osduYvQ9NfRjlMnOWVX5imsoq3mfQxCN1tvytgHMvHGpnCZyY64f5Lhy9Bd kxqJ56ubK8xqWWxnHJDgajmA1lFq2JaxK8gjntjI= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:30 +0530 Message-Id: <20200717094935.9337-10-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 09/14] net/bnxt: change header to SPDX-License X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Randy Schacher Update include file header Signed-off-by: Randy Schacher Reviewed-by: Ajit Kumar Khaparde Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_core/cfa_resource_types.h | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index 45b26b2..19838c3 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -1,13 +1,6 @@ -/* - * Copyright(c) 2001-2020, Broadcom. All rights reserved. The - * term Broadcom refers to Broadcom Inc. and/or its subsidiaries. - * Proprietary and Confidential Information. - * - * This source file is the property of Broadcom Corporation, and - * may not be copied or distributed in any isomorphic form without - * the prior written consent of Broadcom Corporation. - * - * DO NOT MODIFY!!! This file is automatically generated. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2020 Broadcom + * All rights reserved. */ #ifndef _CFA_RESOURCE_TYPES_H_ From patchwork Fri Jul 17 09:49:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74311 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B837A053D; Fri, 17 Jul 2020 11:56:24 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 424781C02C; Fri, 17 Jul 2020 11:55:13 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 4C40F1BFFA for ; Fri, 17 Jul 2020 11:55:05 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id DF0461BBDAF; Fri, 17 Jul 2020 02:55:04 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com DF0461BBDAF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979705; bh=iIIQHaoz4dvgkngTRxCcSekY7mOrHj1lhvqSt93jrfg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pelFV+m/RfPXuQDDvo2YN/3/uokg1OYQzhxvH8J38QiOtcN5ren+Q+9kOlYplkg0B W1KTiF9tQAeOeUoI/D9iCsCEHyxosth58b0DUtwLlemUfCdafGD2d5NQ0LyxM5HHWB fRmGVT9Mc/JnmGivwN+YOytL1M2s4HyDuO3VzjWY= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:31 +0530 Message-Id: <20200717094935.9337-11-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 10/14] net/bnxt: fix dereference of a null pointer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Avoid dereferencing a null pointer. Fixes: 313ac35ac701 ("net/bnxt: support ULP session manager init") Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c index b2c8c34..4df850f 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c @@ -120,9 +120,11 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt) return 0; mem_error: - rte_free(mark_tbl->gfid_tbl); - rte_free(mark_tbl->lfid_tbl); - rte_free(mark_tbl); + if (mark_tbl) { + rte_free(mark_tbl->gfid_tbl); + rte_free(mark_tbl->lfid_tbl); + rte_free(mark_tbl); + } BNXT_TF_DBG(DEBUG, "Failed to allocate memory for mark mgr\n"); return -ENOMEM; } From patchwork Fri Jul 17 09:49:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74312 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19C41A053D; Fri, 17 Jul 2020 11:56:33 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 956EC1C034; Fri, 17 Jul 2020 11:55:14 +0200 (CEST) Received: from relay.smtp.broadcom.com (relay.smtp.broadcom.com [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id AC0BA1BFFE for ; Fri, 17 Jul 2020 11:55:06 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 3E2191BBD65; Fri, 17 Jul 2020 02:55:06 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 3E2191BBD65 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979707; bh=abLWbq8WxZ/Up3f8d9Zb9l1jsoqb/EEEC2zeo75OLcY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P0789IRWDDwd6/z0Z9uT8u+lWWqPTZA40aJW5k/Id1gjRhvgwdXJPDVdungNtJXTX DI/38jd6CjUPX3tlqKy35KFeQDZpTqhR/Pd8+Nbbrsxb1+Mq1TwHjJSy7pl3g/Yhj8 7JiJfppdalGIUoHjGfIcY5IPtQxDI0Ab3QBOt4e8= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:32 +0530 Message-Id: <20200717094935.9337-12-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 11/14] net/bnxt: default egress rule changes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The default egress rule should include buffer descriptor action record only if the VF representor is enabled. Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 13 +++++++++++++ drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 9 +++++++++ drivers/net/bnxt/tf_ulp/ulp_def_rules.c | 11 ++++++++++- drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 3 ++- 4 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index c4ce003..8e44027 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -361,6 +361,7 @@ ulp_ctx_init(struct bnxt *bp, bp->ulp_ctx->cfg_data = ulp_data; session->cfg_data = ulp_data; ulp_data->ref_cnt++; + ulp_data->ulp_flags |= BNXT_ULP_VF_REP_ENABLED; /* Open the ulp session. */ rc = ulp_ctx_session_open(bp, session); @@ -1009,3 +1010,15 @@ bnxt_ulp_cntxt_ptr2_fc_info_get(struct bnxt_ulp_context *ulp_ctx) return ulp_ctx->cfg_data->fc_info; } + +/* Function to get the ulp flags from the ulp context. */ +int32_t +bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, + uint32_t *flags) +{ + if (!ulp_ctx || !ulp_ctx->cfg_data) + return -1; + + *flags = ulp_ctx->cfg_data->ulp_flags; + return 0; +} diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h index a133284..f9e5e2b 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h @@ -14,6 +14,10 @@ #include "ulp_template_db_enum.h" +/* defines for the ulp_flags */ +#define BNXT_ULP_VF_REP_ENABLED 0x1 +#define ULP_VF_REP_IS_ENABLED(flag) ((flag) & BNXT_ULP_VF_REP_ENABLED) + struct bnxt_ulp_data { uint32_t tbl_scope_id; struct bnxt_ulp_mark_tbl *mark_tbl; @@ -23,6 +27,7 @@ struct bnxt_ulp_data { void *mapper_data; struct bnxt_ulp_port_db *port_db; struct bnxt_ulp_fc_info *fc_info; + uint32_t ulp_flags; uint32_t port_to_app_flow_id; uint32_t app_to_port_flow_id; uint32_t tx_cfa_action; @@ -162,4 +167,8 @@ bnxt_ulp_cntxt_ptr2_fc_info_set(struct bnxt_ulp_context *ulp_ctx, struct bnxt_ulp_fc_info * bnxt_ulp_cntxt_ptr2_fc_info_get(struct bnxt_ulp_context *ulp_ctx); +int32_t +bnxt_ulp_cntxt_ptr2_ulp_flags_get(struct bnxt_ulp_context *ulp_ctx, + uint32_t *flags); + #endif /* _BNXT_ULP_H_ */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c index b01ad0b..4d4f7c4 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c +++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c @@ -309,7 +309,7 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, struct ulp_rte_act_prop act_prop; struct ulp_rte_act_bitmap act = { 0 }; struct bnxt_ulp_context *ulp_ctx; - uint32_t type; + uint32_t type, ulp_flags = 0; int rc; memset(&mapper_params, 0, sizeof(mapper_params)); @@ -329,6 +329,15 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev, return -EINVAL; } + /* update the vf rep flag */ + if (bnxt_ulp_cntxt_ptr2_ulp_flags_get(ulp_ctx, &ulp_flags)) { + BNXT_TF_DBG(ERR, "Error in getting ULP context flags\n"); + return -EINVAL; + } + if (ULP_VF_REP_IS_ENABLED(ulp_flags)) + ULP_COMP_FLD_IDX_WR(&mapper_params, + BNXT_ULP_CF_IDX_VFR_MODE, 1); + type = param_list->type; while (type != BNXT_ULP_DF_PARAM_TYPE_LAST) { if (ulp_def_handler_tbl[type].vfr_func) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index a9295e0..fbeb314 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -134,7 +134,8 @@ enum bnxt_ulp_cf_idx { BNXT_ULP_CF_IDX_VF_TO_VF = 38, BNXT_ULP_CF_IDX_L3_HDR_CNT = 39, BNXT_ULP_CF_IDX_L4_HDR_CNT = 40, - BNXT_ULP_CF_IDX_LAST = 41 + BNXT_ULP_CF_IDX_VFR_MODE = 41, + BNXT_ULP_CF_IDX_LAST = 42 }; enum bnxt_ulp_cond_opcode { From patchwork Fri Jul 17 09:49:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74313 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9ECBBA053D; Fri, 17 Jul 2020 11:56:43 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2437A1C043; Fri, 17 Jul 2020 11:55:16 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id E18F91BFCD for ; Fri, 17 Jul 2020 11:55:07 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id 8A9AC1BBDE1; Fri, 17 Jul 2020 02:55:07 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com 8A9AC1BBDE1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979708; bh=GHxEKwCjFokoyk4X8a5rOxQQNQsHzLjI7DPNzVtn4kM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Il0os5Nuo6jsE230Gnq0Rxk6jLLqFiLHzY9JbYQ4kDLebvKEo+fNbOUjpErihRcpO SlIjhUpRVc4tViPyoP99u92fVRo9TH73+wLU6D8OTJWs7tCqfRRI6UXhVNgMhpCl5L Iu5w//M8xUqSeWC1d6sNPS/0pOTQIdU0rPDP4ib4= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:33 +0530 Message-Id: <20200717094935.9337-13-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 12/14] net/bnxt: update cfa truflow resource allocation numbers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha The truflow session open allocation parameters are updated to support NAT records, L2 context regions, engress encap features. Signed-off-by: Kishore Padmanabha Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 8e44027..0869231 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -86,7 +86,8 @@ ulp_ctx_session_open(struct bnxt *bp, resources = ¶ms.resources; /** RX **/ /* Identifiers */ - resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 16; + resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 200; + resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 20; resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 8; resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 8; resources->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 8; @@ -94,10 +95,17 @@ ulp_ctx_session_open(struct bnxt *bp, /* Table Types */ resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 720; resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 720; + resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 8; + + /* ENCAP */ + resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 16; + resources->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 16; /* TCAMs */ resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = - 16; + 200; + resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = + 20; resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 8; resources->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 416; @@ -109,7 +117,8 @@ ulp_ctx_session_open(struct bnxt *bp, /** TX **/ /* Identifiers */ - resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 8; + resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 200; + resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 20; resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 8; resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 8; resources->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 8; @@ -117,6 +126,7 @@ ulp_ctx_session_open(struct bnxt *bp, /* Table Types */ resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 16; resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 16; + resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 8; /* ENCAP */ resources->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 16; @@ -124,7 +134,9 @@ ulp_ctx_session_open(struct bnxt *bp, /* TCAMs */ resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = - 8; + 200; + resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = + 20; resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 8; resources->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 8; From patchwork Fri Jul 17 09:49:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74315 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7512A053D; Fri, 17 Jul 2020 12:01:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 42A391BFCD; Fri, 17 Jul 2020 12:01:43 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 03EE01C014 for ; Fri, 17 Jul 2020 11:55:11 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id D78F11BBE60; Fri, 17 Jul 2020 02:55:08 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com D78F11BBE60 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979711; bh=liGgR+PUGwuA3YdseP9wdMGhrITKgssj0vb7Y0t536U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lVlP6XcAIZtqMy1vTpP5zqS5tlhv7cukzbnC0kxU5nztlOll8z3c7dg8h5rH5mfXS cuLCqbIxI1wmd/uKy24g2tQRY0v5bq6be4iAYlioJYA54xmGpu4WsoXc5pyyEEO7ZH 1ImStkQc1eQZ1aSUVzQMTtgNlXlLZOiJNCdHniTo= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:34 +0530 Message-Id: <20200717094935.9337-14-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> X-Mailman-Approved-At: Fri, 17 Jul 2020 12:01:40 +0200 Subject: [dpdk-dev] [PATCH 13/14] net/bnxt: enable support for exact match templates X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha Added support for exact match templates Signed-off-by: Kishore Padmanabha Reviewed-by: Somnath Kotur Signed-off-by: Somnath Kotur --- drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 2547 +++- drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 17515 ++++++++++++++++++---- drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 323 +- drivers/net/bnxt/tf_ulp/ulp_template_db_field.h | 959 +- drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 478 +- 5 files changed, 18250 insertions(+), 3572 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c index c587ff5..0f19e8e 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c @@ -9,389 +9,1909 @@ #include "ulp_rte_parser.h" uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_ACT_HID_0002] = 1, - [BNXT_ULP_ACT_HID_0022] = 2, - [BNXT_ULP_ACT_HID_0026] = 3, - [BNXT_ULP_ACT_HID_0006] = 4, - [BNXT_ULP_ACT_HID_0009] = 5, - [BNXT_ULP_ACT_HID_0029] = 6, - [BNXT_ULP_ACT_HID_002d] = 7, - [BNXT_ULP_ACT_HID_004b] = 8, - [BNXT_ULP_ACT_HID_004a] = 9, - [BNXT_ULP_ACT_HID_004f] = 10, - [BNXT_ULP_ACT_HID_004e] = 11, - [BNXT_ULP_ACT_HID_006c] = 12, - [BNXT_ULP_ACT_HID_0070] = 13, - [BNXT_ULP_ACT_HID_0021] = 14, - [BNXT_ULP_ACT_HID_0025] = 15, - [BNXT_ULP_ACT_HID_0043] = 16, - [BNXT_ULP_ACT_HID_0042] = 17, - [BNXT_ULP_ACT_HID_0047] = 18, - [BNXT_ULP_ACT_HID_0046] = 19, - [BNXT_ULP_ACT_HID_0064] = 20, - [BNXT_ULP_ACT_HID_0068] = 21, - [BNXT_ULP_ACT_HID_00a1] = 22, - [BNXT_ULP_ACT_HID_00df] = 23 + [BNXT_ULP_ACT_HID_015a] = 1, + [BNXT_ULP_ACT_HID_00eb] = 2, + [BNXT_ULP_ACT_HID_0043] = 3, + [BNXT_ULP_ACT_HID_01d6] = 4, + [BNXT_ULP_ACT_HID_015e] = 5, + [BNXT_ULP_ACT_HID_00ef] = 6, + [BNXT_ULP_ACT_HID_0047] = 7, + [BNXT_ULP_ACT_HID_01da] = 8, + [BNXT_ULP_ACT_HID_025b] = 9, + [BNXT_ULP_ACT_HID_01ec] = 10, + [BNXT_ULP_ACT_HID_0144] = 11, + [BNXT_ULP_ACT_HID_02d7] = 12, + [BNXT_ULP_ACT_HID_025f] = 13, + [BNXT_ULP_ACT_HID_01f0] = 14, + [BNXT_ULP_ACT_HID_0148] = 15, + [BNXT_ULP_ACT_HID_02db] = 16, + [BNXT_ULP_ACT_HID_0000] = 17, + [BNXT_ULP_ACT_HID_0002] = 18, + [BNXT_ULP_ACT_HID_0800] = 19, + [BNXT_ULP_ACT_HID_0101] = 20, + [BNXT_ULP_ACT_HID_0020] = 21, + [BNXT_ULP_ACT_HID_0901] = 22, + [BNXT_ULP_ACT_HID_0121] = 23, + [BNXT_ULP_ACT_HID_0004] = 24, + [BNXT_ULP_ACT_HID_0804] = 25, + [BNXT_ULP_ACT_HID_0105] = 26, + [BNXT_ULP_ACT_HID_0024] = 27, + [BNXT_ULP_ACT_HID_0905] = 28, + [BNXT_ULP_ACT_HID_0125] = 29, + [BNXT_ULP_ACT_HID_0001] = 30, + [BNXT_ULP_ACT_HID_0005] = 31, + [BNXT_ULP_ACT_HID_0009] = 32, + [BNXT_ULP_ACT_HID_000d] = 33, + [BNXT_ULP_ACT_HID_0021] = 34, + [BNXT_ULP_ACT_HID_0029] = 35, + [BNXT_ULP_ACT_HID_0025] = 36, + [BNXT_ULP_ACT_HID_002d] = 37, + [BNXT_ULP_ACT_HID_0801] = 38, + [BNXT_ULP_ACT_HID_0809] = 39, + [BNXT_ULP_ACT_HID_0805] = 40, + [BNXT_ULP_ACT_HID_080d] = 41, + [BNXT_ULP_ACT_HID_0c15] = 42, + [BNXT_ULP_ACT_HID_0c19] = 43, + [BNXT_ULP_ACT_HID_02f6] = 44, + [BNXT_ULP_ACT_HID_04f8] = 45, + [BNXT_ULP_ACT_HID_01df] = 46, + [BNXT_ULP_ACT_HID_05e3] = 47, + [BNXT_ULP_ACT_HID_02fa] = 48, + [BNXT_ULP_ACT_HID_04fc] = 49, + [BNXT_ULP_ACT_HID_01e3] = 50, + [BNXT_ULP_ACT_HID_05e7] = 51, + [BNXT_ULP_ACT_HID_03f7] = 52, + [BNXT_ULP_ACT_HID_05f9] = 53, + [BNXT_ULP_ACT_HID_02e0] = 54, + [BNXT_ULP_ACT_HID_06e4] = 55, + [BNXT_ULP_ACT_HID_03fb] = 56, + [BNXT_ULP_ACT_HID_05fd] = 57, + [BNXT_ULP_ACT_HID_02e4] = 58, + [BNXT_ULP_ACT_HID_06e8] = 59, + [BNXT_ULP_ACT_HID_040d] = 60, + [BNXT_ULP_ACT_HID_040f] = 61, + [BNXT_ULP_ACT_HID_0413] = 62, + [BNXT_ULP_ACT_HID_0c0d] = 63, + [BNXT_ULP_ACT_HID_0567] = 64, + [BNXT_ULP_ACT_HID_0a49] = 65, + [BNXT_ULP_ACT_HID_050e] = 66, + [BNXT_ULP_ACT_HID_0d0e] = 67, + [BNXT_ULP_ACT_HID_0668] = 68, + [BNXT_ULP_ACT_HID_0b4a] = 69, + [BNXT_ULP_ACT_HID_0411] = 70, + [BNXT_ULP_ACT_HID_056b] = 71, + [BNXT_ULP_ACT_HID_0a4d] = 72, + [BNXT_ULP_ACT_HID_0c11] = 73, + [BNXT_ULP_ACT_HID_0512] = 74, + [BNXT_ULP_ACT_HID_0d12] = 75, + [BNXT_ULP_ACT_HID_066c] = 76, + [BNXT_ULP_ACT_HID_0b4e] = 77 }; struct bnxt_ulp_act_match_info ulp_act_match_list[] = { [1] = { - .act_hid = BNXT_ULP_ACT_HID_0002, + .act_hid = BNXT_ULP_ACT_HID_015a, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [2] = { - .act_hid = BNXT_ULP_ACT_HID_0022, + .act_hid = BNXT_ULP_ACT_HID_00eb, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | - BNXT_ULP_ACTION_BIT_VNIC | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [3] = { - .act_hid = BNXT_ULP_ACT_HID_0026, + .act_hid = BNXT_ULP_ACT_HID_0043, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [4] = { - .act_hid = BNXT_ULP_ACT_HID_0006, + .act_hid = BNXT_ULP_ACT_HID_01d6, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_DROP | - BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [5] = { - .act_hid = BNXT_ULP_ACT_HID_0009, + .act_hid = BNXT_ULP_ACT_HID_015e, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [6] = { - .act_hid = BNXT_ULP_ACT_HID_0029, + .act_hid = BNXT_ULP_ACT_HID_00ef, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [7] = { - .act_hid = BNXT_ULP_ACT_HID_002d, + .act_hid = BNXT_ULP_ACT_HID_0047, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [8] = { - .act_hid = BNXT_ULP_ACT_HID_004b, + .act_hid = BNXT_ULP_ACT_HID_01da, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [9] = { - .act_hid = BNXT_ULP_ACT_HID_004a, + .act_hid = BNXT_ULP_ACT_HID_025b, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [10] = { - .act_hid = BNXT_ULP_ACT_HID_004f, + .act_hid = BNXT_ULP_ACT_HID_01ec, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [11] = { - .act_hid = BNXT_ULP_ACT_HID_004e, + .act_hid = BNXT_ULP_ACT_HID_0144, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_COUNT | BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [12] = { - .act_hid = BNXT_ULP_ACT_HID_006c, + .act_hid = BNXT_ULP_ACT_HID_02d7, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [13] = { - .act_hid = BNXT_ULP_ACT_HID_0070, + .act_hid = BNXT_ULP_ACT_HID_025f, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_RSS | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [14] = { - .act_hid = BNXT_ULP_ACT_HID_0021, + .act_hid = BNXT_ULP_ACT_HID_01f0, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [15] = { - .act_hid = BNXT_ULP_ACT_HID_0025, + .act_hid = BNXT_ULP_ACT_HID_0148, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | + BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [16] = { - .act_hid = BNXT_ULP_ACT_HID_0043, + .act_hid = BNXT_ULP_ACT_HID_02db, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 1 }, [17] = { - .act_hid = BNXT_ULP_ACT_HID_0042, + .act_hid = BNXT_ULP_ACT_HID_0000, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 + .act_tid = 2 }, [18] = { - .act_hid = BNXT_ULP_ACT_HID_0047, + .act_hid = BNXT_ULP_ACT_HID_0002, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_ACTION_BIT_DROP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 + .act_tid = 2 }, [19] = { - .act_hid = BNXT_ULP_ACT_HID_0046, + .act_hid = BNXT_ULP_ACT_HID_0800, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 + .act_tid = 2 }, [20] = { - .act_hid = BNXT_ULP_ACT_HID_0064, + .act_hid = BNXT_ULP_ACT_HID_0101, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_ACTION_BIT_DEC_TTL | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 + .act_tid = 2 }, [21] = { - .act_hid = BNXT_ULP_ACT_HID_0068, + .act_hid = BNXT_ULP_ACT_HID_0020, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | - BNXT_ULP_ACTION_BIT_COUNT | - BNXT_ULP_ACTION_BIT_POP_VLAN | - BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, - .act_tid = 1 + .act_tid = 2 }, [22] = { - .act_hid = BNXT_ULP_ACT_HID_00a1, + .act_hid = BNXT_ULP_ACT_HID_0901, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_DECAP | - BNXT_ULP_ACTION_BIT_MARK | - BNXT_ULP_ACTION_BIT_VNIC | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_POP_VLAN | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .act_tid = 2 }, [23] = { - .act_hid = BNXT_ULP_ACT_HID_00df, + .act_hid = BNXT_ULP_ACT_HID_0121, .act_sig = { .bits = - BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | - BNXT_ULP_ACTION_BIT_VPORT | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, - .act_tid = 3 - } -}; - -struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = { - [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 2, - .start_tbl_idx = 0, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 1, - .start_tbl_idx = 2, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + [24] = { + .act_hid = BNXT_ULP_ACT_HID_0004, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - [((3 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 3, - .start_tbl_idx = 3, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR - } -}; - -struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = { - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_STATS_64, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, - .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, - .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, - .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 0, - .result_bit_size = 64, - .result_num_fields = 1, - .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + [25] = { + .act_hid = BNXT_ULP_ACT_HID_0804, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 1, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + [26] = { + .act_hid = BNXT_ULP_ACT_HID_0105, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 27, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + [27] = { + .act_hid = BNXT_ULP_ACT_HID_0024, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, - .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 53, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 3, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + [28] = { + .act_hid = BNXT_ULP_ACT_HID_0905, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, - .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, - .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 56, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 3, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + [29] = { + .act_hid = BNXT_ULP_ACT_HID_0125, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 2 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_EXT, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_TX, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .result_start_idx = 59, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 12, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP - } -}; - -struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { - { - .field_bit_size = 64, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + [30] = { + .act_hid = BNXT_ULP_ACT_HID_0001, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 }, - { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + [31] = { + .act_hid = BNXT_ULP_ACT_HID_0005, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 }, - { + [32] = { + .act_hid = BNXT_ULP_ACT_HID_0009, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [33] = { + .act_hid = BNXT_ULP_ACT_HID_000d, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [34] = { + .act_hid = BNXT_ULP_ACT_HID_0021, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [35] = { + .act_hid = BNXT_ULP_ACT_HID_0029, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [36] = { + .act_hid = BNXT_ULP_ACT_HID_0025, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [37] = { + .act_hid = BNXT_ULP_ACT_HID_002d, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_VXLAN_DECAP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [38] = { + .act_hid = BNXT_ULP_ACT_HID_0801, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [39] = { + .act_hid = BNXT_ULP_ACT_HID_0809, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [40] = { + .act_hid = BNXT_ULP_ACT_HID_0805, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [41] = { + .act_hid = BNXT_ULP_ACT_HID_080d, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_MARK | + BNXT_ULP_ACTION_BIT_RSS | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .act_tid = 3 + }, + [42] = { + .act_hid = BNXT_ULP_ACT_HID_0c15, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [43] = { + .act_hid = BNXT_ULP_ACT_HID_0c19, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_VXLAN_ENCAP | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 4 + }, + [44] = { + .act_hid = BNXT_ULP_ACT_HID_02f6, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [45] = { + .act_hid = BNXT_ULP_ACT_HID_04f8, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [46] = { + .act_hid = BNXT_ULP_ACT_HID_01df, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [47] = { + .act_hid = BNXT_ULP_ACT_HID_05e3, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [48] = { + .act_hid = BNXT_ULP_ACT_HID_02fa, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [49] = { + .act_hid = BNXT_ULP_ACT_HID_04fc, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [50] = { + .act_hid = BNXT_ULP_ACT_HID_01e3, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [51] = { + .act_hid = BNXT_ULP_ACT_HID_05e7, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [52] = { + .act_hid = BNXT_ULP_ACT_HID_03f7, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [53] = { + .act_hid = BNXT_ULP_ACT_HID_05f9, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [54] = { + .act_hid = BNXT_ULP_ACT_HID_02e0, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [55] = { + .act_hid = BNXT_ULP_ACT_HID_06e4, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [56] = { + .act_hid = BNXT_ULP_ACT_HID_03fb, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [57] = { + .act_hid = BNXT_ULP_ACT_HID_05fd, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC | + BNXT_ULP_ACTION_BIT_SET_TP_SRC | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [58] = { + .act_hid = BNXT_ULP_ACT_HID_02e4, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [59] = { + .act_hid = BNXT_ULP_ACT_HID_06e8, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_IPV4_DST | + BNXT_ULP_ACTION_BIT_SET_TP_DST | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 5 + }, + [60] = { + .act_hid = BNXT_ULP_ACT_HID_040d, + .act_sig = { .bits = + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [61] = { + .act_hid = BNXT_ULP_ACT_HID_040f, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DROP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [62] = { + .act_hid = BNXT_ULP_ACT_HID_0413, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DROP | + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [63] = { + .act_hid = BNXT_ULP_ACT_HID_0c0d, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [64] = { + .act_hid = BNXT_ULP_ACT_HID_0567, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [65] = { + .act_hid = BNXT_ULP_ACT_HID_0a49, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [66] = { + .act_hid = BNXT_ULP_ACT_HID_050e, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [67] = { + .act_hid = BNXT_ULP_ACT_HID_0d0e, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [68] = { + .act_hid = BNXT_ULP_ACT_HID_0668, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [69] = { + .act_hid = BNXT_ULP_ACT_HID_0b4a, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [70] = { + .act_hid = BNXT_ULP_ACT_HID_0411, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [71] = { + .act_hid = BNXT_ULP_ACT_HID_056b, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [72] = { + .act_hid = BNXT_ULP_ACT_HID_0a4d, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [73] = { + .act_hid = BNXT_ULP_ACT_HID_0c11, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [74] = { + .act_hid = BNXT_ULP_ACT_HID_0512, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [75] = { + .act_hid = BNXT_ULP_ACT_HID_0d12, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_POP_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [76] = { + .act_hid = BNXT_ULP_ACT_HID_066c, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_VLAN_PCP | + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + }, + [77] = { + .act_hid = BNXT_ULP_ACT_HID_0b4e, + .act_sig = { .bits = + BNXT_ULP_ACTION_BIT_COUNT | + BNXT_ULP_ACTION_BIT_DEC_TTL | + BNXT_ULP_ACTION_BIT_SET_VLAN_VID | + BNXT_ULP_ACTION_BIT_PUSH_VLAN | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .act_tid = 6 + } +}; + +struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = { + [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 0, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 2, + .start_tbl_idx = 5, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((3 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 2, + .start_tbl_idx = 7, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((4 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 9, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((5 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 14, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((6 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 3, + .start_tbl_idx = 19, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + } +}; + +struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = { + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 0, + .result_bit_size = 64, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 1, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 2, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 3, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12, + .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, + .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 15, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 41, + .result_bit_size = 64, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 42, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 68, + .result_bit_size = 64, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_RX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 69, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 95, + .result_bit_size = 64, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 96, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 3, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 99, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 3, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_64B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 102, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 114, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 140, + .result_bit_size = 64, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_SRC, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 141, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_MODIFY_IPV4, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_SET_IPV4_DST, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 142, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 143, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12, + .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, + .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 155, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_STATS_64, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_COUNT, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 181, + .result_bit_size = 64, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET, + .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 182, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_TX, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .result_start_idx = 194, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP + } +}; + +struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { + { + .field_bit_size = 64, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_ECV_L2_EN_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 80, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, +.result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .result_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, +.result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .result_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_DECAP_FUNC_THRU_L2, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 64, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, +.result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .result_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, +.result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .result_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .result_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 64, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 64, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 128, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 0, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 0, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 0, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, + (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, @@ -418,10 +1938,6 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, @@ -435,11 +1951,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 10, @@ -471,17 +1988,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, - .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, @@ -495,53 +2002,225 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 64, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_ECV_L2_EN_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 80, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, - ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, - (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, +.result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .result_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, +.result_opcode = BNXT_ULP_MAPPER_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .result_operand_true = { + (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -554,62 +2233,77 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_DECAP_FUNC_THRU_L2, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, + .result_operand = { + (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, + .field_bit_size = 64, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -620,86 +2314,63 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN, + BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, + .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, + (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 32, + .field_bit_size = 12, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 128, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff, + (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff, + BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, + .field_bit_size = 80, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -715,7 +2386,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -731,11 +2412,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 10, @@ -767,11 +2449,21 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff, + BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 4, @@ -788,7 +2480,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, + .result_operand = { + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -800,107 +2502,24 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT, .result_operand = { - BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff, + ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff, + (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 48, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 0, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ, - .result_operand = { - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff, - (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff, - BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c index 1fd5ab4..200a5a6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c @@ -9,846 +9,12843 @@ #include "ulp_rte_parser.h" uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = { - [BNXT_ULP_CLASS_HID_0080] = 1, - [BNXT_ULP_CLASS_HID_0087] = 2, - [BNXT_ULP_CLASS_HID_0000] = 3 + [BNXT_ULP_CLASS_HID_0138] = 1, + [BNXT_ULP_CLASS_HID_03f0] = 2, + [BNXT_ULP_CLASS_HID_0134] = 3, + [BNXT_ULP_CLASS_HID_03fc] = 4, + [BNXT_ULP_CLASS_HID_0139] = 5, + [BNXT_ULP_CLASS_HID_03f1] = 6, + [BNXT_ULP_CLASS_HID_068b] = 7, + [BNXT_ULP_CLASS_HID_0143] = 8, + [BNXT_ULP_CLASS_HID_0135] = 9, + [BNXT_ULP_CLASS_HID_03fd] = 10, + [BNXT_ULP_CLASS_HID_0687] = 11, + [BNXT_ULP_CLASS_HID_014f] = 12, + [BNXT_ULP_CLASS_HID_0118] = 13, + [BNXT_ULP_CLASS_HID_03d0] = 14, + [BNXT_ULP_CLASS_HID_0114] = 15, + [BNXT_ULP_CLASS_HID_03dc] = 16, + [BNXT_ULP_CLASS_HID_0119] = 17, + [BNXT_ULP_CLASS_HID_03d1] = 18, + [BNXT_ULP_CLASS_HID_06ab] = 19, + [BNXT_ULP_CLASS_HID_0163] = 20, + [BNXT_ULP_CLASS_HID_0115] = 21, + [BNXT_ULP_CLASS_HID_03dd] = 22, + [BNXT_ULP_CLASS_HID_06a7] = 23, + [BNXT_ULP_CLASS_HID_016f] = 24, + [BNXT_ULP_CLASS_HID_0128] = 25, + [BNXT_ULP_CLASS_HID_03e0] = 26, + [BNXT_ULP_CLASS_HID_0124] = 27, + [BNXT_ULP_CLASS_HID_03ec] = 28, + [BNXT_ULP_CLASS_HID_0129] = 29, + [BNXT_ULP_CLASS_HID_03e1] = 30, + [BNXT_ULP_CLASS_HID_069b] = 31, + [BNXT_ULP_CLASS_HID_0153] = 32, + [BNXT_ULP_CLASS_HID_0125] = 33, + [BNXT_ULP_CLASS_HID_03ed] = 34, + [BNXT_ULP_CLASS_HID_0697] = 35, + [BNXT_ULP_CLASS_HID_015f] = 36, + [BNXT_ULP_CLASS_HID_0452] = 37, + [BNXT_ULP_CLASS_HID_0528] = 38, + [BNXT_ULP_CLASS_HID_0790] = 39, + [BNXT_ULP_CLASS_HID_046e] = 40, + [BNXT_ULP_CLASS_HID_0462] = 41, + [BNXT_ULP_CLASS_HID_0518] = 42, + [BNXT_ULP_CLASS_HID_07a0] = 43, + [BNXT_ULP_CLASS_HID_045e] = 44, + [BNXT_ULP_CLASS_HID_0228] = 45, + [BNXT_ULP_CLASS_HID_06d0] = 46, + [BNXT_ULP_CLASS_HID_02be] = 47, + [BNXT_ULP_CLASS_HID_07a6] = 48, + [BNXT_ULP_CLASS_HID_0218] = 49, + [BNXT_ULP_CLASS_HID_06e0] = 50, + [BNXT_ULP_CLASS_HID_028e] = 51, + [BNXT_ULP_CLASS_HID_0796] = 52, + [BNXT_ULP_CLASS_HID_079c] = 53, + [BNXT_ULP_CLASS_HID_0654] = 54, + [BNXT_ULP_CLASS_HID_06d2] = 55, + [BNXT_ULP_CLASS_HID_058a] = 56, + [BNXT_ULP_CLASS_HID_052f] = 57, + [BNXT_ULP_CLASS_HID_07e7] = 58, + [BNXT_ULP_CLASS_HID_079d] = 59, + [BNXT_ULP_CLASS_HID_0655] = 60, + [BNXT_ULP_CLASS_HID_046d] = 61, + [BNXT_ULP_CLASS_HID_0725] = 62, + [BNXT_ULP_CLASS_HID_06d3] = 63, + [BNXT_ULP_CLASS_HID_058b] = 64, + [BNXT_ULP_CLASS_HID_07ac] = 65, + [BNXT_ULP_CLASS_HID_0664] = 66, + [BNXT_ULP_CLASS_HID_06e2] = 67, + [BNXT_ULP_CLASS_HID_05ba] = 68, + [BNXT_ULP_CLASS_HID_051f] = 69, + [BNXT_ULP_CLASS_HID_07d7] = 70, + [BNXT_ULP_CLASS_HID_07ad] = 71, + [BNXT_ULP_CLASS_HID_0665] = 72, + [BNXT_ULP_CLASS_HID_045d] = 73, + [BNXT_ULP_CLASS_HID_0715] = 74, + [BNXT_ULP_CLASS_HID_06e3] = 75, + [BNXT_ULP_CLASS_HID_05bb] = 76, + [BNXT_ULP_CLASS_HID_016a] = 77, + [BNXT_ULP_CLASS_HID_03d2] = 78, + [BNXT_ULP_CLASS_HID_0612] = 79, + [BNXT_ULP_CLASS_HID_00da] = 80, + [BNXT_ULP_CLASS_HID_06bd] = 81, + [BNXT_ULP_CLASS_HID_0165] = 82, + [BNXT_ULP_CLASS_HID_016b] = 83, + [BNXT_ULP_CLASS_HID_03d3] = 84, + [BNXT_ULP_CLASS_HID_03a5] = 85, + [BNXT_ULP_CLASS_HID_066d] = 86, + [BNXT_ULP_CLASS_HID_0613] = 87, + [BNXT_ULP_CLASS_HID_00db] = 88, + [BNXT_ULP_CLASS_HID_015a] = 89, + [BNXT_ULP_CLASS_HID_03e2] = 90, + [BNXT_ULP_CLASS_HID_0622] = 91, + [BNXT_ULP_CLASS_HID_00ea] = 92, + [BNXT_ULP_CLASS_HID_068d] = 93, + [BNXT_ULP_CLASS_HID_0155] = 94, + [BNXT_ULP_CLASS_HID_015b] = 95, + [BNXT_ULP_CLASS_HID_03e3] = 96, + [BNXT_ULP_CLASS_HID_0395] = 97, + [BNXT_ULP_CLASS_HID_065d] = 98, + [BNXT_ULP_CLASS_HID_0623] = 99, + [BNXT_ULP_CLASS_HID_00eb] = 100, + [BNXT_ULP_CLASS_HID_0768] = 101, + [BNXT_ULP_CLASS_HID_073c] = 102, + [BNXT_ULP_CLASS_HID_04bc] = 103, + [BNXT_ULP_CLASS_HID_0442] = 104, + [BNXT_ULP_CLASS_HID_050a] = 105, + [BNXT_ULP_CLASS_HID_06ba] = 106, + [BNXT_ULP_CLASS_HID_0472] = 107, + [BNXT_ULP_CLASS_HID_0700] = 108, + [BNXT_ULP_CLASS_HID_04c8] = 109, + [BNXT_ULP_CLASS_HID_0678] = 110, + [BNXT_ULP_CLASS_HID_064f] = 111, + [BNXT_ULP_CLASS_HID_051d] = 112, + [BNXT_ULP_CLASS_HID_06a5] = 113, + [BNXT_ULP_CLASS_HID_0455] = 114, + [BNXT_ULP_CLASS_HID_04bd] = 115, + [BNXT_ULP_CLASS_HID_0443] = 116, + [BNXT_ULP_CLASS_HID_050b] = 117, + [BNXT_ULP_CLASS_HID_06bb] = 118, + [BNXT_ULP_CLASS_HID_050d] = 119, + [BNXT_ULP_CLASS_HID_04d3] = 120, + [BNXT_ULP_CLASS_HID_059b] = 121, + [BNXT_ULP_CLASS_HID_070b] = 122, + [BNXT_ULP_CLASS_HID_0473] = 123, + [BNXT_ULP_CLASS_HID_0701] = 124, + [BNXT_ULP_CLASS_HID_04c9] = 125, + [BNXT_ULP_CLASS_HID_0679] = 126, + [BNXT_ULP_CLASS_HID_048b] = 127, + [BNXT_ULP_CLASS_HID_0749] = 128, + [BNXT_ULP_CLASS_HID_05f1] = 129, + [BNXT_ULP_CLASS_HID_04b7] = 130, + [BNXT_ULP_CLASS_HID_049b] = 131, + [BNXT_ULP_CLASS_HID_0759] = 132, + [BNXT_ULP_CLASS_HID_05e1] = 133, + [BNXT_ULP_CLASS_HID_04a7] = 134, + [BNXT_ULP_CLASS_HID_0301] = 135, + [BNXT_ULP_CLASS_HID_07f9] = 136, + [BNXT_ULP_CLASS_HID_0397] = 137, + [BNXT_ULP_CLASS_HID_068f] = 138, + [BNXT_ULP_CLASS_HID_02f1] = 139, + [BNXT_ULP_CLASS_HID_0609] = 140, + [BNXT_ULP_CLASS_HID_0267] = 141, + [BNXT_ULP_CLASS_HID_077f] = 142, + [BNXT_ULP_CLASS_HID_01e1] = 143, + [BNXT_ULP_CLASS_HID_0329] = 144, + [BNXT_ULP_CLASS_HID_01dd] = 145, + [BNXT_ULP_CLASS_HID_0315] = 146, + [BNXT_ULP_CLASS_HID_01c1] = 147, + [BNXT_ULP_CLASS_HID_0309] = 148, + [BNXT_ULP_CLASS_HID_003d] = 149, + [BNXT_ULP_CLASS_HID_02f5] = 150, + [BNXT_ULP_CLASS_HID_01d1] = 151, + [BNXT_ULP_CLASS_HID_0319] = 152, + [BNXT_ULP_CLASS_HID_01cd] = 153, + [BNXT_ULP_CLASS_HID_0305] = 154 }; struct bnxt_ulp_class_match_info ulp_class_match_list[] = { [1] = { - .class_hid = BNXT_ULP_CLASS_HID_0080, + .class_hid = BNXT_ULP_CLASS_HID_0138, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 8, - .act_vnic = 0, + .class_tid = 6, .wc_pri = 0 }, [2] = { - .class_hid = BNXT_ULP_CLASS_HID_0087, + .class_hid = BNXT_ULP_CLASS_HID_03f0, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_HDR_BIT_T_VXLAN | - BNXT_ULP_HDR_BIT_I_ETH | - BNXT_ULP_HDR_BIT_I_IPV4 | - BNXT_ULP_HDR_BIT_I_UDP | BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF9_BITMASK_I_IPV4_SRC_ADDR | - BNXT_ULP_HF9_BITMASK_I_IPV4_DST_ADDR | - BNXT_ULP_HF9_BITMASK_I_UDP_SRC_PORT | - BNXT_ULP_HF9_BITMASK_I_UDP_DST_PORT | + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 9, - .act_vnic = 0, - .wc_pri = 0 + .class_tid = 6, + .wc_pri = 1 }, [3] = { - .class_hid = BNXT_ULP_CLASS_HID_0000, + .class_hid = BNXT_ULP_CLASS_HID_0134, .hdr_sig = { .bits = BNXT_ULP_HDR_BIT_O_ETH | - BNXT_ULP_HDR_BIT_O_IPV4 | - BNXT_ULP_HDR_BIT_O_UDP | - BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, .field_sig = { .bits = - BNXT_ULP_HF10_BITMASK_O_IPV4_SRC_ADDR | - BNXT_ULP_HF10_BITMASK_O_IPV4_DST_ADDR | - BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT | - BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | BNXT_ULP_MATCH_TYPE_BITMASK_EM }, - .class_tid = 10, - .act_vnic = 0, - .wc_pri = 0 - } -}; - -struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = { - [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 4, - .start_tbl_idx = 0, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + .class_tid = 6, + .wc_pri = 2 }, - [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 2, - .start_tbl_idx = 4, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + [4] = { + .class_hid = BNXT_ULP_CLASS_HID_03fc, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 3 }, - [((3 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 6, - .start_tbl_idx = 6, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + [5] = { + .class_hid = BNXT_ULP_CLASS_HID_0139, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 4 }, - [((4 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 12, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + [6] = { + .class_hid = BNXT_ULP_CLASS_HID_03f1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 5 }, - [((5 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 3, - .start_tbl_idx = 17, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + [7] = { + .class_hid = BNXT_ULP_CLASS_HID_068b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 6 }, - [((6 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 3, - .start_tbl_idx = 20, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + [8] = { + .class_hid = BNXT_ULP_CLASS_HID_0143, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 7 }, - [((7 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 1, - .start_tbl_idx = 23, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + [9] = { + .class_hid = BNXT_ULP_CLASS_HID_0135, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 8 }, - [((8 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 24, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + [10] = { + .class_hid = BNXT_ULP_CLASS_HID_03fd, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 9 }, - [((9 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 29, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + [11] = { + .class_hid = BNXT_ULP_CLASS_HID_0687, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 10 }, - [((10 << BNXT_ULP_LOG2_MAX_NUM_DEV) | - BNXT_ULP_DEVICE_ID_WH_PLUS)] = { - .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, - .num_tbls = 5, - .start_tbl_idx = 34, - .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR - } -}; - -struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .result_start_idx = 0, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + [12] = { + .class_hid = BNXT_ULP_CLASS_HID_014f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 11 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 0, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 26, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + [13] = { + .class_hid = BNXT_ULP_CLASS_HID_0118, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 12 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_RX, - .result_start_idx = 39, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + [14] = { + .class_hid = BNXT_ULP_CLASS_HID_03d0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 13 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_RX, - .result_start_idx = 40, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + [15] = { + .class_hid = BNXT_ULP_CLASS_HID_0114, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 14 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .result_start_idx = 41, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + [16] = { + .class_hid = BNXT_ULP_CLASS_HID_03dc, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 15 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 13, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 67, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + [17] = { + .class_hid = BNXT_ULP_CLASS_HID_0119, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 16 }, - { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_TX, - .result_start_idx = 80, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + [18] = { + .class_hid = BNXT_ULP_CLASS_HID_03d1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 17 + }, + [19] = { + .class_hid = BNXT_ULP_CLASS_HID_06ab, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 18 + }, + [20] = { + .class_hid = BNXT_ULP_CLASS_HID_0163, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 19 + }, + [21] = { + .class_hid = BNXT_ULP_CLASS_HID_0115, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 20 + }, + [22] = { + .class_hid = BNXT_ULP_CLASS_HID_03dd, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 21 + }, + [23] = { + .class_hid = BNXT_ULP_CLASS_HID_06a7, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 22 + }, + [24] = { + .class_hid = BNXT_ULP_CLASS_HID_016f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 23 + }, + [25] = { + .class_hid = BNXT_ULP_CLASS_HID_0128, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 24 + }, + [26] = { + .class_hid = BNXT_ULP_CLASS_HID_03e0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 25 + }, + [27] = { + .class_hid = BNXT_ULP_CLASS_HID_0124, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 26 + }, + [28] = { + .class_hid = BNXT_ULP_CLASS_HID_03ec, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 27 + }, + [29] = { + .class_hid = BNXT_ULP_CLASS_HID_0129, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 28 + }, + [30] = { + .class_hid = BNXT_ULP_CLASS_HID_03e1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 29 + }, + [31] = { + .class_hid = BNXT_ULP_CLASS_HID_069b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 30 + }, + [32] = { + .class_hid = BNXT_ULP_CLASS_HID_0153, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 31 + }, + [33] = { + .class_hid = BNXT_ULP_CLASS_HID_0125, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 32 + }, + [34] = { + .class_hid = BNXT_ULP_CLASS_HID_03ed, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 33 + }, + [35] = { + .class_hid = BNXT_ULP_CLASS_HID_0697, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 34 + }, + [36] = { + .class_hid = BNXT_ULP_CLASS_HID_015f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 6, + .wc_pri = 35 + }, + [37] = { + .class_hid = BNXT_ULP_CLASS_HID_0452, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 7, + .wc_pri = 0 + }, + [38] = { + .class_hid = BNXT_ULP_CLASS_HID_0528, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 7, + .wc_pri = 1 + }, + [39] = { + .class_hid = BNXT_ULP_CLASS_HID_0790, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF7_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 7, + .wc_pri = 2 + }, + [40] = { + .class_hid = BNXT_ULP_CLASS_HID_046e, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 7, + .wc_pri = 3 + }, + [41] = { + .class_hid = BNXT_ULP_CLASS_HID_0462, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 8, + .wc_pri = 0 + }, + [42] = { + .class_hid = BNXT_ULP_CLASS_HID_0518, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 8, + .wc_pri = 1 + }, + [43] = { + .class_hid = BNXT_ULP_CLASS_HID_07a0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF8_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 8, + .wc_pri = 2 + }, + [44] = { + .class_hid = BNXT_ULP_CLASS_HID_045e, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 8, + .wc_pri = 3 + }, + [45] = { + .class_hid = BNXT_ULP_CLASS_HID_0228, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 9, + .wc_pri = 0 + }, + [46] = { + .class_hid = BNXT_ULP_CLASS_HID_06d0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF9_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 9, + .wc_pri = 1 + }, + [47] = { + .class_hid = BNXT_ULP_CLASS_HID_02be, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 9, + .wc_pri = 2 + }, + [48] = { + .class_hid = BNXT_ULP_CLASS_HID_07a6, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 9, + .wc_pri = 3 + }, + [49] = { + .class_hid = BNXT_ULP_CLASS_HID_0218, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 10, + .wc_pri = 0 + }, + [50] = { + .class_hid = BNXT_ULP_CLASS_HID_06e0, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF10_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 10, + .wc_pri = 1 + }, + [51] = { + .class_hid = BNXT_ULP_CLASS_HID_028e, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 10, + .wc_pri = 2 + }, + [52] = { + .class_hid = BNXT_ULP_CLASS_HID_0796, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 10, + .wc_pri = 3 + }, + [53] = { + .class_hid = BNXT_ULP_CLASS_HID_079c, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 0 + }, + [54] = { + .class_hid = BNXT_ULP_CLASS_HID_0654, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 1 + }, + [55] = { + .class_hid = BNXT_ULP_CLASS_HID_06d2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 2 + }, + [56] = { + .class_hid = BNXT_ULP_CLASS_HID_058a, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 3 + }, + [57] = { + .class_hid = BNXT_ULP_CLASS_HID_052f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 4 + }, + [58] = { + .class_hid = BNXT_ULP_CLASS_HID_07e7, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 5 + }, + [59] = { + .class_hid = BNXT_ULP_CLASS_HID_079d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 6 + }, + [60] = { + .class_hid = BNXT_ULP_CLASS_HID_0655, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 7 + }, + [61] = { + .class_hid = BNXT_ULP_CLASS_HID_046d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 8 + }, + [62] = { + .class_hid = BNXT_ULP_CLASS_HID_0725, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 9 + }, + [63] = { + .class_hid = BNXT_ULP_CLASS_HID_06d3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 10 + }, + [64] = { + .class_hid = BNXT_ULP_CLASS_HID_058b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 11, + .wc_pri = 11 + }, + [65] = { + .class_hid = BNXT_ULP_CLASS_HID_07ac, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 0 + }, + [66] = { + .class_hid = BNXT_ULP_CLASS_HID_0664, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 1 + }, + [67] = { + .class_hid = BNXT_ULP_CLASS_HID_06e2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 2 + }, + [68] = { + .class_hid = BNXT_ULP_CLASS_HID_05ba, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 3 + }, + [69] = { + .class_hid = BNXT_ULP_CLASS_HID_051f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 4 + }, + [70] = { + .class_hid = BNXT_ULP_CLASS_HID_07d7, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 5 + }, + [71] = { + .class_hid = BNXT_ULP_CLASS_HID_07ad, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 6 + }, + [72] = { + .class_hid = BNXT_ULP_CLASS_HID_0665, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 7 + }, + [73] = { + .class_hid = BNXT_ULP_CLASS_HID_045d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 8 + }, + [74] = { + .class_hid = BNXT_ULP_CLASS_HID_0715, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 9 + }, + [75] = { + .class_hid = BNXT_ULP_CLASS_HID_06e3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 10 + }, + [76] = { + .class_hid = BNXT_ULP_CLASS_HID_05bb, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 12, + .wc_pri = 11 + }, + [77] = { + .class_hid = BNXT_ULP_CLASS_HID_016a, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 0 + }, + [78] = { + .class_hid = BNXT_ULP_CLASS_HID_03d2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 1 + }, + [79] = { + .class_hid = BNXT_ULP_CLASS_HID_0612, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 2 + }, + [80] = { + .class_hid = BNXT_ULP_CLASS_HID_00da, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 3 + }, + [81] = { + .class_hid = BNXT_ULP_CLASS_HID_06bd, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 4 + }, + [82] = { + .class_hid = BNXT_ULP_CLASS_HID_0165, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 5 + }, + [83] = { + .class_hid = BNXT_ULP_CLASS_HID_016b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 6 + }, + [84] = { + .class_hid = BNXT_ULP_CLASS_HID_03d3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 7 + }, + [85] = { + .class_hid = BNXT_ULP_CLASS_HID_03a5, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 8 + }, + [86] = { + .class_hid = BNXT_ULP_CLASS_HID_066d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 9 + }, + [87] = { + .class_hid = BNXT_ULP_CLASS_HID_0613, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 10 + }, + [88] = { + .class_hid = BNXT_ULP_CLASS_HID_00db, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 13, + .wc_pri = 11 + }, + [89] = { + .class_hid = BNXT_ULP_CLASS_HID_015a, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 0 + }, + [90] = { + .class_hid = BNXT_ULP_CLASS_HID_03e2, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 1 + }, + [91] = { + .class_hid = BNXT_ULP_CLASS_HID_0622, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 2 + }, + [92] = { + .class_hid = BNXT_ULP_CLASS_HID_00ea, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 3 + }, + [93] = { + .class_hid = BNXT_ULP_CLASS_HID_068d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 4 + }, + [94] = { + .class_hid = BNXT_ULP_CLASS_HID_0155, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 5 + }, + [95] = { + .class_hid = BNXT_ULP_CLASS_HID_015b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 6 + }, + [96] = { + .class_hid = BNXT_ULP_CLASS_HID_03e3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 7 + }, + [97] = { + .class_hid = BNXT_ULP_CLASS_HID_0395, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 8 + }, + [98] = { + .class_hid = BNXT_ULP_CLASS_HID_065d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 9 + }, + [99] = { + .class_hid = BNXT_ULP_CLASS_HID_0623, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 10 + }, + [100] = { + .class_hid = BNXT_ULP_CLASS_HID_00eb, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 14, + .wc_pri = 11 + }, + [101] = { + .class_hid = BNXT_ULP_CLASS_HID_0768, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF15_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF15_BITMASK_I_ETH_TYPE | + BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID | + BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 15, + .wc_pri = 0 + }, + [102] = { + .class_hid = BNXT_ULP_CLASS_HID_073c, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_HDR_BIT_I_ETH | + BNXT_ULP_HDR_BIT_I_IPV4 | + BNXT_ULP_HDR_BIT_I_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF15_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI | + BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR | + BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR | + BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID | + BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT | + BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 15, + .wc_pri = 1 + }, + [103] = { + .class_hid = BNXT_ULP_CLASS_HID_04bc, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 0 + }, + [104] = { + .class_hid = BNXT_ULP_CLASS_HID_0442, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 1 + }, + [105] = { + .class_hid = BNXT_ULP_CLASS_HID_050a, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 2 + }, + [106] = { + .class_hid = BNXT_ULP_CLASS_HID_06ba, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 3 + }, + [107] = { + .class_hid = BNXT_ULP_CLASS_HID_0472, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 4 + }, + [108] = { + .class_hid = BNXT_ULP_CLASS_HID_0700, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 5 + }, + [109] = { + .class_hid = BNXT_ULP_CLASS_HID_04c8, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 6 + }, + [110] = { + .class_hid = BNXT_ULP_CLASS_HID_0678, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 7 + }, + [111] = { + .class_hid = BNXT_ULP_CLASS_HID_064f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 8 + }, + [112] = { + .class_hid = BNXT_ULP_CLASS_HID_051d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 9 + }, + [113] = { + .class_hid = BNXT_ULP_CLASS_HID_06a5, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 10 + }, + [114] = { + .class_hid = BNXT_ULP_CLASS_HID_0455, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 11 + }, + [115] = { + .class_hid = BNXT_ULP_CLASS_HID_04bd, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 12 + }, + [116] = { + .class_hid = BNXT_ULP_CLASS_HID_0443, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 13 + }, + [117] = { + .class_hid = BNXT_ULP_CLASS_HID_050b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 14 + }, + [118] = { + .class_hid = BNXT_ULP_CLASS_HID_06bb, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 15 + }, + [119] = { + .class_hid = BNXT_ULP_CLASS_HID_050d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 16 + }, + [120] = { + .class_hid = BNXT_ULP_CLASS_HID_04d3, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 17 + }, + [121] = { + .class_hid = BNXT_ULP_CLASS_HID_059b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 18 + }, + [122] = { + .class_hid = BNXT_ULP_CLASS_HID_070b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 19 + }, + [123] = { + .class_hid = BNXT_ULP_CLASS_HID_0473, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 20 + }, + [124] = { + .class_hid = BNXT_ULP_CLASS_HID_0701, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 21 + }, + [125] = { + .class_hid = BNXT_ULP_CLASS_HID_04c9, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 22 + }, + [126] = { + .class_hid = BNXT_ULP_CLASS_HID_0679, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_OO_VLAN | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_HDR_BIT_T_VXLAN | + BNXT_ULP_FLOW_DIR_BITMASK_ING }, + .field_sig = { .bits = + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 16, + .wc_pri = 23 + }, + [127] = { + .class_hid = BNXT_ULP_CLASS_HID_048b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 17, + .wc_pri = 0 + }, + [128] = { + .class_hid = BNXT_ULP_CLASS_HID_0749, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF17_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 17, + .wc_pri = 1 + }, + [129] = { + .class_hid = BNXT_ULP_CLASS_HID_05f1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 17, + .wc_pri = 2 + }, + [130] = { + .class_hid = BNXT_ULP_CLASS_HID_04b7, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 17, + .wc_pri = 3 + }, + [131] = { + .class_hid = BNXT_ULP_CLASS_HID_049b, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF18_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 18, + .wc_pri = 0 + }, + [132] = { + .class_hid = BNXT_ULP_CLASS_HID_0759, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF18_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 18, + .wc_pri = 1 + }, + [133] = { + .class_hid = BNXT_ULP_CLASS_HID_05e1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID | + BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 18, + .wc_pri = 2 + }, + [134] = { + .class_hid = BNXT_ULP_CLASS_HID_04a7, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR | + BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR | + BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 18, + .wc_pri = 3 + }, + [135] = { + .class_hid = BNXT_ULP_CLASS_HID_0301, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF19_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 19, + .wc_pri = 0 + }, + [136] = { + .class_hid = BNXT_ULP_CLASS_HID_07f9, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF19_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 19, + .wc_pri = 1 + }, + [137] = { + .class_hid = BNXT_ULP_CLASS_HID_0397, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 19, + .wc_pri = 2 + }, + [138] = { + .class_hid = BNXT_ULP_CLASS_HID_068f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT | + BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 19, + .wc_pri = 3 + }, + [139] = { + .class_hid = BNXT_ULP_CLASS_HID_02f1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF20_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 20, + .wc_pri = 0 + }, + [140] = { + .class_hid = BNXT_ULP_CLASS_HID_0609, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF20_BITMASK_O_ETH_TYPE | + BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 20, + .wc_pri = 1 + }, + [141] = { + .class_hid = BNXT_ULP_CLASS_HID_0267, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID | + BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 20, + .wc_pri = 2 + }, + [142] = { + .class_hid = BNXT_ULP_CLASS_HID_077f, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR | + BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR | + BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT | + BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 20, + .wc_pri = 3 + }, + [143] = { + .class_hid = BNXT_ULP_CLASS_HID_01e1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 0 + }, + [144] = { + .class_hid = BNXT_ULP_CLASS_HID_0329, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 1 + }, + [145] = { + .class_hid = BNXT_ULP_CLASS_HID_01dd, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 2 + }, + [146] = { + .class_hid = BNXT_ULP_CLASS_HID_0315, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 3 + }, + [147] = { + .class_hid = BNXT_ULP_CLASS_HID_01c1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 4 + }, + [148] = { + .class_hid = BNXT_ULP_CLASS_HID_0309, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 5 + }, + [149] = { + .class_hid = BNXT_ULP_CLASS_HID_003d, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 6 + }, + [150] = { + .class_hid = BNXT_ULP_CLASS_HID_02f5, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_UDP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 7 + }, + [151] = { + .class_hid = BNXT_ULP_CLASS_HID_01d1, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 8 + }, + [152] = { + .class_hid = BNXT_ULP_CLASS_HID_0319, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV4 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 9 + }, + [153] = { + .class_hid = BNXT_ULP_CLASS_HID_01cd, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_TYPE | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 10 + }, + [154] = { + .class_hid = BNXT_ULP_CLASS_HID_0305, + .hdr_sig = { .bits = + BNXT_ULP_HDR_BIT_O_ETH | + BNXT_ULP_HDR_BIT_O_IPV6 | + BNXT_ULP_HDR_BIT_O_TCP | + BNXT_ULP_FLOW_DIR_BITMASK_EGR }, + .field_sig = { .bits = + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC | + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC | + BNXT_ULP_MATCH_TYPE_BITMASK_EM }, + .class_tid = 21, + .wc_pri = 11 + } +}; + +struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = { + [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 0, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + }, + [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 6, + .start_tbl_idx = 5, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + }, + [((3 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 7, + .start_tbl_idx = 11, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + }, + [((4 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 6, + .start_tbl_idx = 18, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + }, + [((5 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 1, + .start_tbl_idx = 24, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT + }, + [((6 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 25, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((7 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 29, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((8 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 34, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((9 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 39, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((10 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 44, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((11 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 49, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((12 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 53, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((13 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 57, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((14 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 61, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((15 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 65, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((16 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 69, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((17 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 73, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((18 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 78, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((19 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 83, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((20 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 5, + .start_tbl_idx = 88, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + }, + [((21 << BNXT_ULP_LOG2_MAX_NUM_DEV) | + BNXT_ULP_DEVICE_ID_WH_PLUS)] = { + .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS, + .num_tbls = 4, + .start_tbl_idx = 93, + .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR + } +}; + +struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = { + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_RX, + .result_start_idx = 0, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 0, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 26, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 0, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 1, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 27, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 1, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_RX, + .result_start_idx = 40, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, + .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_RX, + .result_start_idx = 41, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, + .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .result_start_idx = 42, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 14, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 68, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 1, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, + .direction = TF_DIR_TX, + .key_start_idx = 27, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 81, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 1, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET, + .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 28, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 82, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 2, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .result_start_idx = 95, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, + .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .result_start_idx = 96, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, + .index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_TX, + .result_start_idx = 97, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 12, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .result_start_idx = 109, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 41, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 135, + .result_bit_size = 0, + .result_num_fields = 0, + .encap_num_fields = 0, + .ident_start_idx = 2, + .ident_nums = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 42, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 135, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 2, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_RX, + .result_start_idx = 148, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 55, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 174, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 2, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 68, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 187, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 2, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 81, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 200, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 2, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 82, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 201, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 3, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, + .direction = TF_DIR_TX, + .result_start_idx = 214, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, + .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, + .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, + .direction = TF_DIR_TX, + .result_start_idx = 215, + .result_bit_size = 32, + .result_num_fields = 1, + .encap_num_fields = 0, + .index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT, + .index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, + .direction = TF_DIR_RX, + .result_start_idx = 216, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG, + .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, + .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 95, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 242, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 3, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, + .direction = TF_DIR_TX, + .result_start_idx = 255, + .result_bit_size = 128, + .result_num_fields = 26, + .encap_num_fields = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, + .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 108, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 281, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 3, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 121, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 294, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 4, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_1, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 124, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 295, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 5, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 166, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 303, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 5, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 177, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 312, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 5, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 178, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 313, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 6, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 191, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 326, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 6, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 194, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 327, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 7, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 236, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 335, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 7, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 247, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 344, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 7, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 248, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 345, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 8, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 261, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 358, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 8, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 264, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 359, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 9, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 306, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 367, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 9, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 317, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 376, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 9, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 318, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 377, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 10, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 331, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 390, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 10, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 334, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 391, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 11, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 376, + .blob_key_bit_size = 392, + .key_bit_size = 392, + .key_num_fields = 11, + .result_start_idx = 399, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 11, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 387, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 408, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 11, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 388, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 409, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 12, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 401, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 422, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 12, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 404, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 423, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 13, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 446, + .blob_key_bit_size = 392, + .key_bit_size = 392, + .key_num_fields = 11, + .result_start_idx = 431, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 13, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 457, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 440, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 13, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 470, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 453, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 14, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 473, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 454, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 15, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 515, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 462, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 15, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 526, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 471, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 15, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 539, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 484, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 16, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 542, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 485, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 17, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 584, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 493, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 17, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 595, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 502, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 17, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 608, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 515, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 18, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 611, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 516, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 19, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 653, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 524, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 19, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 664, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 533, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 19, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 677, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 546, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 20, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 680, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 547, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 21, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 722, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 555, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 21, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 733, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 564, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 21, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 746, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 577, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 22, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 749, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 578, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 23, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 791, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 586, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 23, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 802, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 595, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 23, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_RX, + .key_start_idx = 815, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 608, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 24, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_RX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 818, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 609, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 25, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_RX, + .key_start_idx = 860, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 617, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 25, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 871, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 626, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 25, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 872, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 627, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 26, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 885, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 640, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 26, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 888, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 641, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 27, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_TX, + .key_start_idx = 930, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 649, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 27, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 941, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 658, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 27, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 942, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 659, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 28, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 955, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 672, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 28, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 958, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 673, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 29, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_TX, + .key_start_idx = 1000, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 681, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 29, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 1011, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 690, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 29, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 1012, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 691, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 30, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 1025, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 704, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 30, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 1028, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 705, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 31, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_TX, + .key_start_idx = 1070, + .blob_key_bit_size = 392, + .key_bit_size = 392, + .key_num_fields = 11, + .result_start_idx = 713, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 31, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 1081, + .blob_key_bit_size = 8, + .key_bit_size = 8, + .key_num_fields = 1, + .result_start_idx = 722, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 31, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 1082, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 723, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 32, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 1095, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 736, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 32, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 1098, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 737, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 33, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_TX, + .key_start_idx = 1140, + .blob_key_bit_size = 200, + .key_bit_size = 200, + .key_num_fields = 11, + .result_start_idx = 745, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 33, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 1151, + .blob_key_bit_size = 167, + .key_bit_size = 167, + .key_num_fields = 13, + .result_start_idx = 754, + .result_bit_size = 64, + .result_num_fields = 13, + .encap_num_fields = 0, + .ident_start_idx = 33, + .ident_nums = 1, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .resource_sub_type = + BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, + .direction = TF_DIR_TX, + .key_start_idx = 1164, + .blob_key_bit_size = 16, + .key_bit_size = 16, + .key_num_fields = 3, + .result_start_idx = 767, + .result_bit_size = 10, + .result_num_fields = 1, + .encap_num_fields = 0, + .ident_start_idx = 34, + .ident_nums = 1 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, + .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, + .direction = TF_DIR_TX, + .priority = BNXT_ULP_PRIORITY_LEVEL_0, + .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, + .key_start_idx = 1167, + .blob_key_bit_size = 81, + .key_bit_size = 81, + .key_num_fields = 42, + .result_start_idx = 768, + .result_bit_size = 38, + .result_num_fields = 8, + .encap_num_fields = 0, + .ident_start_idx = 35, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE, + .resource_type = TF_MEM_INTERNAL, + .direction = TF_DIR_TX, + .key_start_idx = 1209, + .blob_key_bit_size = 104, + .key_bit_size = 104, + .key_num_fields = 7, + .result_start_idx = 776, + .result_bit_size = 64, + .result_num_fields = 9, + .encap_num_fields = 0, + .ident_start_idx = 35, + .ident_nums = 0, + .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, + .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + } +}; + +struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = { + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF6_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF6_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF6_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF6_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF6_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF6_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF6_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF6_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF6_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF6_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF6_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF6_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_ISIP_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF6_IDX_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_HF6_IDX_O_ETH_SMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF7_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF7_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF7_IDX_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF7_IDX_O_UDP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF7_IDX_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF7_IDX_O_UDP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF7_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF7_IDX_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF7_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF7_IDX_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF8_IDX_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF8_IDX_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF8_IDX_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF8_IDX_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF9_IDX_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF9_IDX_O_UDP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 128, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF9_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF9_IDX_O_IPV6_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 128, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF9_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF9_IDX_O_IPV6_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF10_IDX_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF10_IDX_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF10_IDX_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF10_IDX_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 128, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 128, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF11_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF11_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF11_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF11_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF11_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF11_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF11_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF11_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF11_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF11_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF11_IDX_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF11_IDX_O_UDP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF11_IDX_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF11_IDX_O_UDP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF11_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF11_IDX_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF11_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF11_IDX_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF12_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF12_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF12_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF12_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF12_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF12_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF12_IDX_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF12_IDX_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF12_IDX_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF12_IDX_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF13_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF13_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF13_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF13_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF13_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF13_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF13_IDX_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF13_IDX_O_UDP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF13_IDX_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF13_IDX_O_UDP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF13_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF13_IDX_O_IPV6_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF13_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF13_IDX_O_IPV6_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF14_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF14_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF14_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF14_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF14_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF14_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF14_IDX_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF14_IDX_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF14_IDX_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF14_IDX_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF15_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF15_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_I_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF15_IDX_I_UDP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_I_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF15_IDX_I_UDP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_I_IPV4_PROTO_ID >> 8) & 0xff, + BNXT_ULP_HF15_IDX_I_IPV4_PROTO_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_I_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF15_IDX_I_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF15_IDX_I_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF15_IDX_T_VXLAN_VNI >> 8) & 0xff, + BNXT_ULP_HF15_IDX_T_VXLAN_VNI & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF16_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF16_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff, + BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_operand = { + (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff, + BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TL2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF17_IDX_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF17_IDX_O_UDP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF17_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF17_IDX_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF18_IDX_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF18_IDX_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF18_IDX_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF18_IDX_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_TYPE_UDP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF19_IDX_O_UDP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF19_IDX_O_UDP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF19_IDX_O_IPV6_PROTO_ID >> 8) & 0xff, + BNXT_ULP_HF19_IDX_O_IPV6_PROTO_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 128, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF19_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF19_IDX_O_IPV6_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 128, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF19_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF19_IDX_O_IPV6_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L4_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_TYPE_IPV6, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .result_start_idx = 92, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 26, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 118, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .result_start_idx = 131, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 9, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF20_IDX_O_TCP_DST_PORT >> 8) & 0xff, + BNXT_ULP_HF20_IDX_O_TCP_DST_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 16, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF20_IDX_O_TCP_SRC_PORT >> 8) & 0xff, + BNXT_ULP_HF20_IDX_O_TCP_SRC_PORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_IP_PROTO_TCP, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR >> 8) & 0xff, + BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 32, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff, + BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 24, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF21_IDX_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_HF21_IDX_O_ETH_SMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF21_IDX_O_ETH_SMAC >> 8) & 0xff, + BNXT_ULP_HF21_IDX_O_ETH_SMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .mask_operand = { + (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff, + BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 39, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 157, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 52, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 170, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 65, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 183, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 12, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 196, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF + .field_bit_size = 48, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE, - .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR, - .direction = TF_DIR_TX, - .result_start_idx = 197, - .result_bit_size = 32, - .result_num_fields = 1, - .encap_num_fields = 0, - .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD, - .index_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .result_start_idx = 198, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 78, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 224, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_TX, - .result_start_idx = 237, - .result_bit_size = 0, - .result_num_fields = 0, - .encap_num_fields = 12, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_TX, - .result_start_idx = 249, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 91, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 275, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL, - .direction = TF_DIR_RX, - .result_start_idx = 288, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE, - .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR + .field_bit_size = 7, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .spec_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 104, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 314, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 8, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 117, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 327, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION, - .direction = TF_DIR_TX, - .result_start_idx = 340, - .result_bit_size = 128, - .result_num_fields = 26, - .encap_num_fields = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL, - .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 130, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 2, - .result_start_idx = 366, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 0, - .ident_nums = 1 + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 132, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 367, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 145, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 380, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 1, - .ident_nums = 1 + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 148, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 42, - .result_start_idx = 381, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_ISIP_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .direction = TF_DIR_RX, - .key_start_idx = 190, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 389, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 201, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 2, - .result_start_idx = 398, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 2, - .ident_nums = 1 + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 203, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 399, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L3_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_RX, - .key_start_idx = 216, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 412, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 3, - .ident_nums = 1 + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_RX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 219, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 42, - .result_start_idx = 413, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .direction = TF_DIR_RX, - .key_start_idx = 261, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 421, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 272, - .blob_key_bit_size = 12, - .key_bit_size = 12, - .key_num_fields = 2, - .result_start_idx = 430, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 4, - .ident_nums = 1 + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 274, - .blob_key_bit_size = 167, - .key_bit_size = 167, - .key_num_fields = 13, - .result_start_idx = 431, - .result_bit_size = 64, - .result_num_fields = 13, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .resource_sub_type = - BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM, - .direction = TF_DIR_TX, - .key_start_idx = 287, - .blob_key_bit_size = 16, - .key_bit_size = 16, - .key_num_fields = 3, - .result_start_idx = 444, - .result_bit_size = 10, - .result_num_fields = 1, - .encap_num_fields = 0, - .ident_start_idx = 5, - .ident_nums = 1 + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = { + BNXT_ULP_SYM_L2_HDR_VALID_YES, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE, - .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM, - .direction = TF_DIR_TX, - .priority = BNXT_ULP_PRIORITY_LEVEL_0, - .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO, - .key_start_idx = 290, - .blob_key_bit_size = 81, - .key_bit_size = 81, - .key_num_fields = 42, - .result_start_idx = 445, - .result_bit_size = 38, - .result_num_fields = 8, - .encap_num_fields = 0, - .ident_start_idx = 6, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE, - .resource_type = TF_MEM_EXTERNAL, - .direction = TF_DIR_TX, - .key_start_idx = 332, - .blob_key_bit_size = 448, - .key_bit_size = 448, - .key_num_fields = 11, - .result_start_idx = 453, - .result_bit_size = 64, - .result_num_fields = 9, - .encap_num_fields = 0, - .ident_start_idx = 6, - .ident_nums = 0, - .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION, - .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES - } -}; - -struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = { + .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, { - .field_bit_size = 12, + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, + .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, + .field_bit_size = 4, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, @@ -862,44 +12859,70 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = { .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, + .field_bit_size = 1, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, + .field_bit_size = 9, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, + .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { .field_bit_size = 4, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 7, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, + .field_bit_size = 3, + .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, @@ -911,2195 +12934,1767 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = { { .field_bit_size = 48, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, + .spec_operand = { + (BNXT_ULP_HF21_IDX_O_ETH_DMAC >> 8) & 0xff, + BNXT_ULP_HF21_IDX_O_ETH_DMAC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, + .field_bit_size = 10, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, + .field_bit_size = 8, .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .spec_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } +}; + +struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { + { + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, - { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff, + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x81, 0x00} }, { .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x02} - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, + BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 80, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x02} + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .spec_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff, + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff, + BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_VF_FUNC_PARIF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + .field_bit_size = 32, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, + BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL4_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TL2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 14, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_I_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_I_UDP_DST_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_I_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF9_IDX_I_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_I_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_I_IPV4_DST_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF9_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF9_IDX_I_IPV4_SRC_ADDR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + .field_bit_size = 12, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff, + BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .mask_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff, - BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff, + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_TUN_HDR_TYPE_NONE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff, + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_TYPE_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L4_HDR_VALID_YES, + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x0005 >> 8) & 0xff, + 0x0005 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L3_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_L2_HDR_VALID_YES, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 6, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 3, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 9, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 7, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .spec_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 251, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_DST_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_DST_PORT & 0xff, + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 11, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .spec_operand = { - BNXT_ULP_SYM_IP_PROTO_UDP, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV4_DST_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV4_DST_ADDR & 0xff, + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 32, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD, - .spec_operand = { - (BNXT_ULP_HF10_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff, - BNXT_ULP_HF10_IDX_O_IPV4_SRC_ADDR & 0xff, + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 48, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 24, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, - .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO, - .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .spec_operand = { - (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - } -}; - -struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { - { - .field_bit_size = 14, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -3107,81 +14702,121 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, + .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 11, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -3189,18 +14824,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID & 0xff, + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -3265,29 +14907,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 14, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -3295,52 +14928,82 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x0185 >> 8) & 0xff, + 0x0185 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -3348,22 +15011,34 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -3372,31 +15047,36 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -3406,34 +15086,57 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 6, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -3442,36 +15145,52 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x0185 >> 8) & 0xff, + 0x0185 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -3484,16 +15203,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x81, 0x00} + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { - (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff, - BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff, + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -3502,23 +15225,28 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 80, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 14, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -3526,90 +15254,121 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 11, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, + .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff, + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -3617,29 +15376,40 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -3659,9 +15429,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 16, @@ -3682,23 +15450,16 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -3710,79 +15471,82 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, - .result_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_operand = { + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -3790,30 +15554,40 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -3854,72 +15628,120 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + }, + { + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 6, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID & 0xff, + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -3927,8 +15749,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -3938,7 +15760,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -3979,41 +15806,16 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, - .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { - .field_bit_size = 32, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff, + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -4025,77 +15827,82 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff, + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -4103,30 +15910,40 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .result_operand = { + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -4167,15 +15984,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -4183,16 +16005,28 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI, + (0x00fb >> 8) & 0xff, + 0x00fb & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -4201,38 +16035,52 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x81, 0x00} + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x02} + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 80, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -4240,47 +16088,55 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, .result_operand = { - (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff, + (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff, + BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 16, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 10, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -4288,56 +16144,80 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 16, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff, - BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff, + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x0031 >> 8) & 0xff, + 0x0031 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -4347,82 +16227,102 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 6, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 4, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_VF_FUNC_PARIF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, + .field_bit_size = 6, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 3, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -4430,35 +16330,43 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 16, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, + .field_bit_size = 2, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, + .field_bit_size = 8, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -4466,19 +16374,26 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD, + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff, - BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff, + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -4493,23 +16408,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 16, + .field_bit_size = 33, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, @@ -4519,78 +16418,87 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 4, + .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 8, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 9, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 6, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 3, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 2, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, + .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, .result_operand = { - (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 7, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, + .result_operand = { + (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_VF_FUNC_PARIF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -4614,7 +16522,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -4631,23 +16544,16 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 14, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 10, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, + .field_bit_size = 4, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { @@ -4659,77 +16565,82 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 11, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + (0x00f9 >> 8) & 0xff, + 0x00f9 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 8, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 1, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 33, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { - .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .field_bit_size = 5, + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 12, + .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff, - BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff, + (0x00c5 >> 8) & 0xff, + 0x00c5 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, + .field_bit_size = 11, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO }, { .field_bit_size = 2, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO - }, - { - .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -4737,7 +16648,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 1, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 10, @@ -4796,7 +16709,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -4845,7 +16763,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { { .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { @@ -4896,8 +16814,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, + (0x0185 >> 8) & 0xff, + 0x0185 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -4954,7 +16872,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_VF_FUNC_PARIF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -4978,7 +16900,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 16, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, + .result_operand = { + (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff, + BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 1, @@ -5113,20 +17040,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { - .field_bit_size = 10, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE, - .result_operand = { - (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff, - BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} - }, - { .field_bit_size = 7, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE, .result_operand = { - (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff, + (BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -5136,7 +17054,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { }, { .field_bit_size = 4, - .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO + .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, + .result_operand = { + BNXT_ULP_SYM_VF_FUNC_PARIF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 8, @@ -5206,15 +17128,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .field_bit_size = 10, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - (0x00f9 >> 8) & 0xff, - 0x00f9 & 0xff, + (0x0003 >> 8) & 0xff, + 0x0003 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { .field_bit_size = 5, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, - .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00, + .result_operand = {0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, { @@ -5265,8 +17187,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = { .field_bit_size = 9, .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT, .result_operand = { - (0x00c5 >> 8) & 0xff, - 0x00c5 & 0xff, + (0x0061 >> 8) & 0xff, + 0x0061 & 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }, @@ -5302,6 +17224,195 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { }, { .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, .ident_type = TF_IDENT_TYPE_EM_PROF, .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, @@ -5334,5 +17445,19 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = { .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, .ident_bit_size = 10, .ident_bit_pos = 0 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 54 + }, + { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .ident_type = TF_IDENT_TYPE_EM_PROF, + .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0, + .ident_bit_size = 10, + .ident_bit_pos = 0 } }; diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index fbeb314..b5deaf6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -10,22 +10,22 @@ #define BNXT_ULP_MAX_NUM_DEVICES 4 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4 -#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256 -#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4 +#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048 +#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 155 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907 -#define BNXT_ULP_CLASS_HID_SHFTR 16 -#define BNXT_ULP_CLASS_HID_SHFTL 23 -#define BNXT_ULP_CLASS_HID_MASK 255 -#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256 -#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 24 +#define BNXT_ULP_CLASS_HID_SHFTR 32 +#define BNXT_ULP_CLASS_HID_SHFTL 31 +#define BNXT_ULP_CLASS_HID_MASK 2047 +#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 4096 +#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 78 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919 -#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919 +#define BNXT_ULP_ACT_HID_HIGH_PRIME 4721 #define BNXT_ULP_ACT_HID_SHFTR 23 #define BNXT_ULP_ACT_HID_SHFTL 23 -#define BNXT_ULP_ACT_HID_MASK 255 +#define BNXT_ULP_ACT_HID_MASK 4095 #define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2 -#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 5 +#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 8 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1 enum bnxt_ulp_action_bit { @@ -34,29 +34,25 @@ enum bnxt_ulp_action_bit { BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004, BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008, BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010, - BNXT_ULP_ACTION_BIT_VNIC = 0x0000000000000020, - BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040, - BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080, - BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100, - BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200, - BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400, - BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800, - BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000, - BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000, - BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000, - BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000, - BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000, - BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000, - BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000, - BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000, - BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000, - BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000200000, - BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000400000, - BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000800000, - BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000001000000, - BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000002000000, - BNXT_ULP_ACTION_BIT_NVGRE_ENCAP = 0x0000000004000000, - BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000 + BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000020, + BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000040, + BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000080, + BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000100, + BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000000200, + BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000000400, + BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000000800, + BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000001000, + BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000002000, + BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000004000, + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000008000, + BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000010000, + BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000020000, + BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000040000, + BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000080000, + BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000100000, + BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000000200000, + BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000000400000, + BNXT_ULP_ACTION_BIT_LAST = 0x0000000000800000 }; enum bnxt_ulp_hdr_bit { @@ -184,9 +180,11 @@ enum bnxt_ulp_flow_mem_type { enum bnxt_ulp_glb_regfile_index { BNXT_ULP_GLB_REGFILE_INDEX_NOT_USED = 0, BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 1, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID = 2, - BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR = 3, - BNXT_ULP_GLB_REGFILE_INDEX_LAST = 4 + BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR = 2, + BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID = 3, + BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID = 4, + BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR = 5, + BNXT_ULP_GLB_REGFILE_INDEX_LAST = 6 }; enum bnxt_ulp_hdr_type { @@ -628,35 +626,240 @@ enum bnxt_ulp_act_prop_idx { }; enum bnxt_ulp_class_hid { - BNXT_ULP_CLASS_HID_0080 = 0x0080, - BNXT_ULP_CLASS_HID_0087 = 0x0087, - BNXT_ULP_CLASS_HID_0000 = 0x0000 + BNXT_ULP_CLASS_HID_0138 = 0x0138, + BNXT_ULP_CLASS_HID_03f0 = 0x03f0, + BNXT_ULP_CLASS_HID_0134 = 0x0134, + BNXT_ULP_CLASS_HID_03fc = 0x03fc, + BNXT_ULP_CLASS_HID_0139 = 0x0139, + BNXT_ULP_CLASS_HID_03f1 = 0x03f1, + BNXT_ULP_CLASS_HID_068b = 0x068b, + BNXT_ULP_CLASS_HID_0143 = 0x0143, + BNXT_ULP_CLASS_HID_0135 = 0x0135, + BNXT_ULP_CLASS_HID_03fd = 0x03fd, + BNXT_ULP_CLASS_HID_0687 = 0x0687, + BNXT_ULP_CLASS_HID_014f = 0x014f, + BNXT_ULP_CLASS_HID_0118 = 0x0118, + BNXT_ULP_CLASS_HID_03d0 = 0x03d0, + BNXT_ULP_CLASS_HID_0114 = 0x0114, + BNXT_ULP_CLASS_HID_03dc = 0x03dc, + BNXT_ULP_CLASS_HID_0119 = 0x0119, + BNXT_ULP_CLASS_HID_03d1 = 0x03d1, + BNXT_ULP_CLASS_HID_06ab = 0x06ab, + BNXT_ULP_CLASS_HID_0163 = 0x0163, + BNXT_ULP_CLASS_HID_0115 = 0x0115, + BNXT_ULP_CLASS_HID_03dd = 0x03dd, + BNXT_ULP_CLASS_HID_06a7 = 0x06a7, + BNXT_ULP_CLASS_HID_016f = 0x016f, + BNXT_ULP_CLASS_HID_0128 = 0x0128, + BNXT_ULP_CLASS_HID_03e0 = 0x03e0, + BNXT_ULP_CLASS_HID_0124 = 0x0124, + BNXT_ULP_CLASS_HID_03ec = 0x03ec, + BNXT_ULP_CLASS_HID_0129 = 0x0129, + BNXT_ULP_CLASS_HID_03e1 = 0x03e1, + BNXT_ULP_CLASS_HID_069b = 0x069b, + BNXT_ULP_CLASS_HID_0153 = 0x0153, + BNXT_ULP_CLASS_HID_0125 = 0x0125, + BNXT_ULP_CLASS_HID_03ed = 0x03ed, + BNXT_ULP_CLASS_HID_0697 = 0x0697, + BNXT_ULP_CLASS_HID_015f = 0x015f, + BNXT_ULP_CLASS_HID_0452 = 0x0452, + BNXT_ULP_CLASS_HID_0528 = 0x0528, + BNXT_ULP_CLASS_HID_0790 = 0x0790, + BNXT_ULP_CLASS_HID_046e = 0x046e, + BNXT_ULP_CLASS_HID_0462 = 0x0462, + BNXT_ULP_CLASS_HID_0518 = 0x0518, + BNXT_ULP_CLASS_HID_07a0 = 0x07a0, + BNXT_ULP_CLASS_HID_045e = 0x045e, + BNXT_ULP_CLASS_HID_0228 = 0x0228, + BNXT_ULP_CLASS_HID_06d0 = 0x06d0, + BNXT_ULP_CLASS_HID_02be = 0x02be, + BNXT_ULP_CLASS_HID_07a6 = 0x07a6, + BNXT_ULP_CLASS_HID_0218 = 0x0218, + BNXT_ULP_CLASS_HID_06e0 = 0x06e0, + BNXT_ULP_CLASS_HID_028e = 0x028e, + BNXT_ULP_CLASS_HID_0796 = 0x0796, + BNXT_ULP_CLASS_HID_079c = 0x079c, + BNXT_ULP_CLASS_HID_0654 = 0x0654, + BNXT_ULP_CLASS_HID_06d2 = 0x06d2, + BNXT_ULP_CLASS_HID_058a = 0x058a, + BNXT_ULP_CLASS_HID_052f = 0x052f, + BNXT_ULP_CLASS_HID_07e7 = 0x07e7, + BNXT_ULP_CLASS_HID_079d = 0x079d, + BNXT_ULP_CLASS_HID_0655 = 0x0655, + BNXT_ULP_CLASS_HID_046d = 0x046d, + BNXT_ULP_CLASS_HID_0725 = 0x0725, + BNXT_ULP_CLASS_HID_06d3 = 0x06d3, + BNXT_ULP_CLASS_HID_058b = 0x058b, + BNXT_ULP_CLASS_HID_07ac = 0x07ac, + BNXT_ULP_CLASS_HID_0664 = 0x0664, + BNXT_ULP_CLASS_HID_06e2 = 0x06e2, + BNXT_ULP_CLASS_HID_05ba = 0x05ba, + BNXT_ULP_CLASS_HID_051f = 0x051f, + BNXT_ULP_CLASS_HID_07d7 = 0x07d7, + BNXT_ULP_CLASS_HID_07ad = 0x07ad, + BNXT_ULP_CLASS_HID_0665 = 0x0665, + BNXT_ULP_CLASS_HID_045d = 0x045d, + BNXT_ULP_CLASS_HID_0715 = 0x0715, + BNXT_ULP_CLASS_HID_06e3 = 0x06e3, + BNXT_ULP_CLASS_HID_05bb = 0x05bb, + BNXT_ULP_CLASS_HID_016a = 0x016a, + BNXT_ULP_CLASS_HID_03d2 = 0x03d2, + BNXT_ULP_CLASS_HID_0612 = 0x0612, + BNXT_ULP_CLASS_HID_00da = 0x00da, + BNXT_ULP_CLASS_HID_06bd = 0x06bd, + BNXT_ULP_CLASS_HID_0165 = 0x0165, + BNXT_ULP_CLASS_HID_016b = 0x016b, + BNXT_ULP_CLASS_HID_03d3 = 0x03d3, + BNXT_ULP_CLASS_HID_03a5 = 0x03a5, + BNXT_ULP_CLASS_HID_066d = 0x066d, + BNXT_ULP_CLASS_HID_0613 = 0x0613, + BNXT_ULP_CLASS_HID_00db = 0x00db, + BNXT_ULP_CLASS_HID_015a = 0x015a, + BNXT_ULP_CLASS_HID_03e2 = 0x03e2, + BNXT_ULP_CLASS_HID_0622 = 0x0622, + BNXT_ULP_CLASS_HID_00ea = 0x00ea, + BNXT_ULP_CLASS_HID_068d = 0x068d, + BNXT_ULP_CLASS_HID_0155 = 0x0155, + BNXT_ULP_CLASS_HID_015b = 0x015b, + BNXT_ULP_CLASS_HID_03e3 = 0x03e3, + BNXT_ULP_CLASS_HID_0395 = 0x0395, + BNXT_ULP_CLASS_HID_065d = 0x065d, + BNXT_ULP_CLASS_HID_0623 = 0x0623, + BNXT_ULP_CLASS_HID_00eb = 0x00eb, + BNXT_ULP_CLASS_HID_0768 = 0x0768, + BNXT_ULP_CLASS_HID_073c = 0x073c, + BNXT_ULP_CLASS_HID_04bc = 0x04bc, + BNXT_ULP_CLASS_HID_0442 = 0x0442, + BNXT_ULP_CLASS_HID_050a = 0x050a, + BNXT_ULP_CLASS_HID_06ba = 0x06ba, + BNXT_ULP_CLASS_HID_0472 = 0x0472, + BNXT_ULP_CLASS_HID_0700 = 0x0700, + BNXT_ULP_CLASS_HID_04c8 = 0x04c8, + BNXT_ULP_CLASS_HID_0678 = 0x0678, + BNXT_ULP_CLASS_HID_064f = 0x064f, + BNXT_ULP_CLASS_HID_051d = 0x051d, + BNXT_ULP_CLASS_HID_06a5 = 0x06a5, + BNXT_ULP_CLASS_HID_0455 = 0x0455, + BNXT_ULP_CLASS_HID_04bd = 0x04bd, + BNXT_ULP_CLASS_HID_0443 = 0x0443, + BNXT_ULP_CLASS_HID_050b = 0x050b, + BNXT_ULP_CLASS_HID_06bb = 0x06bb, + BNXT_ULP_CLASS_HID_050d = 0x050d, + BNXT_ULP_CLASS_HID_04d3 = 0x04d3, + BNXT_ULP_CLASS_HID_059b = 0x059b, + BNXT_ULP_CLASS_HID_070b = 0x070b, + BNXT_ULP_CLASS_HID_0473 = 0x0473, + BNXT_ULP_CLASS_HID_0701 = 0x0701, + BNXT_ULP_CLASS_HID_04c9 = 0x04c9, + BNXT_ULP_CLASS_HID_0679 = 0x0679, + BNXT_ULP_CLASS_HID_048b = 0x048b, + BNXT_ULP_CLASS_HID_0749 = 0x0749, + BNXT_ULP_CLASS_HID_05f1 = 0x05f1, + BNXT_ULP_CLASS_HID_04b7 = 0x04b7, + BNXT_ULP_CLASS_HID_049b = 0x049b, + BNXT_ULP_CLASS_HID_0759 = 0x0759, + BNXT_ULP_CLASS_HID_05e1 = 0x05e1, + BNXT_ULP_CLASS_HID_04a7 = 0x04a7, + BNXT_ULP_CLASS_HID_0301 = 0x0301, + BNXT_ULP_CLASS_HID_07f9 = 0x07f9, + BNXT_ULP_CLASS_HID_0397 = 0x0397, + BNXT_ULP_CLASS_HID_068f = 0x068f, + BNXT_ULP_CLASS_HID_02f1 = 0x02f1, + BNXT_ULP_CLASS_HID_0609 = 0x0609, + BNXT_ULP_CLASS_HID_0267 = 0x0267, + BNXT_ULP_CLASS_HID_077f = 0x077f, + BNXT_ULP_CLASS_HID_01e1 = 0x01e1, + BNXT_ULP_CLASS_HID_0329 = 0x0329, + BNXT_ULP_CLASS_HID_01dd = 0x01dd, + BNXT_ULP_CLASS_HID_0315 = 0x0315, + BNXT_ULP_CLASS_HID_01c1 = 0x01c1, + BNXT_ULP_CLASS_HID_0309 = 0x0309, + BNXT_ULP_CLASS_HID_003d = 0x003d, + BNXT_ULP_CLASS_HID_02f5 = 0x02f5, + BNXT_ULP_CLASS_HID_01d1 = 0x01d1, + BNXT_ULP_CLASS_HID_0319 = 0x0319, + BNXT_ULP_CLASS_HID_01cd = 0x01cd, + BNXT_ULP_CLASS_HID_0305 = 0x0305 }; enum bnxt_ulp_act_hid { + BNXT_ULP_ACT_HID_015a = 0x015a, + BNXT_ULP_ACT_HID_00eb = 0x00eb, + BNXT_ULP_ACT_HID_0043 = 0x0043, + BNXT_ULP_ACT_HID_01d6 = 0x01d6, + BNXT_ULP_ACT_HID_015e = 0x015e, + BNXT_ULP_ACT_HID_00ef = 0x00ef, + BNXT_ULP_ACT_HID_0047 = 0x0047, + BNXT_ULP_ACT_HID_01da = 0x01da, + BNXT_ULP_ACT_HID_025b = 0x025b, + BNXT_ULP_ACT_HID_01ec = 0x01ec, + BNXT_ULP_ACT_HID_0144 = 0x0144, + BNXT_ULP_ACT_HID_02d7 = 0x02d7, + BNXT_ULP_ACT_HID_025f = 0x025f, + BNXT_ULP_ACT_HID_01f0 = 0x01f0, + BNXT_ULP_ACT_HID_0148 = 0x0148, + BNXT_ULP_ACT_HID_02db = 0x02db, + BNXT_ULP_ACT_HID_0000 = 0x0000, BNXT_ULP_ACT_HID_0002 = 0x0002, - BNXT_ULP_ACT_HID_0022 = 0x0022, - BNXT_ULP_ACT_HID_0026 = 0x0026, - BNXT_ULP_ACT_HID_0006 = 0x0006, + BNXT_ULP_ACT_HID_0800 = 0x0800, + BNXT_ULP_ACT_HID_0101 = 0x0101, + BNXT_ULP_ACT_HID_0020 = 0x0020, + BNXT_ULP_ACT_HID_0901 = 0x0901, + BNXT_ULP_ACT_HID_0121 = 0x0121, + BNXT_ULP_ACT_HID_0004 = 0x0004, + BNXT_ULP_ACT_HID_0804 = 0x0804, + BNXT_ULP_ACT_HID_0105 = 0x0105, + BNXT_ULP_ACT_HID_0024 = 0x0024, + BNXT_ULP_ACT_HID_0905 = 0x0905, + BNXT_ULP_ACT_HID_0125 = 0x0125, + BNXT_ULP_ACT_HID_0001 = 0x0001, + BNXT_ULP_ACT_HID_0005 = 0x0005, BNXT_ULP_ACT_HID_0009 = 0x0009, - BNXT_ULP_ACT_HID_0029 = 0x0029, - BNXT_ULP_ACT_HID_002d = 0x002d, - BNXT_ULP_ACT_HID_004b = 0x004b, - BNXT_ULP_ACT_HID_004a = 0x004a, - BNXT_ULP_ACT_HID_004f = 0x004f, - BNXT_ULP_ACT_HID_004e = 0x004e, - BNXT_ULP_ACT_HID_006c = 0x006c, - BNXT_ULP_ACT_HID_0070 = 0x0070, + BNXT_ULP_ACT_HID_000d = 0x000d, BNXT_ULP_ACT_HID_0021 = 0x0021, + BNXT_ULP_ACT_HID_0029 = 0x0029, BNXT_ULP_ACT_HID_0025 = 0x0025, - BNXT_ULP_ACT_HID_0043 = 0x0043, - BNXT_ULP_ACT_HID_0042 = 0x0042, - BNXT_ULP_ACT_HID_0047 = 0x0047, - BNXT_ULP_ACT_HID_0046 = 0x0046, - BNXT_ULP_ACT_HID_0064 = 0x0064, - BNXT_ULP_ACT_HID_0068 = 0x0068, - BNXT_ULP_ACT_HID_00a1 = 0x00a1, - BNXT_ULP_ACT_HID_00df = 0x00df + BNXT_ULP_ACT_HID_002d = 0x002d, + BNXT_ULP_ACT_HID_0801 = 0x0801, + BNXT_ULP_ACT_HID_0809 = 0x0809, + BNXT_ULP_ACT_HID_0805 = 0x0805, + BNXT_ULP_ACT_HID_080d = 0x080d, + BNXT_ULP_ACT_HID_0c15 = 0x0c15, + BNXT_ULP_ACT_HID_0c19 = 0x0c19, + BNXT_ULP_ACT_HID_02f6 = 0x02f6, + BNXT_ULP_ACT_HID_04f8 = 0x04f8, + BNXT_ULP_ACT_HID_01df = 0x01df, + BNXT_ULP_ACT_HID_05e3 = 0x05e3, + BNXT_ULP_ACT_HID_02fa = 0x02fa, + BNXT_ULP_ACT_HID_04fc = 0x04fc, + BNXT_ULP_ACT_HID_01e3 = 0x01e3, + BNXT_ULP_ACT_HID_05e7 = 0x05e7, + BNXT_ULP_ACT_HID_03f7 = 0x03f7, + BNXT_ULP_ACT_HID_05f9 = 0x05f9, + BNXT_ULP_ACT_HID_02e0 = 0x02e0, + BNXT_ULP_ACT_HID_06e4 = 0x06e4, + BNXT_ULP_ACT_HID_03fb = 0x03fb, + BNXT_ULP_ACT_HID_05fd = 0x05fd, + BNXT_ULP_ACT_HID_02e4 = 0x02e4, + BNXT_ULP_ACT_HID_06e8 = 0x06e8, + BNXT_ULP_ACT_HID_040d = 0x040d, + BNXT_ULP_ACT_HID_040f = 0x040f, + BNXT_ULP_ACT_HID_0413 = 0x0413, + BNXT_ULP_ACT_HID_0c0d = 0x0c0d, + BNXT_ULP_ACT_HID_0567 = 0x0567, + BNXT_ULP_ACT_HID_0a49 = 0x0a49, + BNXT_ULP_ACT_HID_050e = 0x050e, + BNXT_ULP_ACT_HID_0d0e = 0x0d0e, + BNXT_ULP_ACT_HID_0668 = 0x0668, + BNXT_ULP_ACT_HID_0b4a = 0x0b4a, + BNXT_ULP_ACT_HID_0411 = 0x0411, + BNXT_ULP_ACT_HID_056b = 0x056b, + BNXT_ULP_ACT_HID_0a4d = 0x0a4d, + BNXT_ULP_ACT_HID_0c11 = 0x0c11, + BNXT_ULP_ACT_HID_0512 = 0x0512, + BNXT_ULP_ACT_HID_0d12 = 0x0d12, + BNXT_ULP_ACT_HID_066c = 0x066c, + BNXT_ULP_ACT_HID_0b4e = 0x0b4e }; enum bnxt_ulp_df_tpl { @@ -664,9 +867,7 @@ enum bnxt_ulp_df_tpl { BNXT_ULP_DF_TPL_VS_TO_PORT = 2, BNXT_ULP_DF_TPL_VFREP_TO_VF = 3, BNXT_ULP_DF_TPL_VF_TO_VFREP = 4, - BNXT_ULP_DF_TPL_DRV_FUNC_SVIF_PUSH_VLAN = 5, - BNXT_ULP_DF_TPL_PORT_SVIF_VID_VNIC_POP_VLAN = 6, - BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7 + BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 5 }; #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h index 7695420..a5bd3f6 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h @@ -27,11 +27,53 @@ enum bnxt_ulp_hf5 { }; enum bnxt_ulp_hf6 { - BNXT_ULP_HF6_IDX_SVIF_INDEX = 0 + BNXT_ULP_HF6_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF6_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF6_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF6_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF6_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF6_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF6_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF6_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF6_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF6_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF6_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF6_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF6_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF6_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF6_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF6_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF6_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF6_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF6_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF6_IDX_O_IPV4_DST_ADDR = 19 }; enum bnxt_ulp_hf7 { - BNXT_ULP_HF7_IDX_SVIF_INDEX = 0 + BNXT_ULP_HF7_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF7_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF7_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF7_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF7_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF7_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF7_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF7_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF7_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF7_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF7_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF7_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF7_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF7_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF7_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF7_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF7_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF7_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF7_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF7_IDX_O_IPV4_DST_ADDR = 19, + BNXT_ULP_HF7_IDX_O_UDP_SRC_PORT = 20, + BNXT_ULP_HF7_IDX_O_UDP_DST_PORT = 21, + BNXT_ULP_HF7_IDX_O_UDP_LENGTH = 22, + BNXT_ULP_HF7_IDX_O_UDP_CSUM = 23 }; enum bnxt_ulp_hf8 { @@ -55,10 +97,15 @@ enum bnxt_ulp_hf8 { BNXT_ULP_HF8_IDX_O_IPV4_CSUM = 17, BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR = 18, BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF8_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF8_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF8_IDX_O_UDP_CSUM = 23 + BNXT_ULP_HF8_IDX_O_TCP_SRC_PORT = 20, + BNXT_ULP_HF8_IDX_O_TCP_DST_PORT = 21, + BNXT_ULP_HF8_IDX_O_TCP_SENT_SEQ = 22, + BNXT_ULP_HF8_IDX_O_TCP_RECV_ACK = 23, + BNXT_ULP_HF8_IDX_O_TCP_DATA_OFF = 24, + BNXT_ULP_HF8_IDX_O_TCP_TCP_FLAGS = 25, + BNXT_ULP_HF8_IDX_O_TCP_RX_WIN = 26, + BNXT_ULP_HF8_IDX_O_TCP_CSUM = 27, + BNXT_ULP_HF8_IDX_O_TCP_URP = 28 }; enum bnxt_ulp_hf9 { @@ -72,47 +119,18 @@ enum bnxt_ulp_hf9 { BNXT_ULP_HF9_IDX_OI_VLAN_CFI_PRI = 7, BNXT_ULP_HF9_IDX_OI_VLAN_VID = 8, BNXT_ULP_HF9_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF9_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF9_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF9_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF9_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF9_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF9_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF9_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF9_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF9_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF9_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF9_IDX_O_UDP_CSUM = 23, - BNXT_ULP_HF9_IDX_T_VXLAN_FLAGS = 24, - BNXT_ULP_HF9_IDX_T_VXLAN_RSVD0 = 25, - BNXT_ULP_HF9_IDX_T_VXLAN_VNI = 26, - BNXT_ULP_HF9_IDX_T_VXLAN_RSVD1 = 27, - BNXT_ULP_HF9_IDX_I_ETH_DMAC = 28, - BNXT_ULP_HF9_IDX_I_ETH_SMAC = 29, - BNXT_ULP_HF9_IDX_I_ETH_TYPE = 30, - BNXT_ULP_HF9_IDX_IO_VLAN_CFI_PRI = 31, - BNXT_ULP_HF9_IDX_IO_VLAN_VID = 32, - BNXT_ULP_HF9_IDX_IO_VLAN_TYPE = 33, - BNXT_ULP_HF9_IDX_II_VLAN_CFI_PRI = 34, - BNXT_ULP_HF9_IDX_II_VLAN_VID = 35, - BNXT_ULP_HF9_IDX_II_VLAN_TYPE = 36, - BNXT_ULP_HF9_IDX_I_IPV4_VER = 37, - BNXT_ULP_HF9_IDX_I_IPV4_TOS = 38, - BNXT_ULP_HF9_IDX_I_IPV4_LEN = 39, - BNXT_ULP_HF9_IDX_I_IPV4_FRAG_ID = 40, - BNXT_ULP_HF9_IDX_I_IPV4_FRAG_OFF = 41, - BNXT_ULP_HF9_IDX_I_IPV4_TTL = 42, - BNXT_ULP_HF9_IDX_I_IPV4_PROTO_ID = 43, - BNXT_ULP_HF9_IDX_I_IPV4_CSUM = 44, - BNXT_ULP_HF9_IDX_I_IPV4_SRC_ADDR = 45, - BNXT_ULP_HF9_IDX_I_IPV4_DST_ADDR = 46, - BNXT_ULP_HF9_IDX_I_UDP_SRC_PORT = 47, - BNXT_ULP_HF9_IDX_I_UDP_DST_PORT = 48, - BNXT_ULP_HF9_IDX_I_UDP_LENGTH = 49, - BNXT_ULP_HF9_IDX_I_UDP_CSUM = 50 + BNXT_ULP_HF9_IDX_O_IPV6_VER = 10, + BNXT_ULP_HF9_IDX_O_IPV6_TC = 11, + BNXT_ULP_HF9_IDX_O_IPV6_FLOW_LABEL = 12, + BNXT_ULP_HF9_IDX_O_IPV6_PAYLOAD_LEN = 13, + BNXT_ULP_HF9_IDX_O_IPV6_PROTO_ID = 14, + BNXT_ULP_HF9_IDX_O_IPV6_TTL = 15, + BNXT_ULP_HF9_IDX_O_IPV6_SRC_ADDR = 16, + BNXT_ULP_HF9_IDX_O_IPV6_DST_ADDR = 17, + BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT = 18, + BNXT_ULP_HF9_IDX_O_UDP_DST_PORT = 19, + BNXT_ULP_HF9_IDX_O_UDP_LENGTH = 20, + BNXT_ULP_HF9_IDX_O_UDP_CSUM = 21 }; enum bnxt_ulp_hf10 { @@ -126,20 +144,359 @@ enum bnxt_ulp_hf10 { BNXT_ULP_HF10_IDX_OI_VLAN_CFI_PRI = 7, BNXT_ULP_HF10_IDX_OI_VLAN_VID = 8, BNXT_ULP_HF10_IDX_OI_VLAN_TYPE = 9, - BNXT_ULP_HF10_IDX_O_IPV4_VER = 10, - BNXT_ULP_HF10_IDX_O_IPV4_TOS = 11, - BNXT_ULP_HF10_IDX_O_IPV4_LEN = 12, - BNXT_ULP_HF10_IDX_O_IPV4_FRAG_ID = 13, - BNXT_ULP_HF10_IDX_O_IPV4_FRAG_OFF = 14, - BNXT_ULP_HF10_IDX_O_IPV4_TTL = 15, - BNXT_ULP_HF10_IDX_O_IPV4_PROTO_ID = 16, - BNXT_ULP_HF10_IDX_O_IPV4_CSUM = 17, - BNXT_ULP_HF10_IDX_O_IPV4_SRC_ADDR = 18, - BNXT_ULP_HF10_IDX_O_IPV4_DST_ADDR = 19, - BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT = 20, - BNXT_ULP_HF10_IDX_O_UDP_DST_PORT = 21, - BNXT_ULP_HF10_IDX_O_UDP_LENGTH = 22, - BNXT_ULP_HF10_IDX_O_UDP_CSUM = 23 + BNXT_ULP_HF10_IDX_O_IPV6_VER = 10, + BNXT_ULP_HF10_IDX_O_IPV6_TC = 11, + BNXT_ULP_HF10_IDX_O_IPV6_FLOW_LABEL = 12, + BNXT_ULP_HF10_IDX_O_IPV6_PAYLOAD_LEN = 13, + BNXT_ULP_HF10_IDX_O_IPV6_PROTO_ID = 14, + BNXT_ULP_HF10_IDX_O_IPV6_TTL = 15, + BNXT_ULP_HF10_IDX_O_IPV6_SRC_ADDR = 16, + BNXT_ULP_HF10_IDX_O_IPV6_DST_ADDR = 17, + BNXT_ULP_HF10_IDX_O_TCP_SRC_PORT = 18, + BNXT_ULP_HF10_IDX_O_TCP_DST_PORT = 19, + BNXT_ULP_HF10_IDX_O_TCP_SENT_SEQ = 20, + BNXT_ULP_HF10_IDX_O_TCP_RECV_ACK = 21, + BNXT_ULP_HF10_IDX_O_TCP_DATA_OFF = 22, + BNXT_ULP_HF10_IDX_O_TCP_TCP_FLAGS = 23, + BNXT_ULP_HF10_IDX_O_TCP_RX_WIN = 24, + BNXT_ULP_HF10_IDX_O_TCP_CSUM = 25, + BNXT_ULP_HF10_IDX_O_TCP_URP = 26 +}; + +enum bnxt_ulp_hf11 { + BNXT_ULP_HF11_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF11_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF11_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF11_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF11_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF11_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF11_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF11_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF11_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF11_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF11_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF11_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF11_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF11_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF11_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF11_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF11_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF11_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF11_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF11_IDX_O_IPV4_DST_ADDR = 19, + BNXT_ULP_HF11_IDX_O_UDP_SRC_PORT = 20, + BNXT_ULP_HF11_IDX_O_UDP_DST_PORT = 21, + BNXT_ULP_HF11_IDX_O_UDP_LENGTH = 22, + BNXT_ULP_HF11_IDX_O_UDP_CSUM = 23 +}; + +enum bnxt_ulp_hf12 { + BNXT_ULP_HF12_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF12_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF12_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF12_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF12_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF12_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF12_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF12_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF12_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF12_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF12_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF12_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF12_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF12_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF12_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF12_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF12_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF12_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF12_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF12_IDX_O_IPV4_DST_ADDR = 19, + BNXT_ULP_HF12_IDX_O_TCP_SRC_PORT = 20, + BNXT_ULP_HF12_IDX_O_TCP_DST_PORT = 21, + BNXT_ULP_HF12_IDX_O_TCP_SENT_SEQ = 22, + BNXT_ULP_HF12_IDX_O_TCP_RECV_ACK = 23, + BNXT_ULP_HF12_IDX_O_TCP_DATA_OFF = 24, + BNXT_ULP_HF12_IDX_O_TCP_TCP_FLAGS = 25, + BNXT_ULP_HF12_IDX_O_TCP_RX_WIN = 26, + BNXT_ULP_HF12_IDX_O_TCP_CSUM = 27, + BNXT_ULP_HF12_IDX_O_TCP_URP = 28 +}; + +enum bnxt_ulp_hf13 { + BNXT_ULP_HF13_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF13_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF13_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF13_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF13_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF13_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF13_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF13_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF13_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF13_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF13_IDX_O_IPV6_VER = 10, + BNXT_ULP_HF13_IDX_O_IPV6_TC = 11, + BNXT_ULP_HF13_IDX_O_IPV6_FLOW_LABEL = 12, + BNXT_ULP_HF13_IDX_O_IPV6_PAYLOAD_LEN = 13, + BNXT_ULP_HF13_IDX_O_IPV6_PROTO_ID = 14, + BNXT_ULP_HF13_IDX_O_IPV6_TTL = 15, + BNXT_ULP_HF13_IDX_O_IPV6_SRC_ADDR = 16, + BNXT_ULP_HF13_IDX_O_IPV6_DST_ADDR = 17, + BNXT_ULP_HF13_IDX_O_UDP_SRC_PORT = 18, + BNXT_ULP_HF13_IDX_O_UDP_DST_PORT = 19, + BNXT_ULP_HF13_IDX_O_UDP_LENGTH = 20, + BNXT_ULP_HF13_IDX_O_UDP_CSUM = 21 +}; + +enum bnxt_ulp_hf14 { + BNXT_ULP_HF14_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF14_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF14_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF14_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF14_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF14_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF14_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF14_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF14_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF14_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF14_IDX_O_IPV6_VER = 10, + BNXT_ULP_HF14_IDX_O_IPV6_TC = 11, + BNXT_ULP_HF14_IDX_O_IPV6_FLOW_LABEL = 12, + BNXT_ULP_HF14_IDX_O_IPV6_PAYLOAD_LEN = 13, + BNXT_ULP_HF14_IDX_O_IPV6_PROTO_ID = 14, + BNXT_ULP_HF14_IDX_O_IPV6_TTL = 15, + BNXT_ULP_HF14_IDX_O_IPV6_SRC_ADDR = 16, + BNXT_ULP_HF14_IDX_O_IPV6_DST_ADDR = 17, + BNXT_ULP_HF14_IDX_O_TCP_SRC_PORT = 18, + BNXT_ULP_HF14_IDX_O_TCP_DST_PORT = 19, + BNXT_ULP_HF14_IDX_O_TCP_SENT_SEQ = 20, + BNXT_ULP_HF14_IDX_O_TCP_RECV_ACK = 21, + BNXT_ULP_HF14_IDX_O_TCP_DATA_OFF = 22, + BNXT_ULP_HF14_IDX_O_TCP_TCP_FLAGS = 23, + BNXT_ULP_HF14_IDX_O_TCP_RX_WIN = 24, + BNXT_ULP_HF14_IDX_O_TCP_CSUM = 25, + BNXT_ULP_HF14_IDX_O_TCP_URP = 26 +}; + +enum bnxt_ulp_hf15 { + BNXT_ULP_HF15_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF15_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF15_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF15_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF15_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF15_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF15_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF15_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF15_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF15_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF15_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF15_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF15_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF15_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF15_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF15_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF15_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF15_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF15_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF15_IDX_O_IPV4_DST_ADDR = 19, + BNXT_ULP_HF15_IDX_O_UDP_SRC_PORT = 20, + BNXT_ULP_HF15_IDX_O_UDP_DST_PORT = 21, + BNXT_ULP_HF15_IDX_O_UDP_LENGTH = 22, + BNXT_ULP_HF15_IDX_O_UDP_CSUM = 23, + BNXT_ULP_HF15_IDX_T_VXLAN_FLAGS = 24, + BNXT_ULP_HF15_IDX_T_VXLAN_RSVD0 = 25, + BNXT_ULP_HF15_IDX_T_VXLAN_VNI = 26, + BNXT_ULP_HF15_IDX_T_VXLAN_RSVD1 = 27, + BNXT_ULP_HF15_IDX_I_ETH_DMAC = 28, + BNXT_ULP_HF15_IDX_I_ETH_SMAC = 29, + BNXT_ULP_HF15_IDX_I_ETH_TYPE = 30, + BNXT_ULP_HF15_IDX_IO_VLAN_CFI_PRI = 31, + BNXT_ULP_HF15_IDX_IO_VLAN_VID = 32, + BNXT_ULP_HF15_IDX_IO_VLAN_TYPE = 33, + BNXT_ULP_HF15_IDX_II_VLAN_CFI_PRI = 34, + BNXT_ULP_HF15_IDX_II_VLAN_VID = 35, + BNXT_ULP_HF15_IDX_II_VLAN_TYPE = 36, + BNXT_ULP_HF15_IDX_I_IPV4_VER = 37, + BNXT_ULP_HF15_IDX_I_IPV4_TOS = 38, + BNXT_ULP_HF15_IDX_I_IPV4_LEN = 39, + BNXT_ULP_HF15_IDX_I_IPV4_FRAG_ID = 40, + BNXT_ULP_HF15_IDX_I_IPV4_FRAG_OFF = 41, + BNXT_ULP_HF15_IDX_I_IPV4_TTL = 42, + BNXT_ULP_HF15_IDX_I_IPV4_PROTO_ID = 43, + BNXT_ULP_HF15_IDX_I_IPV4_CSUM = 44, + BNXT_ULP_HF15_IDX_I_IPV4_SRC_ADDR = 45, + BNXT_ULP_HF15_IDX_I_IPV4_DST_ADDR = 46, + BNXT_ULP_HF15_IDX_I_UDP_SRC_PORT = 47, + BNXT_ULP_HF15_IDX_I_UDP_DST_PORT = 48, + BNXT_ULP_HF15_IDX_I_UDP_LENGTH = 49, + BNXT_ULP_HF15_IDX_I_UDP_CSUM = 50 +}; + +enum bnxt_ulp_hf16 { + BNXT_ULP_HF16_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF16_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF16_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF16_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF16_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF16_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF16_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF16_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF16_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF16_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF16_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF16_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF16_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF16_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF16_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF16_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF16_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF16_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF16_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR = 19, + BNXT_ULP_HF16_IDX_O_UDP_SRC_PORT = 20, + BNXT_ULP_HF16_IDX_O_UDP_DST_PORT = 21, + BNXT_ULP_HF16_IDX_O_UDP_LENGTH = 22, + BNXT_ULP_HF16_IDX_O_UDP_CSUM = 23, + BNXT_ULP_HF16_IDX_T_VXLAN_FLAGS = 24, + BNXT_ULP_HF16_IDX_T_VXLAN_RSVD0 = 25, + BNXT_ULP_HF16_IDX_T_VXLAN_VNI = 26, + BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1 = 27 +}; + +enum bnxt_ulp_hf17 { + BNXT_ULP_HF17_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF17_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF17_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF17_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF17_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF17_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF17_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF17_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF17_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF17_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF17_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF17_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF17_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF17_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF17_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF17_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF17_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF17_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF17_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR = 19, + BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT = 20, + BNXT_ULP_HF17_IDX_O_UDP_DST_PORT = 21, + BNXT_ULP_HF17_IDX_O_UDP_LENGTH = 22, + BNXT_ULP_HF17_IDX_O_UDP_CSUM = 23 +}; + +enum bnxt_ulp_hf18 { + BNXT_ULP_HF18_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF18_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF18_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF18_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF18_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF18_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF18_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF18_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF18_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF18_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF18_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF18_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF18_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF18_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF18_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF18_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF18_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF18_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR = 19, + BNXT_ULP_HF18_IDX_O_TCP_SRC_PORT = 20, + BNXT_ULP_HF18_IDX_O_TCP_DST_PORT = 21, + BNXT_ULP_HF18_IDX_O_TCP_SENT_SEQ = 22, + BNXT_ULP_HF18_IDX_O_TCP_RECV_ACK = 23, + BNXT_ULP_HF18_IDX_O_TCP_DATA_OFF = 24, + BNXT_ULP_HF18_IDX_O_TCP_TCP_FLAGS = 25, + BNXT_ULP_HF18_IDX_O_TCP_RX_WIN = 26, + BNXT_ULP_HF18_IDX_O_TCP_CSUM = 27, + BNXT_ULP_HF18_IDX_O_TCP_URP = 28 +}; + +enum bnxt_ulp_hf19 { + BNXT_ULP_HF19_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF19_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF19_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF19_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF19_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF19_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF19_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF19_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF19_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF19_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF19_IDX_O_IPV6_VER = 10, + BNXT_ULP_HF19_IDX_O_IPV6_TC = 11, + BNXT_ULP_HF19_IDX_O_IPV6_FLOW_LABEL = 12, + BNXT_ULP_HF19_IDX_O_IPV6_PAYLOAD_LEN = 13, + BNXT_ULP_HF19_IDX_O_IPV6_PROTO_ID = 14, + BNXT_ULP_HF19_IDX_O_IPV6_TTL = 15, + BNXT_ULP_HF19_IDX_O_IPV6_SRC_ADDR = 16, + BNXT_ULP_HF19_IDX_O_IPV6_DST_ADDR = 17, + BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT = 18, + BNXT_ULP_HF19_IDX_O_UDP_DST_PORT = 19, + BNXT_ULP_HF19_IDX_O_UDP_LENGTH = 20, + BNXT_ULP_HF19_IDX_O_UDP_CSUM = 21 +}; + +enum bnxt_ulp_hf20 { + BNXT_ULP_HF20_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF20_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF20_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF20_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF20_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF20_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF20_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF20_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF20_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF20_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF20_IDX_O_IPV6_VER = 10, + BNXT_ULP_HF20_IDX_O_IPV6_TC = 11, + BNXT_ULP_HF20_IDX_O_IPV6_FLOW_LABEL = 12, + BNXT_ULP_HF20_IDX_O_IPV6_PAYLOAD_LEN = 13, + BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID = 14, + BNXT_ULP_HF20_IDX_O_IPV6_TTL = 15, + BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR = 16, + BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR = 17, + BNXT_ULP_HF20_IDX_O_TCP_SRC_PORT = 18, + BNXT_ULP_HF20_IDX_O_TCP_DST_PORT = 19, + BNXT_ULP_HF20_IDX_O_TCP_SENT_SEQ = 20, + BNXT_ULP_HF20_IDX_O_TCP_RECV_ACK = 21, + BNXT_ULP_HF20_IDX_O_TCP_DATA_OFF = 22, + BNXT_ULP_HF20_IDX_O_TCP_TCP_FLAGS = 23, + BNXT_ULP_HF20_IDX_O_TCP_RX_WIN = 24, + BNXT_ULP_HF20_IDX_O_TCP_CSUM = 25, + BNXT_ULP_HF20_IDX_O_TCP_URP = 26 +}; + +enum bnxt_ulp_hf21 { + BNXT_ULP_HF21_IDX_SVIF_INDEX = 0, + BNXT_ULP_HF21_IDX_O_ETH_DMAC = 1, + BNXT_ULP_HF21_IDX_O_ETH_SMAC = 2, + BNXT_ULP_HF21_IDX_O_ETH_TYPE = 3, + BNXT_ULP_HF21_IDX_OO_VLAN_CFI_PRI = 4, + BNXT_ULP_HF21_IDX_OO_VLAN_VID = 5, + BNXT_ULP_HF21_IDX_OO_VLAN_TYPE = 6, + BNXT_ULP_HF21_IDX_OI_VLAN_CFI_PRI = 7, + BNXT_ULP_HF21_IDX_OI_VLAN_VID = 8, + BNXT_ULP_HF21_IDX_OI_VLAN_TYPE = 9, + BNXT_ULP_HF21_IDX_O_IPV4_VER = 10, + BNXT_ULP_HF21_IDX_O_IPV4_TOS = 11, + BNXT_ULP_HF21_IDX_O_IPV4_LEN = 12, + BNXT_ULP_HF21_IDX_O_IPV4_FRAG_ID = 13, + BNXT_ULP_HF21_IDX_O_IPV4_FRAG_OFF = 14, + BNXT_ULP_HF21_IDX_O_IPV4_TTL = 15, + BNXT_ULP_HF21_IDX_O_IPV4_PROTO_ID = 16, + BNXT_ULP_HF21_IDX_O_IPV4_CSUM = 17, + BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR = 18, + BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR = 19 }; enum bnxt_ulp_hf_bitmask1 { @@ -163,11 +520,53 @@ enum bnxt_ulp_hf_bitmask5 { }; enum bnxt_ulp_hf_bitmask6 { - BNXT_ULP_HF6_BITMASK_SVIF_INDEX = 0x8000000000000000 + BNXT_ULP_HF6_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF6_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF6_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF6_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF6_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF6_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF6_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF6_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF6_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF6_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF6_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000 }; enum bnxt_ulp_hf_bitmask7 { - BNXT_ULP_HF7_BITMASK_SVIF_INDEX = 0x8000000000000000 + BNXT_ULP_HF7_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF7_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF7_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF7_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF7_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF7_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF7_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF7_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF7_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF7_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF7_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, + BNXT_ULP_HF7_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF7_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF7_BITMASK_O_UDP_LENGTH = 0x0000020000000000, + BNXT_ULP_HF7_BITMASK_O_UDP_CSUM = 0x0000010000000000 }; enum bnxt_ulp_hf_bitmask8 { @@ -191,10 +590,15 @@ enum bnxt_ulp_hf_bitmask8 { BNXT_ULP_HF8_BITMASK_O_IPV4_CSUM = 0x0000400000000000, BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF8_BITMASK_O_UDP_CSUM = 0x0000010000000000 + BNXT_ULP_HF8_BITMASK_O_TCP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_SENT_SEQ = 0x0000020000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_RECV_ACK = 0x0000010000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_DATA_OFF = 0x0000008000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_TCP_FLAGS = 0x0000004000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_RX_WIN = 0x0000002000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_CSUM = 0x0000001000000000, + BNXT_ULP_HF8_BITMASK_O_TCP_URP = 0x0000000800000000 }; enum bnxt_ulp_hf_bitmask9 { @@ -208,47 +612,18 @@ enum bnxt_ulp_hf_bitmask9 { BNXT_ULP_HF9_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, BNXT_ULP_HF9_BITMASK_OI_VLAN_VID = 0x0080000000000000, BNXT_ULP_HF9_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF9_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF9_BITMASK_O_UDP_CSUM = 0x0000010000000000, - BNXT_ULP_HF9_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000, - BNXT_ULP_HF9_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000, - BNXT_ULP_HF9_BITMASK_T_VXLAN_VNI = 0x0000002000000000, - BNXT_ULP_HF9_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000, - BNXT_ULP_HF9_BITMASK_I_ETH_DMAC = 0x0000000800000000, - BNXT_ULP_HF9_BITMASK_I_ETH_SMAC = 0x0000000400000000, - BNXT_ULP_HF9_BITMASK_I_ETH_TYPE = 0x0000000200000000, - BNXT_ULP_HF9_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000, - BNXT_ULP_HF9_BITMASK_IO_VLAN_VID = 0x0000000080000000, - BNXT_ULP_HF9_BITMASK_IO_VLAN_TYPE = 0x0000000040000000, - BNXT_ULP_HF9_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000, - BNXT_ULP_HF9_BITMASK_II_VLAN_VID = 0x0000000010000000, - BNXT_ULP_HF9_BITMASK_II_VLAN_TYPE = 0x0000000008000000, - BNXT_ULP_HF9_BITMASK_I_IPV4_VER = 0x0000000004000000, - BNXT_ULP_HF9_BITMASK_I_IPV4_TOS = 0x0000000002000000, - BNXT_ULP_HF9_BITMASK_I_IPV4_LEN = 0x0000000001000000, - BNXT_ULP_HF9_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000, - BNXT_ULP_HF9_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000, - BNXT_ULP_HF9_BITMASK_I_IPV4_TTL = 0x0000000000200000, - BNXT_ULP_HF9_BITMASK_I_IPV4_PROTO_ID = 0x0000000000100000, - BNXT_ULP_HF9_BITMASK_I_IPV4_CSUM = 0x0000000000080000, - BNXT_ULP_HF9_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000, - BNXT_ULP_HF9_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000, - BNXT_ULP_HF9_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000, - BNXT_ULP_HF9_BITMASK_I_UDP_DST_PORT = 0x0000000000008000, - BNXT_ULP_HF9_BITMASK_I_UDP_LENGTH = 0x0000000000004000, - BNXT_ULP_HF9_BITMASK_I_UDP_CSUM = 0x0000000000002000 + BNXT_ULP_HF9_BITMASK_O_IPV6_VER = 0x0020000000000000, + BNXT_ULP_HF9_BITMASK_O_IPV6_TC = 0x0010000000000000, + BNXT_ULP_HF9_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, + BNXT_ULP_HF9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, + BNXT_ULP_HF9_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF9_BITMASK_O_IPV6_TTL = 0x0001000000000000, + BNXT_ULP_HF9_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF9_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF9_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF9_BITMASK_O_UDP_CSUM = 0x0000040000000000 }; enum bnxt_ulp_hf_bitmask10 { @@ -262,19 +637,359 @@ enum bnxt_ulp_hf_bitmask10 { BNXT_ULP_HF10_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, BNXT_ULP_HF10_BITMASK_OI_VLAN_VID = 0x0080000000000000, BNXT_ULP_HF10_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_VER = 0x0020000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_TOS = 0x0010000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_LEN = 0x0008000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_TTL = 0x0001000000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_CSUM = 0x0000400000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, - BNXT_ULP_HF10_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_LENGTH = 0x0000020000000000, - BNXT_ULP_HF10_BITMASK_O_UDP_CSUM = 0x0000010000000000 + BNXT_ULP_HF10_BITMASK_O_IPV6_VER = 0x0020000000000000, + BNXT_ULP_HF10_BITMASK_O_IPV6_TC = 0x0010000000000000, + BNXT_ULP_HF10_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, + BNXT_ULP_HF10_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, + BNXT_ULP_HF10_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF10_BITMASK_O_IPV6_TTL = 0x0001000000000000, + BNXT_ULP_HF10_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF10_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF10_BITMASK_O_TCP_URP = 0x0000002000000000 }; + +enum bnxt_ulp_hf_bitmask11 { + BNXT_ULP_HF11_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF11_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF11_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF11_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF11_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF11_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF11_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF11_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF11_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF11_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF11_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, + BNXT_ULP_HF11_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF11_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF11_BITMASK_O_UDP_LENGTH = 0x0000020000000000, + BNXT_ULP_HF11_BITMASK_O_UDP_CSUM = 0x0000010000000000 +}; + +enum bnxt_ulp_hf_bitmask12 { + BNXT_ULP_HF12_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF12_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF12_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF12_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF12_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF12_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF12_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF12_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF12_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF12_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF12_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_SENT_SEQ = 0x0000020000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_RECV_ACK = 0x0000010000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_DATA_OFF = 0x0000008000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_TCP_FLAGS = 0x0000004000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_RX_WIN = 0x0000002000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_CSUM = 0x0000001000000000, + BNXT_ULP_HF12_BITMASK_O_TCP_URP = 0x0000000800000000 +}; + +enum bnxt_ulp_hf_bitmask13 { + BNXT_ULP_HF13_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF13_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF13_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF13_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF13_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF13_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF13_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF13_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF13_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF13_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_VER = 0x0020000000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_TC = 0x0010000000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_TTL = 0x0001000000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF13_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF13_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF13_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF13_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF13_BITMASK_O_UDP_CSUM = 0x0000040000000000 +}; + +enum bnxt_ulp_hf_bitmask14 { + BNXT_ULP_HF14_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF14_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF14_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF14_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF14_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF14_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF14_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF14_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF14_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF14_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_VER = 0x0020000000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_TC = 0x0010000000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_TTL = 0x0001000000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF14_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF14_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf_bitmask15 { + BNXT_ULP_HF15_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF15_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF15_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF15_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF15_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF15_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF15_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF15_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF15_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF15_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF15_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, + BNXT_ULP_HF15_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF15_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF15_BITMASK_O_UDP_LENGTH = 0x0000020000000000, + BNXT_ULP_HF15_BITMASK_O_UDP_CSUM = 0x0000010000000000, + BNXT_ULP_HF15_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000, + BNXT_ULP_HF15_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000, + BNXT_ULP_HF15_BITMASK_T_VXLAN_VNI = 0x0000002000000000, + BNXT_ULP_HF15_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000, + BNXT_ULP_HF15_BITMASK_I_ETH_DMAC = 0x0000000800000000, + BNXT_ULP_HF15_BITMASK_I_ETH_SMAC = 0x0000000400000000, + BNXT_ULP_HF15_BITMASK_I_ETH_TYPE = 0x0000000200000000, + BNXT_ULP_HF15_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000, + BNXT_ULP_HF15_BITMASK_IO_VLAN_VID = 0x0000000080000000, + BNXT_ULP_HF15_BITMASK_IO_VLAN_TYPE = 0x0000000040000000, + BNXT_ULP_HF15_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000, + BNXT_ULP_HF15_BITMASK_II_VLAN_VID = 0x0000000010000000, + BNXT_ULP_HF15_BITMASK_II_VLAN_TYPE = 0x0000000008000000, + BNXT_ULP_HF15_BITMASK_I_IPV4_VER = 0x0000000004000000, + BNXT_ULP_HF15_BITMASK_I_IPV4_TOS = 0x0000000002000000, + BNXT_ULP_HF15_BITMASK_I_IPV4_LEN = 0x0000000001000000, + BNXT_ULP_HF15_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000, + BNXT_ULP_HF15_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000, + BNXT_ULP_HF15_BITMASK_I_IPV4_TTL = 0x0000000000200000, + BNXT_ULP_HF15_BITMASK_I_IPV4_PROTO_ID = 0x0000000000100000, + BNXT_ULP_HF15_BITMASK_I_IPV4_CSUM = 0x0000000000080000, + BNXT_ULP_HF15_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000, + BNXT_ULP_HF15_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000, + BNXT_ULP_HF15_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000, + BNXT_ULP_HF15_BITMASK_I_UDP_DST_PORT = 0x0000000000008000, + BNXT_ULP_HF15_BITMASK_I_UDP_LENGTH = 0x0000000000004000, + BNXT_ULP_HF15_BITMASK_I_UDP_CSUM = 0x0000000000002000 +}; + +enum bnxt_ulp_hf_bitmask16 { + BNXT_ULP_HF16_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF16_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF16_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF16_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF16_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF16_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF16_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF16_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF16_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, + BNXT_ULP_HF16_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF16_BITMASK_O_UDP_LENGTH = 0x0000020000000000, + BNXT_ULP_HF16_BITMASK_O_UDP_CSUM = 0x0000010000000000, + BNXT_ULP_HF16_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000, + BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000, + BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI = 0x0000002000000000, + BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000 +}; + +enum bnxt_ulp_hf_bitmask17 { + BNXT_ULP_HF17_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF17_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF17_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF17_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF17_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF17_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF17_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF17_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF17_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, + BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF17_BITMASK_O_UDP_LENGTH = 0x0000020000000000, + BNXT_ULP_HF17_BITMASK_O_UDP_CSUM = 0x0000010000000000 +}; + +enum bnxt_ulp_hf_bitmask18 { + BNXT_ULP_HF18_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF18_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF18_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF18_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF18_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF18_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF18_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF18_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF18_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF18_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_SRC_PORT = 0x0000080000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_DST_PORT = 0x0000040000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_SENT_SEQ = 0x0000020000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_RECV_ACK = 0x0000010000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_DATA_OFF = 0x0000008000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_TCP_FLAGS = 0x0000004000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_RX_WIN = 0x0000002000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_CSUM = 0x0000001000000000, + BNXT_ULP_HF18_BITMASK_O_TCP_URP = 0x0000000800000000 +}; + +enum bnxt_ulp_hf_bitmask19 { + BNXT_ULP_HF19_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF19_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF19_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF19_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF19_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF19_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF19_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF19_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF19_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF19_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_VER = 0x0020000000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_TC = 0x0010000000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_TTL = 0x0001000000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF19_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF19_BITMASK_O_UDP_LENGTH = 0x0000080000000000, + BNXT_ULP_HF19_BITMASK_O_UDP_CSUM = 0x0000040000000000 +}; + +enum bnxt_ulp_hf_bitmask20 { + BNXT_ULP_HF20_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF20_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF20_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF20_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF20_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF20_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF20_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF20_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF20_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF20_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_VER = 0x0020000000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_TC = 0x0010000000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_TTL = 0x0001000000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000, + BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_DST_PORT = 0x0000100000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_RX_WIN = 0x0000008000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_CSUM = 0x0000004000000000, + BNXT_ULP_HF20_BITMASK_O_TCP_URP = 0x0000002000000000 +}; + +enum bnxt_ulp_hf_bitmask21 { + BNXT_ULP_HF21_BITMASK_SVIF_INDEX = 0x8000000000000000, + BNXT_ULP_HF21_BITMASK_O_ETH_DMAC = 0x4000000000000000, + BNXT_ULP_HF21_BITMASK_O_ETH_SMAC = 0x2000000000000000, + BNXT_ULP_HF21_BITMASK_O_ETH_TYPE = 0x1000000000000000, + BNXT_ULP_HF21_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000, + BNXT_ULP_HF21_BITMASK_OO_VLAN_VID = 0x0400000000000000, + BNXT_ULP_HF21_BITMASK_OO_VLAN_TYPE = 0x0200000000000000, + BNXT_ULP_HF21_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000, + BNXT_ULP_HF21_BITMASK_OI_VLAN_VID = 0x0080000000000000, + BNXT_ULP_HF21_BITMASK_OI_VLAN_TYPE = 0x0040000000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_VER = 0x0020000000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_TOS = 0x0010000000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_LEN = 0x0008000000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_TTL = 0x0001000000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_CSUM = 0x0000400000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000, + BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000 +}; + #endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c index 24bde57..4388a0a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c @@ -95,466 +95,484 @@ uint32_t ulp_act_prop_map_table[] = { struct bnxt_ulp_rte_act_info ulp_act_info[] = { [RTE_FLOW_ACTION_TYPE_END] = { - .act_type = BNXT_ULP_ACT_TYPE_END, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_END, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_VOID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_void_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_void_act_handler }, [RTE_FLOW_ACTION_TYPE_PASSTHRU] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_JUMP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_MARK] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_mark_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_mark_act_handler }, [RTE_FLOW_ACTION_TYPE_FLAG] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_QUEUE] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_DROP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_drop_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_drop_act_handler }, [RTE_FLOW_ACTION_TYPE_COUNT] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_count_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_count_act_handler }, [RTE_FLOW_ACTION_TYPE_RSS] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_rss_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_rss_act_handler }, [RTE_FLOW_ACTION_TYPE_PF] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_pf_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_pf_act_handler }, [RTE_FLOW_ACTION_TYPE_VF] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vf_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_vf_act_handler }, [RTE_FLOW_ACTION_TYPE_PHY_PORT] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_phy_port_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_phy_port_act_handler }, [RTE_FLOW_ACTION_TYPE_PORT_ID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_port_id_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_port_id_act_handler }, [RTE_FLOW_ACTION_TYPE_METER] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_SECURITY] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_pop_vlan_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_pop_vlan_act_handler }, [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_push_vlan_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_push_vlan_act_handler }, [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_set_vlan_vid_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_set_vlan_vid_act_handler }, [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_of_set_vlan_pcp_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_of_set_vlan_pcp_act_handler }, [RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vxlan_encap_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_vxlan_encap_act_handler }, [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_vxlan_decap_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_vxlan_decap_act_handler }, [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_RAW_DECAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_ipv4_src_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_ipv4_src_act_handler }, [RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_ipv4_dst_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_ipv4_dst_act_handler }, [RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_tp_src_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_tp_src_act_handler }, [RTE_FLOW_ACTION_TYPE_SET_TP_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, - .proto_act_func = ulp_rte_set_tp_dst_act_handler + .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, + .proto_act_func = ulp_rte_set_tp_dst_act_handler }, [RTE_FLOW_ACTION_TYPE_MAC_SWAP] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_DEC_TTL] = { .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED, .proto_act_func = ulp_rte_dec_ttl_act_handler }, [RTE_FLOW_ACTION_TYPE_SET_TTL] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL }, [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = { - .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, - .proto_act_func = NULL + .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED, + .proto_act_func = NULL } }; struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = { [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 | TF_DIR_RX] = { - .num_entries = 16384 + .num_entries = 16384 }, [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 | TF_DIR_TX] = { - .num_entries = 16384 + .num_entries = 16384 }, [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 | TF_DIR_RX] = { - .num_entries = 16384 + .num_entries = 16384 }, [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 | TF_DIR_TX] = { - .num_entries = 16384 + .num_entries = 16384 } }; struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = { [BNXT_ULP_DEVICE_ID_WH_PLUS] = { - .flow_mem_type = BNXT_ULP_FLOW_MEM_TYPE_EXT, - .byte_order = BNXT_ULP_BYTE_ORDER_LE, - .encap_byte_swap = 1, - .flow_db_num_entries = 32768, - .mark_db_lfid_entries = 65536, - .mark_db_gfid_entries = 65536, - .flow_count_db_entries = 16384, - .num_resources_per_flow = 8, - .num_phy_ports = 2, - .ext_cntr_table_type = 0, - .byte_count_mask = 0x0000000fffffffff, - .packet_count_mask = 0xffffffff00000000, - .byte_count_shift = 0, - .packet_count_shift = 36 + .flow_mem_type = BNXT_ULP_FLOW_MEM_TYPE_INT, + .byte_order = BNXT_ULP_BYTE_ORDER_LE, + .encap_byte_swap = 1, + .flow_db_num_entries = 16384, + .mark_db_lfid_entries = 65536, + .mark_db_gfid_entries = 0, + .flow_count_db_entries = 16384, + .num_resources_per_flow = 8, + .num_phy_ports = 2, + .ext_cntr_table_type = 0, + .byte_count_mask = 0x0000000fffffffff, + .packet_count_mask = 0xffffffff00000000, + .byte_count_shift = 0, + .packet_count_shift = 36 } }; struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = { [0] = { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_RX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_RX }, [1] = { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_PROF_FUNC, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID, + .direction = TF_DIR_TX }, [2] = { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID, - .direction = TF_DIR_RX + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR, + .direction = TF_DIR_TX }, [3] = { - .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, - .resource_type = TF_IDENT_TYPE_L2_CTXT_HIGH, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID, + .direction = TF_DIR_RX }, [4] = { - .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, - .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD, - .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR, - .direction = TF_DIR_TX + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID, + .direction = TF_DIR_TX + }, + [5] = { + .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER, + .resource_type = TF_IDENT_TYPE_PROF_FUNC, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID, + .direction = TF_DIR_RX + }, + [6] = { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR, + .direction = TF_DIR_RX + }, + [7] = { + .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE, + .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B, + .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR, + .direction = TF_DIR_TX } }; struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = { [RTE_FLOW_ITEM_TYPE_END] = { - .hdr_type = BNXT_ULP_HDR_TYPE_END, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_END, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_VOID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_void_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_void_hdr_handler }, [RTE_FLOW_ITEM_TYPE_INVERT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ANY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_PF] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_pf_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_pf_hdr_handler }, [RTE_FLOW_ITEM_TYPE_VF] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vf_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_vf_hdr_handler }, [RTE_FLOW_ITEM_TYPE_PHY_PORT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_phy_port_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_phy_port_hdr_handler }, [RTE_FLOW_ITEM_TYPE_PORT_ID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_port_id_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_port_id_hdr_handler }, [RTE_FLOW_ITEM_TYPE_RAW] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_eth_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_eth_hdr_handler }, [RTE_FLOW_ITEM_TYPE_VLAN] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vlan_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_vlan_hdr_handler }, [RTE_FLOW_ITEM_TYPE_IPV4] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_ipv4_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_ipv4_hdr_handler }, [RTE_FLOW_ITEM_TYPE_IPV6] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_ipv6_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_ipv6_hdr_handler }, [RTE_FLOW_ITEM_TYPE_ICMP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_UDP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_udp_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_udp_hdr_handler }, [RTE_FLOW_ITEM_TYPE_TCP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_tcp_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_tcp_hdr_handler }, [RTE_FLOW_ITEM_TYPE_SCTP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_VXLAN] = { - .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, - .proto_hdr_func = ulp_rte_vxlan_hdr_handler + .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED, + .proto_hdr_func = ulp_rte_vxlan_hdr_handler }, [RTE_FLOW_ITEM_TYPE_E_TAG] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_NVGRE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_MPLS] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GRE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_FUZZY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GTP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GTPC] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GTPU] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ESP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GENEVE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_IPV6_EXT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ICMP6] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_MARK] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_META] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GRE_KEY] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_GTP_PSC] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_PPPOES] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_PPPOED] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_NSH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_IGMP] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_AH] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL }, [RTE_FLOW_ITEM_TYPE_HIGIG2] = { - .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, - .proto_hdr_func = NULL + .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED, + .proto_hdr_func = NULL } }; From patchwork Fri Jul 17 09:49:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Somnath Kotur X-Patchwork-Id: 74314 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3675DA053D; Fri, 17 Jul 2020 11:56:55 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B8EE61C0AC; Fri, 17 Jul 2020 11:55:18 +0200 (CEST) Received: from relay.smtp.broadcom.com (unknown [192.19.232.149]) by dpdk.org (Postfix) with ESMTP id 084561C026 for ; Fri, 17 Jul 2020 11:55:12 +0200 (CEST) Received: from dhcp-10-123-153-55.dhcp.broadcom.net (dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55]) by relay.smtp.broadcom.com (Postfix) with ESMTP id A41971BBB1D; Fri, 17 Jul 2020 02:55:11 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com A41971BBB1D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1594979712; bh=Z3+Ad8CYcssvo6x8He1nuY3h4crDbmLYJQlWWQWuwX0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E6I9nJof4xLvwsgnMPjLoaANCaeNGPJD2TShVhYDD6w1MMHO2xtmxeQe3zWr46FcM VZmOHStoHa/cf3pFRdh4MSrEtN24XGg6Z8aU8GkUJL76IbtnIT7S4aTOmaBDN3Fy3r EkOrvGeJNvLwfwPSw2HJaeW/pB6P46M0G+fmExps= From: Somnath Kotur To: dev@dpdk.org Cc: ferruh.yigit@intel.com Date: Fri, 17 Jul 2020 15:19:35 +0530 Message-Id: <20200717094935.9337-15-somnath.kotur@broadcom.com> X-Mailer: git-send-email 2.10.1.613.g2cc2e70 In-Reply-To: <20200717094935.9337-1-somnath.kotur@broadcom.com> References: <20200717094935.9337-1-somnath.kotur@broadcom.com> Subject: [dpdk-dev] [PATCH 14/14] net/bnxt: add debug logs to the TF-ULP layer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding debug logs to the TF-ULP, introducing new debug files for the same Signed-off-by: Somnath Kotur --- drivers/net/bnxt/meson.build | 2 + drivers/net/bnxt/tf_ulp/Makefile | 10 + drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 6 + drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 6 + drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 10 + drivers/net/bnxt/tf_ulp/ulp_mapper.c | 130 ++- drivers/net/bnxt/tf_ulp/ulp_matcher.c | 4 + drivers/net/bnxt/tf_ulp/ulp_port_db.c | 8 +- drivers/net/bnxt/tf_ulp/ulp_template_debug.c | 595 ++++++++++ drivers/net/bnxt/tf_ulp/ulp_template_debug.h | 329 ++++++ drivers/net/bnxt/tf_ulp/ulp_template_debug_proto.h | 72 ++ drivers/net/bnxt/tf_ulp/ulp_tf_debug.c | 1161 ++++++++++++++++++++ drivers/net/bnxt/tf_ulp/ulp_tf_debug.h | 26 + drivers/net/bnxt/tf_ulp/ulp_utils.c | 2 +- 14 files changed, 2325 insertions(+), 36 deletions(-) create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_debug.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_debug.h create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_debug_proto.h create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tf_debug.c create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tf_debug.h diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build index 8529b33..cfe9b7c 100644 --- a/drivers/net/bnxt/meson.build +++ b/drivers/net/bnxt/meson.build @@ -64,6 +64,8 @@ sources = files('bnxt_cpr.c', 'tf_ulp/ulp_port_db.c', 'tf_ulp/ulp_def_rules.c', 'tf_ulp/ulp_fc_mgr.c', + 'tf_ulp/ulp_template_debug.c', + 'tf_ulp/ulp_tf_debug.c', 'rte_pmd_bnxt.c') diff --git a/drivers/net/bnxt/tf_ulp/Makefile b/drivers/net/bnxt/tf_ulp/Makefile index abb6815..4312986 100644 --- a/drivers/net/bnxt/tf_ulp/Makefile +++ b/drivers/net/bnxt/tf_ulp/Makefile @@ -18,3 +18,13 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_flow_db.c SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_port_db.c SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_def_rules.c SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_fc_mgr.c + +SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW_DEBUG) += tf_ulp/ulp_template_debug.c +SRCS-$(CONFIG_RTE_LIBRTE_BNXT_TRUFLOW_DEBUG) += tf_ulp/ulp_tf_debug.c + +# +## Export include files +# +# +SYMLINK-y-include += +SYMLINK-$(CONFIG_RTE_LIBRTE_BNXT_PMD)-include += tf_ulp/ulp_tf_debug.h diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h index f0633f0..3aa358c 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h +++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h @@ -13,6 +13,12 @@ #define BNXT_TF_DBG(lvl, fmt, args...) PMD_DRV_LOG(lvl, fmt, ## args) +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#define BNXT_TF_INF(fmt, args...) PMD_DRV_LOG(INFO, fmt, ## args) +#else +#define BNXT_TF_INF(fmt, args...) +#endif + #define BNXT_ULP_EM_FLOWS 8192 #define BNXT_ULP_1M_FLOWS 1000000 #define BNXT_EEM_RX_GLOBAL_ID_MASK (BNXT_ULP_1M_FLOWS - 1) diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c index 0869231..f9a303f 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c @@ -263,6 +263,12 @@ ulp_eem_tbl_scope_init(struct bnxt *bp) return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(DEBUG, "TableScope=0x%0x %d\n", + params.tbl_scope_id, + params.tbl_scope_id); +#endif + rc = bnxt_ulp_cntxt_tbl_scope_id_set(bp->ulp_ctx, params.tbl_scope_id); if (rc) { BNXT_TF_DBG(ERR, "Unable to set table scope id\n"); diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c index 89fffcf..4d2bb1d 100644 --- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c +++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c @@ -11,6 +11,9 @@ #include "ulp_mapper.h" #include "ulp_fc_mgr.h" #include +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_template_debug_proto.h" +#endif static int32_t bnxt_ulp_flow_validate_args(const struct rte_flow_attr *attr, @@ -130,6 +133,13 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev, if (ret != BNXT_TF_RC_SUCCESS) goto parse_error; +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + /* Dump the rte flow pattern */ + ulp_parser_hdr_info_dump(¶ms); + /* Dump the rte flow action */ + ulp_parser_act_info_dump(¶ms); +#endif + ret = ulp_matcher_pattern_match(¶ms, &class_id); if (ret != BNXT_TF_RC_SUCCESS) goto parse_error; diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index 051a095..ef685ee 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -18,6 +18,11 @@ #include "ulp_mapper.h" #include "tf_util.h" +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_template_debug_proto.h" +#include "ulp_tf_debug.h" +#endif + static struct bnxt_ulp_glb_resource_info * ulp_mapper_glb_resource_info_list_get(uint32_t *num_entries) { @@ -102,7 +107,7 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, rc = tf_alloc_identifier(tfp, &iparms); if (rc) { BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n", - (iparms.dir == TF_DIR_RX) ? "RX" : "TX", + tf_dir_2_str(iparms.dir), iparms.ident_type); return rc; } @@ -120,6 +125,11 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx, tf_free_identifier(tfp, &fparms); return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(DEBUG, "Allocated Glb Res Ident [%s][%d][%d] = 0x%04x\n", + tf_dir_2_str(iparms.dir), + glb_res->glb_regfile_index, iparms.ident_type, iparms.id); +#endif return rc; } @@ -160,8 +170,7 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, rc = tf_alloc_tbl_entry(tfp, &aparms); if (rc) { BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n", - (aparms.dir == TF_DIR_RX) ? "RX" : "TX", - aparms.type); + tf_dir_2_str(aparms.dir), aparms.type); return rc; } @@ -178,6 +187,11 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx, tf_free_tbl_entry(tfp, &free_parms); return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(DEBUG, "Allocated Glb Res Index [%s][%d][%d] = 0x%04x\n", + tf_dir_2_str(aparms.dir), + glb_res->glb_regfile_index, aparms.type, aparms.idx); +#endif return rc; } @@ -484,8 +498,7 @@ ulp_mapper_cache_entry_free(struct bnxt_ulp_context *ulp, if (rc) BNXT_TF_DBG(ERR, "Failed to free tcam [%d][%s][0x%04x] rc=%d\n", table_type, - (res->direction == TF_DIR_RX) ? "RX" : "TX", - tcam_parms.idx, rc); + tf_dir_2_str(res->direction), tcam_parms.idx, rc); /* * Free the identifiers associated with the tcam entry. Entries with @@ -503,7 +516,7 @@ ulp_mapper_cache_entry_free(struct bnxt_ulp_context *ulp, BNXT_TF_DBG(ERR, "Failed to free identifier " "[%d][%s][0x%04x] rc=%d\n", ident_parms.ident_type, - (res->direction == TF_DIR_RX) ? "RX" : "TX", + tf_dir_2_str(res->direction), ident_parms.id, trc); rc = trc; } @@ -625,11 +638,13 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_alloc_identifier(tfp, &iparms); if (rc) { - BNXT_TF_DBG(ERR, "Alloc ident %s:%d failed.\n", - (iparms.dir == TF_DIR_RX) ? "RX" : "TX", - iparms.ident_type); + BNXT_TF_DBG(ERR, "Alloc ident %s: failed.\n", + tf_dir_2_str(iparms.dir)); return rc; } + BNXT_TF_INF("Alloc ident %s:%s.success.\n", + tf_dir_2_str(iparms.dir), + tf_tbl_type_2_str(iparms.ident_type)); id = (uint64_t)tfp_cpu_to_be_64(iparms.id); if (!ulp_regfile_write(parms->regfile, idx, id)) { @@ -662,6 +677,10 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, *val = iparms.id; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + ulp_mapper_ident_field_dump("Ident", ident, tbl, iparms.id); +#endif + return 0; error: @@ -674,7 +693,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms, BNXT_TF_DBG(ERR, "Ident process failed for %s:%s\n", ident->description, - (tbl->direction == TF_DIR_RX) ? "RX" : "TX"); + tf_dir_2_str(tbl->direction)); return rc; } @@ -725,7 +744,7 @@ ulp_mapper_ident_extract(struct bnxt_ulp_mapper_parms *parms, sparms.search_id); return rc; } - BNXT_TF_DBG(INFO, "Search ident %s:%x.success.\n", + BNXT_TF_INF("Search ident %s:%x.success.\n", tf_dir_2_str(sparms.dir), sparms.search_id); @@ -782,6 +801,9 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, { uint16_t idx, size_idx; uint8_t *val = NULL; +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + uint16_t write_idx = blob->write_idx; +#endif uint64_t regval; uint32_t val_size = 0, field_size = 0; uint64_t act_bit; @@ -1006,6 +1028,11 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms, fld->result_opcode); return -EINVAL; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + if (fld->result_opcode != BNXT_ULP_MAPPER_OPC_SET_TO_ZERO) + ulp_mapper_result_field_dump(name, fld, blob, + write_idx, val, val_size); +#endif return 0; } @@ -1140,6 +1167,10 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms, return -EINVAL; break; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + if (opcode != BNXT_ULP_MAPPER_OPC_SET_TO_ZERO) + ulp_mapper_key_fld_dump(name, fld, blob, val); +#endif return 0; } @@ -1452,12 +1483,14 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_tcam_entry(tfp, &sparms); if (rc) { - BNXT_TF_DBG(ERR, "tcam[%d][%s][%d] write failed.\n", - sparms.tcam_tbl_type, - (sparms.dir == TF_DIR_RX) ? "RX" : "TX", - sparms.idx); + BNXT_TF_DBG(ERR, "tcam[%s][%s][%x] write failed.\n", + tf_tcam_tbl_2_str(sparms.tcam_tbl_type), + tf_dir_2_str(sparms.dir), sparms.idx); goto error; } + BNXT_TF_INF("tcam[%s][%s][%x] write success.\n", + tf_tcam_tbl_2_str(sparms.tcam_tbl_type), + tf_dir_2_str(sparms.dir), sparms.idx); /* Update cache with TCAM index if the was cache allocated. */ if (parms->tcam_tbl_opc == @@ -1475,6 +1508,10 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, if (rc) goto error; +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + ulp_mapper_tcam_entry_dump("TCAM", aparms.idx, tbl, + &key, &mask, &data); +#endif } else { struct bnxt_ulp_mapper_ident_info *idents; uint32_t num_idents; @@ -1611,6 +1648,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + ulp_mapper_result_dump("EEM Result", tbl, &data); +#endif /* do the transpose for the internal EM keys */ if (tbl->resource_func == BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) @@ -1641,6 +1681,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms, return rc; } +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + ulp_mapper_em_dump("EM", &key, &data, &iparms); + /* tf_dump_tables(tfp, iparms.tbl_scope_id); */ +#endif /* Mark action process */ if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT && tbl->resource_type == TF_MEM_EXTERNAL) @@ -1761,6 +1805,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* if encap bit swap is enabled perform the bit swap */ if (parms->device_params->encap_byte_swap && encap_flds) { ulp_blob_perform_encap_swap(&data); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(INFO, "Dump after encap swap\n"); + ulp_mapper_blob_dump(&data); +#endif } /* @@ -1790,13 +1838,15 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_tbl_entry(tfp, &sparms); if (rc) { BNXT_TF_DBG(ERR, - "Glbl Set table[%d][%s][%d] failed rc=%d\n", - sparms.type, - (sparms.dir == TF_DIR_RX) ? "RX" : "TX", - sparms.idx, - rc); + "Glbl Index table[%s][%s][%x] failed rc=%d\n", + tf_tbl_type_2_str(sparms.type), + tf_dir_2_str(sparms.dir), + sparms.idx, rc); return rc; } + BNXT_TF_INF("Glbl Index table[%s][%s][%x] success.\n", + tf_tbl_type_2_str(sparms.type), + tf_dir_2_str(sparms.dir), sparms.idx); return 0; /* success */ } @@ -1811,10 +1861,9 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* All failures after the alloc succeeds require a free */ rc = tf_alloc_tbl_entry(tfp, &aparms); if (rc) { - BNXT_TF_DBG(ERR, "Alloc table[%d][%s] failed rc=%d\n", - aparms.type, - (aparms.dir == TF_DIR_RX) ? "RX" : "TX", - rc); + BNXT_TF_DBG(ERR, "Alloc table[%s][%s] failed rc=%d\n", + tf_tbl_type_2_str(aparms.type), + tf_dir_2_str(aparms.dir), rc); return rc; } @@ -1850,13 +1899,15 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_tbl_entry(tfp, &sparms); if (rc) { - BNXT_TF_DBG(ERR, "Set table[%d][%s][%d] failed rc=%d\n", - sparms.type, - (sparms.dir == TF_DIR_RX) ? "RX" : "TX", - sparms.idx, - rc); + BNXT_TF_DBG(ERR, "Set table[%s][%s][%x] failed rc=%d\n", + tf_tbl_type_2_str(sparms.type), + tf_dir_2_str(sparms.dir), + sparms.idx, rc); goto error; } + BNXT_TF_INF("Index set table[%s][%s][%x] passed\n", + tf_tbl_type_2_str(sparms.type), + tf_dir_2_str(sparms.dir), sparms.idx); } /* Link the resource to the flow in the flow db */ @@ -1960,6 +2011,9 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms, (tbl->resource_sub_type << 1 | (tbl->direction & 0x1)), *ckey); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + BNXT_TF_DBG(DEBUG, "The cache key is (0x%04x)\n", *ckey); +#endif /* * Get the identifier list for processing by both the hit and miss @@ -2005,6 +2059,11 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms, "Failed to write to regfile\n"); return -EINVAL; } + BNXT_TF_INF("Ident [%s]:[%s]:[0x%04x]:%x\n", + tf_dir_2_str(tbl->direction), + tf_ident_2_str(idents[i].ident_type), + cache_entry->tcam_idx, + cache_entry->idents[i]); } /* * The cached entry is being used, so let the tcam processing @@ -2120,13 +2179,16 @@ ulp_mapper_if_tbl_process(struct bnxt_ulp_mapper_parms *parms, rc = tf_set_if_tbl_entry(tfp, &iftbl_params); if (rc) { - BNXT_TF_DBG(ERR, "Set table[%d][%s][%d] failed rc=%d\n", - iftbl_params.type, - (iftbl_params.dir == TF_DIR_RX) ? "RX" : "TX", - iftbl_params.idx, - rc); + BNXT_TF_DBG(ERR, "Set table[%d][%s][%x] failed rc=%d\n", + iftbl_params.type,/* TBD: add tf_if_tbl_2_str */ + tf_dir_2_str(iftbl_params.dir), + iftbl_params.idx, rc); return rc; } + BNXT_TF_INF("Set table[%s][%s][%x] success.\n", + tf_if_tbl_2_str(iftbl_params.type), + tf_dir_2_str(iftbl_params.dir), + iftbl_params.idx); /* * TBD: Need to look at the need to store idx in flow db for restore diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c index 9112647..b87705a 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c +++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c @@ -6,6 +6,10 @@ #include "ulp_matcher.h" #include "ulp_utils.h" +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_template_debug_proto.h" +#endif + /* Utility function to calculate the class matcher hash */ static uint32_t ulp_matcher_class_hash_calculate(uint64_t hi_sig, uint64_t lo_sig) diff --git a/drivers/net/bnxt/tf_ulp/ulp_port_db.c b/drivers/net/bnxt/tf_ulp/ulp_port_db.c index 0fc7c0a..eee2860 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_port_db.c +++ b/drivers/net/bnxt/tf_ulp/ulp_port_db.c @@ -9,6 +9,10 @@ #include "bnxt_tf_common.h" #include "ulp_port_db.h" +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "ulp_tf_debug.h" +#endif + static uint32_t ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db) { @@ -193,7 +197,9 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt, port_data->port_vport = bnxt_get_vport(port_id); port_data->port_valid = true; } - +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + ulp_port_db_dump(port_db, intf, port_id); +#endif return 0; } diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_debug.c b/drivers/net/bnxt/tf_ulp/ulp_template_debug.c new file mode 100644 index 0000000..5f07bef --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_template_debug.c @@ -0,0 +1,595 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2019 Broadcom + * All rights reserved. + */ + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +#include "bnxt.h" +#include "ulp_utils.h" +#include "ulp_template_db_enum.h" +#include "ulp_template_struct.h" +#include "ulp_template_debug.h" +#include "ulp_template_debug_proto.h" +#include "bnxt_tf_common.h" + +/* #define RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_DETAIL 1 */ + +const char *ulp_rte_hdr_comp_field_names[] = { + "BNXT_ULP_CF_IDX_NOT_USED", + "BNXT_ULP_CF_IDX_MPLS_TAG_NUM", + "BNXT_ULP_CF_IDX_O_VTAG_NUM", + "BNXT_ULP_CF_IDX_O_NO_VTAG", + "BNXT_ULP_CF_IDX_O_ONE_VTAG", + "BNXT_ULP_CF_IDX_O_TWO_VTAGS", + "BNXT_ULP_CF_IDX_I_VTAG_NUM", + "BNXT_ULP_CF_IDX_I_NO_VTAG", + "BNXT_ULP_CF_IDX_I_ONE_VTAG", + "BNXT_ULP_CF_IDX_I_TWO_VTAGS", + "BNXT_ULP_CF_IDX_INCOMING_IF", + "BNXT_ULP_CF_IDX_DIRECTION", + "BNXT_ULP_CF_IDX_SVIF_FLAG", + "BNXT_ULP_CF_IDX_O_L3", + "BNXT_ULP_CF_IDX_I_L3", + "BNXT_ULP_CF_IDX_O_L4", + "BNXT_ULP_CF_IDX_I_L4", + "BNXT_ULP_CF_IDX_DEV_PORT_ID", + "BNXT_ULP_CF_IDX_PMD_FUNC_SVIF", + "BNXT_ULP_CF_IDX_PMD_FUNC_SPIF", + "BNXT_ULP_CF_IDX_PMD_FUNC_PARIF", + "BNXT_ULP_CF_IDX_PMD_FUNC_VNIC", + "BNXT_ULP_CF_IDX_PMD_FUNC_PHY_PORT", + "BNXT_ULP_CF_IDX_VF_FUNC_SVIF", + "BNXT_ULP_CF_IDX_VF_FUNC_SPIF", + "BNXT_ULP_CF_IDX_VF_FUNC_PARIF", + "BNXT_ULP_CF_IDX_VF_FUNC_VNIC", + "BNXT_ULP_CF_IDX_PHY_PORT_SVIF", + "BNXT_ULP_CF_IDX_PHY_PORT_SPIF", + "BNXT_ULP_CF_IDX_PHY_PORT_PARIF", + "BNXT_ULP_CF_IDX_PHY_PORT_VPORT", + "BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG", + "BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG", + "BNXT_ULP_CF_IDX_ACT_DEC_TTL", + "BNXT_ULP_CF_IDX_ACT_T_DEC_TTL", + "BNXT_ULP_CF_IDX_ACT_PORT_IS_SET", + "BNXT_ULP_CF_IDX_ACT_PORT_TYPE", + "BNXT_ULP_CF_IDX_MATCH_PORT_TYPE", + "BNXT_ULP_CF_IDX_VF_TO_VF", + "BNXT_ULP_CF_IDX_LAST" +}; + +const char *ulp_rte_hdr_svif_names[] = { + "SVIF", +}; + +const char *ulp_rte_hdr_eth_field_names[] = { + "Dst Mac", + "Src Mac", + "Ether Type", +}; + +const char *ulp_rte_hdr_vlan_field_names[] = { + "Priority", + "Vlan Id", + "Vlan-Ether Type", +}; + +const char *ulp_rte_hdr_ipv4_field_names[] = { + "Version", + "Type of Service", + "Length", + "Fragment Id", + "Fragment Offset", + "TTL", + "Next Proto", + "Checksum", + "Src Addr", + "Dst Addr" +}; + +const char *ulp_rte_hdr_ipv6_field_names[] = { + "Flow", + "Length", + "Proto", + "Hop limits", + "Src Addr", + "Dst Addr" +}; + +const char *ulp_rte_hdr_udp_field_names[] = { + "Src Port", + "Dst Port", + "Length", + "Checksum" +}; + +const char *ulp_rte_hdr_vxlan_field_names[] = { + "Vxlan Flags", + "Reserved", + "VNI", + "Reserved" +}; + +const char *ulp_rte_hdr_tcp_field_names[] = { + "Src Port", + "Dst Port", + "Sent Seq", + "Recv Ack", + "Data Offset", + "Tcp flags", + "Rx Window", + "Checksum", + "URP", +}; + +/* Utility Function to dump a simple buffer of a given length. */ +static void dump_hex(uint8_t *ptr, uint32_t size) +{ + uint32_t i; + uint8_t lbuffer[1024]; + uint8_t *lbuffer_ptr = lbuffer; + int32_t ret; + + memset(lbuffer, 0, sizeof(lbuffer)); + ret = sprintf((char *)lbuffer_ptr, "\t\t\t"); + lbuffer_ptr += ret; + for (i = 0; i < size; i++, ptr++) { + if (i && !(i % 16)) { + ret = sprintf((char *)lbuffer_ptr, "\t\t\t\t"); + lbuffer_ptr += ret; + } + ret = sprintf((char *)lbuffer_ptr, "0x%02x ", *ptr); + lbuffer_ptr += ret; + if ((i & 0x0F) == 0x0F) { + ret = sprintf((char *)lbuffer_ptr, "\n"); + lbuffer_ptr += ret; + } + } + if (size & 0x0F) + sprintf((char *)lbuffer_ptr, "\n"); + BNXT_TF_DBG(DEBUG, "%s", lbuffer); +} + +/* Utility Function to dump the computed field properties */ +static void +ulp_parser_comp_field_dump(struct ulp_rte_parser_params *params, + const char *field_names[], + uint32_t count_list) +{ + uint32_t idx = 0; + + BNXT_TF_DBG(DEBUG, "Default computed fields\n"); + for (idx = 0; idx < count_list; idx++) { + BNXT_TF_DBG(DEBUG, "\t%s =\n", field_names[idx]); + dump_hex((uint8_t *)¶ms->comp_fld[idx], sizeof(uint32_t)); + } +} + +/* Utility Function to dump the field properties.*/ +static void +ulp_parser_field_dump(struct ulp_rte_hdr_field *hdr_field, + const char *field_names[], + uint32_t start_idx, + uint32_t count_list) +{ + uint32_t f_idx = 0, idx = 0; + + for (f_idx = start_idx; f_idx < (start_idx + count_list); f_idx++) { + if (hdr_field[f_idx].size) { + BNXT_TF_DBG(DEBUG, "\t%s =\n", field_names[idx]); + dump_hex(hdr_field[f_idx].spec, hdr_field[f_idx].size); + dump_hex(hdr_field[f_idx].mask, hdr_field[f_idx].size); + } + idx++; + } +} + +/* Utility Function to dump the field properties.*/ +static inline void +ulp_parser_vlan_dump(struct ulp_rte_hdr_field *hdr_field, + uint32_t f_idx) +{ + ulp_parser_field_dump(hdr_field, ulp_rte_hdr_vlan_field_names, + f_idx, BNXT_ULP_PROTO_HDR_S_VLAN_NUM); +} + +/* Function to dump the Pattern header bitmaps and fields. */ +void +ulp_parser_hdr_info_dump(struct ulp_rte_parser_params *params) +{ + uint32_t idx = 0, f_idx = 0; + uint32_t num_idx; + uint64_t hdr_bit; + struct ulp_rte_hdr_bitmap *hdr_bitmap = ¶ms->hdr_bitmap; + struct ulp_rte_hdr_field *hdr_field = params->hdr_field; + + BNXT_TF_DBG(DEBUG, "Configured Header Protocols for matching\n"); + if (ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_FLOW_DIR_BITMASK_EGR)) + BNXT_TF_DBG(DEBUG, "It is a Egress Flow - %x\n", + params->dir_attr); + else + BNXT_TF_DBG(DEBUG, "It is a Ingress Flow - %x\n", + params->dir_attr); + ulp_parser_comp_field_dump(params, ulp_rte_hdr_comp_field_names, + BNXT_ULP_CF_IDX_LAST); + + num_idx = sizeof(bnxt_ulp_hdr_bit_names) / + sizeof(bnxt_ulp_hdr_bit_names[0]); + + /* Print the svif details, there is no bitmap for this field */ + ulp_parser_field_dump(hdr_field, ulp_rte_hdr_svif_names, f_idx, + BNXT_ULP_PROTO_HDR_SVIF_NUM); + f_idx += BNXT_ULP_PROTO_HDR_SVIF_NUM; + + for (idx = 0; idx < num_idx; idx++) { + hdr_bit = 1UL << idx; + if (!ULP_BITMAP_ISSET(hdr_bitmap->bits, hdr_bit)) { + if (ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_OO_VLAN) || + ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_OI_VLAN) || + ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_IO_VLAN) || + ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_II_VLAN)) { + f_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; + } + continue; + } + + BNXT_TF_DBG(DEBUG, "%s\n", bnxt_ulp_hdr_bit_names[idx]); + if (ULP_BITMAP_ISSET(hdr_bit, BNXT_ULP_HDR_BIT_O_ETH)) { + ulp_parser_field_dump(hdr_field, + ulp_rte_hdr_eth_field_names, + f_idx, + BNXT_ULP_PROTO_HDR_ETH_NUM); + f_idx += BNXT_ULP_PROTO_HDR_ETH_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, BNXT_ULP_HDR_BIT_I_ETH)) { + ulp_parser_field_dump(hdr_field, + ulp_rte_hdr_eth_field_names, + f_idx, + BNXT_ULP_PROTO_HDR_ETH_NUM); + f_idx += BNXT_ULP_PROTO_HDR_ETH_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_OO_VLAN)) { + ulp_parser_vlan_dump(hdr_field, f_idx); + f_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_OI_VLAN)) { + ulp_parser_vlan_dump(hdr_field, f_idx); + f_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_IO_VLAN)) { + ulp_parser_vlan_dump(hdr_field, f_idx); + f_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_II_VLAN)) { + ulp_parser_vlan_dump(hdr_field, f_idx); + f_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, BNXT_ULP_HDR_BIT_O_IPV4)) { + ulp_parser_field_dump(hdr_field, + ulp_rte_hdr_ipv4_field_names, + f_idx, + BNXT_ULP_PROTO_HDR_IPV4_NUM); + f_idx += BNXT_ULP_PROTO_HDR_IPV4_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, BNXT_ULP_HDR_BIT_O_IPV6)) { + ulp_parser_field_dump(hdr_field, + ulp_rte_hdr_ipv6_field_names, + f_idx, + BNXT_ULP_PROTO_HDR_IPV6_NUM); + f_idx += BNXT_ULP_PROTO_HDR_IPV6_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, BNXT_ULP_HDR_BIT_O_UDP)) { + ulp_parser_field_dump(hdr_field, + ulp_rte_hdr_udp_field_names, + f_idx, + BNXT_ULP_PROTO_HDR_UDP_NUM); + f_idx += BNXT_ULP_PROTO_HDR_UDP_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, BNXT_ULP_HDR_BIT_O_TCP)) { + ulp_parser_field_dump(hdr_field, + ulp_rte_hdr_tcp_field_names, + f_idx, + BNXT_ULP_PROTO_HDR_TCP_NUM); + f_idx += BNXT_ULP_PROTO_HDR_TCP_NUM; + } else if (ULP_BITMAP_ISSET(hdr_bit, + BNXT_ULP_HDR_BIT_T_VXLAN)) { + ulp_parser_field_dump(hdr_field, + ulp_rte_hdr_vxlan_field_names, + f_idx, + BNXT_ULP_PROTO_HDR_VXLAN_NUM); + f_idx += BNXT_ULP_PROTO_HDR_VXLAN_NUM; + } + } + BNXT_TF_DBG(DEBUG, "******************************************\n"); +} + +static void +ulp_parser_action_prop_dump(struct ulp_rte_act_prop *act_prop, + uint32_t start_idx, + uint32_t dump_size) +{ + BNXT_TF_DBG(DEBUG, "\t%s =\n", + bnxt_ulp_rte_parser_action_prop_names[start_idx]); + dump_hex(&act_prop->act_details[start_idx], dump_size); +} + +/* Function to dump the Action header bitmaps and properties. */ +void +ulp_parser_act_info_dump(struct ulp_rte_parser_params *params) +{ + uint32_t idx = 0; + uint32_t num_idx = 0; + uint64_t act_bit; + struct ulp_rte_act_bitmap *act_bitmap = ¶ms->act_bitmap; + struct ulp_rte_act_prop *act_prop = ¶ms->act_prop; + + BNXT_TF_DBG(DEBUG, "Configured actions for matching\n"); + BNXT_TF_DBG(DEBUG, "Default computed fields\n"); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ, + BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ, + BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ, + BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE, + BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM, + BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE, + BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_VNIC, + BNXT_ULP_ACT_PROP_SZ_VNIC); + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_VPORT, + BNXT_ULP_ACT_PROP_SZ_VPORT); + + num_idx = sizeof(bnxt_ulp_action_bit_names) / + sizeof(bnxt_ulp_action_bit_names[0]); + + for (idx = 0; idx < num_idx; idx++) { + enum bnxt_ulp_act_prop_idx tmp_act_p; + enum bnxt_ulp_act_prop_sz tmp_act_sz; + + act_bit = 1UL << idx; + if (!ULP_BITMAP_ISSET(act_bitmap->bits, act_bit)) + continue; + + BNXT_TF_DBG(DEBUG, "%s\n", bnxt_ulp_action_bit_names[idx]); + if (ULP_BITMAP_ISSET(act_bit, BNXT_ULP_ACTION_BIT_MARK)) { + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_MARK, + BNXT_ULP_ACT_PROP_SZ_MARK); + } else if (ULP_BITMAP_ISSET(act_bit, + BNXT_ULP_ACTION_BIT_VXLAN_ENCAP)) { + tmp_act_p = BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC; + tmp_act_sz = BNXT_ULP_ACT_PROP_IDX_LAST - + BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC; + printf("size %d and %d\n", tmp_act_p, tmp_act_sz); + ulp_parser_action_prop_dump(act_prop, tmp_act_p, + tmp_act_sz); + } else if (ULP_BITMAP_ISSET(act_bit, + BNXT_ULP_ACTION_BIT_COUNT)) { + ulp_parser_action_prop_dump(act_prop, + BNXT_ULP_ACT_PROP_IDX_COUNT, + BNXT_ULP_ACT_PROP_SZ_COUNT); + } else if (ULP_BITMAP_ISSET(act_bit, + BNXT_ULP_ACTION_BIT_PUSH_VLAN)) { + tmp_act_p = BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN; + tmp_act_sz = BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN; + ulp_parser_action_prop_dump(act_prop, + tmp_act_p, + tmp_act_sz); + } else if (ULP_BITMAP_ISSET(act_bit, + BNXT_ULP_ACTION_BIT_SET_IPV4_SRC)) { + tmp_act_p = BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC; + tmp_act_sz = BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC; + ulp_parser_action_prop_dump(act_prop, + tmp_act_p, + tmp_act_sz); + } else if (ULP_BITMAP_ISSET(act_bit, + BNXT_ULP_ACTION_BIT_SET_IPV4_DST)) { + tmp_act_p = BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST; + tmp_act_sz = BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST; + ulp_parser_action_prop_dump(act_prop, + tmp_act_p, + tmp_act_sz); + } else if (ULP_BITMAP_ISSET(act_bit, + BNXT_ULP_ACTION_BIT_SET_TP_SRC)) { + tmp_act_p = BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC; + tmp_act_sz = BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC; + ulp_parser_action_prop_dump(act_prop, + tmp_act_p, + tmp_act_sz); + } else if (ULP_BITMAP_ISSET(act_bit, + BNXT_ULP_ACTION_BIT_SET_TP_DST)) { + tmp_act_p = BNXT_ULP_ACT_PROP_IDX_SET_TP_DST; + tmp_act_sz = BNXT_ULP_ACT_PROP_SZ_SET_TP_DST; + ulp_parser_action_prop_dump(act_prop, + tmp_act_p, + tmp_act_sz); + } + } + BNXT_TF_DBG(DEBUG, "******************************************\n"); +} + +/* Function to dump the error field during matching. */ +void +ulp_matcher_act_field_dump(uint32_t idx, + uint32_t jdx, + uint32_t mask_id) +{ + BNXT_TF_DBG(DEBUG, "Match failed template=%d,field=%s,mask=%s\n", + idx, + bnxt_ulp_rte_template_field_names[(jdx + + (idx + 1) * 1)], + bnxt_ulp_flow_matcher_field_mask_opcode_names[mask_id]); +} + +/* Function to dump the blob during the mapper processing. */ +void +ulp_mapper_result_field_dump(const char *name, + struct bnxt_ulp_mapper_result_field_info *fld, + struct ulp_blob *blob, + uint16_t write_idx, + uint8_t *val, + uint32_t field_size) +{ + uint32_t len = 0, slen = 0; + uint8_t lbuffer[64]; + uint8_t *lbuffer_ptr = lbuffer; + uint32_t ret = 0, idx = 0; + uint32_t p_size; + + if (!val || !blob) + return; + + if (fld->result_opcode == BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ) + slen = field_size; + else + slen = fld->field_bit_size; + + if (slen % 8) + len = (slen / 8) + 1; + else + len = (slen / 8); + + memset(lbuffer, 0, sizeof(lbuffer)); + while (len > 0 && idx < 32) { + ret = sprintf((char *)lbuffer_ptr, "%02x", val[idx]); + lbuffer_ptr += ret; + len--; + idx++; + } + + BNXT_TF_DBG(DEBUG, + "%-16s %-20s, bits = %-3d and pos = %-3d val = 0x%s\n", + name, fld->description, slen, write_idx, lbuffer); + p_size = (write_idx + slen + 7) / 8; + dump_hex((uint8_t *)blob->data, p_size); +} + +/* Function to dump the blob during the mapper processing. */ +void +ulp_mapper_key_fld_dump(const char *name, + struct bnxt_ulp_mapper_class_key_field_info *fld, + struct ulp_blob *blob, + uint8_t *val) +{ + uint32_t len = fld->field_bit_size / 8; + uint8_t lbuffer[64]; + uint8_t *lbuffer_ptr = lbuffer; + uint32_t ret = 0, idx = 0; + + if (!val) + return; + + /* The value was already written, so calculate the write_idx. */ + uint16_t write_idx = blob->write_idx - fld->field_bit_size; + + if (fld->field_bit_size % 8) + len++; + + memset(lbuffer, 0, sizeof(lbuffer)); + while (len > 0 && idx < 32) { + ret = sprintf((char *)lbuffer_ptr, "%02x", val[idx]); + lbuffer_ptr += ret; + len--; + idx++; + } + + BNXT_TF_DBG(DEBUG, "%-16s %-20s, bits = %-3d pos = %-3d val = 0x%s\n", + name, fld->description, fld->field_bit_size, + write_idx, lbuffer); +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG_DETAIL + dump_hex((uint8_t *)blob->data, 16); +#endif +} + +void +ulp_mapper_ident_field_dump(const char *name, + struct bnxt_ulp_mapper_ident_info *ident, + struct bnxt_ulp_mapper_tbl_info *tbl, + int32_t id) +{ + BNXT_TF_DBG(DEBUG, "%-16s alloc %-16s, dir= %s, id = 0x%x\n", + name, ident->description, + (tbl->direction == TF_DIR_RX) ? "RX" : "TX", id); +} + +void +ulp_mapper_tcam_entry_dump(const char *name, + uint32_t idx, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_blob *key, + struct ulp_blob *mask, + struct ulp_blob *result) +{ + BNXT_TF_DBG(DEBUG, "%-16s [%s][0x%0x],keysz=%-3d resultsz=%-3d\n", + name, + (tbl->direction == TF_DIR_RX) ? "RX" : "TX", + idx, key->write_idx, result->write_idx); + dump_hex((uint8_t *)key->data, (key->bitlen + 7) / 8); + dump_hex((uint8_t *)mask->data, (key->bitlen + 7) / 8); + dump_hex((uint8_t *)result->data, (key->bitlen + 7) / 8); +} + +void +ulp_mapper_result_dump(const char *name, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_blob *result) +{ + BNXT_TF_DBG(DEBUG, "%-16s [%s], bitlen=%-3d\n", + name, + (tbl->direction == TF_DIR_RX) ? "RX" : "TX", + result->write_idx); + dump_hex((uint8_t *)result->data, (result->bitlen + 7) / 8); +} + +void +ulp_mapper_act_dump(const char *name, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_blob *data) +{ + BNXT_TF_DBG(DEBUG, "%-16s [%s], bitlen=%-3d\n", + name, + (tbl->direction == TF_DIR_RX) ? "RX" : "TX", + data->write_idx); + dump_hex((uint8_t *)data->data, (data->bitlen + 7) / 8); +} + +void +ulp_mapper_em_dump(const char *name, + struct ulp_blob *key, + struct ulp_blob *data, + struct tf_insert_em_entry_parms *iparms) +{ + BNXT_TF_DBG(DEBUG, "%s ins %s[%s] scope=0x%02x keysz=%d recsz=%d\n", + name, + (iparms->mem == TF_MEM_EXTERNAL) ? "EXT" : "INT", + (iparms->dir == TF_DIR_RX) ? "RX" : "TX", + iparms->tbl_scope_id, + iparms->key_sz_in_bits, + iparms->em_record_sz_in_bits); + + BNXT_TF_DBG(DEBUG, "FlowHdl=0x%016" PRIx64 " FlowID=0x%016" PRIx64 "\n", + iparms->flow_handle, iparms->flow_id); + + BNXT_TF_DBG(DEBUG, "Key Size %d, Data Size %d\n", + key->write_idx, data->write_idx); + + dump_hex(iparms->key, (key->write_idx + 7) / 8); + dump_hex(iparms->em_record, (data->write_idx + 7) / 8); +} + +void +ulp_mapper_blob_dump(struct ulp_blob *blob) +{ + dump_hex(blob->data, (blob->write_idx + 7) / 8); +} + +#endif /* RTE_LIBRTE_BNXT_TRUFLOW_DEBUG */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_debug.h b/drivers/net/bnxt/tf_ulp/ulp_template_debug.h new file mode 100644 index 0000000..706562b --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_template_debug.h @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2019 Broadcom + * All rights reserved. + */ + +#ifndef ULP_TEMPLATE_DEBUG_H_ +#define ULP_TEMPLATE_DEBUG_H_ + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + +/* + * THIS FILE IS AUTOGENERATED AND MUST NOT BE MODIFIED WITHOUT FEEDING BACK + * TO THE TEMPLATE COMPILER. + */ + +const char *bnxt_ulp_hdr_bit_names[] = { + "BNXT_ULP_HDR_BIT_O_ETH", + "BNXT_ULP_HDR_BIT_OO_VLAN", + "BNXT_ULP_HDR_BIT_OI_VLAN", + "BNXT_ULP_HDR_BIT_O_IPV4", + "BNXT_ULP_HDR_BIT_O_IPV6", + "BNXT_ULP_HDR_BIT_O_TCP", + "BNXT_ULP_HDR_BIT_O_UDP", + "BNXT_ULP_HDR_BIT_T_VXLAN", + "BNXT_ULP_HDR_BIT_T_GRE", + "BNXT_ULP_HDR_BIT_I_ETH", + "BNXT_ULP_HDR_BIT_IO_VLAN", + "BNXT_ULP_HDR_BIT_II_VLAN", + "BNXT_ULP_HDR_BIT_I_IPV4", + "BNXT_ULP_HDR_BIT_I_IPV6", + "BNXT_ULP_HDR_BIT_I_TCP", + "BNXT_ULP_HDR_BIT_I_UDP", + "BNXT_ULP_HDR_PROTO_LAST", +}; + +const char *bnxt_ulp_action_bit_names[] = { + "BNXT_ULP_ACTION_BIT_MARK", + "BNXT_ULP_ACTION_BIT_DROP", + "BNXT_ULP_ACTION_BIT_COUNT", + "BNXT_ULP_ACTION_BIT_RSS", + "BNXT_ULP_ACTION_BIT_METER", + "BNXT_ULP_ACTION_BIT_VXLAN_DECAP", + "BNXT_ULP_ACTION_BIT_NVGRE_DECAP", + "BNXT_ULP_ACTION_BIT_OF_POP_MPLS", + "BNXT_ULP_ACTION_BIT_OF_PUSH_MPLS", + "BNXT_ULP_ACTION_BIT_MAC_SWAP", + "BNXT_ULP_ACTION_BIT_SET_MAC_SRC", + "BNXT_ULP_ACTION_BIT_SET_MAC_DST", + "BNXT_ULP_ACTION_BIT_POP_VLAN", + "BNXT_ULP_ACTION_BIT_PUSH_VLAN", + "BNXT_ULP_ACTION_BIT_SET_VLAN_PCP", + "BNXT_ULP_ACTION_BIT_SET_VLAN_VID", + "BNXT_ULP_ACTION_BIT_SET_IPV4_SRC", + "BNXT_ULP_ACTION_BIT_SET_IPV4_DST", + "BNXT_ULP_ACTION_BIT_SET_IPV6_SRC", + "BNXT_ULP_ACTION_BIT_SET_IPV6_DST", + "BNXT_ULP_ACTION_BIT_DEC_TTL", + "BNXT_ULP_ACTION_BIT_SET_TP_SRC", + "BNXT_ULP_ACTION_BIT_SET_TP_DST", + "BNXT_ULP_ACTION_BIT_VXLAN_ENCAP", + "BNXT_ULP_ACTION_BIT_NVGRE_ENCAP", + "BNXT_ULP_ACTION_BIT_LAST" +}; + +const char *bnxt_ulp_rte_parser_action_prop_names[] = { + [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE", + [BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] = + "BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM", + [BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] = + "BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM", + [BNXT_ULP_ACT_PROP_IDX_PORT_ID] = + "BNXT_ULP_ACT_PROP_IDX_PORT_ID", + [BNXT_ULP_ACT_PROP_IDX_VNIC] = + "BNXT_ULP_ACT_PROP_IDX_VNIC", + [BNXT_ULP_ACT_PROP_IDX_VPORT] = + "BNXT_ULP_ACT_PROP_IDX_VPORT", + [BNXT_ULP_ACT_PROP_IDX_MARK] = + "BNXT_ULP_ACT_PROP_IDX_MARK", + [BNXT_ULP_ACT_PROP_IDX_COUNT] = + "BNXT_ULP_ACT_PROP_IDX_COUNT", + [BNXT_ULP_ACT_PROP_IDX_METER] = + "BNXT_ULP_ACT_PROP_IDX_METER", + [BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] = + "BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC", + [BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] = + "BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST", + [BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN] = + "BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN", + [BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP] = + "BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP", + [BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID] = + "BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID", + [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] = + "BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC", + [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] = + "BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST", + [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] = + "BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC", + [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] = + "BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST", + [BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] = + "BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC", + [BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] = + "BNXT_ULP_ACT_PROP_IDX_SET_TP_DST", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6", + [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] = + "BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_IP", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP", + [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] = + "BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN", + [BNXT_ULP_ACT_PROP_IDX_LAST] = + "BNXT_ULP_ACT_PROP_IDX_LAST" +}; + +const char *bnxt_ulp_flow_matcher_field_mask_opcode_names[] = { + "MASK_IGNORE", + "MASK_ANY", + "MASK_EXACT", + "MASK_WC", + "MASK_LAST", +}; + +const char *bnxt_ulp_rte_template_field_names[] = { + /* Ingress Template 0 */ + "BNXT_ULP_HF0_SVIF_INDEX", + "BNXT_ULP_HF0_O_ETH_DMAC", + "BNXT_ULP_HF0_O_ETH_SMAC", + "BNXT_ULP_HF0_O_ETH_TYPE", + "BNXT_ULP_HF0_OO_VLAN_CFI_PRI", + "BNXT_ULP_HF0_OO_VLAN_VID", + "BNXT_ULP_HF0_OO_VLAN_TYPE", + "BNXT_ULP_HF0_OI_VLAN_CFI_PRI", + "BNXT_ULP_HF0_OI_VLAN_VID", + "BNXT_ULP_HF0_OI_VLAN_TYPE", + "BNXT_ULP_HF0_O_IPV4_VER", + "BNXT_ULP_HF0_O_IPV4_TOS", + "BNXT_ULP_HF0_O_IPV4_LEN", + "BNXT_ULP_HF0_O_IPV4_FRAG_ID", + "BNXT_ULP_HF0_O_IPV4_FRAG_OFF", + "BNXT_ULP_HF0_O_IPV4_TTL", + "BNXT_ULP_HF0_O_IPV4_NEXT_PID", + "BNXT_ULP_HF0_O_IPV4_CSUM", + "BNXT_ULP_HF0_O_IPV4_SRC_ADDR", + "BNXT_ULP_HF0_O_IPV4_DST_ADDR", + "BNXT_ULP_HF0_O_UDP_SRC_PORT", + "BNXT_ULP_HF0_O_UDP_DST_PORT", + "BNXT_ULP_HF0_O_UDP_LENGTH", + "BNXT_ULP_HF0_O_UDP_CSUM", + "BNXT_ULP_HF0_VXLAN_FLAGS", + "BNXT_ULP_HF0_VXLAN_RSVD0", + "BNXT_ULP_HF0_VXLAN_VNI", + "BNXT_ULP_HF0_VXLAN_RSVD1", + "BNXT_ULP_HF0_I_ETH_DMAC", + "BNXT_ULP_HF0_I_ETH_SMAC", + "BNXT_ULP_HF0_I_ETH_TYPE", + "BNXT_ULP_HF0_IO_VLAN_CFI_PRI", + "BNXT_ULP_HF0_IO_VLAN_VID", + "BNXT_ULP_HF0_IO_VLAN_TYPE", + "BNXT_ULP_HF0_II_VLAN_CFI_PRI", + "BNXT_ULP_HF0_II_VLAN_VID", + "BNXT_ULP_HF0_II_VLAN_TYPE", + "BNXT_ULP_HF0_I_IPV4_VER", + "BNXT_ULP_HF0_I_IPV4_TOS", + "BNXT_ULP_HF0_I_IPV4_LEN", + "BNXT_ULP_HF0_I_IPV4_FRAG_ID", + "BNXT_ULP_HF0_I_IPV4_FRAG_OFF", + "BNXT_ULP_HF0_I_IPV4_TTL", + "BNXT_ULP_HF0_I_IPV4_NEXT_PID", + "BNXT_ULP_HF0_I_IPV4_CSUM", + "BNXT_ULP_HF0_I_IPV4_SRC_ADDR", + "BNXT_ULP_HF0_I_IPV4_DST_ADDR", + "BNXT_ULP_HF0_I_TCP_SRC_PORT", + "BNXT_ULP_HF0_I_TCP_DST_PORT", + "BNXT_ULP_HF0_I_TCP_SENT_SEQ", + "BNXT_ULP_HF0_I_TCP_RECV_ACK", + "BNXT_ULP_HF0_I_TCP_DATA_OFF", + "BNXT_ULP_HF0_I_TCP_TCP_FLAGS", + "BNXT_ULP_HF0_I_TCP_RX_WIN", + "BNXT_ULP_HF0_I_TCP_CSUM", + "BNXT_ULP_HF0_I_TCP_UR", + + /* Ingress template 1 */ + "BNXT_ULP_HF1_MPLS_TAG_NUM", + "BNXT_ULP_HF1_O_VTAG_NUM", + "BNXT_ULP_HF1_I_VTAG_NUM", + "BNXT_ULP_HF1_SVIF_INDEX", + "BNXT_ULP_HF1_O_ETH_DMAC", + "BNXT_ULP_HF1_O_ETH_SMAC", + "BNXT_ULP_HF1_O_ETH_TYPE", + "BNXT_ULP_HF1_O_OVLAN_CFI_PRI", + "BNXT_ULP_HF1_O_OVLAN_VID", + "BNXT_ULP_HF1_O_OVLAN_TYPE", + "BNXT_ULP_HF1_O_IVLAN_CFI_PRI", + "BNXT_ULP_HF1_O_IVLAN_VID", + "BNXT_ULP_HF1_O_IVLAN_TYPE", + "BNXT_ULP_HF1_O_IPV4_VER", + "BNXT_ULP_HF1_O_IPV4_TOS", + "BNXT_ULP_HF1_O_IPV4_LEN", + "BNXT_ULP_HF1_O_IPV4_FRAG_ID", + "BNXT_ULP_HF1_O_IPV4_FRAG_OFF", + "BNXT_ULP_HF1_O_IPV4_TTL", + "BNXT_ULP_HF1_O_IPV4_NEXT_PID", + "BNXT_ULP_HF1_O_IPV4_CSUM", + "BNXT_ULP_HF1_O_IPV4_SRC_ADDR", + "BNXT_ULP_HF1_O_IPV4_DST_ADDR", + "BNXT_ULP_HF1_O_UDP_SRC_PORT", + "BNXT_ULP_HF1_O_UDP_DST_PORT", + "BNXT_ULP_HF1_O_UDP_LENGTH", + "BNXT_ULP_HF1_O_UDP_CSUM", + "BNXT_ULP_HF1_VXLAN_FLAGS", + "BNXT_ULP_HF1_VXLAN_RSVD0", + "BNXT_ULP_HF1_VXLAN_VNI", + "BNXT_ULP_HF1_VXLAN_RSVD1", + "BNXT_ULP_HF1_I_ETH_DMAC", + "BNXT_ULP_HF1_I_ETH_SMAC", + "BNXT_ULP_HF1_I_ETH_TYPE", + "BNXT_ULP_HF1_I_OVLAN_CFI_PRI", + "BNXT_ULP_HF1_I_OVLAN_VID", + "BNXT_ULP_HF1_I_OVLAN_TYPE", + "BNXT_ULP_HF1_I_IVLAN_CFI_PRI", + "BNXT_ULP_HF1_I_IVLAN_VID", + "BNXT_ULP_HF1_I_IVLAN_TYPE", + "BNXT_ULP_HF1_I_IPV4_VER", + "BNXT_ULP_HF1_I_IPV4_TOS", + "BNXT_ULP_HF1_I_IPV4_LEN", + "BNXT_ULP_HF1_I_IPV4_FRAG_ID", + "BNXT_ULP_HF1_I_IPV4_FRAG_OFF", + "BNXT_ULP_HF1_I_IPV4_TTL", + "BNXT_ULP_HF1_I_IPV4_NEXT_PID", + "BNXT_ULP_HF1_I_IPV4_CSUM", + "BNXT_ULP_HF1_I_IPV4_SRC_ADDR", + "BNXT_ULP_HF1_I_IPV4_DST_ADDR", + "BNXT_ULP_HF1_I_UDP_SRC_PORT", + "BNXT_ULP_HF1_I_UDP_DST_PORT", + "BNXT_ULP_HF1_I_UDP_UR", + + /* Egress template 2 */ + "BNXT_ULP_HF2_MPLS_TAG_NUM", + "BNXT_ULP_HF2_O_VTAG_NUM", + "BNXT_ULP_HF2_I_VTAG_NUM", + "BNXT_ULP_HF2_SVIF_INDEX", + "BNXT_ULP_HF2_O_ETH_DMAC", + "BNXT_ULP_HF2_O_ETH_SMAC", + "BNXT_ULP_HF2_O_ETH_TYPE", + "BNXT_ULP_HF2_O_OVLAN_CFI_PRI", + "BNXT_ULP_HF2_O_OVLAN_VID", + "BNXT_ULP_HF2_O_OVLAN_TYPE", + "BNXT_ULP_HF2_O_IVLAN_CFI_PRI", + "BNXT_ULP_HF2_O_IVLAN_VID", + "BNXT_ULP_HF2_O_IVLAN_TYPE", + "BNXT_ULP_HF2_O_IPV4_VER", + "BNXT_ULP_HF2_O_IPV4_TOS", + "BNXT_ULP_HF2_O_IPV4_LEN", + "BNXT_ULP_HF2_O_IPV4_FRAG_ID", + "BNXT_ULP_HF2_O_IPV4_FRAG_OFF", + "BNXT_ULP_HF2_O_IPV4_TTL", + "BNXT_ULP_HF2_O_IPV4_NEXT_PID", + "BNXT_ULP_HF2_O_IPV4_CSUM", + "BNXT_ULP_HF2_O_IPV4_SRC_ADDR", + "BNXT_ULP_HF2_O_IPV4_DST_ADDR", + "BNXT_ULP_HF2_O_UDP_SRC_PORT", + "BNXT_ULP_HF2_O_UDP_DST_PORT", + "BNXT_ULP_HF2_O_UDP_LENGTH", + "BNXT_ULP_HF2_O_UDP_CSUM", + "BNXT_ULP_HF2_VXLAN_FLAGS", + "BNXT_ULP_HF2_VXLAN_RSVD0", + "BNXT_ULP_HF2_VXLAN_VNI", + "BNXT_ULP_HF2_VXLAN_RSVD1", + "BNXT_ULP_HF2_I_ETH_DMAC", + "BNXT_ULP_HF2_I_ETH_SMAC", + "BNXT_ULP_HF2_I_ETH_TYPE", + "BNXT_ULP_HF2_I_OVLAN_CFI_PRI", + "BNXT_ULP_HF2_I_OVLAN_VID", + "BNXT_ULP_HF2_I_OVLAN_TYPE", + "BNXT_ULP_HF2_I_IVLAN_CFI_PRI", + "BNXT_ULP_HF2_I_IVLAN_VID", + "BNXT_ULP_HF2_I_IVLAN_TYPE", + "BNXT_ULP_HF2_I_IPV4_VER", + "BNXT_ULP_HF2_I_IPV4_TOS", + "BNXT_ULP_HF2_I_IPV4_LEN", + "BNXT_ULP_HF2_I_IPV4_FRAG_ID", + "BNXT_ULP_HF2_I_IPV4_FRAG_OFF", + "BNXT_ULP_HF2_I_IPV4_TTL", + "BNXT_ULP_HF2_I_IPV4_NEXT_PID", + "BNXT_ULP_HF2_I_IPV4_CSUM", + "BNXT_ULP_HF2_I_IPV4_SRC_ADDR", + "BNXT_ULP_HF2_I_IPV4_DST_ADDR", + "BNXT_ULP_HF2_I_UDP_SRC_PORT", + "BNXT_ULP_HF2_I_UDP_DST_PORT", + "BNXT_ULP_HF2_I_UDP_UR", +}; + +#endif /* RTE_LIBRTE_BNXT_TRUFLOW_DEBUG */ +#endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_debug_proto.h b/drivers/net/bnxt/tf_ulp/ulp_template_debug_proto.h new file mode 100644 index 0000000..6148f58 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_template_debug_proto.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2019 Broadcom + * All rights reserved. + **/ + +#ifndef ULP_TEMPLATE_DEBUG_PROTO_H_ +#define ULP_TEMPLATE_DEBUG_PROTO_H_ + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + +/* Function to dump the rte flow pattern. */ +void +ulp_parser_hdr_info_dump(struct ulp_rte_parser_params *params); + +/* Function to dump the rte flow actions. */ +void +ulp_parser_act_info_dump(struct ulp_rte_parser_params *params); + +/* Function to dump the error field during matching. */ +void +ulp_matcher_act_field_dump(uint32_t idx, + uint32_t jdx, + uint32_t mask_id); + +/* * Function to dump the blob during the mapper processing. */ +void +ulp_mapper_result_field_dump(const char *name, + struct bnxt_ulp_mapper_result_field_info *fld, + struct ulp_blob *blob, + uint16_t write_idx, + uint8_t *val, + uint32_t field_size); +/* Function to dump the blob during the mapper processing. */ +void +ulp_mapper_key_fld_dump(const char *name, + struct bnxt_ulp_mapper_class_key_field_info *fld, + struct ulp_blob *blob, + uint8_t *val); +/* Function to dump the identifiers during the mapper processing. */ +void +ulp_mapper_ident_field_dump(const char *name, + struct bnxt_ulp_mapper_ident_info *ident, + struct bnxt_ulp_mapper_tbl_info *tbl, + int32_t id); +void +ulp_mapper_tcam_entry_dump(const char *name, + uint32_t idx, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_blob *key, + struct ulp_blob *mask, + struct ulp_blob *result); +void +ulp_mapper_result_dump(const char *name, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_blob *result); + +void +ulp_mapper_act_dump(const char *name, + struct bnxt_ulp_mapper_tbl_info *tbl, + struct ulp_blob *data); + +void +ulp_mapper_em_dump(const char *name, + struct ulp_blob *key, + struct ulp_blob *data, + struct tf_insert_em_entry_parms *iparms); + +void +ulp_mapper_blob_dump(struct ulp_blob *blob); + +#endif /* RTE_LIBRTE_BNXT_TRUFLOW_DEBUG */ +#endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_tf_debug.c b/drivers/net/bnxt/tf_ulp/ulp_tf_debug.c new file mode 100644 index 0000000..79a3611 --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_tf_debug.c @@ -0,0 +1,1161 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2019 Broadcom + * All rights reserved. + */ + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG + +#include "bnxt.h" +#include +#include +#include "ulp_tf_debug.h" +#include "bnxt_tf_common.h" + +/* #define TF_EEM_DEBUG */ +#include "tf_core.h" +#include "tf_em.h" +#include "tf_msg.h" +#include "tfp.h" +#include "tf_ext_flow_handle.h" + +#include "ulp_port_db.h" + +/* Enable EEM table dump. */ +#define TF_EEM_DUMP + +#if 0 // def TF_EEM_DEBUG +static void dump_raw(uint8_t *data, uint32_t size, const char *msg) +{ + uint32_t i; + uint8_t lbuffer[1024]; + uint8_t *lbuffer_ptr = lbuffer; + int32_t ret, amt; + + amt = sizeof(lbuffer) - 1; + + memset(lbuffer, 0, sizeof(lbuffer)); + + ret = snprintf((char *)lbuffer_ptr, amt, "\n%15s:\n", msg); + if (ret >= amt) + goto printit; + lbuffer_ptr += ret; + amt -= ret; + + for (i = 0; i < (size / 4); i++) { + ret = snprintf((char *)lbuffer_ptr, amt, "+-------"); + if (ret >= amt) + goto printit; + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, "\n"); + if (ret >= amt) + goto printit; + lbuffer_ptr += ret; + amt -= ret; + + for (i = 0; i < size; i++) { + ret = snprintf((char *)lbuffer_ptr, amt, "%02x", *data); + if (ret >= amt) + goto printit; + lbuffer_ptr += ret; + amt -= ret; + data++; + } + + snprintf((char *)lbuffer_ptr, amt, "\n"); +printit: + BNXT_TF_DBG(DEBUG, "%s", lbuffer); +} +#endif + +#if 0 //def TF_EEM_DUMP +/************************ DEBBUG *******************************/ +enum {B_TE, B_RE, B_RXP, B_A0, B_A1, B_C0, B_C1, B_C2, B_ALL }; + +enum {P_LOW, P_HIGH, P_OUT, P_IN, P_INTDIS, + P_INTEN, P_APE, P_CHIMP, P_NORMAL, + P_SHARE, P_PORT, P_PF, P_VF }; + +#define STR_CMD_SIZE 32 +#define KEY_ENTRY_SIZE 64 +#define EAR_RECORD_SIZE 16 +#define MAX_BUF_SIZE 1024 + +/* + * Keep a selection of action record pointers to display action records. + * The actual number of action records could be huge and detecting a + * valid action record in memory is not easy so we since this code is + * just a debug facility we keep just a small number. + */ +#define TF_MAX_ACT_REC_PTRS 256 +struct tf_act_rec_ref { + uint32_t ptr; + uint32_t size; +}; + +static struct tf_act_rec_ref act_rec_data[TF_DIR_MAX][TF_MAX_ACT_REC_PTRS]; +static uint32_t act_rec_counts[TF_DIR_MAX]; + +static int cdbg_cfa_eem_host_key_decode(int dir, + uint32_t index, + uint8_t *eem_buf); +static uint32_t getbits(uint32_t *data, int offset, int blen); + +static void eem_decode_hdr(uint32_t type) +{ + uint8_t lbuffer[1024]; + uint8_t *lbuffer_ptr = lbuffer; + int32_t ret, amt; + + amt = sizeof(lbuffer) - 1; + + memset(lbuffer, 0, sizeof(lbuffer)); + + switch (type) { + case 0: + ret = snprintf((char *)lbuffer_ptr, amt, + "\n\n=============== EEM KEY0 TABLE ============" + "==========================\n"); + break; + case 1: + ret = snprintf((char *)lbuffer_ptr, amt, + "\n\n=============== EEM KEY1 TABLE ============" + "==========================\n"); + break; + case 2: + ret = snprintf((char *)lbuffer_ptr, amt, + "\n\n=============== EEM RECORD TABLE ==========" + "============================\n"); + break; + case 3: + ret = snprintf((char *)lbuffer_ptr, amt, + "\n\n=============== EEM EFC TABLE =============" + "=========================\n"); + break; + } + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + switch (type) { + case 0: + case 1: + ret = snprintf((char *)lbuffer_ptr, amt, + " | | | | | Act| ext|" + " Act| | |\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " | | | KEY | Rec | Rec| flw|" + " Rec| EM | EM | EM\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " id V| C| S| Size| Size| int| ctr|" + " Ptr| Prof| Msk| KEY\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + "======== =|==|==|=====|=====|====|====|" + "=========|=====|====|=============\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 2: + case 3: + ret = snprintf((char *)lbuffer_ptr, amt, + "Only showing first %d action records\n", + TF_MAX_ACT_REC_PTRS); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " | | | | |vnic | |" + " TTL |Meter| " + "NAT | Encap | TCP | Flow|" + " | | |Flow\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " Offset |Drop|Mrr|Mtr|VLAN|vport|Dcap|" + "TD D TR R| Ptr |SPort " + "SIP Dport DIP|int Ptr |Ma Mi Ke|e Fl|" + "Rt|Agg|Age| Id\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + "======== |====|===|===|====|=====|====" + "|== = == =|=====|===== " + "=== ===== ===|=== =====|== == ==|== ==" + "|==|===|===|====\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + break; + } +printit: + BNXT_TF_DBG(DEBUG, "%s", lbuffer); +} + +static uint32_t getbits(uint32_t *data, int offset, int blen) +{ + int start = offset >> 5; + int end = (offset + blen - 1) >> 5; + uint32_t val = data[start] >> (offset & 0x1f); + + if (start != end) + val |= (data[start + 1] << (32 - (offset & 0x1f))); + return (blen == 32) ? val : (val & ((1 << blen) - 1)); +} + +static int cdbg_cfa_eem_host_key_decode(int dir, + uint32_t index, + uint8_t *eem_buf) +{ + static const char * const strength[] = { "Lo", "M1", "M2", "Hi" }; + uint32_t valid, cache, internal_act_rec, external_fc; + uint32_t key_size_bits, record_size_bytes, profile_id; + uint32_t *eem_buf_ptr = (uint32_t *)eem_buf; + uint32_t key_id, em_mask; + uint64_t act_record_ptr; + char lbuffer[2048]; + char *lbuffer_ptr = lbuffer; + int32_t amt; + int ret = 0; + + amt = sizeof(lbuffer) - 1; + + memset(lbuffer, 0, sizeof(lbuffer)); + ret = snprintf((char *)lbuffer_ptr, amt, "\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + +#ifdef TF_EEM_DEBUG + int i; + + for (i = 0; i < 64; i += 4) { + if (eem_buf[i] != 0 || + eem_buf[i + 1] != 0 || + eem_buf[i + 2] != 0 || + eem_buf[i + 3] != 0) + break; + } + + if (i >= 64) + return 0; + + for (i = 0; i < 64; i++) { + ret = snprintf((char *)lbuffer_ptr, amt, "%02x", eem_buf[i]); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + } + ret = snprintf((char *)lbuffer_ptr, amt, "\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + for (i = 63; i >= 0; i--) { + ret = snprintf((char *)lbuffer_ptr, amt, "%02x", eem_buf[i]); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + } + ret = snprintf((char *)lbuffer_ptr, amt, "\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } +#endif + + valid = getbits(eem_buf_ptr, 511, 1); + if (!valid) + return 0; + + cache = getbits(eem_buf_ptr, 510, 1); + + key_size_bits = getbits(eem_buf_ptr, 488, 9); + record_size_bytes = (getbits(eem_buf_ptr, 483, 5) + 1) * 16; + internal_act_rec = getbits(eem_buf_ptr, 482, 1); + external_fc = getbits(eem_buf_ptr, 481, 1); + act_record_ptr = getbits(eem_buf_ptr, 448, 32) + + ((uint64_t)getbits(eem_buf_ptr, 480, 1) << 32); + + if (!internal_act_rec) { + if (act_rec_counts[dir] < TF_MAX_ACT_REC_PTRS) { + act_rec_data[dir][act_rec_counts[dir]].ptr = + act_record_ptr << 4; + act_rec_data[dir][act_rec_counts[dir]].size = + record_size_bytes; + act_rec_counts[dir]++; + } + } + profile_id = getbits(eem_buf_ptr, 440, 8); + + if (key_size_bits == 197) + key_id = 21; /* Matches example flow create in DPDK */ + else if (key_size_bits == 173) + key_id = 3; + else if (key_size_bits == 109) + key_id = 2; + else + key_id = 21; + + em_mask = 0; + + ret = snprintf((char *)lbuffer_ptr, amt, + "%08x %x %x %s %4d %4d %x" + " %x %p %d %d", + index, + valid, + cache, + strength[getbits(eem_buf_ptr, 508, 2)], + key_size_bits, + record_size_bytes, + internal_act_rec, + external_fc, + (void *)((uintptr_t)act_record_ptr), + profile_id, + em_mask); + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + switch (key_id) { + case 0: + ret = snprintf((char *)lbuffer_ptr, amt, + " parif-%x svif-%x dst-%02x:%02x:%02x:" + "%02x:%02x:%02x iv-%x etype-%x cos-%x\n\n", + getbits(eem_buf_ptr, 430, 4), + getbits(eem_buf_ptr, 426, 8), + getbits(eem_buf_ptr, 418, 8), + getbits(eem_buf_ptr, 410, 8), + getbits(eem_buf_ptr, 402, 8), + getbits(eem_buf_ptr, 394, 8), + getbits(eem_buf_ptr, 386, 8), + getbits(eem_buf_ptr, 374, 12), + getbits(eem_buf_ptr, 358, 16), + getbits(eem_buf_ptr, 355, 3), + 0); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 1: + ret = snprintf((char *)lbuffer_ptr, amt, + " parif-%x svif-%2x dst-%02x%02x:%02x%02x:" + "%02x%02x src-%02x%02x:%02x%02x:%02x%02x\n", + getbits(eem_buf_ptr, 430, 4), + getbits(eem_buf_ptr, 426, 8), + getbits(eem_buf_ptr, 418, 8), + getbits(eem_buf_ptr, 410, 8), /* dst */ + getbits(eem_buf_ptr, 402, 8), + getbits(eem_buf_ptr, 394, 8), + getbits(eem_buf_ptr, 386, 8), /* dst */ + getbits(eem_buf_ptr, 378, 8), + getbits(eem_buf_ptr, 370, 8), + getbits(eem_buf_ptr, 362, 8), /* src */ + getbits(eem_buf_ptr, 354, 8), + getbits(eem_buf_ptr, 346, 8), + getbits(eem_buf_ptr, 334, 8), /* src */ + getbits(eem_buf_ptr, 326, 8) + ); + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " ov-%x iv-%x etype-%x" + " dip-%x.%x.%x.%x proto:%x cos:%x\n\n", + getbits(eem_buf_ptr, 322, 12), + getbits(eem_buf_ptr, 310, 12), + getbits(eem_buf_ptr, 294, 16), /* ov iv etype */ + getbits(eem_buf_ptr, 286, 8), + getbits(eem_buf_ptr, 278, 8), + getbits(eem_buf_ptr, 270, 8), + getbits(eem_buf_ptr, 262, 8), /* l3_dst */ + getbits(eem_buf_ptr, 254, 8), + getbits(eem_buf_ptr, 251, 3) /* l3_pro, l_cos */ + ); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 2: + ret = snprintf((char *)lbuffer_ptr, amt, + " ctx-%x sip-%02x.%02x.%02x.%02x", + getbits(eem_buf_ptr, 430, 10), + getbits(eem_buf_ptr, 422, 8), /* SIP */ + getbits(eem_buf_ptr, 414, 8), + getbits(eem_buf_ptr, 406, 8), + getbits(eem_buf_ptr, 398, 8) + ); + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " dip-%02x.%02x.%02x.%02x prot-%x dport-%x" + " cos-%x\n\n", + getbits(eem_buf_ptr, 390, 8), /* DIP */ + getbits(eem_buf_ptr, 382, 8), + getbits(eem_buf_ptr, 374, 8), + getbits(eem_buf_ptr, 366, 8), + getbits(eem_buf_ptr, 358, 8), /* L3 Proto */ + getbits(eem_buf_ptr, 342, 16),/* L4 Dest */ + getbits(eem_buf_ptr, 339, 3) /* COS */ + ); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 3: + ret = snprintf((char *)lbuffer_ptr, amt, + " ctx-%x smac-%02x:%02x:%02x:%02x:%02x:" + "%02x sip-%02x.%02x.%02x.%02x", + getbits(eem_buf_ptr, 430, 10), + getbits(eem_buf_ptr, 422, 8), /* SMAC */ + getbits(eem_buf_ptr, 414, 8), + getbits(eem_buf_ptr, 406, 8), + getbits(eem_buf_ptr, 398, 8), + getbits(eem_buf_ptr, 390, 8), + getbits(eem_buf_ptr, 382, 8), + getbits(eem_buf_ptr, 374, 8), /* SIP */ + getbits(eem_buf_ptr, 366, 8), + getbits(eem_buf_ptr, 358, 8), + getbits(eem_buf_ptr, 350, 8) + ); + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " dip-%02x.%02x.%02x.%02x prot-%x sport-%x" + " dport-%x cos-%x\n\n", + getbits(eem_buf_ptr, 342, 8), /* DIP */ + getbits(eem_buf_ptr, 334, 8), + getbits(eem_buf_ptr, 326, 8), + getbits(eem_buf_ptr, 318, 8), + getbits(eem_buf_ptr, 310, 8), /* L3 Proto */ + getbits(eem_buf_ptr, 294, 16),/* L4 Scr */ + getbits(eem_buf_ptr, 278, 16),/* L4 Dest */ + getbits(eem_buf_ptr, 275, 3) /* COS */ + ); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 4: + ret = snprintf((char *)lbuffer_ptr, amt, + " ctx-%x dmac-%02x:%02x:%02x:%02x:%02x:%02x" + " dip-%02x.%02x.%02x.%02x", + getbits(eem_buf_ptr, 430, 10), + getbits(eem_buf_ptr, 422, 8), + getbits(eem_buf_ptr, 414, 8), + getbits(eem_buf_ptr, 406, 8), /* src */ + getbits(eem_buf_ptr, 398, 8), + getbits(eem_buf_ptr, 390, 8), + getbits(eem_buf_ptr, 382, 8), /* src */ + getbits(eem_buf_ptr, 374, 8), + getbits(eem_buf_ptr, 366, 8), + getbits(eem_buf_ptr, 358, 8), + getbits(eem_buf_ptr, 350, 8) /* l3_dst */ + ); + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " dip-%02x.%02x.%02x.%02x prot-%x sport-%x" + " dport-%x cos-%x\n\n", + getbits(eem_buf_ptr, 342, 8), + getbits(eem_buf_ptr, 334, 8), + getbits(eem_buf_ptr, 326, 8), + getbits(eem_buf_ptr, 318, 8), /* l3_dst */ + getbits(eem_buf_ptr, 310, 8), + getbits(eem_buf_ptr, 294, 16), + getbits(eem_buf_ptr, 278, 16), + getbits(eem_buf_ptr, 275, 3) /* + * l3_pro,l4_src, + * l4_dst,l_cos + */ + ); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 7: + ret = snprintf((char *)lbuffer_ptr, amt, + " ctx-%x dst-%02x%02x:%02x%02x:%02x%02x " + "src-%02x%02x:%02x%02x:%02x%02x\n", + getbits(eem_buf_ptr, 430, 10), + getbits(eem_buf_ptr, 420, 8), + getbits(eem_buf_ptr, 412, 8), + getbits(eem_buf_ptr, 404, 8), /* dst */ + getbits(eem_buf_ptr, 396, 8), + getbits(eem_buf_ptr, 388, 8), + getbits(eem_buf_ptr, 380, 8), /* dst */ + getbits(eem_buf_ptr, 372, 8), + getbits(eem_buf_ptr, 364, 8), + getbits(eem_buf_ptr, 356, 8), /* src */ + getbits(eem_buf_ptr, 348, 8), + getbits(eem_buf_ptr, 340, 8), + getbits(eem_buf_ptr, 328, 8) /* src */ + ); + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " sip-%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x" + " dip-%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + getbits(eem_buf_ptr, 312, 16), + getbits(eem_buf_ptr, 296, 16), + getbits(eem_buf_ptr, 280, 16), /* l3_src_v6 */ + getbits(eem_buf_ptr, 264, 16), + getbits(eem_buf_ptr, 248, 16), + getbits(eem_buf_ptr, 232, 16), /* l3_src_v6 */ + getbits(eem_buf_ptr, 372, 16), + getbits(eem_buf_ptr, 364, 16), + getbits(eem_buf_ptr, 356, 16), /* l3_dst_v6 */ + getbits(eem_buf_ptr, 348, 16), + getbits(eem_buf_ptr, 340, 16), + getbits(eem_buf_ptr, 328, 16), /* l3_dst_v6 */ + getbits(eem_buf_ptr, 328, 16), + getbits(eem_buf_ptr, 328, 16), + getbits(eem_buf_ptr, 328, 16), + getbits(eem_buf_ptr, 328, 16) + ); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 12: + ret = snprintf((char *)lbuffer_ptr, amt, + " ctx-%x dst-%02x:%02x:%02x:%02x:%02x:%02x" + " iv-%x etype-%x cos-%x\n\n", + getbits(eem_buf_ptr, 430, 10), + getbits(eem_buf_ptr, 422, 8), + getbits(eem_buf_ptr, 414, 8), + getbits(eem_buf_ptr, 406, 8), + getbits(eem_buf_ptr, 398, 8), + getbits(eem_buf_ptr, 390, 8), + getbits(eem_buf_ptr, 382, 8), + getbits(eem_buf_ptr, 370, 12), + getbits(eem_buf_ptr, 354, 16), + getbits(eem_buf_ptr, 351, 3) + ); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + case 21: + ret = snprintf((char *)lbuffer_ptr, amt, + " ctx-%x tid-%x smac-%02x:%02x:%02x:%02x:" + "%02x:%02x", + getbits(eem_buf_ptr, 430, 10), + getbits(eem_buf_ptr, 406, 24), /* ctx, tid */ + getbits(eem_buf_ptr, 398, 8), + getbits(eem_buf_ptr, 390, 8), + getbits(eem_buf_ptr, 382, 8), /* src */ + getbits(eem_buf_ptr, 374, 8), + getbits(eem_buf_ptr, 366, 8), + getbits(eem_buf_ptr, 358, 8) /* src */ + ); + + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ret = snprintf((char *)lbuffer_ptr, amt, + " sip-%02x.%02x.%02x.%02x dip-%02x.%02x." + "%02x.%02x prot-%x sport-%x dport-%x cos-%x\n\n", + getbits(eem_buf_ptr, 350, 8), + getbits(eem_buf_ptr, 342, 8), + getbits(eem_buf_ptr, 334, 8), + getbits(eem_buf_ptr, 326, 8), /* l3_src */ + getbits(eem_buf_ptr, 318, 8), + getbits(eem_buf_ptr, 310, 8), + getbits(eem_buf_ptr, 302, 8), + getbits(eem_buf_ptr, 294, 8), /* l3_dst */ + getbits(eem_buf_ptr, 286, 8), + getbits(eem_buf_ptr, 270, 16), + getbits(eem_buf_ptr, 254, 16), + getbits(eem_buf_ptr, 251, 3) + ); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + + default: + ret = snprintf((char *)lbuffer_ptr, amt, + " doesn't support yet\n\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + break; + } + +printit: + PMD_DRV_LOG(DEBUG, "%s", lbuffer); + + return 1; +} + + +static int cdbg_cfa_eem_host_record_decode(uint32_t index, + uint8_t *eem_buf) +{ + uint32_t *data = (uint32_t *)eem_buf; + uint8_t lbuffer[2048]; + uint8_t *lbuffer_ptr = lbuffer; + uint8_t count_enable; + uint8_t count_type; + int32_t ret, amt; + int j; + + amt = sizeof(lbuffer) - 1; + + memset(lbuffer, 0, sizeof(lbuffer)); + ret = snprintf((char *)lbuffer_ptr, amt, "\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + for (j = 0; j < 4; j++) { + if (data[j] != 0) + break; + } + + if (j >= 4) + return 0; + +#ifdef TF_EEM_DEBUG + for (j = 0; j < 16; j += 4) { + ret = snprintf((char *)lbuffer_ptr, amt, "%02x%02x%02x%02x", + eem_buf[j], + eem_buf[j + 1], + eem_buf[j + 2], + eem_buf[j + 3]); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + } + ret = snprintf((char *)lbuffer_ptr, amt, "\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + for (j = 0; j < 4; j++) { + ret = snprintf((char *)lbuffer_ptr, amt, "%08x", data[j]); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + } + ret = snprintf((char *)lbuffer_ptr, amt, "\n"); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } +#endif + + count_type = getbits(data, 17, 1); + count_enable = getbits(data, 18, 1); + + ret = snprintf((char *)lbuffer_ptr, amt, + "%8x %d %d %d %d %3x %2x " + "%d %d %d %d %3x %4x %3x %4x %3x " + "%d %3x %d %d %2x %d %d %d %d %d %4x %p\n", + index, + getbits(data, 127, 1), + getbits(data, 125, 2), + getbits(data, 124, 1), + getbits(data, 123, 1), + getbits(data, 111, 12), + getbits(data, 107, 4), + getbits(data, 106, 1), + getbits(data, 105, 1), + getbits(data, 104, 1), + getbits(data, 103, 1), + getbits(data, 93, 10), + getbits(data, 77, 16), + getbits(data, 67, 10), + getbits(data, 51, 16), + getbits(data, 41, 10), + getbits(data, 40, 1), + getbits(data, 29, 11), + getbits(data, 28, 1), + getbits(data, 27, 1), + getbits(data, 19, 8), + getbits(data, 18, 1), + getbits(data, 17, 1), + getbits(data, 16, 1), + getbits(data, 15, 1), + getbits(data, 14, 1), + getbits(data, 0, 14), + data); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + if (count_type == 1 && count_enable == 1) { + uint32_t ch; + uint32_t cl; + uint32_t *ptr; + + data += 4; + ret = snprintf((char *)lbuffer_ptr, amt, + "EFC: ByteCntPtr:0x%x PktCntPtr:0x%x ", + *((uint32_t *)data), + *((uint32_t *)(data + 1))); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ptr = data + ((((*data & 0xffff) << 3)) / 4) - 4; + cl = *ptr; + ch = *(ptr + 1); + ret = snprintf((char *)lbuffer_ptr, amt, + "B:0x%08x%08x ", ch, cl); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + + ptr = data + ((((*(data + 1) & 0xffff) << 3)) / 4) - 4; + cl = *ptr; + ch = *(ptr + 1); + ret = snprintf((char *)lbuffer_ptr, amt, + "P:0x%08x%08x\n", ch, cl); + if (ret >= amt) + goto printit; + if (ret > 0) { + lbuffer_ptr += ret; + amt -= ret; + } + } + +printit: + PMD_DRV_LOG(DEBUG, "%s", lbuffer); + + return 0; +} + +static +void tf_diag_dump_table(struct tf_tbl_scope_cb *tbl_scope_cb, + struct tf_em_ctx_mem_info *eem_ctx_info) +{ + uint32_t key0_count = 0; + uint32_t key1_count = 0; + uint32_t num_entries; + uint32_t entry_size; + uint8_t *eem_entry; + uint8_t *table; + uint32_t offset; + int dir = 0; + uint32_t i; + + act_rec_counts[TF_DIR_TX] = 0; + act_rec_counts[TF_DIR_RX] = 0; + + for (dir = 0; dir < 2; dir++) { + num_entries = + eem_ctx_info[dir].em_tables[KEY0_TABLE].num_entries; + PMD_DRV_LOG(DEBUG, "\n\n"); + PMD_DRV_LOG(DEBUG, "\n>>>>>>>>>>>>>>> Dir:%s <<<<<<<<<<<<\n", + (dir == TF_DIR_TX ? "Tx" : "Rx")); + + entry_size = 64; + table = tf_em_get_table_page(tbl_scope_cb, + dir, + 0, + KEY0_TABLE); + if (table == NULL) { + PMD_DRV_LOG(DEBUG, "EEM Not configured\n"); + continue; + } + + eem_decode_hdr(KEY0_TABLE); + + for (i = 0, offset = 0; i < num_entries; i++) { + if ((offset % TF_EM_PAGE_SIZE) == 0) { + table = + tf_em_get_table_page(tbl_scope_cb, + dir, + offset, + KEY0_TABLE); +#ifdef TF_EEM_DUMP_DEBUG + PMD_DRV_LOG(DEBUG, + "----- Page:%d %p -----\n", + (offset / TF_EM_PAGE_SIZE), + table); +#endif + } + + eem_entry = table + (offset % TF_EM_PAGE_SIZE); + + if (cdbg_cfa_eem_host_key_decode(dir, + i, + eem_entry)) { +#ifdef TF_EEM_DUMP_DEBUG + PMD_DRV_LOG(DEBUG, "Page:%p entry:%p" + " offset:0x%x" + " page-offset:0x%x\n", + table, + eem_entry, + offset, + (offset % TF_EM_PAGE_SIZE)); +#endif + key0_count++; + } + + offset += entry_size; + } + + eem_decode_hdr(KEY1_TABLE); + table = tf_em_get_table_page(tbl_scope_cb, + dir, + 0, + KEY1_TABLE); + + for (i = 0, offset = 0; i < num_entries; i++) { + if ((offset % TF_EM_PAGE_SIZE) == 0) { + table = + tf_em_get_table_page(tbl_scope_cb, + dir, + offset, + KEY1_TABLE); +#ifdef TF_EEM_DUMP_DEBUG + PMD_DRV_LOG(DEBUG, + "----- Page:%d %p -----\n", + (offset / TF_EM_PAGE_SIZE), + table); +#endif + } + + eem_entry = table + (offset % TF_EM_PAGE_SIZE); + + if (cdbg_cfa_eem_host_key_decode(dir, + i, + eem_entry)) + key1_count++; + + offset += entry_size; + } + + PMD_DRV_LOG(DEBUG, "Key0 table has %d entries and Key1" + " table has %d entries, total:%d\n\n", + key0_count, + key1_count, + (key0_count + key1_count)); + + entry_size = 16; + eem_decode_hdr(RECORD_TABLE); + table = tf_em_get_table_page(tbl_scope_cb, + dir, + 0, + RECORD_TABLE); +#if 0 + for (i = 0, offset = 0; i < num_entries; i++) { + if ((offset % TF_EM_PAGE_SIZE) == 0) { + table = + tf_em_get_table_page(tbl_scope_cb, + dir, + offset, + RECORD_TABLE); +#ifdef TF_EEM_DUMP_DEBUG + printf("----- Page:%d %p -----\n", + (offset / TF_EM_PAGE_SIZE), + table); +#endif + } + + eem_entry = table + (offset % TF_EM_PAGE_SIZE); + cdbg_cfa_eem_host_record_decode(i, eem_entry); + offset += entry_size; + } +#else + for (i = 0; i < act_rec_counts[dir]; i++) { + offset = act_rec_data[dir][i].ptr; + /* printf("Offset:0x%x\n", offset); */ + if ((offset % TF_EM_PAGE_SIZE) == 0) { + table = + tf_em_get_table_page(tbl_scope_cb, + dir, + offset, + RECORD_TABLE); +#ifdef TF_EEM_DUMP_DEBUG + PMD_DRV_LOG(DEBUG, + "----- Page:%d %p -----\n", + (offset / TF_EM_PAGE_SIZE), + table); +#endif + } + + eem_entry = table + (offset % TF_EM_PAGE_SIZE); + cdbg_cfa_eem_host_record_decode(offset, + eem_entry); + offset += entry_size; + } +#endif + } +} + +void tf_dump_tables(struct tf *tfp, uint32_t tbl_scope_id); +struct tf_tbl_scope_cb *tbl_scope_cb_find(struct tf_session *session, + uint32_t tbl_scope_id); + +void tf_dump_tables(struct tf *tfp, uint32_t tbl_scope_id) +{ + struct tf_session *session; + struct tf_tbl_scope_cb *tbl_scope_cb; + + BNXT_TF_DBG(DEBUG, "called %s\n", __func__); + + /* find session struct */ + session = (struct tf_session *)tfp->session->core_data; + + /* find control block for table scope */ + tbl_scope_cb = tbl_scope_cb_find(session, + tbl_scope_id); + if (tbl_scope_cb == NULL) + BNXT_TF_DBG(ERR, "No table scope\n"); + + tf_diag_dump_table(tbl_scope_cb, + tbl_scope_cb->em_ctx_info); +} +#endif + +/****************************** End of DEBUG *************************/ + +static struct bnxt *bnxt_get_bp(uint16_t port) +{ + struct bnxt *bp; + struct rte_eth_dev *dev; + + if (!rte_eth_dev_is_valid_port(port)) { + BNXT_TF_DBG(ERR, + "Invalid port %d\n", port); + return NULL; + } + + dev = &rte_eth_devices[port]; + + if (!is_bnxt_supported(dev)) { + BNXT_TF_DBG(ERR, + "Device %d not supported\n", + port); + return NULL; + } + + bp = (struct bnxt *)dev->data->dev_private; + return bp; +} + +void bnxt_ulp_cli_tf_dump_tables(uint16_t port, + uint32_t tbl_scope_id __rte_unused) +{ + struct bnxt *bp; + + bp = bnxt_get_bp(port); + + if (!bp) { + BNXT_TF_DBG(ERR, + "Failed to get bp for port:%d\n", port); + return; + } + + //tf_dump_tables(&bp->tfp, tbl_scope_id); +} + +void +ulp_port_db_dump(struct bnxt_ulp_port_db *port_db, + struct ulp_interface_info *intf, + uint32_t port_id) +{ + struct ulp_func_if_info *func; + struct ulp_phy_port_info *port_data; + + BNXT_TF_DBG(INFO, "*****Dump for DPDK port_id %d ******\n", port_id); + BNXT_TF_DBG(INFO, "type=0x%0x, drv_func_id=0x%0x, vf_func_id=0x%0x\n", + intf->type, intf->drv_func_id, intf->vf_func_id); + + func = &port_db->ulp_func_id_tbl[intf->drv_func_id]; + BNXT_TF_DBG(INFO, "drv_func_svif=0x%0x, drv_func_spif=0x%0x," + "drv_func_parif=0x%0x, drv_default_vnic=0x%0x\n", + func->func_svif, func->func_spif, func->func_parif, + func->func_vnic); + + if (intf->type == BNXT_ULP_INTF_TYPE_VF_REP) { + func = &port_db->ulp_func_id_tbl[intf->vf_func_id]; + BNXT_TF_DBG(INFO, " vf_func_svif=0x%0x, vf_func_spif=0x%0x," + " vf_func_parif=0x%0x, vf_default_vnic=0x%0x\n", + func->func_svif, func->func_spif, func->func_parif, + func->func_vnic); + } + port_data = &port_db->phy_port_list[func->phy_port_id]; + BNXT_TF_DBG(INFO, "phy_port_svif=0x%0x, phy_port_spif=0x%0x," + "phy_port_parif=0x%0x, phy_port_vport=0x%0x\n", + port_data->port_svif, port_data->port_spif, + port_data->port_parif, port_data->port_vport); + BNXT_TF_DBG(INFO, "***** dump complete ******\n"); +} + +const char * +tf_if_tbl_2_str(uint32_t type) +{ + enum tf_if_tbl_type id_type = type; + + switch (id_type) { + case TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT: + return "spif dflt l2 ctxt"; + case TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR: + return "parif act rec ptr"; + case TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR: + return "parif err act rec ptr"; + case TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR: + return "lkup parif act rec ptr"; + case TF_IF_TBL_TYPE_ILT: + return "ilt tbl"; + case TF_IF_TBL_TYPE_VNIC_SVIF: + return "vnic svif tbl"; + default: + return "Invalid identifier"; + } +} + +#endif /* RTE_LIBRTE_BNXT_TRUFLOW_DEBUG */ diff --git a/drivers/net/bnxt/tf_ulp/ulp_tf_debug.h b/drivers/net/bnxt/tf_ulp/ulp_tf_debug.h new file mode 100644 index 0000000..cc6dace --- /dev/null +++ b/drivers/net/bnxt/tf_ulp/ulp_tf_debug.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2014-2019 Broadcom + * All rights reserved. + */ + +#ifndef _ULP_TF_DEBUG_H_ +#define _ULP_TF_DEBUG_H_ + +#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG +struct tf; +struct ulp_interface_info; +struct bnxt_ulp_port_db; + +void bnxt_ulp_cli_tf_dump_tables(uint16_t port, uint32_t tbl_scope_id); +void tf_dump_tables(struct tf *tfp, uint32_t tbl_scope_id); +void +ulp_port_db_dump(struct bnxt_ulp_port_db *port_db, + struct ulp_interface_info *intf, + uint32_t port_id); + +const char * +tf_if_tbl_2_str(uint32_t id_type); + +#endif + +#endif diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c index a923da8..85eb42b 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_utils.c +++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c @@ -411,7 +411,7 @@ ulp_blob_pad_push(struct ulp_blob *blob, { if (datalen > (uint32_t)(blob->bitlen - blob->write_idx)) { BNXT_TF_DBG(ERR, "Pad too large for blob\n"); - return 0; + return -1; } blob->write_idx += datalen;