From patchwork Wed Jul 1 11:54:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72602 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BB35FA0350; Wed, 1 Jul 2020 13:56:31 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ECF241C440; Wed, 1 Jul 2020 13:56:30 +0200 (CEST) Received: from huawei.com (szxga06-in.huawei.com [45.249.212.32]) by dpdk.org (Postfix) with ESMTP id 686101C2F8 for ; Wed, 1 Jul 2020 13:56:29 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 56FB875F6C95EDD0E538 for ; Wed, 1 Jul 2020 19:56:27 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:20 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:33 +0800 Message-ID: <1593604482-47494-2-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 01/10] net/hns3: support symmetric RSS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Lijun Ou This patch adds support of symmetric algorithm of RSS. Signed-off-by: Lijun Ou Signed-off-by: Wei Hu (Xavier) Signed-off-by: Chengwen Feng --- drivers/net/hns3/hns3_flow.c | 12 +++++++----- drivers/net/hns3/hns3_rss.c | 27 +++++++++++++++++---------- drivers/net/hns3/hns3_rss.h | 5 +++-- 3 files changed, 27 insertions(+), 17 deletions(-) diff --git a/drivers/net/hns3/hns3_flow.c b/drivers/net/hns3/hns3_flow.c index c7851b2..1e58ad7 100644 --- a/drivers/net/hns3/hns3_flow.c +++ b/drivers/net/hns3/hns3_flow.c @@ -1287,6 +1287,7 @@ hns3_parse_rss_filter(struct rte_eth_dev *dev, case RTE_ETH_HASH_FUNCTION_DEFAULT: case RTE_ETH_HASH_FUNCTION_TOEPLITZ: case RTE_ETH_HASH_FUNCTION_SIMPLE_XOR: + case RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ: break; default: return rte_flow_error_set(error, ENOTSUP, @@ -1365,6 +1366,9 @@ hns3_parse_rss_algorithm(struct hns3_hw *hw, enum rte_eth_hash_function *func, case RTE_ETH_HASH_FUNCTION_SIMPLE_XOR: *hash_algo = HNS3_RSS_HASH_ALGO_SIMPLE; break; + case RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ: + *hash_algo = HNS3_RSS_HASH_ALGO_SYMMETRIC_TOEP; + break; default: hns3_err(hw, "Invalid RSS algorithm configuration(%u)", algo_func); @@ -1378,9 +1382,6 @@ hns3_parse_rss_algorithm(struct hns3_hw *hw, enum rte_eth_hash_function *func, static int hns3_hw_rss_hash_set(struct hns3_hw *hw, struct rte_flow_action_rss *rss_config) { - uint8_t hash_algo = - (hw->rss_info.conf.func == RTE_ETH_HASH_FUNCTION_TOEPLITZ ? - HNS3_RSS_HASH_ALGO_TOEPLITZ : HNS3_RSS_HASH_ALGO_SIMPLE); struct hns3_rss_tuple_cfg *tuple; int ret; @@ -1388,11 +1389,12 @@ hns3_hw_rss_hash_set(struct hns3_hw *hw, struct rte_flow_action_rss *rss_config) hns3_parse_rss_key(hw, rss_config); /* Parse hash algorithm */ - ret = hns3_parse_rss_algorithm(hw, &rss_config->func, &hash_algo); + ret = hns3_parse_rss_algorithm(hw, &rss_config->func, + &hw->rss_info.hash_algo); if (ret) return ret; - ret = hns3_set_rss_algo_key(hw, hash_algo, rss_config->key); + ret = hns3_set_rss_algo_key(hw, rss_config->key); if (ret) return ret; diff --git a/drivers/net/hns3/hns3_rss.c b/drivers/net/hns3/hns3_rss.c index a6cab29..247bd7d 100644 --- a/drivers/net/hns3/hns3_rss.c +++ b/drivers/net/hns3/hns3_rss.c @@ -28,7 +28,7 @@ static const uint8_t hns3_hash_key[] = { * Used to set algorithm, key_offset and hash key of rss. */ int -hns3_set_rss_algo_key(struct hns3_hw *hw, uint8_t hash_algo, const uint8_t *key) +hns3_set_rss_algo_key(struct hns3_hw *hw, const uint8_t *key) { #define HNS3_KEY_OFFSET_MAX 3 #define HNS3_SET_HASH_KEY_BYTE_FOUR 2 @@ -51,7 +51,8 @@ hns3_set_rss_algo_key(struct hns3_hw *hw, uint8_t hash_algo, const uint8_t *key) hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RSS_GENERIC_CONFIG, false); - req->hash_config |= (hash_algo & HNS3_RSS_HASH_ALGO_MASK); + req->hash_config |= + (hw->rss_info.hash_algo & HNS3_RSS_HASH_ALGO_MASK); req->hash_config |= (key_offset << HNS3_RSS_HASH_KEY_OFFSET_B); if (key_offset == HNS3_SET_HASH_KEY_BYTE_FOUR) @@ -256,7 +257,6 @@ hns3_dev_rss_hash_update(struct rte_eth_dev *dev, struct hns3_rss_tuple_cfg *tuple = &hw->rss_info.rss_tuple_sets; struct hns3_rss_conf *rss_cfg = &hw->rss_info; uint8_t key_len = rss_conf->rss_key_len; - uint8_t algo; uint64_t rss_hf = rss_conf->rss_hf; uint8_t *key = rss_conf->rss_key; int ret; @@ -292,9 +292,7 @@ hns3_dev_rss_hash_update(struct rte_eth_dev *dev, ret = -EINVAL; goto conf_err; } - algo = rss_cfg->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR ? - HNS3_RSS_HASH_ALGO_SIMPLE : HNS3_RSS_HASH_ALGO_TOEPLITZ; - ret = hns3_set_rss_algo_key(hw, algo, key); + ret = hns3_set_rss_algo_key(hw, key); if (ret) goto conf_err; } @@ -529,20 +527,29 @@ hns3_config_rss(struct hns3_adapter *hns) { struct hns3_hw *hw = &hns->hw; struct hns3_rss_conf *rss_cfg = &hw->rss_info; - uint8_t hash_algo = - (hw->rss_info.conf.func == RTE_ETH_HASH_FUNCTION_TOEPLITZ ? - HNS3_RSS_HASH_ALGO_TOEPLITZ : HNS3_RSS_HASH_ALGO_SIMPLE); uint8_t *hash_key = rss_cfg->key; int ret, ret1; enum rte_eth_rx_mq_mode mq_mode = hw->data->dev_conf.rxmode.mq_mode; + switch (hw->rss_info.conf.func) { + case RTE_ETH_HASH_FUNCTION_SIMPLE_XOR: + hw->rss_info.hash_algo = HNS3_RSS_HASH_ALGO_SIMPLE; + break; + case RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ: + hw->rss_info.hash_algo = HNS3_RSS_HASH_ALGO_SYMMETRIC_TOEP; + break; + default: + hw->rss_info.hash_algo = HNS3_RSS_HASH_ALGO_TOEPLITZ; + break; + } + /* When RSS is off, redirect the packet queue 0 */ if (((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) hns3_rss_uninit(hns); /* Configure RSS hash algorithm and hash key offset */ - ret = hns3_set_rss_algo_key(hw, hash_algo, hash_key); + ret = hns3_set_rss_algo_key(hw, hash_key); if (ret) return ret; diff --git a/drivers/net/hns3/hns3_rss.h b/drivers/net/hns3/hns3_rss.h index 3c79051..df5bba6 100644 --- a/drivers/net/hns3/hns3_rss.h +++ b/drivers/net/hns3/hns3_rss.h @@ -27,6 +27,7 @@ #define HNS3_RSS_HASH_ALGO_TOEPLITZ 0 #define HNS3_RSS_HASH_ALGO_SIMPLE 1 +#define HNS3_RSS_HASH_ALGO_SYMMETRIC_TOEP 2 #define HNS3_RSS_HASH_ALGO_MASK 0xf #define HNS3_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) @@ -49,6 +50,7 @@ struct hns3_rss_tuple_cfg { struct hns3_rss_conf { /* RSS parameters :algorithm, flow_types, key, queue */ struct rte_flow_action_rss conf; + uint8_t hash_algo; /* hash function type definited by hardware */ uint8_t key[HNS3_RSS_KEY_SIZE]; /* Hash key */ struct hns3_rss_tuple_cfg rss_tuple_sets; uint8_t rss_indirection_tbl[HNS3_RSS_IND_TBL_SIZE]; /* Shadow table */ @@ -109,8 +111,7 @@ void hns3_rss_uninit(struct hns3_adapter *hns); int hns3_set_rss_tuple_by_rss_hf(struct hns3_hw *hw, struct hns3_rss_tuple_cfg *tuple, uint64_t rss_hf); -int hns3_set_rss_algo_key(struct hns3_hw *hw, uint8_t hash_algo, - const uint8_t *key); +int hns3_set_rss_algo_key(struct hns3_hw *hw, const uint8_t *key); int hns3_restore_rss_filter(struct rte_eth_dev *dev); #endif /* _HNS3_RSS_H_ */ From patchwork Wed Jul 1 11:54:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72604 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5985AA0350; Wed, 1 Jul 2020 13:56:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7E7721D381; Wed, 1 Jul 2020 13:56:33 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 8A14C1D148 for ; Wed, 1 Jul 2020 13:56:29 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 2859AF13C9A5B95109E1 for ; Wed, 1 Jul 2020 19:56:27 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:21 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:34 +0800 Message-ID: <1593604482-47494-3-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 02/10] net/hns3: support LRO X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds support of LRO offload for hns3 PMD driver. Signed-off-by: Hongbo Zheng Signed-off-by: Wei Hu (Xavier) --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/nics/hns3.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 35 ++++++++++++---------------- drivers/net/hns3/hns3_ethdev.h | 2 +- drivers/net/hns3/hns3_ethdev_vf.c | 16 ++++++++++++- drivers/net/hns3/hns3_rxtx.c | 45 ++++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 4 +++- 8 files changed, 82 insertions(+), 23 deletions(-) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index c3a8544..66abda7 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -9,6 +9,7 @@ Rx interrupt = Y MTU update = Y Jumbo frame = Y TSO = Y +LRO = Y Promiscuous mode = Y Allmulticast mode = Y Unicast MAC filter = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index 80773ac..71d246a 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -9,6 +9,7 @@ Rx interrupt = Y MTU update = Y Jumbo frame = Y TSO = Y +LRO = Y Promiscuous mode = Y Allmulticast mode = Y Unicast MAC filter = Y diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst index 05dbe41..ae3c5f6 100644 --- a/doc/guides/nics/hns3.rst +++ b/doc/guides/nics/hns3.rst @@ -18,6 +18,7 @@ Features of the HNS3 PMD are: - Packet type information - Checksum offload - TSO offload +- LRO offload - Promiscuous mode - Multicast mode - Port hardware statistics diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 62d8758..7758855 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -1099,25 +1099,6 @@ hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, return hns3_cmd_send(hw, &desc, 1); } -int -hns3_config_gro(struct hns3_hw *hw, bool en) -{ - struct hns3_cfg_gro_status_cmd *req; - struct hns3_cmd_desc desc; - int ret; - - hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false); - req = (struct hns3_cfg_gro_status_cmd *)desc.data; - - req->gro_en = rte_cpu_to_le_16(en ? 1 : 0); - - ret = hns3_cmd_send(hw, &desc, 1); - if (ret) - hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret); - - return ret; -} - static int hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, uint16_t *allocated_size, bool is_alloc) @@ -2276,6 +2257,7 @@ hns3_dev_configure(struct rte_eth_dev *dev) uint16_t nb_tx_q = dev->data->nb_tx_queues; struct rte_eth_rss_conf rss_conf; uint16_t mtu; + bool gro_en; int ret; /* @@ -2342,6 +2324,12 @@ hns3_dev_configure(struct rte_eth_dev *dev) if (ret) goto cfg_err; + /* config hardware GRO */ + gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; + ret = hns3_config_gro(hw, gro_en); + if (ret) + goto cfg_err; + hw->adapter_state = HNS3_NIC_CONFIGURED; return 0; @@ -2449,6 +2437,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) info->min_rx_bufsize = hw->rx_buf_len; info->max_mac_addrs = HNS3_UC_MACADDR_NUM; info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; + info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM | @@ -2460,7 +2449,8 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_RX_OFFLOAD_VLAN_STRIP | DEV_RX_OFFLOAD_VLAN_FILTER | DEV_RX_OFFLOAD_JUMBO_FRAME | - DEV_RX_OFFLOAD_RSS_HASH); + DEV_RX_OFFLOAD_RSS_HASH | + DEV_RX_OFFLOAD_TCP_LRO); info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_IPV4_CKSUM | @@ -4381,6 +4371,7 @@ hns3_uninit_pf(struct rte_eth_dev *eth_dev) hns3_enable_hw_error_intr(hns, false); hns3_rss_uninit(hns); + (void)hns3_config_gro(hw, false); hns3_promisc_uninit(hw); hns3_fdir_filter_uninit(hns); hns3_uninit_umv_space(hw); @@ -5215,6 +5206,10 @@ hns3_restore_conf(struct hns3_adapter *hns) if (ret) goto err_promisc; + ret = hns3_restore_gro_conf(hw); + if (ret) + goto err_promisc; + if (hns->hw.adapter_state == HNS3_NIC_STARTED) { ret = hns3_do_start(hns, false); if (ret) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 21412c4..93fe2fe 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -46,6 +46,7 @@ #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1) #define HNS3_MAX_TSO_HDR_SIZE 512 #define HNS3_MAX_TSO_HDR_BD_NUM 3 +#define HNS3_MAX_LRO_SIZE 64512 #define HNS3_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2) @@ -654,7 +655,6 @@ hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr) } int hns3_buffer_alloc(struct hns3_hw *hw); -int hns3_config_gro(struct hns3_hw *hw, bool en); int hns3_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type filter_type, enum rte_filter_op filter_op, void *arg); diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 0fdee4d..ccf44a1 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -757,6 +757,7 @@ hns3vf_dev_configure(struct rte_eth_dev *dev) uint16_t nb_tx_q = dev->data->nb_tx_queues; struct rte_eth_rss_conf rss_conf; uint16_t mtu; + bool gro_en; int ret; /* @@ -817,6 +818,12 @@ hns3vf_dev_configure(struct rte_eth_dev *dev) if (ret) goto cfg_err; + /* config hardware GRO */ + gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; + ret = hns3_config_gro(hw, gro_en); + if (ret) + goto cfg_err; + hw->adapter_state = HNS3_NIC_CONFIGURED; return 0; @@ -898,6 +905,7 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) info->min_rx_bufsize = hw->rx_buf_len; info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; + info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM | @@ -910,7 +918,8 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_RX_OFFLOAD_VLAN_STRIP | DEV_RX_OFFLOAD_VLAN_FILTER | DEV_RX_OFFLOAD_JUMBO_FRAME | - DEV_RX_OFFLOAD_RSS_HASH); + DEV_RX_OFFLOAD_RSS_HASH | + DEV_RX_OFFLOAD_TCP_LRO); info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_IPV4_CKSUM | @@ -1648,6 +1657,7 @@ hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(); hns3_rss_uninit(hns); + (void)hns3_config_gro(hw, false); (void)hns3vf_set_alive(hw, false); (void)hns3vf_set_promisc_mode(hw, false, false, false); hns3vf_disable_irq0(hw); @@ -2219,6 +2229,10 @@ hns3vf_restore_conf(struct hns3_adapter *hns) if (ret) goto err_vlan_table; + ret = hns3_restore_gro_conf(hw); + if (ret) + goto err_vlan_table; + if (hw->adapter_state == HNS3_NIC_STARTED) { ret = hns3vf_do_start(hns, false); if (ret) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 57017b6..4e3391d 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -1519,6 +1519,7 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) uint32_t bd_base_info; uint32_t cksum_err; uint32_t l234_info; + uint32_t gro_size; uint32_t ol_info; uint64_t dma_addr; uint16_t data_len; @@ -1665,6 +1666,13 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) } rxm->next = NULL; + gro_size = hns3_get_field(bd_base_info, HNS3_RXD_GRO_SIZE_M, + HNS3_RXD_GRO_SIZE_S); + if (gro_size != 0) { + first_seg->ol_flags |= PKT_RX_LRO; + first_seg->tso_segsz = gro_size; + } + ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info, l234_info, &cksum_err); if (unlikely(ret)) @@ -1850,6 +1858,43 @@ hns3_tso_proc_tunnel(struct hns3_desc *desc, uint64_t ol_flags, return 0; } +int +hns3_config_gro(struct hns3_hw *hw, bool en) +{ + struct hns3_cfg_gro_status_cmd *req; + struct hns3_cmd_desc desc; + int ret; + + hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false); + req = (struct hns3_cfg_gro_status_cmd *)desc.data; + + req->gro_en = rte_cpu_to_le_16(en ? 1 : 0); + + ret = hns3_cmd_send(hw, &desc, 1); + if (ret) + hns3_err(hw, "%s hardware GRO failed, ret = %d", + en ? "enable" : "disable", ret); + + return ret; +} + +int +hns3_restore_gro_conf(struct hns3_hw *hw) +{ + uint64_t offloads; + bool gro_en; + int ret; + + offloads = hw->data->dev_conf.rxmode.offloads; + gro_en = offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; + ret = hns3_config_gro(hw, gro_en); + if (ret) + hns3_err(hw, "restore hardware GRO to %s failed, ret = %d", + gro_en ? "enabled" : "disabled", ret); + + return ret; +} + static inline bool hns3_pkt_is_tso(struct rte_mbuf *m) { diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 0cb92ce..380d27b 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -73,7 +73,7 @@ #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) #define HNS3_RXD_LKBK_B 15 #define HNS3_RXD_GRO_SIZE_S 16 -#define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S) +#define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S) #define HNS3_TXD_L3T_S 0 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) @@ -376,5 +376,7 @@ void hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value); int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q); +int hns3_config_gro(struct hns3_hw *hw, bool en); +int hns3_restore_gro_conf(struct hns3_hw *hw); #endif /* _HNS3_RXTX_H_ */ From patchwork Wed Jul 1 11:54:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72612 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 76974A0350; Wed, 1 Jul 2020 13:58:03 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 382051D531; Wed, 1 Jul 2020 13:56:44 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 5C2951D423 for ; Wed, 1 Jul 2020 13:56:35 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 2EE59D52EC871C8FF89A for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:21 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:35 +0800 Message-ID: <1593604482-47494-4-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 03/10] net/hns3: decrease non-nearby memory access in Rx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang Currently, hns3 PMD driver needs know the PVID configuration state and do different processing in the 'rx_pkt_burst' ops implementation function. This patch adds a member to struct hns3_rx_queue/hns3_tx_queue of the driver to indicate the PVID configuration status, so it isn't need to access other data structure in the 'rx_pkt_burst' ops implementation, to avoid performance loss because of reducing cache miss. Signed-off-by: Chengchang Tang Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_ethdev.c | 21 ++++++++++++++++++++- drivers/net/hns3/hns3_rxtx.c | 37 +++++++++++++++++++++++++++++++------ drivers/net/hns3/hns3_rxtx.h | 13 +++++++++++++ 3 files changed, 64 insertions(+), 7 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 7758855..926efce 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -908,6 +908,8 @@ hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) { struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; + bool pvid_en_state_change; + uint16_t pvid_state; int ret; if (pvid > RTE_ETHER_MAX_VLAN_ID) { @@ -916,10 +918,27 @@ hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) return -EINVAL; } + /* + * If PVID configuration state change, should refresh the PVID + * configuration state in struct hns3_tx_queue/hns3_rx_queue. + */ + pvid_state = hw->port_base_vlan_cfg.state; + if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || + (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) + pvid_en_state_change = false; + else + pvid_en_state_change = true; + rte_spinlock_lock(&hw->lock); ret = hns3_vlan_pvid_configure(hns, pvid, on); rte_spinlock_unlock(&hw->lock); - return ret; + if (ret) + return ret; + + if (pvid_en_state_change) + hns3_update_all_queues_pvid_state(hw); + + return 0; } static void diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 4e3391d..d744d85 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -316,6 +316,31 @@ hns3_init_tx_queue_hw(struct hns3_tx_queue *txq) } void +hns3_update_all_queues_pvid_state(struct hns3_hw *hw) +{ + uint16_t nb_rx_q = hw->data->nb_rx_queues; + uint16_t nb_tx_q = hw->data->nb_tx_queues; + struct hns3_rx_queue *rxq; + struct hns3_tx_queue *txq; + int pvid_state; + int i; + + pvid_state = hw->port_base_vlan_cfg.state; + for (i = 0; i < hw->cfg_max_queues; i++) { + if (i < nb_rx_q) { + rxq = hw->data->rx_queues[i]; + if (rxq != NULL) + rxq->pvid_state = pvid_state; + } + if (i < nb_tx_q) { + txq = hw->data->tx_queues[i]; + if (txq != NULL) + txq->pvid_state = pvid_state; + } + } +} + +void hns3_enable_all_queues(struct hns3_hw *hw, bool en) { uint16_t nb_rx_q = hw->data->nb_rx_queues; @@ -1223,6 +1248,7 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, rxq->pkt_first_seg = NULL; rxq->pkt_last_seg = NULL; rxq->port_id = dev->data->port_id; + rxq->pvid_state = hw->port_base_vlan_cfg.state; rxq->configured = true; rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + idx * HNS3_TQP_REG_SIZE); @@ -1451,7 +1477,7 @@ hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, uint64_t packet_type, } static inline void -hns3_rxd_to_vlan_tci(struct rte_eth_dev *dev, struct rte_mbuf *mb, +hns3_rxd_to_vlan_tci(struct hns3_rx_queue *rxq, struct rte_mbuf *mb, uint32_t l234_info, const struct hns3_desc *rxd) { #define HNS3_STRP_STATUS_NUM 0x4 @@ -1459,8 +1485,6 @@ hns3_rxd_to_vlan_tci(struct rte_eth_dev *dev, struct rte_mbuf *mb, #define HNS3_NO_STRP_VLAN_VLD 0x0 #define HNS3_INNER_STRP_VLAN_VLD 0x1 #define HNS3_OUTER_STRP_VLAN_VLD 0x2 - struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_hw *hw = &hns->hw; uint32_t strip_status; uint32_t report_mode; @@ -1486,7 +1510,7 @@ hns3_rxd_to_vlan_tci(struct rte_eth_dev *dev, struct rte_mbuf *mb, }; strip_status = hns3_get_field(l234_info, HNS3_RXD_STRP_TAGP_M, HNS3_RXD_STRP_TAGP_S); - report_mode = report_type[hw->port_base_vlan_cfg.state][strip_status]; + report_mode = report_type[rxq->pvid_state][strip_status]; switch (report_mode) { case HNS3_NO_STRP_VLAN_VLD: mb->vlan_tci = 0; @@ -1532,7 +1556,6 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) nb_rx = 0; nb_rx_bd = 0; rxq = rx_queue; - dev = &rte_eth_devices[rxq->port_id]; rx_id = rxq->next_to_clean; rx_ring = rxq->rx_ring; @@ -1609,6 +1632,7 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) nmb = rte_mbuf_raw_alloc(rxq->mb_pool); if (unlikely(nmb == NULL)) { + dev = &rte_eth_devices[rxq->port_id]; dev->data->rx_mbuf_alloc_failed++; break; } @@ -1685,7 +1709,7 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) hns3_rx_set_cksum_flag(first_seg, first_seg->packet_type, cksum_err); - hns3_rxd_to_vlan_tci(dev, first_seg, l234_info, &rxd); + hns3_rxd_to_vlan_tci(rxq, first_seg, l234_info, &rxd); rx_pkts[nb_rx++] = first_seg; first_seg = NULL; @@ -1763,6 +1787,7 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, txq->next_to_clean = 0; txq->tx_bd_ready = txq->nb_tx_desc - 1; txq->port_id = dev->data->port_id; + txq->pvid_state = hw->port_base_vlan_cfg.state; txq->configured = true; txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + idx * HNS3_TQP_REG_SIZE); diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 380d27b..b85c64f 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -242,6 +242,12 @@ struct hns3_rx_queue { uint16_t rx_buf_len; uint16_t rx_free_thresh; + /* + * port based vlan configuration state. + * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE + */ + uint16_t pvid_state; + bool rx_deferred_start; /* don't start this queue in dev start */ bool configured; /* indicate if rx queue has been configured */ @@ -268,6 +274,12 @@ struct hns3_tx_queue { uint16_t next_to_use; uint16_t tx_bd_ready; + /* + * port based vlan configuration state. + * value range: HNS3_PORT_BASE_VLAN_DISABLE / HNS3_PORT_BASE_VLAN_ENABLE + */ + uint16_t pvid_state; + bool tx_deferred_start; /* don't start this queue in dev start */ bool configured; /* indicate if tx queue has been configured */ @@ -378,5 +390,6 @@ int hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q); int hns3_config_gro(struct hns3_hw *hw, bool en); int hns3_restore_gro_conf(struct hns3_hw *hw); +void hns3_update_all_queues_pvid_state(struct hns3_hw *hw); #endif /* _HNS3_RXTX_H_ */ From patchwork Wed Jul 1 11:54:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72610 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 48E28A0350; Wed, 1 Jul 2020 13:57:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 98FEF1D51E; Wed, 1 Jul 2020 13:56:41 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 556891D41F for ; Wed, 1 Jul 2020 13:56:35 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3E94471C0B4A329530E6 for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:21 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:36 +0800 Message-ID: <1593604482-47494-5-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 04/10] net/hns3: support setting VF PVID by PF driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang This patch adds support setting VF PVID by hns3 PF kernel ethdev driver on the host by "ip link set vf vlan " command. Because of the hardware constraints, the striped VLAN tag will always in Rx descriptors which should has been dropped when PVID is enabled and the PVID will overwrite the outer VLAN tag in Tx descriptor. So, hns3 PMD driver need to change the processing of VLAN tags in the process of Tx and Rx according to whether PVID is enabled. 1) If the hns3 PF kernel ethdev driver sets the PVID for VF device before the initialization of the related VF device, hns3 VF PMD driver should get the PVID state from PF driver through mailbox and update the related state in txq and rxq maintained by hns3 VF driver to change the process of Tx and Rx. 2) If the hns3 PF kernel ethdev driver sets the PVID for VF device after initialization of the related VF device, the PF driver will notify VF driver to update the PVID state. The VF driver will update the PVID configuration state immediately to ensure that the VLAN process in Tx and Rx is correct. But in the window period of this state transition, packets loss or packets with wrong VLAN may occur. 3) Due to hardware limitations, we only support two-layer VLAN hardware offload in Tx direction based on hns3 network engine, so when PVID is enabled, QinQ insert is no longer supported. And when PVID is enabled, in the following two cases: i) packets with more than two VLAN tags. ii) packets with one VLAN tag while the hardware VLAN insert is enabled. The packets will be regarded as abnormal packets and discarded by hardware in Tx direction. For debugging purposes, a validation check for these types of packets is added to the '.tx_pkt_prepare' ops implementation function named hns3_prep_pkts to inform users that these packets will be discarded. Signed-off-by: Chengchang Tang Signed-off-by: Wei Hu (Xavier) Signed-off-by: Chengwen Feng --- drivers/net/hns3/hns3_ethdev.c | 5 ++-- drivers/net/hns3/hns3_ethdev.h | 9 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 56 ++++++++++++++++++++++++++++++++++++--- drivers/net/hns3/hns3_mbx.c | 33 +++++++++++++++++++++++ drivers/net/hns3/hns3_mbx.h | 3 +++ drivers/net/hns3/hns3_rxtx.c | 47 ++++++++++++++++++++++++++++++++ 6 files changed, 147 insertions(+), 6 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 926efce..5a2f049 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2476,14 +2476,13 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_SCTP_CKSUM | - DEV_TX_OFFLOAD_VLAN_INSERT | - DEV_TX_OFFLOAD_QINQ_INSERT | DEV_TX_OFFLOAD_MULTI_SEGS | DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | - info->tx_queue_offload_capa); + info->tx_queue_offload_capa | + hns3_txvlan_cap_get(hw)); info->rx_desc_lim = (struct rte_eth_desc_lim) { .nb_max = HNS3_MAX_RING_DESC, diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 93fe2fe..a4db1c9 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -673,4 +673,13 @@ is_reset_pending(struct hns3_adapter *hns) return ret; } +static inline uint64_t +hns3_txvlan_cap_get(struct hns3_hw *hw) +{ + if (hw->port_base_vlan_cfg.state) + return DEV_TX_OFFLOAD_VLAN_INSERT; + else + return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT; +} + #endif /* _HNS3_ETHDEV_H_ */ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index ccf44a1..afa79a7 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -926,14 +926,13 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_SCTP_CKSUM | - DEV_TX_OFFLOAD_VLAN_INSERT | - DEV_TX_OFFLOAD_QINQ_INSERT | DEV_TX_OFFLOAD_MULTI_SEGS | DEV_TX_OFFLOAD_TCP_TSO | DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | - info->tx_queue_offload_capa); + info->tx_queue_offload_capa | + hns3_txvlan_cap_get(hw)); info->rx_desc_lim = (struct rte_eth_desc_lim) { .nb_max = HNS3_MAX_RING_DESC, @@ -1078,6 +1077,49 @@ hns3vf_check_tqp_info(struct hns3_hw *hw) return 0; } +static int +hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw) +{ + uint8_t resp_msg; + int ret; + + ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, + HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0, + true, &resp_msg, sizeof(resp_msg)); + if (ret) { + if (ret == -ETIME) { + /* + * Getting current port based VLAN state from PF driver + * will not affect VF driver's basic function. Because + * the VF driver relies on hns3 PF kernel ether driver, + * to avoid introducing compatibility issues with older + * version of PF driver, no failure will be returned + * when the return value is ETIME. This return value has + * the following scenarios: + * 1) Firmware didn't return the results in time + * 2) the result return by firmware is timeout + * 3) the older version of kernel side PF driver does + * not support this mailbox message. + * For scenarios 1 and 2, it is most likely that a + * hardware error has occurred, or a hardware reset has + * occurred. In this case, these errors will be caught + * by other functions. + */ + PMD_INIT_LOG(WARNING, + "failed to get PVID state for timeout, maybe " + "kernel side PF driver doesn't support this " + "mailbox message, or firmware didn't respond."); + resp_msg = HNS3_PORT_BASE_VLAN_DISABLE; + } else { + PMD_INIT_LOG(ERR, "failed to get port based VLAN state," + " ret = %d", ret); + return ret; + } + } + hw->port_base_vlan_cfg.state = resp_msg ? + HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; + return 0; +} static int hns3vf_get_queue_info(struct hns3_hw *hw) @@ -1181,6 +1223,10 @@ hns3vf_get_configuration(struct hns3_hw *hw) if (ret) return ret; + ret = hns3vf_get_port_base_vlan_filter_state(hw); + if (ret) + return ret; + /* Get tc configuration from PF */ return hns3vf_get_tc_info(hw); } @@ -2225,6 +2271,10 @@ hns3vf_restore_conf(struct hns3_adapter *hns) if (ret) goto err_vlan_table; + ret = hns3vf_get_port_base_vlan_filter_state(hw); + if (ret) + goto err_vlan_table; + ret = hns3vf_restore_rx_interrupt(hw); if (ret) goto err_vlan_table; diff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c index 34c8c68..2510582 100644 --- a/drivers/net/hns3/hns3_mbx.c +++ b/drivers/net/hns3/hns3_mbx.c @@ -23,6 +23,7 @@ #include "hns3_regs.h" #include "hns3_logs.h" #include "hns3_intr.h" +#include "hns3_rxtx.h" #define HNS3_CMD_CODE_OFFSET 2 @@ -327,6 +328,30 @@ hns3_handle_link_change_event(struct hns3_hw *hw, } static void +hns3_update_port_base_vlan_info(struct hns3_hw *hw, + struct hns3_mbx_pf_to_vf_cmd *req) +{ +#define PVID_STATE_OFFSET 1 + uint16_t new_pvid_state = req->msg[PVID_STATE_OFFSET] ? + HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; + /* + * Currently, hardware doesn't support more than two layers VLAN offload + * based on hns3 network engine, which would cause packets loss or wrong + * packets for these types of packets. If the hns3 PF kernel ethdev + * driver sets the PVID for VF device after initialization of the + * related VF device, the PF driver will notify VF driver to update the + * PVID configuration state. The VF driver will update the PVID + * configuration state immediately to ensure that the VLAN process in Tx + * and Rx is correct. But in the window period of this state transition, + * packets loss or packets with wrong VLAN may occur. + */ + if (hw->port_base_vlan_cfg.state != new_pvid_state) { + hw->port_base_vlan_cfg.state = new_pvid_state; + hns3_update_all_queues_pvid_state(hw); + } +} + +static void hns3_handle_promisc_info(struct hns3_hw *hw, uint16_t promisc_en) { if (!promisc_en) { @@ -399,6 +424,14 @@ hns3_dev_handle_mbx_msg(struct hns3_hw *hw) case HNS3_MBX_PUSH_LINK_STATUS: hns3_handle_link_change_event(hw, req); break; + case HNS3_MBX_PUSH_VLAN_INFO: + /* + * When the PVID configuration status of VF device is + * changed by the hns3 PF kernel driver, VF driver will + * receive this mailbox message from PF driver. + */ + hns3_update_port_base_vlan_info(hw, req); + break; case HNS3_MBX_PUSH_PROMISC_INFO: /* * When the trust status of VF device changed by the diff --git a/drivers/net/hns3/hns3_mbx.h b/drivers/net/hns3/hns3_mbx.h index d6d70f6..7f7ade1 100644 --- a/drivers/net/hns3/hns3_mbx.h +++ b/drivers/net/hns3/hns3_mbx.h @@ -40,6 +40,8 @@ enum HNS3_MBX_OPCODE { HNS3_MBX_SET_MTU, /* (VF -> PF) set mtu */ HNS3_MBX_GET_QID_IN_PF, /* (VF -> PF) get queue id in pf */ + HNS3_MBX_PUSH_VLAN_INFO = 34, /* (PF -> VF) push port base vlan */ + HNS3_MBX_PUSH_PROMISC_INFO = 36, /* (PF -> VF) push vf promisc info */ HNS3_MBX_HANDLE_VF_TBL = 38, /* (VF -> PF) store/clear hw cfg tbl */ @@ -62,6 +64,7 @@ enum hns3_mbx_vlan_cfg_subcode { HNS3_MBX_VLAN_FILTER = 0, /* set vlan filter */ HNS3_MBX_VLAN_TX_OFF_CFG, /* set tx side vlan offload */ HNS3_MBX_VLAN_RX_OFF_CFG, /* set rx side vlan offload */ + HNS3_MBX_GET_PORT_BASE_VLAN_STATE = 4, /* get port based vlan state */ }; enum hns3_mbx_tbl_cfg_subcode { diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index d744d85..0f9825f 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2422,6 +2422,48 @@ hns3_check_tso_pkt_valid(struct rte_mbuf *m) return 0; } +#ifdef RTE_LIBRTE_ETHDEV_DEBUG +static inline int +hns3_vld_vlan_chk(struct hns3_tx_queue *txq, struct rte_mbuf *m) +{ + struct rte_ether_hdr *eh; + struct rte_vlan_hdr *vh; + + if (!txq->pvid_state) + return 0; + + /* + * Due to hardware limitations, we only support two-layer VLAN hardware + * offload in Tx direction based on hns3 network engine, so when PVID is + * enabled, QinQ insert is no longer supported. + * And when PVID is enabled, in the following two cases: + * i) packets with more than two VLAN tags. + * ii) packets with one VLAN tag while the hardware VLAN insert is + * enabled. + * The packets will be regarded as abnormal packets and discarded by + * hardware in Tx direction. For debugging purposes, a validation check + * for these types of packets is added to the '.tx_pkt_prepare' ops + * implementation function named hns3_prep_pkts to inform users that + * these packets will be discarded. + */ + if (m->ol_flags & PKT_TX_QINQ_PKT) + return -EINVAL; + + eh = rte_pktmbuf_mtod(m, struct rte_ether_hdr *); + if (eh->ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) { + if (m->ol_flags & PKT_TX_VLAN_PKT) + return -EINVAL; + + /* Ensure the incoming packet is not a QinQ packet */ + vh = (struct rte_vlan_hdr *)(eh + 1); + if (vh->eth_proto == rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) + return -EINVAL; + } + + return 0; +} +#endif + uint16_t hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) @@ -2446,6 +2488,11 @@ hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, rte_errno = -ret; return i; } + + if (hns3_vld_vlan_chk(tx_queue, m)) { + rte_errno = EINVAL; + return i; + } #endif ret = rte_net_intel_cksum_prepare(m); if (ret != 0) { From patchwork Wed Jul 1 11:54:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72606 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E14E7A0350; Wed, 1 Jul 2020 13:57:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E818D1D423; Wed, 1 Jul 2020 13:56:36 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 1E6D51D407 for ; Wed, 1 Jul 2020 13:56:34 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 268D9267C5DD9C932944 for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:21 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:37 +0800 Message-ID: <1593604482-47494-6-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 05/10] net/hns3: get device capability in primary process X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch optimizes the code to get device capability in primary process, and moves the code of getting PCI revison id in order to avoid evaluating the private hw->revision of shared PMD-specific private data in slave process. Signed-off-by: Wei Hu (Xavier) Signed-off-by: Huisong Li Signed-off-by: Chengwen Feng Signed-off-by: Chengchang Tang --- drivers/net/hns3/hns3_ethdev.c | 57 +++++++++++++++++++++++++-------------- drivers/net/hns3/hns3_ethdev.h | 4 +-- drivers/net/hns3/hns3_ethdev_vf.c | 43 ++++++++++++++++++++--------- 3 files changed, 69 insertions(+), 35 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 5a2f049..a43ed82 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2798,6 +2798,36 @@ hns3_parse_speed(int speed_cmd, uint32_t *speed) } static int +hns3_get_capability(struct hns3_hw *hw) +{ + struct rte_pci_device *pci_dev; + struct rte_eth_dev *eth_dev; + uint16_t device_id; + uint8_t revision; + int ret; + + eth_dev = &rte_eth_devices[hw->data->port_id]; + pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + device_id = pci_dev->id.device_id; + + if (device_id == HNS3_DEV_ID_25GE_RDMA || + device_id == HNS3_DEV_ID_50GE_RDMA || + device_id == HNS3_DEV_ID_100G_RDMA_MACSEC) + hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); + + /* Get PCI revision id */ + ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, + HNS3_PCI_REVISION_ID); + if (ret != HNS3_PCI_REVISION_ID_LEN) { + PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret); + return -EIO; + } + hw->revision = revision; + + return 0; +} + +static int hns3_get_board_configuration(struct hns3_hw *hw) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); @@ -2872,6 +2902,13 @@ hns3_get_configuration(struct hns3_hw *hw) return ret; } + /* Get device capability */ + ret = hns3_get_capability(hw); + if (ret) { + PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); + return ret; + } + /* Get pf resource */ ret = hns3_query_pf_resource(hw); if (ret) { @@ -5366,26 +5403,12 @@ static const struct hns3_reset_ops hns3_reset_ops = { static int hns3_dev_init(struct rte_eth_dev *eth_dev) { - struct rte_device *dev = eth_dev->device; - struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - uint16_t device_id = pci_dev->id.device_id; - uint8_t revision; int ret; PMD_INIT_FUNC_TRACE(); - /* Get PCI revision id */ - ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, - HNS3_PCI_REVISION_ID); - if (ret != HNS3_PCI_REVISION_ID_LEN) { - PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d", - ret); - return -EIO; - } - hw->revision = revision; - eth_dev->process_private = (struct hns3_process_private *) rte_zmalloc_socket("hns3_filter_list", sizeof(struct hns3_process_private), @@ -5407,12 +5430,6 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) hns3_mp_init_primary(); hw->adapter_state = HNS3_NIC_UNINITIALIZED; - - if (device_id == HNS3_DEV_ID_25GE_RDMA || - device_id == HNS3_DEV_ID_50GE_RDMA || - device_id == HNS3_DEV_ID_100G_RDMA_MACSEC) - hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1); - hns->is_vf = false; hw->data = eth_dev->data; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index a4db1c9..c390263 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -402,7 +402,7 @@ struct hns3_hw { uint16_t alloc_rss_size; /* RX queue number per TC */ uint16_t tx_qnum_per_tc; /* TX queue number per TC */ - uint32_t flag; + uint32_t capability; struct hns3_port_base_vlan_config port_base_vlan_cfg; /* @@ -533,7 +533,7 @@ struct hns3_adapter { #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define hns3_dev_dcb_supported(hw) \ - hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B) + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index afa79a7..04a8364 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1059,6 +1059,29 @@ hns3vf_interrupt_handler(void *param) } static int +hns3vf_get_capability(struct hns3_hw *hw) +{ + struct rte_pci_device *pci_dev; + struct rte_eth_dev *eth_dev; + uint8_t revision; + int ret; + + eth_dev = &rte_eth_devices[hw->data->port_id]; + pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + + /* Get PCI revision id */ + ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, + HNS3_PCI_REVISION_ID); + if (ret != HNS3_PCI_REVISION_ID_LEN) { + PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret); + return -EIO; + } + hw->revision = revision; + + return 0; +} + +static int hns3vf_check_tqp_info(struct hns3_hw *hw) { uint16_t tqps_num; @@ -1208,6 +1231,13 @@ hns3vf_get_configuration(struct hns3_hw *hw) hw->mac.media_type = HNS3_MEDIA_TYPE_NONE; hw->rss_dis_flag = false; + /* Get device capability */ + ret = hns3vf_get_capability(hw); + if (ret) { + PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); + return ret; + } + /* Get queue configuration from PF */ ret = hns3vf_get_queue_info(hw); if (ret) @@ -2474,25 +2504,12 @@ static const struct hns3_reset_ops hns3vf_reset_ops = { static int hns3vf_dev_init(struct rte_eth_dev *eth_dev) { - struct rte_device *dev = eth_dev->device; - struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); struct hns3_adapter *hns = eth_dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - uint8_t revision; int ret; PMD_INIT_FUNC_TRACE(); - /* Get PCI revision id */ - ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, - HNS3_PCI_REVISION_ID); - if (ret != HNS3_PCI_REVISION_ID_LEN) { - PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d", - ret); - return -EIO; - } - hw->revision = revision; - eth_dev->process_private = (struct hns3_process_private *) rte_zmalloc_socket("hns3_filter_list", sizeof(struct hns3_process_private), From patchwork Wed Jul 1 11:54:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72607 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56954A0350; Wed, 1 Jul 2020 13:57:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1F93E1D44B; Wed, 1 Jul 2020 13:56:38 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 34EC71D40A for ; Wed, 1 Jul 2020 13:56:34 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 2B41EC95BDA785F5B4D7 for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:22 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:38 +0800 Message-ID: <1593604482-47494-7-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 06/10] net/hns3: clear residual hardware configurations on init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng When the last driver exits abnormally, for example, it is killed by 'kill -9', it may be too late to clear the configuration and cause the configuration to remain. Therefore, to ensure that the hardware environment is clean during initialization, the PF driver actively clear the hardware environment during initialization, including PF and corresponding VFs' vlan, mac, flow table configurations, etc. Fixes: d51867db65c1 ("net/hns3: add initialization") Cc: stable@dpdk.org Signed-off-by: Hongbo Zheng Signed-off-by: Wei Hu (Xavier) Signed-off-by: Chengwen Feng --- drivers/net/hns3/hns3_cmd.h | 3 +++ drivers/net/hns3/hns3_ethdev.c | 27 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index da770ac..b203e66 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -207,6 +207,9 @@ enum hns3_opcode_type { HNS3_OPC_FD_AD_OP = 0x1204, HNS3_OPC_FD_COUNTER_OP = 0x1205, + /* Clear hardware state command */ + HNS3_OPC_CLEAR_HW_STATE = 0x700A, + /* SFP command */ HNS3_OPC_SFP_GET_SPEED = 0x7104, diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index a43ed82..1c234da 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -4322,6 +4322,21 @@ hns3_init_hardware(struct hns3_adapter *hns) } static int +hns3_clear_hw(struct hns3_hw *hw) +{ + struct hns3_cmd_desc desc; + int ret; + + hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); + + ret = hns3_cmd_send(hw, &desc, 1); + if (ret && ret != -EOPNOTSUPP) + return ret; + + return 0; +} + +static int hns3_init_pf(struct rte_eth_dev *eth_dev) { struct rte_device *dev = eth_dev->device; @@ -4351,6 +4366,18 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } + /* + * To ensure that the hardware environment is clean during + * initialization, the driver actively clear the hardware environment + * during initialization, including PF and corresponding VFs' vlan, mac, + * flow table configurations, etc. + */ + ret = hns3_clear_hw(hw); + if (ret) { + PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); + goto err_cmd_init; + } + ret = rte_intr_callback_register(&pci_dev->intr_handle, hns3_interrupt_handler, eth_dev); From patchwork Wed Jul 1 11:54:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72609 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C30D4A0350; Wed, 1 Jul 2020 13:57:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 70D111D514; Wed, 1 Jul 2020 13:56:40 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 6238E1D40D for ; Wed, 1 Jul 2020 13:56:34 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3B6D67D64DCBBDBC8705 for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:22 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:39 +0800 Message-ID: <1593604482-47494-8-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 07/10] net/hns3: report Tx descriptor segment limitations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Lijun Ou According to the user manual of Kunpeng920 SoC, the max allowed number of segments per whole packet is 63 and the max number of segments per packet is 8 in datapath. This patch reports the Two segment parameters of Tx descriptor limitations to DPDK framework. Signed-off-by: Lijun Ou Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_ethdev.c | 2 ++ drivers/net/hns3/hns3_ethdev_vf.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 1c234da..7bc9b17 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2494,6 +2494,8 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) .nb_max = HNS3_MAX_RING_DESC, .nb_min = HNS3_MIN_RING_DESC, .nb_align = HNS3_ALIGN_RING_DESC, + .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, + .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT, }; info->vmdq_queue_num = 0; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 04a8364..9c45ffa 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -944,6 +944,8 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) .nb_max = HNS3_MAX_RING_DESC, .nb_min = HNS3_MIN_RING_DESC, .nb_align = HNS3_ALIGN_RING_DESC, + .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, + .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT, }; info->vmdq_queue_num = 0; From patchwork Wed Jul 1 11:54:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72611 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 29E0CA0350; Wed, 1 Jul 2020 13:57:54 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0EE0B1D526; Wed, 1 Jul 2020 13:56:43 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id A3DE01D41B for ; Wed, 1 Jul 2020 13:56:35 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 37057F4C2CA48A119C92 for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:22 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:40 +0800 Message-ID: <1593604482-47494-9-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 08/10] net/hns3: fix Rx buffer size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, rx_buf_size of hns3 PMD driver is fixed on, and it's value depends on the firmware which will decrease the flexibility of PMD. The receive side mbufs was allocated from the mempool given by upper application calling rte_eth_rx_queue_setup API function. So the memory chunk used for net device DMA is depend on the data room size of the objects in this mempool. Hns3 PMD driver should set the rx_buf_len smaller than the data room size of mempool and our hardware only support the following four specifications: 512, 1024, 2148 and 4096. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_ethdev.c | 3 +-- drivers/net/hns3/hns3_ethdev.h | 1 - drivers/net/hns3/hns3_ethdev_vf.c | 5 +--- drivers/net/hns3/hns3_rxtx.c | 56 +++++++++++++++++++++++++++++++++++++-- drivers/net/hns3/hns3_rxtx.h | 8 ++++++ 5 files changed, 64 insertions(+), 9 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 7bc9b17..00ed3e2 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2453,7 +2453,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) info->max_rx_queues = queue_num; info->max_tx_queues = hw->tqps_num; info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ - info->min_rx_bufsize = hw->rx_buf_len; + info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; info->max_mac_addrs = HNS3_UC_MACADDR_NUM; info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; @@ -2851,7 +2851,6 @@ hns3_get_board_configuration(struct hns3_hw *hw) hw->mac.media_type = cfg.media_type; hw->rss_size_max = cfg.rss_size_max; hw->rss_dis_flag = false; - hw->rx_buf_len = cfg.rx_buf_len; memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); hw->mac.phy_addr = cfg.phy_addr; hw->mac.default_addr_setted = false; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index c390263..3c991f4 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -375,7 +375,6 @@ struct hns3_hw { uint16_t tqps_num; /* num task queue pairs of this function */ uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */ uint16_t rss_size_max; /* HW defined max RSS task queue */ - uint16_t rx_buf_len; uint16_t num_tx_desc; /* desc num of per tx queue */ uint16_t num_rx_desc; /* desc num of per rx queue */ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 9c45ffa..3c5998a 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -902,7 +902,7 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) info->max_rx_queues = q_num; info->max_tx_queues = hw->tqps_num; info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ - info->min_rx_bufsize = hw->rx_buf_len; + info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM; info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; @@ -1096,8 +1096,6 @@ hns3vf_check_tqp_info(struct hns3_hw *hw) return -EINVAL; } - if (hw->rx_buf_len == 0) - hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN; hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num); return 0; @@ -1162,7 +1160,6 @@ hns3vf_get_queue_info(struct hns3_hw *hw) memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t)); memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t)); - memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t)); return hns3vf_check_tqp_info(hw); } diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 0f9825f..931d89a 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -909,7 +909,7 @@ hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, nb_rx_q = dev->data->nb_rx_queues; rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + (nb_rx_q + idx) * HNS3_TQP_REG_SIZE); - rxq->rx_buf_len = hw->rx_buf_len; + rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE; rte_spinlock_lock(&hw->lock); hw->fkq_data.rx_queues[idx] = rxq; @@ -1185,6 +1185,48 @@ hns3_dev_release_mbufs(struct hns3_adapter *hns) } } +static int +hns3_rx_buf_len_calc(struct rte_mempool *mp, uint16_t *rx_buf_len) +{ + uint16_t vld_buf_size; + uint16_t num_hw_specs; + uint16_t i; + + /* + * hns3 network engine only support to set 4 typical specification, and + * different buffer size will affect the max packet_len and the max + * number of segmentation when hw gro is turned on in receive side. The + * relationship between them is as follows: + * rx_buf_size | max_gro_pkt_len | max_gro_nb_seg + * ---------------------|-------------------|---------------- + * HNS3_4K_BD_BUF_SIZE | 60KB | 15 + * HNS3_2K_BD_BUF_SIZE | 62KB | 31 + * HNS3_1K_BD_BUF_SIZE | 63KB | 63 + * HNS3_512_BD_BUF_SIZE | 31.5KB | 63 + */ + static const uint16_t hw_rx_buf_size[] = { + HNS3_4K_BD_BUF_SIZE, + HNS3_2K_BD_BUF_SIZE, + HNS3_1K_BD_BUF_SIZE, + HNS3_512_BD_BUF_SIZE + }; + + vld_buf_size = (uint16_t)(rte_pktmbuf_data_room_size(mp) - + RTE_PKTMBUF_HEADROOM); + + if (vld_buf_size < HNS3_MIN_BD_BUF_SIZE) + return -EINVAL; + + num_hw_specs = RTE_DIM(hw_rx_buf_size); + for (i = 0; i < num_hw_specs; i++) { + if (vld_buf_size >= hw_rx_buf_size[i]) { + *rx_buf_len = hw_rx_buf_size[i]; + break; + } + } + return 0; +} + int hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_rxconf *conf, @@ -1194,6 +1236,7 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, struct hns3_hw *hw = &hns->hw; struct hns3_queue_info q_info; struct hns3_rx_queue *rxq; + uint16_t rx_buf_size; int rx_entry_len; if (dev->data->dev_started) { @@ -1218,6 +1261,15 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, q_info.nb_desc = nb_desc; q_info.type = "hns3 RX queue"; q_info.ring_name = "rx_ring"; + + if (hns3_rx_buf_len_calc(mp, &rx_buf_size)) { + hns3_err(hw, "rxq mbufs' data room size:%u is not enough! " + "minimal data room size:%u.", + rte_pktmbuf_data_room_size(mp), + HNS3_MIN_BD_BUF_SIZE + RTE_PKTMBUF_HEADROOM); + return -EINVAL; + } + rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info); if (rxq == NULL) { hns3_err(hw, @@ -1252,7 +1304,7 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, rxq->configured = true; rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + idx * HNS3_TQP_REG_SIZE); - rxq->rx_buf_len = hw->rx_buf_len; + rxq->rx_buf_len = rx_buf_size; rxq->l2_errors = 0; rxq->pkt_len_errors = 0; rxq->l3_csum_erros = 0; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index b85c64f..ccd508b 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -11,6 +11,14 @@ #define HNS3_ALIGN_RING_DESC 32 #define HNS3_RING_BASE_ALIGN 128 +#define HNS3_512_BD_BUF_SIZE 512 +#define HNS3_1K_BD_BUF_SIZE 1024 +#define HNS3_2K_BD_BUF_SIZE 2048 +#define HNS3_4K_BD_BUF_SIZE 4096 + +#define HNS3_MIN_BD_BUF_SIZE HNS3_512_BD_BUF_SIZE +#define HNS3_MAX_BD_BUF_SIZE HNS3_4K_BD_BUF_SIZE + #define HNS3_BD_SIZE_512_TYPE 0 #define HNS3_BD_SIZE_1024_TYPE 1 #define HNS3_BD_SIZE_2048_TYPE 2 From patchwork Wed Jul 1 11:54:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72605 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCF2BA0350; Wed, 1 Jul 2020 13:56:59 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5D5661D426; Wed, 1 Jul 2020 13:56:35 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 309F91D183 for ; Wed, 1 Jul 2020 13:56:33 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 335883952F3187DBB78D for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:22 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:41 +0800 Message-ID: <1593604482-47494-10-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 09/10] net/hns3: fix reassembling multiple segment packets in Tx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Because of the hardware constraints, hns3 network engine doesn't support sending packets with more than eight fragments. And hns3 pmd driver tries to reassemble these kind of packets to meet hardware requirements. Currently, there are two problems: 1) when the input buffer_len * 8 < pkt_len, the packets are impossible to be reassembled into 8 Buffer Descriptors. In this case, the packets will be passed to hardware, which eventually causes a hardware reset. 2) The meta data in origin packets which are required to fill into the descriptor haven't been copied into the reassembled pkts. This patch adds a check for 1) to ensure such packets will be dropped by driver and copies useful meta data from the origin packets to the reassembled packets. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang Signed-off-by: Wei Hu (Xavier) Signed-off-by: Chengwen Feng --- drivers/net/hns3/hns3_rxtx.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 931d89a..8892fc1 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2095,6 +2095,20 @@ hns3_tx_alloc_mbufs(struct hns3_tx_queue *txq, struct rte_mempool *mb_pool, return 0; } +static inline void +hns3_pktmbuf_copy_hdr(struct rte_mbuf *new_pkt, struct rte_mbuf *old_pkt) +{ + new_pkt->ol_flags = old_pkt->ol_flags; + new_pkt->pkt_len = rte_pktmbuf_pkt_len(old_pkt); + new_pkt->outer_l2_len = old_pkt->outer_l2_len; + new_pkt->outer_l3_len = old_pkt->outer_l3_len; + new_pkt->l2_len = old_pkt->l2_len; + new_pkt->l3_len = old_pkt->l3_len; + new_pkt->l4_len = old_pkt->l4_len; + new_pkt->vlan_tci_outer = old_pkt->vlan_tci_outer; + new_pkt->vlan_tci = old_pkt->vlan_tci; +} + static int hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt, struct rte_mbuf **new_pkt) @@ -2118,9 +2132,11 @@ hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt, mb_pool = tx_pkt->pool; buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM; - nb_new_buf = (tx_pkt->pkt_len - 1) / buf_size + 1; + nb_new_buf = (rte_pktmbuf_pkt_len(tx_pkt) - 1) / buf_size + 1; + if (nb_new_buf > HNS3_MAX_NON_TSO_BD_PER_PKT) + return -EINVAL; - last_buf_len = tx_pkt->pkt_len % buf_size; + last_buf_len = rte_pktmbuf_pkt_len(tx_pkt) % buf_size; if (last_buf_len == 0) last_buf_len = buf_size; @@ -2132,7 +2148,7 @@ hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt, /* Copy the original packet content to the new mbufs */ temp = tx_pkt; s = rte_pktmbuf_mtod(temp, char *); - len_s = temp->data_len; + len_s = rte_pktmbuf_data_len(temp); temp_new = new_mbuf; for (i = 0; i < nb_new_buf; i++) { d = rte_pktmbuf_mtod(temp_new, char *); @@ -2155,13 +2171,14 @@ hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt, if (temp == NULL) break; s = rte_pktmbuf_mtod(temp, char *); - len_s = temp->data_len; + len_s = rte_pktmbuf_data_len(temp); } } temp_new->data_len = buf_len; temp_new = temp_new->next; } + hns3_pktmbuf_copy_hdr(new_mbuf, tx_pkt); /* free original mbufs */ rte_pktmbuf_free(tx_pkt); From patchwork Wed Jul 1 11:54:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 72608 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0837BA0350; Wed, 1 Jul 2020 13:57:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1A3911D454; Wed, 1 Jul 2020 13:56:39 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id 213681D41B for ; Wed, 1 Jul 2020 13:56:35 +0200 (CEST) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 22B4A6C76484E559C8C2 for ; Wed, 1 Jul 2020 19:56:32 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Wed, 1 Jul 2020 19:56:23 +0800 From: "Wei Hu (Xavier)" To: CC: Date: Wed, 1 Jul 2020 19:54:42 +0800 Message-ID: <1593604482-47494-11-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> References: <1593604482-47494-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 10/10] net/hns3: add Scattered Rx and Multiprocess to feature list X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds 'Scattered Rx' and 'Multiprocess aware' those are supported by current hns3 PMD driver for feature list file named hns3.ini and hns3_vf.ini. Signed-off-by: Wei Hu (Xavier) --- doc/guides/nics/features/hns3.ini | 2 ++ doc/guides/nics/features/hns3_vf.ini | 2 ++ 2 files changed, 4 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 66abda7..2533345 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -8,6 +8,7 @@ Link status = Y Rx interrupt = Y MTU update = Y Jumbo frame = Y +Scattered Rx = Y TSO = Y LRO = Y Promiscuous mode = Y @@ -31,6 +32,7 @@ Basic stats = Y Extended stats = Y Stats per queue = Y FW version = Y +Multiprocess aware = Y Linux UIO = Y Linux VFIO = Y ARMv8 = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index 71d246a..05a32c8 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -8,6 +8,7 @@ Link status = Y Rx interrupt = Y MTU update = Y Jumbo frame = Y +Scattered Rx = Y TSO = Y LRO = Y Promiscuous mode = Y @@ -28,6 +29,7 @@ Inner L4 checksum = Y Basic stats = Y Extended stats = Y Stats per queue = Y +Multiprocess aware = Y Linux UIO = Y Linux VFIO = Y ARMv8 = Y