diff mbox series

[V2,4/4] conf/loopback_vhost_async_perf_dsa: add new testsuite config file

Message ID 20230216080944.1025523-1-weix.ling@intel.com (mailing list archive)
State Accepted
Headers
Series add loopback_vhost_async_perf_dsa |

Checks

Context Check Description
ci/Intel-dts-format-test success Testing OK
ci/Intel-dts-pylama-test success Testing OK
ci/Intel-dts-doc-test success Testing OK
ci/Intel-dts-suite-test warning SKIPPED

Commit Message

Ling, WeiX Feb. 16, 2023, 8:09 a.m. UTC 
  Add conf/loopback_vhost_async_perf_dsa.cfg.

Signed-off-by: Wei Ling <weix.ling@intel.com>
---
 conf/loopback_vhost_async_perf_dsa.cfg | 165 +++++++++++++++++++++++++
 1 file changed, 165 insertions(+)
 create mode 100644 conf/loopback_vhost_async_perf_dsa.cfg

Comments

Tu, Lijuan March 7, 2023, 3:10 a.m. UTC | #1 
On Thu, 16 Feb 2023 16:09:44 +0800, Wei Ling <weix.ling@intel.com> wrote:
> Add conf/loopback_vhost_async_perf_dsa.cfg.
> 
> Signed-off-by: Wei Ling <weix.ling@intel.com>


Series applied, thanks
diff mbox series

Patch

diff --git a/conf/loopback_vhost_async_perf_dsa.cfg b/conf/loopback_vhost_async_perf_dsa.cfg
new file mode 100644
index 00000000..bba33d76
--- /dev/null
+++ b/conf/loopback_vhost_async_perf_dsa.cfg
@@ -0,0 +1,165 @@ 
+[suite]
+update_expected = True
+test_parameters = {64: [1024], 128: [1024], 256: [1024], 512: [1024], 1024: [1024], 1518: [1024]}
+test_duration = 60
+accepted_tolerance = 1
+expected_throughput = {
+	'test_loopback_split_ring_inorder_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_inorder_non_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_non_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_vector_rx_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_inorder_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_inorder_non_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_non_mergedable_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_vector_rx_idxd': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_inorder_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_inorder_non_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_non_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_split_ring_vector_rx_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_inorder_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_inorder_non_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_non_mergedable_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}
+	},
+	'test_loopback_packed_ring_vector_rx_vfio_pci': {
+		64: {1024: 0.00},
+		128: {1024: 0.00},
+		256: {1024: 0.00},
+		512: {1024: 0.00},
+		1024: {1024: 0.00},
+		1518: {1024: 0.00}}}