diff mbox series

[V1] framework/crb: optimize code

Message ID 20210326032023.26113-1-haiyangx.zhao@intel.com (mailing list archive)
State Accepted
Headers
Series [V1] framework/crb: optimize code |

Commit Message

Zhao, HaiyangX March 26, 2021, 3:20 a.m. UTC 
  when the param dut_arch in conf/crbs.cfg not exist, dts will generate
a keyerror exception and terminate the test, but this param could not
be set actually.

Signed-off-by: Haiyang Zhao <haiyangx.zhao@intel.com>
---
 framework/crb.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Zhao, HaiyangX March 26, 2021, 3:31 a.m. UTC | #1 
> -----Original Message-----
> From: Haiyang Zhao <haiyangx.zhao@intel.com>
> Sent: Friday, March 26, 2021 11:20
> To: dts@dpdk.org
> Cc: Tu, Lijuan <lijuan.tu@intel.com>; Zhao, HaiyangX
> <haiyangx.zhao@intel.com>
> Subject: [dts][PATCH V1] framework/crb: optimize code

Tested-by: Haiyang Zhao <haiyangx.zhao@intel.com>
Tu, Lijuan March 30, 2021, 2:28 a.m. UTC | #2 
> -----Original Message-----
> From: Zhao, HaiyangX <haiyangx.zhao@intel.com>
> Sent: 2021年3月26日 11:31
> To: Zhao, HaiyangX <haiyangx.zhao@intel.com>; dts@dpdk.org
> Cc: Tu, Lijuan <lijuan.tu@intel.com>
> Subject: RE: [dts][PATCH V1] framework/crb: optimize code
> 
> 
> 
> > -----Original Message-----
> > From: Haiyang Zhao <haiyangx.zhao@intel.com>
> > Sent: Friday, March 26, 2021 11:20
> > To: dts@dpdk.org
> > Cc: Tu, Lijuan <lijuan.tu@intel.com>; Zhao, HaiyangX
> > <haiyangx.zhao@intel.com>
> > Subject: [dts][PATCH V1] framework/crb: optimize code
> 
> Tested-by: Haiyang Zhao <haiyangx.zhao@intel.com>

Applied
diff mbox series

Patch

diff --git a/framework/crb.py b/framework/crb.py
index cd29b8e3..e7c1cc1c 100644
--- a/framework/crb.py
+++ b/framework/crb.py
@@ -666,7 +666,7 @@  class Crb(object):
             if self.crb['bypass core0'] and core == '0' and socket == '0':
                 self.logger.info("Core0 bypassed")
                 continue
-            if self.crb['dut arch'] == "arm64":
+            if self.crb.get('dut arch') == "arm64":
                 self.cores.append(
                         {'thread': thread, 'socket': node, 'core': coremap[core]})
             else: