diff mbox series

[v2,5/5] riscv: override machine_args only when default

Message ID tencent_C36C8B675AB5C9C26B48AD986FEE0FCB2905@qq.com (mailing list archive)
State New
Delegated to: Thomas Monjalon
Headers
Series Add RISC-V V extension detection and LPM, FIB optimization |

Checks

Context Check Description
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ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
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ci/intel-Functional success Functional PASS
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Commit Message

uk7b@foxmail.com July 1, 2025, 6:20 p.m. UTC 
From: Sun Yuechi <sunyuechi@iscas.ac.cn>

Support using -Dcpu_instruction_set=rv64gcv to enable V extension.

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
 config/riscv/meson.build | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..f93ea3e145 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -111,13 +111,15 @@  arch_config = arch_config[arch_id]
 # Concatenate flags respecting priorities.
 dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
 
-# apply supported machine args
-machine_args = [] # Clear previous machine args
-foreach flag: arch_config['machine_args']
-    if cc.has_argument(flag)
-        machine_args += flag
-    endif
-endforeach
+if (cpu_instruction_set == 'rv64gc')
+    # apply supported machine args
+    machine_args = [] # Clear previous machine args
+    foreach flag: arch_config['machine_args']
+        if cc.has_argument(flag)
+            machine_args += flag
+        endif
+    endforeach
+endif
 
 # check if we can do buildtime detection of extensions supported by the target
 riscv_extension_macros = false