diff mbox

[dpdk-dev,2/2] examples/ipsec-secgw: fix SPI byte order in flow item

Message ID a014eabcbdfcd8b20640cc6ef91885f631dc5e3e.1515662067.git.nelio.laranjeiro@6wind.com (mailing list archive)
State Accepted, archived
Delegated to: Pablo de Lara Guarch
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Nélio Laranjeiro Jan. 11, 2018, 9:15 a.m. UTC 
  SPI field is defined in the RFC2406 [1] as a big endian field it should be
provided in its final form to the drivers through RTE flow.

Fixes: ec17993a145a ("examples/ipsec-secgw: support security offload")
Cc: akhil.goyal@nxp.com

Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>

[1] https://tools.ietf.org/html/rfc2406
---
 examples/ipsec-secgw/ipsec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Akhil Goyal Jan. 11, 2018, 9:53 a.m. UTC | #1 
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
De Lara Guarch, Pablo Jan. 19, 2018, 9:34 a.m. UTC | #2 
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Nelio Laranjeiro
> Sent: Thursday, January 11, 2018 9:16 AM
> To: dev@dpdk.org; Olivier Matz <olivier.matz@6wind.com>
> Cc: akhil.goyal@nxp.com
> Subject: [dpdk-dev] [PATCH 2/2] examples/ipsec-secgw: fix SPI byte order in
> flow item
> 
> SPI field is defined in the RFC2406 [1] as a big endian field it should be
> provided in its final form to the drivers through RTE flow.
> 
> Fixes: ec17993a145a ("examples/ipsec-secgw: support security offload")
> Cc: akhil.goyal@nxp.com

Cc'ing stable ML.

> 
> Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>

Applied to dpdk-next-crypto.
Thanks,

Pablo
diff mbox

Patch

diff --git a/examples/ipsec-secgw/ipsec.c b/examples/ipsec-secgw/ipsec.c
index 580e09a3a..8df0f00ab 100644
--- a/examples/ipsec-secgw/ipsec.c
+++ b/examples/ipsec-secgw/ipsec.c
@@ -195,7 +195,7 @@  create_session(struct ipsec_ctx *ipsec_ctx, struct ipsec_sa *sa)
 			sa->pattern[2].type = RTE_FLOW_ITEM_TYPE_ESP;
 			sa->pattern[2].spec = &sa->esp_spec;
 			sa->pattern[2].mask = &rte_flow_item_esp_mask;
-			sa->esp_spec.hdr.spi = sa->spi;
+			sa->esp_spec.hdr.spi = rte_cpu_to_be_32(sa->spi);
 
 			sa->pattern[3].type = RTE_FLOW_ITEM_TYPE_END;