[dpdk-dev] Fwd: [PATCH] em: enable flash access, tested with Intel 82577LM

Message ID CA+JyDZRF=1yZnG9nFyQ0wtB3ApK8ufgun9vUvAEbnfxczOin2A@mail.gmail.com (mailing list archive)
State Rejected, archived
Headers

Commit Message

Jiuling Bie Oct. 7, 2015, 5:27 p.m. UTC
  ---
 drivers/net/e1000/base/e1000_osdep.h            | 18 ++++++++----------
 drivers/net/e1000/em_ethdev.c                   |  1 +
 lib/librte_eal/common/include/rte_pci_dev_ids.h |  1 +
 3 files changed, 10 insertions(+), 10 deletions(-)

 /******************** Physical IGB devices from e1000_hw.h
********************/
--
1.9.1
  

Comments

Thomas Monjalon Oct. 26, 2015, 4:01 p.m. UTC | #1
This patch does not comply with the DPDK rules.
But the needs deserved to be discussed with the e1000 maintainer.
Wenzhuo?

2015-10-07 13:27, Jiuling Bie:
> ---
>  drivers/net/e1000/base/e1000_osdep.h            | 18 ++++++++----------
>  drivers/net/e1000/em_ethdev.c                   |  1 +
>  lib/librte_eal/common/include/rte_pci_dev_ids.h |  1 +
>  3 files changed, 10 insertions(+), 10 deletions(-)
  
Wenzhuo Lu Oct. 27, 2015, 1:01 a.m. UTC | #2
Hi Jiuling, Thomas,
I think we can change the osdep in the base directory.
But the tittle is a little weird, I mean the "Fwd:" :)  And some comments are needed to explain why we need this patch. Thanks.

> -----Original Message-----
> From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com]
> Sent: Tuesday, October 27, 2015 12:01 AM
> To: Lu, Wenzhuo
> Cc: dev@dpdk.org; Jiuling Bie
> Subject: Re: [dpdk-dev] Fwd: [PATCH] em: enable flash access, tested with
> Intel 82577LM
> 
> This patch does not comply with the DPDK rules.
> But the needs deserved to be discussed with the e1000 maintainer.
> Wenzhuo?
> 
> 2015-10-07 13:27, Jiuling Bie:
> > ---
> >  drivers/net/e1000/base/e1000_osdep.h            | 18 ++++++++----------
> >  drivers/net/e1000/em_ethdev.c                   |  1 +
> >  lib/librte_eal/common/include/rte_pci_dev_ids.h |  1 +
> >  3 files changed, 10 insertions(+), 10 deletions(-)
>
  

Patch

diff --git a/drivers/net/e1000/base/e1000_osdep.h
b/drivers/net/e1000/base/e1000_osdep.h
index d04ec73..ed08441 100644
--- a/drivers/net/e1000/base/e1000_osdep.h
+++ b/drivers/net/e1000/base/e1000_osdep.h
@@ -155,21 +155,19 @@  static inline uint32_t e1000_read_addr(volatile void*
addr)
 #define E1000_WRITE_REG_IO(hw, reg, value) \
        E1000_WRITE_REG(hw, reg, value)

-/*
- * Not implemented.
- */
-
 #define E1000_READ_FLASH_REG(hw, reg) \
-       (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG, hw, reg, 0), 0)
+       rte_le_to_cpu_32(*(volatile uint32_t *)(hw->flash_address + reg))

 #define E1000_READ_FLASH_REG16(hw, reg)  \
-       (E1000_ACCESS_PANIC(E1000_READ_FLASH_REG16, hw, reg, 0), 0)
+       rte_le_to_cpu_16(*(volatile uint16_t *)(hw->flash_address + reg))

-#define E1000_WRITE_FLASH_REG(hw, reg, value)  \
-       E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG, hw, reg, value)
+#define E1000_WRITE_FLASH_REG(hw, reg, value) do { \
+       *(volatile uint32_t *)(hw->flash_address + reg) =
rte_cpu_to_le_32(value); \
+} while (0)

-#define E1000_WRITE_FLASH_REG16(hw, reg, value) \
-       E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG16, hw, reg, value)
+#define E1000_WRITE_FLASH_REG16(hw, reg, value) do { \
+       *(volatile uint16_t *)(hw->flash_address + reg) =
rte_cpu_to_le_16(value); \
+} while (0)

 #define STATIC static

diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c
index 912f5dd..dd82bad 100644
--- a/drivers/net/e1000/em_ethdev.c
+++ b/drivers/net/e1000/em_ethdev.c
@@ -247,6 +247,7 @@  eth_em_dev_init(struct rte_eth_dev *eth_dev)
        }

        hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
+       hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
        hw->device_id = pci_dev->id.device_id;
        adapter->stopped = 0;

diff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h
b/lib/librte_eal/common/include/rte_pci_dev_ids.h
index 265e66c..071cf8a 100644
--- a/lib/librte_eal/common/include/rte_pci_dev_ids.h
+++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h
@@ -304,6 +304,7 @@  RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL,
E1000_DEV_ID_82572EI)
 RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82573L)
 RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574L)
 RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574LA)
+RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_M_HV_LM)
 RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82583V)